JP2017526178A5 - - Google Patents

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Publication number
JP2017526178A5
JP2017526178A5 JP2017505838A JP2017505838A JP2017526178A5 JP 2017526178 A5 JP2017526178 A5 JP 2017526178A5 JP 2017505838 A JP2017505838 A JP 2017505838A JP 2017505838 A JP2017505838 A JP 2017505838A JP 2017526178 A5 JP2017526178 A5 JP 2017526178A5
Authority
JP
Japan
Prior art keywords
layer
substrate layer
insulator
semiconductor
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017505838A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017526178A (ja
Filing date
Publication date
Priority claimed from US14/454,262 external-priority patent/US20160043108A1/en
Application filed filed Critical
Publication of JP2017526178A publication Critical patent/JP2017526178A/ja
Publication of JP2017526178A5 publication Critical patent/JP2017526178A5/ja
Pending legal-status Critical Current

Links

JP2017505838A 2014-08-07 2015-07-23 Ｓｏｉウエハ中に複数の活性層を備えた半導体構造 Pending JP2017526178A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/454,262 2014-08-07
US14/454,262 US20160043108A1 (en) 2014-08-07 2014-08-07 Semiconductor Structure with Multiple Active Layers in an SOI Wafer
PCT/US2015/041769 WO2016022302A1 (en) 2014-08-07 2015-07-23 Semiconductor structure with multiple active layers in an soi wafer

Publications (2)

Publication Number Publication Date
JP2017526178A JP2017526178A (ja) 2017-09-07
JP2017526178A5 true JP2017526178A5 (OSRAM) 2018-08-09

Family

ID=55264334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017505838A Pending JP2017526178A (ja) 2014-08-07 2015-07-23 Ｓｏｉウエハ中に複数の活性層を備えた半導体構造

Country Status (7)

Country Link
US (1) US20160043108A1 (OSRAM)
EP (1) EP3180802B1 (OSRAM)
JP (1) JP2017526178A (OSRAM)
KR (1) KR20170040226A (OSRAM)
CN (1) CN106716620B (OSRAM)
TW (1) TW201613035A (OSRAM)
WO (1) WO2016022302A1 (OSRAM)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9847293B1 (en) * 2016-08-18 2017-12-19 Qualcomm Incorporated Utilization of backside silicidation to form dual side contacted capacitor
US11735585B2 (en) 2021-01-18 2023-08-22 Samsung Electronics Co., Ltd. Stacked semiconductor device having mirror-symmetric pattern
CN116207036A (zh) * 2023-02-28 2023-06-02 上海华虹宏力半导体制造有限公司 射频开关的形成方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2617798B2 (ja) * 1989-09-22 1997-06-04 三菱電機株式会社 積層型半導体装置およびその製造方法
KR100268419B1 (ko) * 1998-08-14 2000-10-16 윤종용 고집적 반도체 메모리 장치 및 그의 제조 방법
US7767484B2 (en) * 2006-05-31 2010-08-03 Georgia Tech Research Corporation Method for sealing and backside releasing of microelectromechanical systems
US7485508B2 (en) * 2007-01-26 2009-02-03 International Business Machines Corporation Two-sided semiconductor-on-insulator structures and methods of manufacturing the same
JP4825778B2 (ja) * 2007-11-16 2011-11-30 株式会社日立製作所 半導体装置およびその製造方法
US8334729B1 (en) * 2009-03-19 2012-12-18 Rf Micro Devices, Inc. Elimination of hot switching in MEMS based impedance matching circuits
US9299641B2 (en) * 2012-08-10 2016-03-29 Monolithic 3D Inc. Semiconductor system, device and structure with heat removal
KR101134819B1 (ko) * 2010-07-02 2012-04-13 이상윤 반도체 메모리 장치의 제조 방법
US8124470B1 (en) * 2010-09-29 2012-02-28 International Business Machines Corporation Strained thin body semiconductor-on-insulator substrate and device
US9553013B2 (en) * 2010-12-24 2017-01-24 Qualcomm Incorporated Semiconductor structure with TRL and handle wafer cavities
US8481405B2 (en) * 2010-12-24 2013-07-09 Io Semiconductor, Inc. Trap rich layer with through-silicon-vias in semiconductor devices
EP3734645B1 (en) * 2010-12-24 2025-09-10 Qualcomm Incorporated Trap rich layer for semiconductor devices
US9029173B2 (en) * 2011-10-18 2015-05-12 Monolithic 3D Inc. Method for fabrication of a semiconductor device and structure
US9496255B2 (en) * 2011-11-16 2016-11-15 Qualcomm Incorporated Stacked CMOS chipset having an insulating layer and a secondary layer and method of forming same
CN104249991B (zh) * 2013-06-26 2016-08-10 中芯国际集成电路制造(上海)有限公司 Mems器件及其制作方法

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