JP2017199720A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve a highly-reliable vertical semiconductor device.SOLUTION: A semiconductor device 100 comprises a first semiconductor region 50a and a second semiconductor region 50b separated from each other by a dielectric body 18. The first semiconductor region 50a has an n-type drain region 30, an n-type drift region 28 having a lower impurity concentration than the drain region 30, a p-type base region 26, and an n-type source region 20. The second semiconductor region 50b has a p-type first region 6, an n-type second region 8, an n-type third region 10 having a lower impurity concentration than the second region 8, and a p-type fourth region 12. In the semiconductor device 100, both the drain region 30 and the first region 6 are contacted with an n-type semiconductor substrate 4. In addition, a Zener diode is configured by the first region 6 and the semiconductor substrate 4.SELECTED DRAWING: Figure 1

Description

  The present specification discloses a technique related to a vertical semiconductor device.

  Vertical semiconductor devices are being developed. Patent Document 1 (FIG. 19) discloses a semiconductor device in which a dielectric 4 extending from the front surface to the back surface of a semiconductor layer is provided in the semiconductor layer. The dielectric 4 separates the semiconductor layer into a first semiconductor region and a second semiconductor region. In Patent Document 1, the potential in the second semiconductor region rises when the device is in an on state. A low-resistance channel is formed in a portion of the first semiconductor region facing the second semiconductor region via the dielectric 4. As a result, a current flows through the first semiconductor region. In such a semiconductor device, a channel is formed in almost the entire region from the front surface to the back surface of the first semiconductor region. Therefore, carrier movement resistance (particularly drift resistance) can be lowered.

The second semiconductor region of Patent Document 1 includes an n ⁺ type drain region 5, a p ⁻ type connection region 32, an n type connection region 31, an n ⁻ type drift control region 3 and a p ⁻ type connection region from the back side of the semiconductor layer. 33 and p ⁺ type connection region 34 are stacked in this order. The n ⁺ type drain region 5 is connected to the drain electrode 11, and the p ⁺ type connection region 34 is connected to the control electrode 19. When a voltage is applied to the control electrode 19, an electric field is applied to the p ⁻ type connection region 32 and the n type connection region 31, and the potential of the n ⁻ type drift control region 3 increases. A channel is formed in the first semiconductor region at a position facing the second semiconductor region via the dielectric 4, and electrons move through the channel. In addition, when the voltage application to the control electrode 19 is stopped while the voltage is applied to the drain electrode 11, the electric field spreads from the p ⁻ type connection region 33 toward the n ⁻ type drift control region 3 (the depletion layer is Elongation), the breakdown voltage of the second semiconductor region is maintained.

In Patent Document 1, a p ⁻ type connection region 32 containing a p type impurity at a low concentration is provided on the surface of the n ⁺ type drain region 5 in order to ensure a breakdown voltage when the device is off. As a result, the regions 5 and 32 have substantially the same potential when the device is turned off. When an electric field is generated at the junction interface between the regions 5 and 32, the breakdown voltage of the device decreases. In Patent Document 1, by setting the regions 5 and 32 to substantially the same potential in the off state, the generation of an electric field at the interface between the two is suppressed, and the breakdown voltage of the device is suppressed from decreasing.

JP 2012-182463 A

As described above, the p ⁻ type connection region 32 is provided between the n ⁺ type drain region 5 and the n type connection region 31. For this reason, it is difficult to form a p-type semiconductor having a low impurity concentration as designed between n-type semiconductors having a high impurity concentration. Therefore, for example, if the impurity concentration of the p ⁻ -type connection region 32 deviates from the design value, the reliability of the device decreases, for example, the breakdown voltage of the device decreases. The present specification provides a technique for realizing a device in which reliability is ensured in a vertical semiconductor device.

  The vertical semiconductor device disclosed in this specification includes a first semiconductor region and a second semiconductor region separated by a dielectric extending from the front surface to the back surface of the semiconductor layer. The first semiconductor region has a first conductivity type drain region, a first conductivity type drift region, a second conductivity type base region, and a first conductivity type source region. The drain region is provided on the back surface of the semiconductor layer. The drift region is provided on the surface of the drain region and has a lower impurity concentration than the drain region. The base region is provided on the surface of the drift region. The source region is provided on the surface of the base region, and is separated from the drift region by the base region. The second semiconductor region includes a first conductivity type first region, a first conductivity type second region, a first conductivity type third region, and a second conductivity type fourth region. The first region is provided on the back surface of the semiconductor layer. The second region is provided on the surface of the first region. The third region is provided on the surface of the second region and has a lower impurity concentration than the second region. The fourth region is provided on the surface of the third region. In the semiconductor device, both the drain region and the first region are in contact with the first conductivity type semiconductor substrate. A Zener diode is constituted by the first region and the semiconductor substrate. Note that the source region is connected to the source electrode, the fourth region is connected to a control electrode for controlling on / off of the semiconductor device, and the semiconductor substrate is connected to the drain electrode.

  In the semiconductor device, when a voltage is applied to the control electrode, an electric field is generated by the first conductivity type first region and the first conductivity type second region, and the potential in the second semiconductor region increases. As a result, a channel is formed in the first semiconductor region facing the second semiconductor region via the dielectric. The channel is formed from the front surface to the back surface of the semiconductor layer. The source region and the drain region are connected by a channel, and a current flows in the first semiconductor region. Further, when the voltage application to the control electrode is stopped while the voltage is applied to the drain electrode, the electric field spreads from the second conductivity type base region to the first conductivity type drift region, and the breakdown voltage of the first semiconductor region is reduced. Can be maintained. Similarly, the electric field spreads from the second conductivity type fourth region toward the first conductivity type third region, and the breakdown voltage of the second semiconductor region can be maintained. In the semiconductor device, a Zener diode is constituted by a first conductivity type semiconductor substrate and a second conductivity type first region. Therefore, an electric field is not applied between the semiconductor substrate and the first region when the semiconductor device is turned off (when application of voltage to the control electrode is stopped). Since the semiconductor substrate and the first region constitute a Zener diode, a second conductivity type impurity is introduced into the first region at a high concentration. Since the first region includes a high impurity concentration, the first region is not easily affected by impurities in the semiconductor substrate and the second region. In the semiconductor device, the impurity concentration of the first region can be easily adjusted as designed, and the reliability of the semiconductor device is improved.

Sectional drawing of the semiconductor device of an Example is shown.

  The technical features disclosed in this specification will be summarized below. The items described below have technical usefulness independently.

  The semiconductor device disclosed in this specification is a vertical semiconductor device, and a pair of main electrodes are provided on the front and back surfaces of a semiconductor layer. The semiconductor layer may be provided on the surface of the semiconductor substrate. In this case, the semiconductor layer and the semiconductor substrate can be combined and regarded as one semiconductor layer. The material of the semiconductor layer and the semiconductor substrate may be silicon or a compound semiconductor (silicon carbide, gallium nitride, gallium arsenide, etc.).

A dielectric that extends from the front surface to the back surface of the semiconductor layer is provided in the semiconductor layer. The semiconductor layer is separated into a first semiconductor region and a second semiconductor region by a dielectric. The dielectric may extend from the front surface to the back surface of the semiconductor layer. The dielectric may be filled in a trench formed in the semiconductor layer. An example of the dielectric is an oxide film (for example, SiO ₂ ). The thickness of the dielectric (the distance between the surface in contact with the first semiconductor region and the surface in contact with the second semiconductor region) may be 10 to 200 nm.

  The first semiconductor region includes a first conductivity type drain region, a first conductivity type drift region, a second conductivity type base region, and a first conductivity type source region. The drain region is provided on the back surface of the first semiconductor region. The drift region is provided on the surface of the drain region. The drift region has a lower impurity concentration than the drain region. The base region is provided on the surface of the drift region. The source region is provided on the surface of the base region. The source region is separated from the drift region by the base region. The source region is connected to the source electrode. Note that the source region may be provided over the entire surface of the base region or may be provided in part. In the case where the source region is provided on a part of the surface of the base region, a contact region of the second conductivity type may be provided on the surface of the base region. The impurity concentration of the contact region may be higher than that of the base region. Both the source region and the contact region may be electrically connected to the source electrode. A part of the base region may be exposed on the surface of the semiconductor layer. That is, the base region may have a surface on which neither the source region nor the contact region is formed.

The semiconductor device may be an n-type semiconductor device or a p-type semiconductor device. In the case of an n-type semiconductor device, in the first semiconductor region, the n-type drain region has an impurity concentration adjusted to 1 × 10 ¹⁹ to 1 × 10 ²³ cm ⁻³ and has a thickness (the front and back surfaces of the semiconductor layer). May be adjusted to 0.5 to 1.0 μm. The n-type drift region has an impurity concentration adjusted to 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻³ and a thickness adjusted to 5 to 200 μm. The p-type base region may have an impurity concentration adjusted to 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ and a thickness adjusted to 1.0 to 10 μm. The n-type source region has an impurity concentration adjusted to 1 × 10 ¹⁹ to 1 × 10 ²³ cm ⁻³ and a thickness adjusted to 0.5 to 2.0 μm. The p-type contact region has an impurity concentration adjusted to 1 × 10 ¹⁹ to 1 × 10 ²³ cm ⁻³ and a thickness adjusted to 0.5 to 2.0 μm.

  The second semiconductor region includes a first conductivity type first region, a first conductivity type second region, a first conductivity type third region, and a second conductivity type fourth region. The first region is provided on the entire back surface of the second semiconductor region. The second region is provided on the surface of the first region. The third region is provided on the surface of the second region. The third region has a lower impurity concentration than the second region. The fourth region is provided on the surface of the third region. The fourth region is connected to a control electrode that controls on / off of the semiconductor device. A fifth region of the second conductivity type may be provided on the surface of the fourth region. The impurity concentration of the fifth region may be higher than that of the fourth region. In this case, the fourth region is connected to the control electrode via the fifth region.

When the semiconductor device is an n-type semiconductor device, in the second semiconductor region, the p-type first region has an impurity concentration adjusted to 1 × 10 ²¹ to 1 × 10 ²³ cm ⁻³ and a thickness of 0. It may be adjusted to 5 to 1.0 μm. The n-type second region may have an impurity concentration adjusted to 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ and a thickness adjusted to 0.5 to 2.0 μm. The n-type third region may have an impurity concentration adjusted to 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻³ and a thickness adjusted to 5 to 200 μm. The p-type fourth region may have an impurity concentration adjusted to 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ and a thickness adjusted to 1.0 to 10 μm. The p-type fifth region may have an impurity concentration adjusted to 1 × 10 ¹⁹ to 1 × 10 ²³ cm ⁻³ and a thickness adjusted to 0.5 to 2.0 μm.

The semiconductor layer is provided on the surface of a first conductivity type semiconductor substrate (in the case of an n-type semiconductor device, an n-type semiconductor substrate). The back surface of the semiconductor layer is in contact with the surface of the semiconductor substrate. That is, both the first conductivity type drain region and the second conductivity type first region are in contact with the first conductivity type semiconductor substrate. As described above, the first region is provided on the entire back surface of the second semiconductor region. Therefore, the first conductivity type semiconductor substrate and the first conductivity type second region are separated by the second conductivity type first region. The above-described dielectric may extend from the surface of the semiconductor layer to the bonding surface between the semiconductor layer and the semiconductor substrate. Alternatively, the dielectric may penetrate through the semiconductor layer and extend into the semiconductor substrate. After each region containing impurities is formed in the semiconductor layer, the semiconductor layer and the semiconductor substrate may be bonded. Alternatively, the semiconductor layer may be a crystal grown on the surface of the semiconductor substrate. In this case, the semiconductor layer and the semiconductor substrate can be combined and regarded as one semiconductor layer. In the case of an n-type semiconductor device, the n-type semiconductor substrate has an impurity concentration adjusted to 1 × 10 ²¹ to 1 × 10 ²³ cm ⁻³ and a thickness adjusted to 100 to 500 μm. As described above, the impurity concentration of the first region may be adjusted to 1 × 10 ²¹ to 1 × 10 ²³ cm ⁻³ . That is, the first region and the semiconductor substrate may be doped with impurities so as to be in a degenerate semiconductor state. A Zener diode is constituted by the first region and the semiconductor substrate. The back surface of the semiconductor substrate is connected to the drain electrode.

  The impurity concentration of the drift region and the third region may be equal. The distance from the back surface of the semiconductor layer to the end portion of the drift region on the semiconductor layer surface side may be equal to the distance from the back surface of the semiconductor layer to the end portion of the third region on the semiconductor layer surface side. That is, the distance from the back surface of the semiconductor layer to the end of the base region on the back side of the semiconductor layer may be equal to the distance from the back surface of the semiconductor layer to the end of the fourth region on the surface side of the semiconductor layer. The impurity concentration of the base region and the fourth region may be equal. The base region and the fourth region may have the same thickness. Further, the impurity concentration of the contact region and the fifth region may be equal. The contact region and the fifth region may have the same thickness. In such a case, the drift region and the third region, the base region and the fourth region, and the contact region and the fifth region can be formed simultaneously. After forming a structure corresponding to the drift region, the base region, and the contact region in the semiconductor layer, a dielectric is formed in the semiconductor layer to divide the semiconductor layer, so that one of the divided regions is the drift region, the base region, and It becomes a contact region, and the other becomes a third region, a fourth region, and a fifth region.

The semiconductor device 100 will be described with reference to FIG. The semiconductor device 100 includes a semiconductor substrate 4, a semiconductor layer 50, a drain electrode 2, a source electrode 22, and a gate electrode 16. The drain electrode 2 is provided on the back surface of the n ⁺ type semiconductor substrate 4, and the semiconductor layer 50 is provided on the front surface. The material of the drain electrode 2 is aluminum (Al). The drain electrode 2 is electrically connected to the semiconductor substrate 4. The material of the semiconductor substrate 4 and the semiconductor layer 50 is silicon. The semiconductor substrate 4 contains phosphorus (P) as an n-type impurity. The impurity concentration of the semiconductor substrate 4 is 1 × 10 ²¹ to 1 × 10 ²³ cm ⁻³ and the thickness is 100 to 500 μm. A source electrode 22 and a gate electrode 16 are provided on the surface of the semiconductor layer 50. The semiconductor device 100 is a vertical transistor. The material of the source electrode 22 is aluminum, and the material of the gate electrode 16 is polycrystalline silicon. The gate electrode 16 is an example of a control electrode described in the claims.

A silicon oxide (SiO ₂ ) film 18 extends from the front surface to the back surface of the semiconductor layer 50. The semiconductor layer 50 is separated into a first semiconductor region 50 a and a second semiconductor region 50 b by the silicon oxide film 18. The thickness t5 of the silicon oxide film 18 is 10 to 200 nm. The silicon oxide film 18 is an example of a dielectric described in the claims. The first semiconductor region 50 a includes an n ⁺ -type drain region 30, an n-type drift region 28, a p-type base region 26, an n ⁺ -type source region 20, and a p ⁺ -type base contact region 24. I have. The drain region 30 is formed by ion-implanting phosphorus into the back surface of the semiconductor layer 50 (first semiconductor region 50a). The drain region 30 is in contact with the silicon oxide film 18. The drain region 30 has an impurity concentration of 1 × 10 ¹⁹ to 1 × 10 ²³ cm ⁻³ and a thickness of 0.5 to 1.0 μm. The base region 26 is formed by ion-implanting boron (B) into the surface of the semiconductor layer 50. The impurity concentration of the base region 26 is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ and the thickness is 1.0 to 10 μm. By forming the drain region 30 on the back surface of the semiconductor layer 50 and forming the base region 26 on the surface, the drift region 28 is provided on the surface of the drain region 30, and the base region 26 is provided on the surface of the drift region 28.

The source region 20 is formed by ion implantation of phosphorus into a part of the surface of the base region 26. The source region 20 is in contact with the silicon oxide film 18. Note that the source region 20 does not reach the back surface of the base region 26. Therefore, the source region 20 is separated from the drift region 28 by the base region 26. The impurity concentration of the source region 20 is 1 × 10 ¹⁹ to 1 × 10 ²³ cm ⁻³ and the thickness is 0.5 to 2.0 μm. The base contact region 24 is formed by ion implantation of boron at a position different from the source region 20 on the surface of the base region 26. The source region 20 and the base contact region 24 are electrically connected to the source electrode 22. The contact resistance between the source electrode 22 and the base region 26 is reduced by the base contact region 24. The impurity concentration of the base contact is 1 × 10 ¹⁹ to 1 × 10 ²³ cm ⁻³ and the thickness is 0.5 to 2.0 μm.

The drift region 28 contains phosphorus as an impurity. The drift region 28 is a remaining portion in which the drain region 30, the base region 26, the source region 20, and the base contact region 24 are formed in the semiconductor layer 50. Therefore, the impurity concentration of the drift region 28 is lower than the impurity concentration of the drain region. The impurity concentration of the drift region 28 is 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻³ and the thickness is 5 to 200 μm. The drift region 28 and the base region 26 are also in contact with the silicon oxide film 18.

The second semiconductor region 50b includes a p ⁺ -type first region 6, an n ⁺ -type second region 8, an n-type third region 10, a p-type fourth region 12, and a p ⁺ -type first region. 5 regions 14 are provided. The first region 6 and the second region 8 are provided on the back surface of the semiconductor layer 50 (second semiconductor region 50b). In the first region 6 and the second region 8, phosphorus is ion-implanted into the back surface of the semiconductor layer 50 to form the second region 8, and then boron is ion-implanted into the back surface of the semiconductor layer 50 shallower than the second region 8. Formed by. As a result, the first region 6 is formed on the back surface of the semiconductor layer 50, and the second region 8 is formed on the surface of the first region 6. The first region 6 and the second region 8 are in contact with the silicon oxide film 18. The impurity concentration of the first region 6 is 1 × 10 ²¹ to 1 × 10 ²³ cm ⁻³ and the thickness is 0.5 to 1.0 μm. The impurity concentration of the second region is 1 × 10 ¹⁸ to 1 × 10 ²¹ cm ⁻³ and the thickness is 0.5 to 2.0 μm.

The fourth region 12 is formed by implanting boron into the surface of the semiconductor layer 50. The impurity concentration of the fourth region 12 is 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ and the thickness is 1.0 to 10 μm. The fifth region 14 is formed by ion-implanting boron into the surface of the fourth region 12. The impurity concentration of the fifth region 14 is 1 × 10 ¹⁹ to 1 × 10 ²³ cm ⁻³ and the thickness is 0.5 to 2.0 μm. The impurity concentration of the fifth region 14 is higher than the impurity concentration of the fourth region 12. By providing the fifth region 14, the contact resistance between the gate electrode 16 and the fourth region 12 is reduced. The third region 10 contains phosphorus as an impurity. The third region 10 is a remaining portion in which the first region 6, the second region 8, the fourth region 12, and the fifth region are formed in the semiconductor layer 50. Therefore, the impurity concentration of the third region 10 is lower than the impurity concentration of the second region 8. The impurity concentration of the third region 10 is 1 × 10 ¹³ to 1 × 10 ¹⁶ cm ⁻³ and the thickness is 5 to 200 μm.

  The base contact region 24 and the fifth region 14 are formed simultaneously. For this reason, the base contact region 24 and the fifth region 14 have the same thickness t1. In other words, the thickness t1 from the surface of the semiconductor layer 50 to the end portions of the base contact region 24 and the fifth region 14 on the back surface side of the semiconductor layer 50 is equal. Further, the base region 26 and the fourth region 12 are also formed at the same time. The base region 26 and the fourth region 12 have the same thickness t2. In other words, the thickness t4 from the surface of the semiconductor layer 50 to the ends of the base region 26 and the fourth region 12 on the back side of the semiconductor layer 50 is equal. Or thickness t3 from the back surface of the semiconductor layer 50 to the edge part of the semiconductor region 50 back surface side of the base area | region 26 and the 4th area | region 12 is equal. In the semiconductor device, after each semiconductor region is formed in the semiconductor layer 50, a trench extending from the front surface to the back surface of the semiconductor layer 50 is formed, and the trench is filled with silicon oxide, thereby being separated by the silicon oxide film 18. A first semiconductor region 50a and a second semiconductor region 50b are formed.

In the semiconductor device 100, both the n ⁺ type drain region 30 and the p ⁺ type first region 6 are in contact with the n ⁺ type semiconductor substrate 4. Therefore, the drain region 30 and the semiconductor substrate 4 are connected to a low resistance. Further, a pn diode is formed by the first region 6 and the semiconductor substrate 4. As described above, the p-type impurity concentration of the first region 6 is 1 × 10 ²¹ to 1 × 10 ²³ cm ⁻³ , and the n-type impurity concentration of the semiconductor substrate 4 is 1 × 10 ²¹ to 1 × 10 ²³ cm ^{−. 3} . Both impurity concentrations are degenerate semiconductor levels. Therefore, the first region 6 and the semiconductor substrate 4 constitute a Zener diode.

  In the semiconductor device 100, the drain electrode 2 is connected to the high potential side of the power source, the source electrode 22 is connected to the low potential side (for example, ground potential) of the power source, and the gate electrode 16 is connected to a gate drive circuit (not shown). Connected. The gate electrode 16 is a control electrode that controls on / off of the semiconductor device 100. When an on voltage is applied to the gate electrode 16, a reverse bias is applied to the pn junction between the first region 6 and the second region 8, an electric field is applied to the first region 6 and the second region 8, and the second semiconductor region 50b. The potential of (especially the third region 10) increases. As a result, an electron channel is formed at a position facing the second semiconductor region 50b through the silicon oxide film 18 of the first semiconductor region 50a. Source region 20 and drain region 30 are connected by a channel. Electrons move from the source region 20 to the drain region 30, and a current flows in the first semiconductor region 50a. In the semiconductor device 100, the channel is formed not only in the base region 26 but also in the drift region 28. Therefore, the semiconductor device 100 can reduce the movement resistance and suppress power loss.

  When the application of the on-voltage to the gate electrode 16 is stopped, the channel formed in the first semiconductor region 50a disappears. In the first semiconductor region 50 a, the n-type source region 20 and the n-type drift region 28 are separated by the p-type base region 26. Therefore, no current flows between the drain electrode 2 and the source electrode 22. When no on-voltage is applied to the gate electrode 16, the electric field spreads (depletes) from the base region 26 toward the drift region 28, and the breakdown voltage of the first semiconductor region 50a is ensured. Similarly, the electric field spreads from the fourth region 12 toward the third region 10, and the breakdown voltage of the second semiconductor region 50b is secured. As described above, the impurity concentrations of the base region 26 and the fourth region 12 are equal, and the impurity concentrations of the drift region 28 and the third region 10 are equal. For this reason, the first semiconductor region 50a and the second semiconductor region 50b have the same breakdown voltage.

  In the second semiconductor region 50 b, a reverse bias is applied to the pn junction between the first region 6 and the semiconductor substrate 4 when the semiconductor device 100 is in the off state (when no on-voltage is applied to the gate electrode 16). However, as described above, the first region 6 and the semiconductor substrate 4 constitute a Zener diode. Therefore, when the semiconductor device 100 is in the off state, both are substantially short-circuited and have the same potential. A strong electric field is not generated at the bonding interface between the first region 6 and the semiconductor substrate 4. If a strong electric field is generated at the junction interface between the first region 6 and the semiconductor substrate 4, the breakdown voltage of the second semiconductor region 50 b decreases, and as a result, the breakdown voltage of the semiconductor device 100 decreases.

As described above, in the semiconductor device 100, the first region 6 and the semiconductor substrate 4 constitute a Zener diode by increasing the impurity concentration of the first region 6. Thereby, when the semiconductor device 100 is in the OFF state, the first region 6 and the semiconductor substrate 4 are substantially short-circuited, and the breakdown voltage of the semiconductor device 100 is maintained. For example, as in Patent Document 1, even if the first region of low impurity concentration p-type is provided between the second region of the semiconductor substrate and the n ⁺ -type n ⁺ -type semiconductor substrate when the semiconductor device is off And the first region can be substantially short-circuited. However, it is difficult to form a low-concentration p-type semiconductor (first region) as designed between high-concentration n-type semiconductors (semiconductor substrate, second region). If the impurity concentration of the p-type semiconductor (first region) deviates from the design value, problems such as a breakdown voltage lowering than the design value occur, and the reliability of the semiconductor device decreases. The semiconductor device 100, since the provision of the first region 6 of high impurity concentration p-type during the n ⁺ -type semiconductor substrate 4 and the n ⁺ -type second region 8, the design value of the impurity concentration of the first region 6 Therefore, the reliability of the apparatus can be ensured.

  In the above embodiment, each region is formed in the semiconductor layer by ion implantation into the semiconductor layer, and then an insulating film (silicon oxide film) is formed in the semiconductor layer, and the first semiconductor region and the second semiconductor region are formed. The example which manufactures the semiconductor device 100 provided with this was demonstrated. However, the semiconductor device 100 including the first semiconductor region and the second semiconductor region may be formed by growing a semiconductor layer containing a predetermined amount of impurities on the semiconductor substrate and then forming an insulating film in the semiconductor layer. Alternatively, a semiconductor layer including a structure corresponding to one of the first semiconductor region and the second semiconductor region is formed on the semiconductor substrate, a trench extending from the front surface to the back surface is formed in a part of the semiconductor layer, and the side surface of the trench is oxidized. Then, a structure corresponding to the other of the first semiconductor region and the second semiconductor region may be formed in the trench.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

4: semiconductor substrate 6: first region 8: second region 10: third region 12: fourth region 15: fifth region 18: dielectric 20: source region 26: base region 28: drift region 30: drain region 50 : Semiconductor layer 50a: first semiconductor region 50b: second semiconductor region 100: semiconductor device

Claims (3)

A vertical semiconductor device comprising a first semiconductor region and a second semiconductor region separated by a dielectric extending from the front surface to the back surface of the semiconductor layer;
The first semiconductor region is
A drain region of a first conductivity type provided on the back surface of the semiconductor layer;
A drift region of a first conductivity type provided on a surface of the drain region and having an impurity concentration lower than that of the drain region;
A base region of a second conductivity type provided on the surface of the drift region;
A source region of a first conductivity type provided on a surface of the base region and separated from the drift region by the base region;
The second semiconductor region is
A first region of a second conductivity type provided on the back surface of the semiconductor layer;
A second region of the first conductivity type provided on the surface of the first region;
A third region of a first conductivity type provided on a surface of the second region and having an impurity concentration lower than that of the second region;
A second region of the second conductivity type provided on the surface of the third region,
Both the drain region and the first region are in contact with the semiconductor substrate of the first conductivity type,
A Zener diode is constituted by the first region and the semiconductor substrate,
The source region is connected to a source electrode;
The fourth region is connected to a control electrode for controlling on / off of the semiconductor device,
A semiconductor device, wherein the semiconductor substrate is connected to a drain electrode.   2. The semiconductor device according to claim 1, wherein the drift region and the third region have the same impurity concentration, and the base region and the fourth region have the same impurity concentration.   The thickness from the surface of the said semiconductor layer to the edge part by the side of the semiconductor layer back surface of the said base area is equal to the thickness from the surface of the said semiconductor layer to the edge part by the side of the semiconductor layer back surface of the said 4th area | region. Semiconductor device.

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