JP2017183656A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2017183656A
JP2017183656A JP2016072923A JP2016072923A JP2017183656A JP 2017183656 A JP2017183656 A JP 2017183656A JP 2016072923 A JP2016072923 A JP 2016072923A JP 2016072923 A JP2016072923 A JP 2016072923A JP 2017183656 A JP2017183656 A JP 2017183656A
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resin
semiconductor element
slit
semiconductor
bent portion
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JP6493277B2 (en
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宗彦 増谷
Munehiko Masutani
宗彦 増谷
繁和 東元
Shigekazu Higashimoto
繁和 東元
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Toyota Industries Corp
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Toyota Industries Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To inhibit a resin crack.SOLUTION: In a semiconductor device, a first slit 26 is formed in a first section wall 23 and a vertical distance H1 from an exposed surface 25e of a resin 25 to a plane part 18e is made smaller than a vertical distance H2 from the exposed surface 25e to a bottom end 26e of the first slit 26. When a heat dissipation member 11 and the resin 25 expand due to heat generation and the like of a semiconductor element 12, the resin 25 pushes the first section wall 23, but deformation of the first section wall 23 is allowed by forming dimensions of the first slit 26 and stress applied to the resin 25 is alleviated. Accordingly, an intensity of the resin 25 is ensured and a crack is unlikely to occur.SELECTED DRAWING: Figure 2

Description

本発明は、半導体装置に関する。   The present invention relates to a semiconductor device.

半導体装置は、金属製の放熱部材（ヒートシンク）と、半導体素子及び基板を有するとともに放熱部材の面に搭載される半導体モジュールと、放熱部材に取り付けられるとともに複数の半導体モジュールを収容する樹脂製のケースとを備えている。ケースは、複数の基板の周囲を囲む周壁と、周壁の内側を複数の空間に区画する区画壁とを有している。空間には、半導体モジュールが少なくとも一つ収容されている。そして、例えば特許文献１のように、空間には、半導体モジュールを異物等から保護するために、半導体モジュールを覆う樹脂が封止されている。   The semiconductor device includes a metal heat dissipation member (heat sink), a semiconductor module having a semiconductor element and a substrate and mounted on the surface of the heat dissipation member, and a resin case attached to the heat dissipation member and accommodating a plurality of semiconductor modules And. The case has a peripheral wall that surrounds the periphery of the plurality of substrates, and a partition wall that partitions the inside of the peripheral wall into a plurality of spaces. At least one semiconductor module is accommodated in the space. For example, as in Patent Document 1, a resin that covers the semiconductor module is sealed in the space in order to protect the semiconductor module from foreign matter or the like.

特許第５６３８６２３号公報Japanese Patent No. 5638623

半導体素子の発熱等によって放熱部材及び樹脂が膨脹すると、半導体装置において全体的に反りが生じる。すると、樹脂に応力が加わって樹脂に割れが生じてしまう虞がある。
本発明は、上記課題を解決するためになされたものであって、その目的は、樹脂の割れを抑制することができる半導体装置を提供することにある。 When the heat dissipating member and the resin expand due to heat generation of the semiconductor element, the entire semiconductor device is warped. Then, stress may be applied to the resin and the resin may be cracked.
The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of suppressing resin cracking.

上記課題を解決する半導体装置は、金属製の放熱部材と、第１の半導体素子と第２の半導体素子と基板とを備え、前記第１の半導体素子の下面電極が前記基板のパターンにベアチップ実装されるとともに前記第２の半導体素子の下面電極が前記基板のパターンにベアチップ実装されてなり、前記放熱部材の面に搭載される半導体モジュールと、前記基板の周囲を囲む周壁と、前記周壁の内側において複数の空間に区画する第１の区画壁とを有し、前記放熱部材の面に固定される樹脂製のケースと、を有し、前記空間に前記半導体モジュールが少なくとも一つ収容されており、前記空間に前記半導体モジュールを覆う樹脂が封止されている半導体装置であって、前記第１の区画壁の上面には第１のスリットが設けられており、前記第１の半導体素子の上面電極と前記第２の半導体素子の上面電極とは板状の導電部材によって互いに電気的に接続されており、前記導電部材は前記第１の半導体素子の上面電極に接合される第１の接合部と、前記第２の半導体素子の上面電極に接合される第２の接合部と、前記第１の接合部から延設されて前記第１の半導体素子から離れる方向に屈曲する第１の屈曲部と、前記第２の接合部から延設されて前記第２の半導体素子から離れる方向に屈曲する第２の屈曲部と、前記第１の屈曲部から前記第２の屈曲部まで延設される平面状の平面部とを有するとともに、前記樹脂によって覆われており、前記樹脂の露出面から前記平面部までの上下方向の距離は前記露出面から前記第１のスリットの下端までの上下方向の距離よりも小さい。   A semiconductor device that solves the above-described problem includes a metal heat dissipating member, a first semiconductor element, a second semiconductor element, and a substrate, and the lower surface electrode of the first semiconductor element is bare-chip mounted on the pattern of the substrate In addition, the bottom electrode of the second semiconductor element is bare-chip mounted on the pattern of the substrate, the semiconductor module is mounted on the surface of the heat dissipation member, the peripheral wall surrounding the periphery of the substrate, the inner side of the peripheral wall And a resin case fixed to the surface of the heat dissipating member, and at least one of the semiconductor modules is accommodated in the space. A semiconductor device in which the resin covering the semiconductor module is sealed in the space, wherein a first slit is provided on an upper surface of the first partition wall, and the first semiconductor The upper electrode of the child and the upper electrode of the second semiconductor element are electrically connected to each other by a plate-like conductive member, and the conductive member is joined to the upper electrode of the first semiconductor element. , A second joint joined to the upper surface electrode of the second semiconductor element, and a first extension extending from the first joint and bending away from the first semiconductor element. A bent portion, a second bent portion extending from the second bonding portion and bent in a direction away from the second semiconductor element, and extending from the first bent portion to the second bent portion. And a flat plane portion provided and covered with the resin, and a vertical distance from the exposed surface of the resin to the planar portion is from the exposed surface to the lower end of the first slit. It is smaller than the distance in the vertical direction.

半導体素子の発熱等によって放熱部材及び樹脂が膨張すると、樹脂が第１の区画壁を押圧する。このとき、樹脂の露出面から平面部までの上下方向の距離は樹脂の露出面から第１のスリットの下端までの上下方向の距離よりも小さいため、第１の区画壁が、第１のスリットが形成された分だけ変形が許容され、この第１の区画壁の変形によって、樹脂に加わる応力が緩和される。よって、樹脂の割れを抑制することができる。   When the heat radiating member and the resin expand due to heat generated by the semiconductor element, the resin presses the first partition wall. At this time, since the distance in the vertical direction from the exposed surface of the resin to the flat portion is smaller than the distance in the vertical direction from the exposed surface of the resin to the lower end of the first slit, the first partition wall is the first slit. The deformation is allowed by the amount formed, and the stress applied to the resin is relieved by the deformation of the first partition wall. Therefore, cracking of the resin can be suppressed.

この発明によれば、樹脂の割れを抑制することができる。   According to this invention, cracking of the resin can be suppressed.

実施形態における半導体装置を示す斜視図。The perspective view which shows the semiconductor device in embodiment. 図１における２−２線断面図。FIG. 2 is a sectional view taken along line 2-2 in FIG. 1. 導電部材と半導体素子との関係を説明する斜視図。The perspective view explaining the relationship between a conductive member and a semiconductor element. 別の実施形態における半導体装置の一部分を示す斜視図。The perspective view which shows a part of semiconductor device in another embodiment. 別の実施形態における半導体装置の断面図。Sectional drawing of the semiconductor device in another embodiment. 別の実施形態における半導体装置を示す斜視図。The perspective view which shows the semiconductor device in another embodiment.

以下、半導体装置を具体化した一実施形態を図１〜図３にしたがって説明する。
図１及び図２に示すように、半導体装置１０は、金属製（本実施形態ではアルミニウム製）の放熱部材１１（ヒートシンク）と、放熱部材１１の面１１ａに搭載される半導体モジュール４０と、半導体モジュール４０が収容される樹脂製のケース２０とを備えている。 Hereinafter, an embodiment embodying a semiconductor device will be described with reference to FIGS.
As shown in FIGS. 1 and 2, the semiconductor device 10 includes a metal (in this embodiment, aluminum) heat radiating member 11 (heat sink), a semiconductor module 40 mounted on the surface 11a of the heat radiating member 11, and a semiconductor. And a resin case 20 in which the module 40 is accommodated.

半導体モジュール４０は、例えばＩＧＢＴやダイオード等の半導体素子１２と基板１３と導電部材１８とを備えている。半導体モジュール４０は、４つの半導体素子１２の下面電極１２ａが基板１３のパターンにベアチップ実装されてなる。半導体素子１２の上面電極１２ｂには導電部材１８が接続されている。   The semiconductor module 40 includes a semiconductor element 12 such as an IGBT or a diode, a substrate 13, and a conductive member 18. In the semiconductor module 40, the bottom electrodes 12 a of the four semiconductor elements 12 are bare-chip mounted on the pattern of the substrate 13. A conductive member 18 is connected to the upper surface electrode 12 b of the semiconductor element 12.

ケース２０は、複数の基板１３（本実施形態では６つ）の周囲を囲む平面視長方形状の周壁２１と、周壁２１の内側において周壁２１の長手方向（図１に示す矢印Ｘ１の方向）に対して複数（本実施形態では三つ）の空間２２に区画する第１の区画壁２３とを有する。空間２２は、平面視において、周壁２１の短手方向（図１に示す矢印Ｙ１の方向）を長手方向とする平面視長四角形状である。第１の区画壁２３は、空間２２の長手方向（周壁２１の短手方向）に沿って延びている。各空間２２には、半導体モジュール４０が二つずつ空間２２の長手方向に並んで収容されている。なお、空間２２には半導体モジュール４０が少なくとも一つ収容されていればよい。   The case 20 includes a peripheral wall 21 having a rectangular shape in plan view that surrounds the periphery of a plurality of substrates 13 (six in this embodiment), and a longitudinal direction of the peripheral wall 21 inside the peripheral wall 21 (in the direction of the arrow X1 shown in FIG. 1). On the other hand, the first partition wall 23 is partitioned into a plurality of (three in this embodiment) spaces 22. The space 22 has a rectangular shape in plan view with the short direction of the peripheral wall 21 (the direction of the arrow Y1 shown in FIG. 1) as the longitudinal direction in plan view. The first partition wall 23 extends along the longitudinal direction of the space 22 (short direction of the peripheral wall 21). In each space 22, two semiconductor modules 40 are accommodated in the longitudinal direction of the space 22. It should be noted that at least one semiconductor module 40 may be accommodated in the space 22.

図２において拡大して示すように、基板１３は、放熱部材１１の面１１ａに接合される金属層１４と、金属層１４における放熱部材１１の面１１ａとは反対側に積層される絶縁層１５と、絶縁層１５における金属層１４とは反対側に積層される配線層１６とを有する。そして、配線層１６における絶縁層１５とは反対側の実装面１６ａに半導体素子１２が実装されている。   As shown in an enlarged view in FIG. 2, the substrate 13 includes a metal layer 14 bonded to the surface 11 a of the heat radiating member 11 and an insulating layer 15 stacked on the opposite side of the metal layer 14 from the surface 11 a of the heat radiating member 11. And a wiring layer 16 laminated on the opposite side of the insulating layer 15 from the metal layer 14. The semiconductor element 12 is mounted on the mounting surface 16 a on the wiring layer 16 opposite to the insulating layer 15.

また、基板１３には、一端が基板１３のパターンを含む配線層１６に接続されるとともに他端が図示しない電源端子及び図示しない負荷に電気的に接続される板状の電極１７が実装されている。電源端子は例えばバッテリの端子である。負荷は例えばモータである。電極１７は、配線層１６に接合される平板状の接合部１７ａと、接合部１７ａから接合部１７ａに対して直交する方向に屈曲して延びるとともに図示しない電源端子及び図示しない負荷に電気的に接続される平板状の端子部１７ｂとを有する。端子部１７ｂは、空間２２から突出している。また、導電部材１８は、４つの半導体素子１２を電気的に接続する。導電部材１８は、各半導体素子１２の上面電極１２ｂに接合されている。なお、導電部材１８は板状である。   The substrate 13 is mounted with a plate-like electrode 17 having one end connected to the wiring layer 16 including the pattern of the substrate 13 and the other end electrically connected to a power supply terminal (not shown) and a load (not shown). Yes. The power supply terminal is, for example, a battery terminal. The load is, for example, a motor. The electrode 17 extends flatly in a direction perpendicular to the joint 17a from the joint 17a, and is electrically connected to a power supply terminal (not shown) and a load (not shown). And a flat terminal portion 17b to be connected. The terminal portion 17 b protrudes from the space 22. The conductive member 18 electrically connects the four semiconductor elements 12. The conductive member 18 is bonded to the upper surface electrode 12 b of each semiconductor element 12. The conductive member 18 has a plate shape.

図３に示すように、導電部材１８は、４つの半導体素子１２のうちの第１の半導体素子１２１の上面電極１２ｂに接合される第１の接合部１８ａと、４つの半導体素子１２のうちの第２の半導体素子１２２の上面電極１２ｂに接合される第２の接合部１８ｂとを有する。また、導電部材１８は、第１の接合部１８ａから延設されて第１の半導体素子１２１から離れる方向に屈曲する第１の屈曲部１８ｃと、第２の接合部１８ｂから延設されて第２の半導体素子１２２から離れる方向に屈曲する第２の屈曲部１８ｄと、第１の屈曲部１８ｃから第２の屈曲部１８ｄまで延設される平面状の平面部１８ｅとを有する。   As shown in FIG. 3, the conductive member 18 includes a first joint 18 a that is joined to the upper surface electrode 12 b of the first semiconductor element 121 of the four semiconductor elements 12, and the conductive member 18 of the four semiconductor elements 12. And a second bonding portion 18b bonded to the upper surface electrode 12b of the second semiconductor element 122. In addition, the conductive member 18 extends from the first joint 18a and bends in a direction away from the first semiconductor element 121, and extends from the second joint 18b. A second bent portion 18d bent in a direction away from the second semiconductor element 122, and a flat planar portion 18e extending from the first bent portion 18c to the second bent portion 18d.

さらに、導電部材１８は、４つの半導体素子１２のうちの第３の半導体素子１２３の上面電極１２ｂに接合される第３の接合部１８ｆと、４つの半導体素子１２のうちの第４の半導体素子１２４の上面電極１２ｂに接合される第４の接合部１８ｇとを有する。また、導電部材１８は、第３の接合部１８ｆから延設されて第３の半導体素子１２３から離れる方向に屈曲する第３の屈曲部１８ｈと、第４の接合部１８ｇから延設されて第４の半導体素子１２４から離れる方向に屈曲する第４の屈曲部１８ｉとを有する。平面部１８ｅは第３の屈曲部１８ｈ及び第４の屈曲部１８ｉまで延設されている。すなわち、平面部１８ｅは、第１の屈曲部１８ｃ、第２の屈曲部１８ｄ、第３の屈曲部１８ｈ及び第４の屈曲部１８ｉそれぞれに連続している。   Further, the conductive member 18 includes a third joint 18 f that is joined to the upper surface electrode 12 b of the third semiconductor element 123 of the four semiconductor elements 12, and a fourth semiconductor element of the four semiconductor elements 12. And a fourth bonding portion 18g bonded to the upper surface electrode 12b. In addition, the conductive member 18 extends from the third joint portion 18f and bends in a direction away from the third semiconductor element 123, and extends from the fourth joint portion 18g. And a fourth bent portion 18 i bent in a direction away from the fourth semiconductor element 124. The flat portion 18e extends to the third bent portion 18h and the fourth bent portion 18i. That is, the plane portion 18e is continuous with the first bent portion 18c, the second bent portion 18d, the third bent portion 18h, and the fourth bent portion 18i.

図２に示すように、各空間２２には、半導体モジュール４０を覆う樹脂２５が封止されている。詳細には、電極１７の接合部１７ａを含む一部、導電部材１８、基板１３及び半導体素子１２が、樹脂２５に覆われている。電極１７の端子部１７ｂを含む他端は樹脂２５から露出している。樹脂２５は、基板１３、半導体素子１２及び導電部材１８を異物等から保護する。樹脂２５は、例えばエポキシ樹脂である。   As shown in FIG. 2, each space 22 is sealed with a resin 25 that covers the semiconductor module 40. Specifically, a part including the joint 17 a of the electrode 17, the conductive member 18, the substrate 13, and the semiconductor element 12 are covered with the resin 25. The other end including the terminal portion 17 b of the electrode 17 is exposed from the resin 25. The resin 25 protects the substrate 13, the semiconductor element 12, and the conductive member 18 from foreign matters and the like. The resin 25 is, for example, an epoxy resin.

各第１の区画壁２３の上面には、第１のスリット２６が形成されている。第１のスリット２６は、第１の区画壁２３における放熱部材１１とは反対側の端面２３ｅから放熱部材１１に向けて凹設されている。また、第１のスリット２６は、平面視すると、空間２２の長手方向に沿って延びている。本実施形態では、第１のスリット２６の内側は空気層である。樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１は露出面２５ｅから第１のスリット２６の下端２６ｅまでの上下方向の距離Ｈ２よりも小さい。   A first slit 26 is formed on the upper surface of each first partition wall 23. The first slit 26 is recessed from the end surface 23 e of the first partition wall 23 opposite to the heat dissipation member 11 toward the heat dissipation member 11. The first slit 26 extends along the longitudinal direction of the space 22 when viewed in plan. In the present embodiment, the inside of the first slit 26 is an air layer. The vertical distance H1 from the exposed surface 25e of the resin 25 to the flat portion 18e is smaller than the vertical distance H2 from the exposed surface 25e to the lower end 26e of the first slit 26.

次に、本実施形態の作用について説明する。
半導体素子１２の発熱等によって放熱部材１１及び樹脂２５が膨脹すると、半導体装置１０において全体的に反りが生じる。そして、放熱部材１１及び樹脂２５が膨張して、樹脂２５が第１の区画壁２３を押圧する。このとき、樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１は露出面２５ｅから第１のスリット２６の下端２６ｅまでの上下方向の距離Ｈ２よりも小さいため、第１の区画壁２３が、第１のスリット２６が形成された分だけ変形が許容され、この第１の区画壁２３の変形によって、樹脂２５に加わる応力が緩和される。よって、樹脂２５の割れが抑制される。例えば、端子部１７ｂの周辺の樹脂２５を起点として樹脂２５に割れが生じ易いが、端子部１７ｂの周辺の樹脂２５を起点とした樹脂２５の割れが抑制される。また、平面部１８ｅを覆う樹脂２５の厚みが薄いため、割れが生じ易いが、この割れが抑制される。 Next, the operation of this embodiment will be described.
When the heat radiating member 11 and the resin 25 expand due to heat generation of the semiconductor element 12, the semiconductor device 10 is warped as a whole. Then, the heat radiating member 11 and the resin 25 expand, and the resin 25 presses the first partition wall 23. At this time, since the vertical distance H1 from the exposed surface 25e of the resin 25 to the flat portion 18e is smaller than the vertical distance H2 from the exposed surface 25e to the lower end 26e of the first slit 26, the first partition wall 23 is allowed to be deformed as much as the first slit 26 is formed, and the stress applied to the resin 25 is relieved by the deformation of the first partition wall 23. Therefore, cracking of the resin 25 is suppressed. For example, the resin 25 is easily cracked starting from the resin 25 around the terminal portion 17b, but the cracking of the resin 25 originating from the resin 25 around the terminal portion 17b is suppressed. Further, since the resin 25 covering the flat portion 18e is thin, cracks are easily generated, but the cracks are suppressed.

上記実施形態では以下の効果を得ることができる。
（１）第１の区画壁２３に第１のスリット２６を形成し、樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１を露出面２５ｅから第１のスリット２６の下端２６ｅまでの上下方向の距離Ｈ２よりも小さくした。半導体素子１２の発熱等によって放熱部材１１及び樹脂２５が膨張すると、樹脂２５が第１の区画壁２３を押圧する。このとき、樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１は露出面２５ｅから第１のスリット２６の下端２６ｅまでの上下方向の距離Ｈ２よりも小さいため、第１の区画壁２３が、第１のスリット２６が形成された分だけ変形が許容され、この第１の区画壁２３の変形によって、樹脂２５に加わる応力が緩和される。よって、樹脂２５の割れを抑制することができる。 In the above embodiment, the following effects can be obtained.
(1) The first slit 26 is formed in the first partition wall 23, and the vertical distance H1 from the exposed surface 25e of the resin 25 to the flat portion 18e is from the exposed surface 25e to the lower end 26e of the first slit 26. It was made smaller than the vertical distance H2. When the heat radiating member 11 and the resin 25 expand due to heat generated by the semiconductor element 12, the resin 25 presses the first partition wall 23. At this time, since the vertical distance H1 from the exposed surface 25e of the resin 25 to the flat portion 18e is smaller than the vertical distance H2 from the exposed surface 25e to the lower end 26e of the first slit 26, the first partition wall 23 is allowed to be deformed as much as the first slit 26 is formed, and the stress applied to the resin 25 is relieved by the deformation of the first partition wall 23. Therefore, cracking of the resin 25 can be suppressed.

（２）平面部１８ｅは第３の屈曲部１８ｈ及び第４の屈曲部１８ｉまで延設している。これによれば、平面部１８ｅの面積が大きくなり、平面部１８ｅを覆う樹脂２５の割れが発生し易いが、樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１は露出面２５ｅから第１のスリット２６の下端２６ｅまでの上下方向の距離Ｈ２よりも小さいため、平面部１８ｅを覆う樹脂２５の割れを抑制することができる。   (2) The flat portion 18e extends to the third bent portion 18h and the fourth bent portion 18i. According to this, the area of the flat surface portion 18e becomes large and the resin 25 covering the flat surface portion 18e is easily cracked. However, the vertical distance H1 from the exposed surface 25e of the resin 25 to the flat surface portion 18e is the exposed surface 25e. Since it is smaller than the vertical distance H2 from the first slit 26 to the lower end 26e of the first slit 26, it is possible to suppress cracking of the resin 25 covering the flat surface portion 18e.

（３）基板１３には、一端が基板１３のパターンに接続されるとともに、他端が樹脂２５から露出する板状の電極１７が実装されている。これによれば、他端が樹脂２５から露出する板状の電極１７が基板１３に実装されていたとしても、露出する電極１７の他端の樹脂２５を起点とした樹脂２５の割れを抑制することができる。特に、端子部１７ｂの周辺の樹脂２５を起点として樹脂２５に割れが生じ易いが、端子部１７ｂの周辺の樹脂２５を起点とした樹脂２５の割れを抑制することができる。   (3) The substrate 13 is mounted with a plate-like electrode 17 having one end connected to the pattern of the substrate 13 and the other end exposed from the resin 25. According to this, even if the plate-like electrode 17 whose other end is exposed from the resin 25 is mounted on the substrate 13, cracking of the resin 25 starting from the resin 25 at the other end of the exposed electrode 17 is suppressed. be able to. In particular, the resin 25 is likely to crack starting from the resin 25 around the terminal portion 17b, but the resin 25 cracking starting from the resin 25 around the terminal portion 17b can be suppressed.

なお、上記実施形態は以下のように変更してもよい。
○ 図４に示すように、第１の区画壁２３における第１のスリット２６とは異なる部位に、隣り合う空間２２同士を連通する開口部２３ｈが形成されており、開口部２３ｈの少なくとも一部が樹脂２５で覆われていてもよい。第１の区画壁２３には、第１のスリット２６が二つ形成されている。両第１のスリット２６は、平面視すると、空間２２の長手方向に沿って延びている。両第１のスリット２６は、空間２２の長手方向に沿って配置されている。開口部２３ｈは、第１の区画壁２３における両第１のスリット２６の間に配置されるとともに、端面２３ｅから凹設されている。これによれば、各空間２２に封止される樹脂２５が固化する前では、樹脂２５が開口部２３ｈを介して隣り合う空間２２を行き来できるようになるため、各空間２２に封止される樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１のばらつきを低減させることができる。 In addition, you may change the said embodiment as follows.
As shown in FIG. 4, an opening 23 h that connects the adjacent spaces 22 is formed in a portion different from the first slit 26 in the first partition wall 23, and at least a part of the opening 23 h May be covered with the resin 25. Two first slits 26 are formed in the first partition wall 23. Both the first slits 26 extend along the longitudinal direction of the space 22 in plan view. Both first slits 26 are arranged along the longitudinal direction of the space 22. The opening 23h is disposed between the first slits 26 in the first partition wall 23 and is recessed from the end surface 23e. According to this, before the resin 25 sealed in each space 22 is solidified, the resin 25 can go back and forth between the adjacent spaces 22 through the opening 23h, and thus is sealed in each space 22. Variation in the distance H1 in the vertical direction from the exposed surface 25e of the resin 25 to the flat portion 18e can be reduced.

○ 図５に示すように、周壁２１に、第２のスリット２７を形成してもよい。第２のスリット２７は、周壁２１における放熱部材１１とは反対側の端面２１ｅから放熱部材１１に向けて凹設されている。樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１は露出面２５ｅから第２のスリット２７の下端２７ｅまでの上下方向の距離Ｈ３よりも小さい。半導体素子１２の発熱等によって放熱部材１１及び樹脂２５が膨脹すると、樹脂２５が周壁２１を押圧する。このとき、樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１は露出面２５ｅから第２のスリット２７の下端２７ｅまでの上下方向の距離Ｈ３よりも小さいため、周壁２１が、第２のスリット２７が形成された分だけ変形が許容され、この周壁２１の変形によって、樹脂２５に加わる応力が緩和される。よって、樹脂２５の割れをさらに抑制することができる。   As shown in FIG. 5, the second slit 27 may be formed in the peripheral wall 21. The second slit 27 is recessed from the end surface 21 e of the peripheral wall 21 opposite to the heat dissipation member 11 toward the heat dissipation member 11. The vertical distance H1 from the exposed surface 25e of the resin 25 to the flat portion 18e is smaller than the vertical distance H3 from the exposed surface 25e to the lower end 27e of the second slit 27. When the heat radiating member 11 and the resin 25 are expanded due to heat generated by the semiconductor element 12, the resin 25 presses the peripheral wall 21. At this time, since the vertical distance H1 from the exposed surface 25e of the resin 25 to the flat surface portion 18e is smaller than the vertical distance H3 from the exposed surface 25e to the lower end 27e of the second slit 27, the peripheral wall 21 is The deformation is allowed by the amount of the two slits 27 formed, and the stress applied to the resin 25 is relieved by the deformation of the peripheral wall 21. Therefore, cracking of the resin 25 can be further suppressed.

○ 図６に示すように、周壁２１の内側において周壁２１の短手方向に対して複数（図６の実施形態では二つ）の空間３２に区画する第２の区画壁３３を備えてもよい。第２の区画壁３３の外底面と放熱部材１１の面１１ａとは離間している。そして、第２の区画壁３３の外底面と放熱部材１１の面１１ａとの間を、周壁２１の短手方向で隣り合う半導体モジュール４０同士を電気的に接続する接続端子１９が通過している。周壁２１の短手方向で隣り合う空間３２に封止される樹脂２５同士は、第２の区画壁３３の外底面と放熱部材１１の面１１ａとの間を介して繋がっている。なお、図６において、樹脂２５の図示を説明の都合上省略している。第２の区画壁３３には、第１の区画壁２３と同様な第３のスリット２８が形成されている。樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１は露出面２５ｅから第３のスリット２８の下端までの上下方向の距離よりも小さい。   As shown in FIG. 6, a second partition wall 33 that partitions into a plurality of (two in the embodiment of FIG. 6) spaces 32 with respect to the short direction of the peripheral wall 21 inside the peripheral wall 21 may be provided. . The outer bottom surface of the second partition wall 33 and the surface 11a of the heat dissipation member 11 are separated from each other. And the connection terminal 19 which electrically connects the semiconductor modules 40 adjacent in the transversal direction of the surrounding wall 21 passes between the outer bottom face of the 2nd partition wall 33 and the surface 11a of the thermal radiation member 11. . The resins 25 sealed in the space 32 adjacent in the short direction of the peripheral wall 21 are connected via the outer bottom surface of the second partition wall 33 and the surface 11 a of the heat radiating member 11. In FIG. 6, illustration of the resin 25 is omitted for convenience of explanation. In the second partition wall 33, a third slit 28 similar to the first partition wall 23 is formed. The vertical distance H1 from the exposed surface 25e of the resin 25 to the flat portion 18e is smaller than the vertical distance from the exposed surface 25e to the lower end of the third slit 28.

これによれば、樹脂２５を小分けすることができる。そして、小分けされた樹脂２５が膨張して、樹脂２５が第２の区画壁３３を押圧する。このとき、樹脂２５の露出面２５ｅから平面部１８ｅまでの上下方向の距離Ｈ１は露出面２５ｅから第３のスリット２８の下端までの上下方向の距離よりも小さいため、第２の区画壁３３が、第３のスリット２８が形成された分だけ変形が許容され、この第２の区画壁３３の変形によって、樹脂２５に加わる応力が緩和される。   According to this, the resin 25 can be subdivided. Then, the subdivided resin 25 expands, and the resin 25 presses the second partition wall 33. At this time, since the vertical distance H1 from the exposed surface 25e of the resin 25 to the flat surface portion 18e is smaller than the vertical distance from the exposed surface 25e to the lower end of the third slit 28, the second partition wall 33 is The deformation is allowed as much as the third slit 28 is formed, and the stress applied to the resin 25 is relieved by the deformation of the second partition wall 33.

○ 実施形態において、半導体装置１０が電極１７を備えていない構成であってもよい。
○ 実施形態において、第１のスリット２６内に液体や固体等が入れられていてもよい。例えば、固体の場合、低弾性のスポンジやゴム等が好ましい。 In the embodiment, the semiconductor device 10 may not include the electrode 17.
In the embodiment, a liquid, a solid, or the like may be placed in the first slit 26. For example, in the case of a solid, a low elasticity sponge or rubber is preferable.

○ 実施形態において、例えば、第１のスリット２６ではなく、第１の区画壁２３の内部に中空部を形成してもよい。
○ 実施形態において、樹脂２５の露出面２５ｅが、第１の区画壁２３の端面２３ｅと同じ高さに位置していてもよい。 In the embodiment, for example, a hollow portion may be formed inside the first partition wall 23 instead of the first slit 26.
In the embodiment, the exposed surface 25 e of the resin 25 may be located at the same height as the end surface 23 e of the first partition wall 23.

○ 実施形態において、半導体素子１２は樹脂によってモールドされたものであってもよい。
○ 実施形態において、半導体モジュール４０の数は特に限定されるものではない。 In the embodiment, the semiconductor element 12 may be molded with resin.
In the embodiment, the number of semiconductor modules 40 is not particularly limited.

○ 実施形態において、空間２２の数は、二つであってもよいし、四つ以上であってもよい。
○ 実施形態において、半導体モジュール４０における半導体素子１２は、２枚の基板１３にそれぞれ２個ずつ実装されているものであってもよいし、４枚の基板１３にそれぞれ１個ずつ実装されているものであってもよい。 In the embodiment, the number of spaces 22 may be two, or may be four or more.
In the embodiment, two semiconductor elements 12 in the semiconductor module 40 may be mounted on each of the two substrates 13, or one each on the four substrates 13. It may be a thing.

１０…半導体装置、１１…放熱部材、１１ａ…面、１２…半導体素子、１２ａ…下面電極、１２ｂ…上面電極、１３…基板、１７…電極、１８…導電部材、１８ａ…第１の接合部、１８ｂ…第２の接合部、１８ｃ…第１の屈曲部、１８ｄ…第２の屈曲部、１８ｅ…平面部、１８ｆ…第３の接合部、１８ｇ…第４の接合部、１８ｈ…第３の屈曲部、１８ｉ…第４の屈曲部、２０…ケース、２１…周壁、２２，３２…空間、２３…第１の区画壁、２３ｈ…開口部、２５…樹脂、２５ｅ…露出面、２６…第１のスリット、２６ｅ，２７ｅ…下端、２７…第２のスリット、２８…第３のスリット、３３…第２の区画壁、４０…半導体モジュール、１２１…第１の半導体素子、１２２…第２の半導体素子、１２３…第３の半導体素子、１２４…第４の半導体素子。   DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Heat dissipation member, 11a ... Surface, 12 ... Semiconductor element, 12a ... Lower surface electrode, 12b ... Upper surface electrode, 13 ... Substrate, 17 ... Electrode, 18 ... Conductive member, 18a ... 1st junction part, 18b ... second joint, 18c ... first bend, 18d ... second bend, 18e ... planar part, 18f ... third joint, 18g ... fourth joint, 18h ... third Bending portion, 18i ... fourth bending portion, 20 ... case, 21 ... peripheral wall, 22, 32 ... space, 23 ... first partition wall, 23h ... opening, 25 ... resin, 25e ... exposed surface, 26 ... first 1 slit, 26e, 27e ... lower end, 27 ... second slit, 28 ... third slit, 33 ... second partition wall, 40 ... semiconductor module, 121 ... first semiconductor element, 122 ... second Semiconductor element 123 ... third semiconductor element 124 ... fourth half Body element.

Claims (6)

金属製の放熱部材と、
第１の半導体素子と第２の半導体素子と基板とを備え、前記第１の半導体素子の下面電極が前記基板のパターンにベアチップ実装されるとともに前記第２の半導体素子の下面電極が前記基板のパターンにベアチップ実装されてなり、前記放熱部材の面に搭載される半導体モジュールと、
前記基板の周囲を囲む周壁と、前記周壁の内側において複数の空間に区画する第１の区画壁とを有し、前記放熱部材の面に固定される樹脂製のケースと、を有し、
前記空間に前記半導体モジュールが少なくとも一つ収容されており、
前記空間に前記半導体モジュールを覆う樹脂が封止されている半導体装置であって、
前記第１の区画壁の上面には第１のスリットが設けられており、
前記第１の半導体素子の上面電極と前記第２の半導体素子の上面電極とは板状の導電部材によって互いに電気的に接続されており、
前記導電部材は前記第１の半導体素子の上面電極に接合される第１の接合部と、前記第２の半導体素子の上面電極に接合される第２の接合部と、前記第１の接合部から延設されて前記第１の半導体素子から離れる方向に屈曲する第１の屈曲部と、前記第２の接合部から延設されて前記第２の半導体素子から離れる方向に屈曲する第２の屈曲部と、前記第１の屈曲部から前記第２の屈曲部まで延設される平面状の平面部とを有するとともに、前記樹脂によって覆われており、
前記樹脂の露出面から前記平面部までの上下方向の距離は前記露出面から前記第１のスリットの下端までの上下方向の距離よりも小さいことを特徴とする半導体装置。 A metal heat dissipating member;
A first semiconductor element, a second semiconductor element, and a substrate, wherein the lower surface electrode of the first semiconductor element is bare-chip mounted on the pattern of the substrate, and the lower surface electrode of the second semiconductor element is formed on the substrate; A semiconductor module that is mounted on a pattern on a bare chip and is mounted on the surface of the heat dissipation member;
A peripheral wall that surrounds the periphery of the substrate, a first partition wall that is partitioned into a plurality of spaces inside the peripheral wall, and a resin case that is fixed to the surface of the heat dissipation member,
At least one of the semiconductor modules is accommodated in the space;
A semiconductor device in which a resin covering the semiconductor module is sealed in the space,
A first slit is provided on the upper surface of the first partition wall;
The upper surface electrode of the first semiconductor element and the upper surface electrode of the second semiconductor element are electrically connected to each other by a plate-like conductive member,
The conductive member includes a first bonding portion bonded to the upper surface electrode of the first semiconductor element, a second bonding portion bonded to the upper surface electrode of the second semiconductor element, and the first bonding portion. A first bent portion extending from the first semiconductor element and bent in a direction away from the first semiconductor element; and a second bent portion extending from the second joint portion and bent in a direction away from the second semiconductor element. And having a bent portion and a flat planar portion extending from the first bent portion to the second bent portion, and is covered with the resin,
The vertical distance from the exposed surface of the resin to the flat portion is smaller than the vertical distance from the exposed surface to the lower end of the first slit. 前記基板のパターンには第３の半導体素子の下面電極がベアチップ実装されるとともに第４の半導体素子の下面電極がベアチップ実装され、前記導電部材は前記第３の半導体素子の上面電極に接合される第３の接合部と、前記第４の半導体素子の上面電極に接合される第４の接合部と、前記第３の接合部から延設されて前記第３の半導体素子から離れる方向に屈曲する第３の屈曲部と、前記第４の接合部から延設されて前記第４の半導体素子から離れる方向に屈曲する第４の屈曲部と、を有し、
前記平面部は前記第３の屈曲部及び前記第４の屈曲部まで延設されていることを特徴とする請求項１に記載の半導体装置。 The bottom electrode of the third semiconductor element is bare-chip mounted on the pattern of the substrate, the bottom electrode of the fourth semiconductor element is bare-chip mounted, and the conductive member is joined to the top electrode of the third semiconductor element. A third joint, a fourth joint joined to the upper surface electrode of the fourth semiconductor element, and a bent portion extending from the third joint and away from the third semiconductor element. A third bent portion, and a fourth bent portion extending from the fourth bonding portion and bending in a direction away from the fourth semiconductor element,
The semiconductor device according to claim 1, wherein the planar portion extends to the third bent portion and the fourth bent portion. 前記基板には、
一端が前記基板のパターンに接続されるとともに、他端が前記樹脂から露出する板状の電極が実装されていることを特徴とする請求項１又は請求項２に記載の半導体装置。 The substrate includes
3. The semiconductor device according to claim 1, wherein a plate-like electrode having one end connected to the pattern of the substrate and the other end exposed from the resin is mounted. 4. 前記第１の区画壁における前記第１のスリットとは異なる部位には、隣り合う前記空間同士を連通する開口部が形成されており、前記開口部の少なくとも一部は前記樹脂で覆われていることを特徴とする請求項１〜請求項３のいずれか一項に記載の半導体装置。   An opening that communicates between the adjacent spaces is formed in a portion of the first partition wall that is different from the first slit, and at least a part of the opening is covered with the resin. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 前記周壁には、第２のスリットが形成されており、
前記樹脂の露出面から前記平面部までの上下方向の距離は前記露出面から前記第２のスリットの下端までの上下方向の距離よりも小さいことを特徴とする請求項１〜請求項４のいずれか一項に記載の半導体装置。 A second slit is formed in the peripheral wall,
The distance in the up-down direction from the exposed surface of the resin to the flat portion is smaller than the distance in the up-down direction from the exposed surface to the lower end of the second slit. The semiconductor device according to claim 1. 前記周壁の内側において前記周壁の短手方向に対して複数の空間に区画する第２の区画壁を有し、
前記第２の区画壁には、第３のスリットが形成されており、
前記樹脂の露出面から前記平面部までの上下方向の距離は前記露出面から前記第３のスリットの下端までの上下方向の距離よりも小さいことを特徴とする請求項１〜請求項５のいずれか一項に記載の半導体装置。 A second partition wall that partitions into a plurality of spaces with respect to a short direction of the peripheral wall inside the peripheral wall;
A third slit is formed in the second partition wall,
The vertical distance from the exposed surface of the resin to the flat portion is smaller than the vertical distance from the exposed surface to the lower end of the third slit. The semiconductor device according to claim 1.
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JP2020039251A (en) * 2019-10-29 2020-03-12 日立金属株式会社 Motor sintered magnet, manufacturing method thereof, and permanent magnet type synchronous motor

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JPS5694045U (en) * 1979-12-18 1981-07-25
JPS59136953A (en) * 1983-01-25 1984-08-06 Fuji Electric Co Ltd Composite element
JP2012151342A (en) * 2011-01-20 2012-08-09 Aisin Aw Co Ltd Semiconductor device
WO2015045648A1 (en) * 2013-09-30 2015-04-02 富士電機株式会社 Semiconductor device, method for assembling semiconductor device, component for semiconductor devices and unit module

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JPS5694045U (en) * 1979-12-18 1981-07-25
JPS59136953A (en) * 1983-01-25 1984-08-06 Fuji Electric Co Ltd Composite element
JP2012151342A (en) * 2011-01-20 2012-08-09 Aisin Aw Co Ltd Semiconductor device
WO2015045648A1 (en) * 2013-09-30 2015-04-02 富士電機株式会社 Semiconductor device, method for assembling semiconductor device, component for semiconductor devices and unit module

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020039251A (en) * 2019-10-29 2020-03-12 日立金属株式会社 Motor sintered magnet, manufacturing method thereof, and permanent magnet type synchronous motor

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