JP2017183482A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2017183482A JP2017183482A JP2016068017A JP2016068017A JP2017183482A JP 2017183482 A JP2017183482 A JP 2017183482A JP 2016068017 A JP2016068017 A JP 2016068017A JP 2016068017 A JP2016068017 A JP 2016068017A JP 2017183482 A JP2017183482 A JP 2017183482A
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Abstract
Description
以下、図面を参照しながら本実施の形態の半導体装置について詳細に説明する。
図1は、本実施の形態の半導体装置の構成を示す断面図である。図1に示す半導体装置は、窒化物半導体を用いた電界効果トランジスタ(FET;Field Effect Transistor)である。また、高電子移動度トランジスタ(HEMT:High Electron Mobility Transistor)とも呼ばれる。
例えば、図1および図2に示す本実施の形態の半導体装置において、ソース電極SEの電位を0V、ドレイン電極DEの電位を0V、ゲート電極GEの電位を定格電圧である+20Vとした場合、2次元電子ガス2DEGの電位はソース電極SEおよびドレイン電極DEの電位である0Vとなる。したがって、ゲート電極GEの直下においては、ゲート電極GEと2次元電子ガス2DEGとの間において、垂直方法に、ゲート電極GEに印加した電圧(20V)が加わる。この際、本実施の形態においては、メサ型の第4の窒化物半導体層(キャップ層)S4の側面の上方および下方において、角部(図中の破線の丸部)が鈍角となり、メサ型の第4の窒化物半導体層(キャップ層)S4の側面に沿って形成されるゲート絶縁膜GIに対する電界集中が緩和される。
例えば、図1および図3に示す本実施の形態の半導体装置において、ゲート電極GEの電位を0Vとし、オフ状態とした場合において、ソース電極SEの電位とドレイン電極DEの電位との間に、400Vの電位差が生じた場合、即ち、このような高電圧が印加された場合について考える。このような場合において、本実施の形態の場合には、メサ型の第4の窒化物半導体層(キャップ層)S4の側面がテーパ形状となっているため、ドレイン電極DE側の第3の窒化物半導体層(電子供給層)S3中の電界強度は緩和される。このため、第3の窒化物半導体層(電子供給層)S3および第2の窒化物半導体層(チャネル層)S2への電子の注入が抑制される(図中の破線の丸部)。これによって、電子の注入によって発生する電流狭さくが抑制されるため、ゲート電極GEの電圧が0Vから10Vとなり、トランジスタがオフ状態からオン状態となる場合において、トランジスタのオン抵抗の劣化を抑制することができる。
次いで、図7〜図15を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図7〜図15は、本実施の形態の半導体装置の製造工程を示す断面図である。
上記実施の形態1においては、ゲート電極GEやソース電極SEおよびドレイン電極DEを、いわゆるフォトリソグラフィおよびエッチング技術を用いて形成したが、これらの電極をいわゆるリフトオフ法により形成してもよい。
図16は、本実施の形態の半導体装置の構成を示す断面図である。ソース電極SEおよびドレイン電極DE以外の構成は、実施の形態1(図1)に示す半導体装置と、同様である。
次いで、図17〜図25を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図17〜図25は、本実施の形態の半導体装置の製造工程を示す断面図である。
本実施の形態においては、表面保護膜PROのメサ型の第4の窒化物半導体層(キャップ層)S4側の端部の側面を、テーパ形状とする。
図26は、本実施の形態の半導体装置の構成を示す断面図である。表面保護膜PROのメサ型の第4の窒化物半導体層(キャップ層)S4側の端部の側面形状以外の構成は、実施の形態1(図1)に示す半導体装置と、同様である。図27および図28は、本実施の形態の半導体装置のゲート絶縁膜の近傍の構成を示す断面図である。図27は、ソース電極の表面保護膜PROの端部近傍の拡大図であり、図28は、ドレイン電極の表面保護膜PROの端部近傍の拡大図である。
次いで、図29〜図35を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図29〜図35は、本実施の形態の半導体装置の製造工程を示す断面図である。
上記実施の形態3においては、ゲート電極GEやソース電極SEおよびドレイン電極DEを、いわゆるフォトリソグラフィおよびエッチング技術を用いて形成したが、これらの電極をいわゆるリフトオフ法により形成してもよい。
図36は、本実施の形態の半導体装置の構成を示す断面図である。ソース電極SEおよびドレイン電極DE以外の構成は、実施の形態3(図26)に示す半導体装置と、同様である。
次いで、図37〜図39を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図37〜図39は、本実施の形態の半導体装置の製造工程を示す断面図である。
本実施の形態においては、ゲート絶縁膜GIの膜厚を厚くする。
図40は、本実施の形態の半導体装置の構成を示す断面図である。第4の窒化物半導体層(キャップ層)S4の形状およびゲート絶縁膜GIの膜厚以外の構成は、実施の形態1(図1)に示す半導体装置と、同様である。図41は、本実施の形態の半導体装置のゲート絶縁膜の近傍の構成を示す断面図である。
本実施の形態の半導体装置は、実施の形態1の場合と同様の工程により形成することができる。但し、絶縁膜(IF1)をマスクとして、第4の窒化物半導体層S4を加工する際、異方性のドライエッチングを行い、第4の窒化物半導体層S4の側面を略垂直形状としてもよい。また、第4の窒化物半導体層S4の加工の後、ゲート絶縁膜GIを形成する際、その膜厚が、第4の窒化物半導体層S4の膜厚(t)の1.5倍以上、より好ましくは2倍以上となるよう、調整すればよい。
実施の形態1(図1)においては、第4の窒化物半導体層S4の側面をテーパ形状としたが、第4の窒化物半導体層S4の側面を階段状としてもよい。即ち、第4の窒化物半導体層S4は、その両端部においてその膜厚が徐々に(段々と)減少していればよく、その形状は、テーパ形状でも階段状でもよい。別の言い方をすれば、第4の窒化物半導体層S4は、その端に向かってその膜厚が小さくなっていればよい。
図42は、本実施の形態の半導体装置の構成を示す断面図である。第4の窒化物半導体層(キャップ層)S4の両端部の形状以外の構成は、実施の形態1(図1)に示す半導体装置と、同様である。図43および図44は、本実施の形態の半導体装置のゲート絶縁膜の近傍の構成を示す断面図である。図43は、第4の窒化物半導体層(キャップ層)S4のドレイン電極側の端部近傍の拡大図であり、図44は、第4の窒化物半導体層(キャップ層)S4のドレイン電極側の端部近傍の拡大図である。
次いで、図45〜図50を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図45〜図50は、本実施の形態の半導体装置の製造工程を示す断面図である。
上記実施の形態においては、第4の窒化物半導体層S4の両端部の形状を左右でほぼ対称となるように構成したが、第4の窒化物半導体層S4の両端部の形状をソース電極側とドレイン電極側とで異なるものとしてもよい。
図52は、本実施の形態の応用例1の半導体装置の構成を示す断面図である。実施の形態6(図42)においては、第4の窒化物半導体層(キャップ層)S4の両端部の第2膜厚部の大きさを同程度としたが、それぞれのX方向の長さを変えてもよい。
図54は、本実施の形態の応用例2の半導体装置の構成を示す断面図である。実施の形態1(図1)においては、第4の窒化物半導体層(キャップ層)S4の両側面のテーパ形状を同様の形状としたが、それぞれの形状を変えてもよい。
DE ドレイン電極
GE ゲート電極
GI ゲート絶縁膜
IF1 絶縁膜
IF2 絶縁膜
IL1 層間絶縁膜
ML1 金属膜
ML2 金属膜
PR1 フォトレジスト膜
PR2 フォトレジスト膜
PRO 表面保護膜
S1 第1の窒化物半導体層(バッファ層)
S2 第2の窒化物半導体層(チャネル層)
S3 第3の窒化物半導体層(電子供給層)
S4 第4の窒化物半導体層(キャップ層)
SE ソース電極
SUB 基板
Claims (20)
- 第1窒化物半導体層と、
前記第1窒化物半導体層上に形成された第2窒化物半導体層と、
前記第2窒化物半導体層上に形成された第3窒化物半導体層と、
前記第3窒化物半導体層上に形成されたメサ型の第4窒化物半導体層と、
前記第3窒化物半導体層上で、かつ、前記第4窒化物半導体層の一方の側に形成されたソース電極と、
前記第3窒化物半導体層上で、かつ、前記第4窒化物半導体層の他方の側に形成されたドレイン電極と、
前記第4窒化物半導体層を覆うゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
を有し、
前記第2窒化物半導体層の電子親和力は、前記第1窒化物半導体層の電子親和力以上であり、
前記第3窒化物半導体層の電子親和力は、前記第1窒化物半導体層の電子親和力より小さく、
前記第4窒化物半導体層の電子親和力は、前記第2窒化物半導体層の電子親和力以上であり、
前記第4窒化物半導体層と前記ゲート電極とは前記ゲート絶縁膜で分離されており、
前記第4窒化物半導体層は、前記ドレイン電極側の端部においてその膜厚が徐々に減少している、半導体装置。 - 請求項1記載の半導体装置において、
前記第4窒化物半導体層は、前記ソース電極側の端部においてその膜厚が徐々に減少している、半導体装置。 - 請求項2記載の半導体装置において、
前記メサ型の前記第4窒化物半導体層は、上面と、前記ドレイン電極側の側面と、前記ソース電極側の側面と、を有し、
前記ドレイン電極側の側面は、テーパ形状であり、
前記第3窒化物半導体層と前記ドレイン電極側の側面とのなす角は、120度以上である、半導体装置。 - 請求項3記載の半導体装置において、
前記ソース電極側の側面は、テーパ形状であり、
前記第3窒化物半導体層と前記ソース電極側の側面とのなす角は、120度以上である、半導体装置。 - 請求項4記載の半導体装置において、
前記第3窒化物半導体層と前記ドレイン電極側の側面とのなす角は、前記第3窒化物半導体層と前記ソース電極側の側面とのなす角より大きい、半導体装置。 - 請求項4記載の半導体装置において、
前記ドレイン電極側の側面の上面から見たゲート長方向の長さは、前記ソース電極側の側面の上面から見たゲート長方向の長さより大きい、半導体装置。 - 請求項4記載の半導体装置において、
前記第3窒化物半導体層上で、かつ、前記第4窒化物半導体層の前記ドレイン電極側に形成された第1絶縁膜と、
前記第3窒化物半導体層上で、かつ、前記第4窒化物半導体層の前記ソース電極側に形成された第2絶縁膜と、を有する、半導体装置。 - 請求項7記載の半導体装置において、
前記ゲート絶縁膜は、前記第1絶縁膜上から前記第2絶縁膜上まで延在している、半導体装置。 - 請求項8記載の半導体装置において、
前記第1絶縁膜の前記ゲート絶縁膜と重なる側の側面はテーパ形状である、半導体装置。 - 請求項9記載の半導体装置において、
前記第2絶縁膜の前記ゲート絶縁膜と重なる側の側面はテーパ形状である、半導体装置。 - 請求項2記載の半導体装置において、
前記メサ型の前記第4窒化物半導体層は、前記ドレイン電極側の端部に、第1膜厚部と第2膜厚部とを有し、
前記第2膜厚部は、前記第1膜厚部より外側に配置され、
前記第2膜厚部の膜厚は、前記第1膜厚部の膜厚より小さい、半導体装置。 - 請求項11記載の半導体装置において、
前記メサ型の前記第4窒化物半導体層は、前記ソース電極側の端部に、第3膜厚部と第4膜厚部とを有し、
前記第4膜厚部は、前記第3膜厚部より外側に配置され、
前記第3膜厚部の膜厚は、前記第4膜厚部の膜厚より小さい、半導体装置。 - 請求項12記載の半導体装置において、
前記第1膜厚部のゲート長方向の長さは、前記第3膜厚部のゲート長方向の長さより大きい、半導体装置。 - 請求項12記載の半導体装置において、
前記第3窒化物半導体層上で、かつ、前記第4窒化物半導体層の前記ドレイン電極側に形成された第1絶縁膜と、
前記第3窒化物半導体層上で、かつ、前記第4窒化物半導体層の前記ソース電極側に形成された第2絶縁膜と、を有する、半導体装置。 - 請求項14記載の半導体装置において、
前記ゲート絶縁膜は、前記第1絶縁膜上から前記第2絶縁膜上まで延在している、半導体装置。 - 請求項15記載の半導体装置において、
前記第1絶縁膜の前記ゲート絶縁膜と重なる側の側面はテーパ形状である、半導体装置。 - 請求項16記載の半導体装置において、
前記第2絶縁膜の前記ゲート絶縁膜と重なる側の側面はテーパ形状である、半導体装置。 - 第1窒化物半導体層と、
前記第1窒化物半導体層上に形成された第2窒化物半導体層と、
前記第2窒化物半導体層上に形成された第3窒化物半導体層と、
前記第3窒化物半導体層上に形成されたメサ型の第4窒化物半導体層と、
前記第3窒化物半導体層上で、かつ、前記第4窒化物半導体層の一方の側に形成されたソース電極と、
前記第3窒化物半導体層上で、かつ、前記第4窒化物半導体層の他方の側に形成されたドレイン電極と、
前記第4窒化物半導体層を覆うゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
を有し、
前記第2窒化物半導体層の電子親和力は、前記第1窒化物半導体層の電子親和力以上であり、
前記第3窒化物半導体層の電子親和力は、前記第1窒化物半導体層の電子親和力より小さく、
前記第4窒化物半導体層の電子親和力は、前記第2窒化物半導体層の電子親和力以上であり、
前記第4窒化物半導体層と前記ゲート電極とは前記ゲート絶縁膜で分離されており、
前記ゲート絶縁膜の膜厚は、前記第4窒化物半導体層の膜厚より大きい、半導体装置。 - 請求項18記載の半導体装置において、
前記ゲート絶縁膜の膜厚は、前記第4窒化物半導体層の膜厚の1.5倍以上である、半導体装置。 - (a)前記第1窒化物半導体層上に、第2窒化物半導体層を形成する工程、
(b)前記第2窒化物半導体層上に、第3窒化物半導体層を形成する工程、
(c)前記第3窒化物半導体層上に、第4窒化物半導体層を形成する工程、
(d)前記第4窒化物半導体層をメサ型に加工する工程、
(e)前記メサ型の前記第4窒化物半導体層上にゲート絶縁膜を介してゲート電極を形成する工程、を有し、
前記(d)工程は、
(d1)前記第4窒化物半導体層をエッチングする工程、
(d2)前記(d1)工程の後、前記第4窒化物半導体層に熱処理を施す工程、を有し、
前記(d2)工程により、前記第4窒化物半導体層の側面がテーパ形状となる、半導体装置の製造方法。
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