JP2017183471A - Evaluation method for point detect region - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an evaluation method for a point detect region of a silicon wafer, in which an Nv region and an Ni region can be distinguished in an N region in a short time, at low cost, and with high accuracy.SOLUTION: An evaluation method for a point detect region of a silicon wafer includes: a step of introducing interstitial silicon in a bulk of the silicon wafer by performing a thermal oxidization process on the silicon wafer at 800 to 1100°C for 30 to 90 minutes under the pyrogenic oxidation condition; a step of removing a thermally oxidized film formed on the silicon wafer in the thermal oxidization step, by HF etching; a step of measuring the minor carrier diffusion length in the silicon wafer after the thermally oxidized film removing step; and a step of evaluating the point defect region on the basis of the minor carrier diffusion length measured in the measurement step.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a method for evaluating a point defect area of a silicon wafer.

  In a silicon single crystal pulled by the Czochralski method (CZ method) or the like, point defects (vacancies, interstitial silicon) are introduced in the crystal manufacturing process, and these aggregate to form a glow-in defect (V Region, I region), and a complete crystal region (N region) in which point defects are not aggregated. In the N region, there is an Nv region in which vacancies are dominant and an Ni region in which interstitial silicon is dominant although point defects are not aggregated.

  Since the grow-in defect may impair the characteristics of the device, it is desirable to inspect the wafer manufacturing process or immediately before the shipment of the wafer so that the wafer including the glow-in defect generation area is not put into the device forming process.

  Also in the N region, a difference in behavior such as oxygen precipitation occurs, which may impair device characteristics such as a gettering effect. Therefore, it is desirable to grasp the distribution of the point defects in the N region where no glow-in defect occurs, and in particular, it is desirable to specify the boundary between the Nv region and the Ni region.

  As described above, in the silicon single crystal ingot, it is important to evaluate the quality level of the single crystal by dividing the V region, the I region, and the N region, and at the same time, the Nv region and the Ni region in the N region. It is also important to make the classification.

  In recent years, in particular, there is a demand for an evaluation method of a point defect region that can accurately classify an Nv region and an Ni region in the N region.

JP 2004-87591 A Special table 2014-523139 gazette

  In the prior art, for example, as disclosed in Patent Document 1, minority carrier diffusion length is measured after the intentional contamination process of transition metal and three stages of heat treatment processes, and the Ni region and Nv region of the wafer are inspected based on the measured values. A classification method is used. However, in this method, since the measurement is performed after the transition metal intentional contamination process and the three-stage heat treatment process, it takes time to determine the result and a lot of cost is required. Furthermore, when the wafer is excessively contaminated with the transition metal, the transition metal's own precipitates introduced into the supersaturation also appear in regions other than the Ni region and the Nv region, and there is a high possibility of reducing the measurement accuracy. . Therefore, it is necessary to control the contamination amount and in-plane distribution of the transition metal with high accuracy, which is technically difficult.

  In Patent Document 2, after forming an oxide film by dry oxidation, the minority carrier diffusion length is measured by a surface electromotive force method (SPV method), and thereby, the Nv region, the Ni region, and the like are classified. However, it is considered that the introduction of interstitial silicon does not occur sufficiently in dry oxidation, and further, contamination during oxidation exists at the interface between the oxide film and silicon. As a result, the contamination behaves as a lifetime killer, and the measured value of the minority carrier diffusion length varies, causing the measurement accuracy to deteriorate. Furthermore, in Patent Document 2, the absolute value of the diffusion length is used for the determination, but it is considered difficult to evaluate the absolute value due to factors such as resistivity and oxygen concentration because of the characteristics of the silicon wafer.

  The present invention has been made in view of the above-described problems, and evaluates a point defect region of a silicon wafer that can accurately separate an Nv region and an Ni region from the N region in a short time and at a low cost. It aims to provide a method.

  In order to achieve the above object, the present invention is a method for evaluating a point defect region of a silicon wafer, wherein the silicon wafer is thermally oxidized at 800 to 1100 ° C. under pyrogenic oxidation conditions for 30 to 90 minutes. A step of introducing interstitial silicon into the bulk of the silicon wafer, a step of removing a thermal oxide film formed on the silicon wafer by the thermal oxidation process by an HF etching process, and the thermal oxide film. A point defect region comprising: a step of measuring a minority carrier diffusion length in the silicon wafer after the removing step; and a step of evaluating the point defect region based on the minority carrier diffusion length measured in the measurement step. Provides an evaluation method.

  As described above, in the present invention, basically, only the thermal oxidation process and the thermal oxide film removal process are indispensable as pre-processing for the minority carrier diffusion length measurement. Since the Ni region can be specified from the point, it is possible to evaluate the point defect region with high accuracy in a short time and at a low cost. In the present invention, since the Ni region and the boundary between the Ni region and the Nv region can be determined, a portion other than the identified Ni region in the N region can be identified as the Nv region.

  At this time, the method for measuring the minority carrier diffusion length may be a surface electromotive force method or a wafer lifetime method.

  In the present invention, the minority carrier diffusion length can be measured by these methods.

  The silicon wafer may be a p-type silicon wafer.

  The method for evaluating a point defect area of a silicon wafer according to the present invention is an effective method particularly for evaluating a point defect area of a p-type silicon wafer.

  With the point defect region evaluation method of the present invention, the Nv region and the Ni region can be distinguished from the N region with high accuracy in a short time and at a low cost.

It is a flowchart which shows an example of the evaluation method of the point defect area | region of this invention. It is the flowchart which showed the evaluation procedure of the point defect area | region performed in the Example and the comparative example. It is a map which shows the distribution in a wafer surface of the minority carrier diffusion length measured before heat processing and after heat processing in an example and a comparative example. It is the defect distribution formed by the thermal oxidation process of an Example, and the observation image of a defect.

  Hereinafter, although an embodiment is described about the present invention, the present invention is not limited to this.

  Hereinafter, a method for evaluating a point defect area of a silicon wafer according to the present invention will be described with reference to FIG.

  The present invention is an evaluation method of a silicon wafer, and more specifically, a method capable of specifying a region (Ni region) where interstitial silicon is dominant in a silicon single crystal ingot from the evaluation of the silicon wafer. is there. In particular, the present invention is effective when a p-type silicon wafer is an evaluation target.

  The silicon wafer evaluation method of the present invention is a process of introducing interstitial silicon into a silicon wafer bulk by thermally oxidizing the silicon wafer at 800 to 1100 ° C. under pyrogenic oxidation conditions for 30 to 90 minutes ( (7) in FIG. 1 and the step of removing the thermal oxide film formed on the silicon wafer by the thermal oxidation treatment process (FIG. 1 (8)), and the thermal oxide film removal step, The step of measuring the minority carrier diffusion length in the silicon wafer ((9) in FIG. 1) and the step of evaluating the point defect region based on the minority carrier diffusion length measured in the measurement step ((10) in FIG. 1). Have.

  First, for a silicon wafer to be evaluated in the present invention, for example, a silicon single crystal ingot is pulled up by a method such as the CZ method ((1) in FIG. 1), and the ingot is sliced ((2) in FIG. 1). Can be produced.

  Moreover, it is particularly preferable that the silicon wafer is one in which processing strain remaining on the wafer surface has been removed in advance. If the silicon wafer has almost no processing distortion, the measurement accuracy of the minority carrier diffusion length is further improved, so that a more accurate evaluation can be performed.

  For example, a product level polished wafer (hereinafter also referred to as PW) may be used as the silicon wafer having almost no processing distortion ((11) in FIG. 1). Moreover, you may use the silicon wafer extracted in the middle of the polishing process. In the manufacturing process of the PW wafer, the damage on the front and back surfaces of the silicon wafer is removed as it passes through the processing process.

  Further, a silicon wafer is sliced from a silicon single crystal ingot ((2) in FIG. 1), for example, a silicon wafer near the N region is used as a slab sample ((3) in FIG. 1), and the slab sample is subjected to high-precision surface grinding. However, a silicon wafer ((5) in FIG. 1) subjected to etching for removing grinding distortion may be used as an evaluation target silicon wafer ((4) in FIG. 1). As described above, when the slab sample is cut out from the silicon single crystal ingot to specify the Ni region, it is preferable to perform the evaluation method of the present invention after removing the processing strain of the slab sample.

  Further, cleaning ((6) in FIG. 1) may be performed before the silicon wafer to be evaluated is thermally oxidized ((7) in FIG. 1). This cleaning may be performed by combining the cleaning with the HF solution and the SC1 cleaning after the cleaning with the HF solution.

  Next, the silicon wafer is thermally oxidized under pyrogenic oxidation conditions at 800 to 1100 ° C. for 30 to 90 minutes to introduce interstitial silicon into the bulk of the silicon wafer ((7) in FIG. 1). The pyrogenic oxidation condition refers to wet oxidation using a gas containing water vapor, for example, oxygen gas containing water vapor or the like as an oxidizing species. In addition, nitrogen gas containing water vapor, argon gas containing water vapor, or the like can be used as the oxidizing species. As a result of the inventor's research, in the Ni region among the point defect introduction regions, supersaturated interstitial silicon is introduced into the Ni region by oxidation treatment at 800 to 1100 ° C. under pyrogenic oxidation conditions for 30 to 90 minutes. I found out that That is, it was found that a large amount of interstitial silicon can be efficiently introduced into the Ni region by performing pyrogenic oxidation instead of dry oxidation.

  The interstitial silicon introduced into the supersaturation in this way aggregates between the interstitial silicons in the cooling process after the thermal oxidation treatment of the silicon wafer, and stress is generated in the periphery, and dislocations are introduced when the stress becomes unacceptable. It becomes a crystal defect. The density of dislocations generated in the Ni region by the thermal oxidation treatment under pyrogenic oxidation conditions is higher than that in the case where the same thermal oxidation treatment is applied to other regions such as the Nv region. Therefore, as will be described later, a large difference occurs in the minority carrier diffusion length between the Ni region and the Nv region, so that the Ni region and the Nv region can be accurately distinguished.

  Next, the thermal oxide film formed on the silicon wafer by the thermal oxidation process is removed by HF etching ((8) in FIG. 1).

  After the thermal oxide film removing step, the minority carrier diffusion length is measured in the silicon wafer ((9) in FIG. 1). In the present invention, the minority carrier diffusion length measurement method can be a surface electromotive force method or a wafer lifetime method.

  Subsequently, the point defect region is evaluated based on the measured minority carrier diffusion length ((10) in FIG. 1). The dislocations introduced as described above are known to be so-called lifetime killer defects that inhibit the minority carrier diffusion length, and due to the action of this defect, the diffusion length becomes a region in which interstitial silicon is excessive ( That is, it becomes shorter in the region where interstitial silicon is supersaturated in the Ni region by the thermal oxidation process. Therefore, if a measuring device that can accurately grasp the diffusion length is used, a site that was in the Ni region before the thermal oxidation treatment can be specified.

  For example, when the minority carrier diffusion length is measured after the thermal oxidation process is performed and the thermal oxide film is removed, a region where the minority carrier diffusion length is reduced appears in a ring shape in the minority carrier diffusion length distribution. When such a ring-shaped diffusion length reduction region appears, it can be easily determined that the silicon wafer is cut out from the Ni region.

  As described above, a silicon wafer in which a portion with a short diffusion length is seen in the diffusion length distribution obtained by measuring the minority carrier diffusion length was produced from a crystal portion where the interstitial silicon of the silicon single crystal ingot was dominant. It can be evaluated that it is a silicon wafer. Thus, for example, when a crystal is grown by gradually reducing the pulling rate by the CZ method, in terms of the crystal growth direction of the ingot, all the wafers made below the wafer, that is, from the melt side, have interstitial silicon. It can be judged that there is a high possibility that the crystals are dominant. That is, the boundary between the Nv region and the Ni region in the N region of the silicon single crystal ingot can be determined by the point defect region evaluation method of the present invention. In the present invention, since the Ni region can be determined and the boundary between the Ni region and the Nv region can be determined, a portion other than the specified Ni region in the N region can be specified as the Nv region.

  The length of minority carrier diffusion length depends on resistivity, oxygen concentration, etc., so there is a difference between varieties, but these influences in the silicon wafer surface are due to the decrease in diffusion length due to the contribution of interstitial silicon. Less than impact. Therefore, if the evaluation method is as in the present invention, for example, standardize and inspect the diffusion length reduction ratio comparing the position where the minority carrier diffusion length in the wafer surface is reduced and the normal position where there is almost no reduction. The crystal quality can also be evaluated.

  For example, if 20 or more sites where the minority carrier diffusion length is 15% or more lower than the average value of 100 points of the site with a long minority carrier diffusion length can be confirmed, it may be determined as a silicon wafer in the Ni region. As described above, the difference in diffusion length used for determination changes depending on the dopant concentration and oxygen concentration, and may be changed as appropriate.

  As described above, according to the present invention, a single-stage thermal oxidation process, a thermal process is basically performed regardless of a method that is complicated and technically difficult as in the prior art and has a large variation in measurement accuracy. The Ni region in the N region can be specified by the oxide film removal step and the minority carrier diffusion length measurement.

  EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples and comparative examples of the present invention, but the present invention is not limited to these examples.

(Example)
In the example, the point defect region of the p-type silicon wafer was evaluated by a process flow according to the point defect region evaluation method of the present invention as shown in FIG.

  First, in this example, a slab wafer cut out from a preferential position (Ni region) of interstitial silicon in a p-type silicon crystal ingot pulled up by the CZ method was prepared as a p-type silicon wafer for evaluation (FIG. 2). (1) to (3)). Thus, a p-type silicon wafer that was previously known to be cut out from an ingot including a Ni region of a silicon single crystal ingot was prepared.

  Next, in order to remove the processing distortion of the silicon wafer, high-precision surface grinding and grinding distortion removal etching were performed ((4) to (5) in FIG. 2). After removal of the processing strain, HF cleaning and SC1 cleaning were performed ((6) in FIG. 2).

  Next, the minority carrier diffusion length before the thermal oxidation treatment was measured by the surface electromotive force method ((7) in FIG. 2).

  Next, the silicon wafer was thermally oxidized at 950 ° C. for 90 minutes under pyrogenic oxidation conditions to introduce interstitial silicon into the bulk of the silicon wafer ((8) in FIG. 2). Thereafter, the silicon wafer was sufficiently cooled, and the thermal oxide film was removed by etching with an HF solution ((9) in FIG. 2).

  Next, the minority carrier diffusion length after thermal oxidation treatment and removal of the thermal oxide film was measured by the surface electromotive force method ((10) in FIG. 2).

  Next, the point defect region was evaluated based on the minority carrier diffusion length ((11) in FIG. 2). FIG. 3 shows the in-wafer distribution of minority carrier diffusion length measured before and after thermal oxidation. In order to exclude the influence of the wafer edge, only the minority carrier diffusion length data at a position 5 mm or more inside from the outer peripheral edge of the wafer was used.

  As can be seen from FIG. 3, after the thermal oxidation treatment of the example, a band-like (ring shape on the entire surface of the wafer) reduced minority carrier diffusion length was confirmed at a position about a half of the radius from the center of the silicon wafer. The As described above, it can be presumed that this reduced portion of the minority carrier diffusion length was a Ni region in which interstitial silicon was dominant before the thermal oxidation treatment. Therefore, it could be easily evaluated that this silicon wafer was cut from the Ni region of the silicon single crystal ingot. Thus, it was confirmed that the point defect region of the p-type silicon wafer can be easily evaluated with the evaluation method of the present invention.

  In addition, in silicon wafers after thermal oxidation treatment under pyrogenic oxidation conditions, the position of defects using MAGICS manufactured by Lasertec Co., Ltd., and the defect whose position is specified from the wafer surface by a mirror focus laser microscope (mounted on MAGICS) are identified. Observation, preparation of a cross-sectional sample of the defect, and cross-sectional observation with a TEM (transmission electron microscope) were performed. FIG. 4 shows a map of defect positions and an image obtained by a mirror focus laser microscope and TEM. As can be seen from FIG. 4, it was confirmed that dislocations that reduce the minority carrier diffusion length occurred in the Ni region by thermal oxidation under pyrogenic oxidation conditions, as expected.

(Comparative example)
Instead of thermal oxidation treatment under pyrogenic oxidation conditions, a point defect region of a silicon wafer was formed in the same manner as in the example except that heat treatment was performed at 950 ° C. for 90 minutes ((108) in FIG. 2) in a nitrogen atmosphere. evaluated. In the comparative example, in the same p-type silicon single crystal ingot as in the example, a slab wafer obtained by taking a sample adjacent to the silicon wafer used in the example was used as a p-type silicon wafer for evaluation. Therefore, it was previously known that the silicon wafer prepared in the comparative example was cut out from the Ni region of the silicon single crystal ingot.

  As a result, as can be seen from FIG. 3, in the comparative example, a characteristic distribution such as a band-like distribution of minority carrier diffusion lengths as in the example did not appear. From this result, it was confirmed that the method of the comparative example could not be determined as being cut out from the Ni region of the silicon single crystal ingot.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

Claims (3)

A method for evaluating a point defect area of a silicon wafer,
Introducing the interstitial silicon into the bulk of the silicon wafer by thermally oxidizing the silicon wafer at 800-1100 ° C. under pyrogenic oxidation conditions for 30-90 minutes;
Removing the thermal oxide film formed on the silicon wafer by the thermal oxidation treatment step by HF etching;
After the thermal oxide film removing step, measuring the minority carrier diffusion length in the silicon wafer;
Evaluating the point defect region based on the minority carrier diffusion length measured in the measurement step;
A point defect region evaluation method characterized by comprising:   2. The point defect region evaluation method according to claim 1, wherein the minority carrier diffusion length measurement method is a surface electromotive force method or a wafer lifetime method.   The point defect region evaluation method according to claim 1, wherein the silicon wafer is a p-type silicon wafer.