JP2004119446A - Annealed wafer and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing an annealed wafer which can easily reduce DNN defects without changing conditions the crystal growing step or heat treating conditions of a heat treating process in a step of manufacturing the annealed wafer. <P>SOLUTION: The method for manufacturing the annealed wafer by heat treating a silicon wafer includes a step of dissolving an oxygen precipitate on the surface of the wafer before the heat treating. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing an annealed wafer used for a highly integrated device for a semiconductor and an annealed wafer. More specifically, Surfscan SP1-TBI manufactured by KLA-Tencor (Surfscan manufactured by KLA-Tencor) The present invention relates to a method of manufacturing an annealed wafer having few defects detected in a DNN measurement mode (≧ 0.12 μm) of a particle counter and an annealed wafer.
[0002]
[Related technology]
As a wafer for manufacturing a device such as a semiconductor integrated circuit, a silicon single crystal wafer mainly grown by the Czochralski method (CZ method) is used. If a crystal defect exists in such a silicon single crystal wafer, a pattern defect or the like is caused at the time of manufacturing a semiconductor device. In particular, the pattern width of a highly integrated device in recent years is very fine, such as 0.3 μm or less. This causes a defect or the like, and significantly reduces the production yield or quality characteristics of the device. Therefore, there must be no crystal defects existing in the silicon single crystal wafer, or the size must be reduced as much as possible.
[0003]
In particular, in a silicon single crystal grown by the CZ method, there is a crystal defect called a grown-in defect introduced during crystal growth. It is thought that the main cause of such crystal defects is oxygen precipitates, which are clusters of atomic vacancies that aggregate during the production of single crystals or aggregates of oxygen atoms mixed in from a quartz crucible. If these crystal defects are present in the surface layer of the wafer on which the device is formed, they become harmful defects that degrade the device characteristics. Therefore, such crystal defects are reduced and the defect-free layer (DZ) having a sufficient depth is reduced. It is desirable to produce a wafer having () in the surface layer.
[0004]
Also, if heavy metal impurities such as Fe and Cu are present in the surface layer of the silicon single crystal wafer, device characteristics will be degraded during device fabrication. Therefore, intrinsic gettering (IG) for depositing internal minute defects and removing heavy metal impurities as a gettering site in a bulk portion of a silicon wafer is important. In order to make this intrinsic gettering effective, it is necessary to form internal micro defects (BMD) of sufficient density in the bulk portion of the wafer. The term “internal micro defects” as used herein refers to oxygen precipitates existing in the bulk and micro defects such as dislocations and stacking faults generated by the oxygen precipitation.
[0005]
From the above points, in manufacturing a silicon semiconductor wafer, a heat treatment may be performed in order to form such a defect-free layer and a gettering site.
[0006]
The heat treatment for forming the defect-free layer (DZ) and the gettering site is generally performed at a high temperature in an inert atmosphere such as hydrogen or argon. By such heat treatment, defects such as COP on the wafer surface are eliminated to form a defect-free layer (DZ) on the surface layer of the wafer, and oxygen precipitates are formed in the bulk of the wafer. A wafer subjected to a special heat treatment after such mirror polishing is generally called an annealed wafer.
[0007]
This annealed wafer is generally manufactured by a method as shown in FIG. First, a silicon single crystal is grown by the CZ method (single crystal growth process, step 100). Next, the wafer is processed into a mirror-finished wafer by a normal method (wafer processing step, step 102). Thereafter, the wafer is washed (cleaning step before heat treatment, step 104), and heat treatment is performed (heat treatment step, step 106) to obtain an annealed wafer.
[0008]
The wafer processing step (step 102) is specifically performed according to a procedure as shown in FIG. The grown silicon single crystal is sliced (slicing step, step 102a) by wafer cutting with an inner peripheral saw or a wire saw after, for example, orientation processing, chamfering (chamfering step, step 102b), lapping (lapping). Subsequent to the step 102c), a chemical etching is performed to remove the work-affected layer (etching step 102d), and a mirror-finished wafer having an optical luster is finished by polishing (polishing step 102e). ).
[0009]
The defect-free layer (DZ) width and the oxygen precipitate density in the annealed wafer manufactured by the above-described conventional method mainly depend on the silicon single crystal pulling condition, the oxygen concentration in the crystal, and the heat treatment condition performed after mirror polishing. . In order to increase the width of the defect-free layer (DZ), it is necessary to eliminate the COP to a deeper region. As a method of heat treatment, there is a method in which the heat treatment temperature is higher and the heat treatment time is longer. However, these conditions are limited by the performance of the heat treatment furnace, and the production cost increases. Is being reduced. Generally, the COP size can be reduced by lowering the pulling speed in the single crystal growing step. Conversely, there is a method of shortening the staying time in the COP formation temperature region and reducing the COP size by remarkably increasing the pulling speed. It is also known that doping a silicon single crystal with nitrogen reduces the COP size. Since nitrogen doping also has the effect of increasing the size of the grown-in oxygen precipitate, nitrogen-doped crystals have been increasingly used in recent years as raw materials for annealed wafers (see Patent Documents 1 to 4).
[0010]
[Patent Document 1]
JP-A-9-223668
[Patent Document 2]
JP-A-11-135511
[Patent Document 3]
JP 2000-91342 A
[Patent Document 4]
JP-A-2002-20200
[0011]
[Problems to be solved by the invention]
By the above heat treatment, a defect-free layer (DZ) and a gettering site are formed. In particular, the COP on the surface of the silicon wafer can be almost completely eliminated by this heat treatment. COP is a defect having vacancies in which an oxide film is formed. Therefore, when heat treatment is performed in an inert gas atmosphere, an oxide film or the like in the COP diffuses outward, and further heat treatment at a high temperature causes reflow of silicon, thereby eliminating defects. Similarly, on the wafer surface, oxygen in the crystal diffuses outward and the oxygen concentration decreases, so that no oxygen precipitation occurs and a defect-free layer (DZ) is formed. Since oxygen does not diffuse outward inside the crystal, oxygen precipitation occurs. Form a nucleus and act as a gettering site.
[0012]
However, it has recently been confirmed that even when the above-described heat treatment is performed to produce an annealed wafer in which COP does not completely exist on the wafer surface, another type of defect newly generated or revealed by the heat treatment is generated. . For example, when observed in a high sensitivity mode of a Surfscan SP1-TBI particle counter (hereinafter sometimes abbreviated as SP1-TBI or simply referred to as SP1) manufactured by KLA-Tencor, many dents of several tens of nm are detected. there were. This defect could not be observed with a conventional laser particle counter or the like, and had a form (characteristic) different from that of COP or the like. This defect is particularly easily detected in the DNN mode of SP1, and is hereinafter simply referred to as a DNN defect. The cause of this defect has not been accurately grasped.
[0013]
Here, Surfscan SP1-TBI is a family device of Surfscan SP1 manufactured by KLA-Tencor and is a kind of surface defect and foreign matter inspection device. This device is a device designed and used for a wafer maker, a device maker, and an IC maker. SP1 can inspect a pattern-free wafer up to a maximum of 300 mm at high speed and with high sensitivity, and is used for the development of a process technology of 0.25 μm or less. For high sensitivity, multiple dark-field focusing optics and bright-field channels using Nomarski differential interference contrast technology are provided, and fine particles, scratches, and mounds of 0.25 μm or less on an unpatterned wafer It is a device that can detect pits (dimples), stacking faults, slip lines, other material defects, and the like (see Non-Patent Document 1). In particular, SP1-TBI has a normal incidence laser system similar to the conventional SP1, and further has an oblique incidence laser system (triple beam irradiation).
[0014]
[Non-patent document 1]
Special edition of Semiconductor World "'97 Semiconductor Inspection / Measurement / Analysis Technology Technology &Equipment", pp. 61-66 and 92.
[0015]
FIG. 5 is a partial cross-sectional side view illustrating the structure of SP1. In FIG. 5, reference numeral 10 denotes SP1, which has a rotatable sample stage 12 on which a sample wafer W is mounted. The laser light L incident from one side is reflected downward by the first reflection plate 14 and is reflected again by the surface of the rotating sample wafer W. Part of the reflected light is condensed by a light collector 16 erected around the first reflector 14 and guided to a first DWN detector 18 provided above. The rest of the reflected light is condensed by a condenser lens 20 provided above the first reflection plate 14, then reflected by the second reflection plate 22 to the other side, and used for DNN provided on the other side. To the second detector 24. In order to make the configuration of FIG. 5 easy to understand, FIG. 6A shows the DWN mode, and FIG. 6B shows the DNN mode separately.
[0016]
As shown in FIG. 6, the apparatus 10 has a measurement system called a DWN mode and a DNN mode. In the DWN mode, as shown in FIG. 6A, a laser is irradiated perpendicularly to the wafer, and the state of irregular reflection due to defects is collected and observed at a position close to the wafer, and is particularly used for detecting particles, COP, and the like. This is a valid mode. In the DNN mode, as shown in FIG. 6B, a laser is irradiated perpendicularly to the wafer, and the state of irregular reflection due to a defect is collected and observed in a portion close to regular reflection. This is an effective mode.
[0017]
The present invention has been made for the purpose of reducing DNN defects generated in such an annealed wafer, and in the step of manufacturing an annealed wafer, without changing the conditions of the crystal growth step and the heat treatment conditions of the heat treatment process. An object of the present invention is to provide a method for manufacturing an annealed wafer that can easily reduce the occurrence of DNN defects and an annealed wafer with reduced DNN defects.
[0018]
[Means for Solving the Problems]
The present inventors have investigated the characteristics of DNN defects in order to solve the above problems. First, when the relationship between the heat treatment time and the number of DNN defects was examined, the COP decreased as the heat treatment time was increased, whereas the DNN defect increased as the heat treatment time was increased. As described above, the DNN defect is a defect that becomes apparent by annealing, and has a characteristic different from that of the COP.
[0019]
Cross-sectional TEM observation of DNN defects was also performed. As a result, an irregular DNN defect of about 20 to 30 nm was detected, and this DNN defect had a different shape from the residual COP observed on the wafer surface after the heat treatment. Further, when an epitaxial silicon layer was formed on the wafer after the heat treatment, no epi-defect was generated from the residual COP after the heat treatment, but many epi-defects such as stacking faults were generated from the place where the DNN defect was present. As described above, the DNN defect generated in the annealed wafer has various properties different from the COP, and can be concluded as a different kind of defect.
[0020]
Thus, the cause of the DNN defect was determined. First, regarding the influence of the presence or absence of nitrogen doping, when annealing was performed under the same conditions, the number of DNN defects generated in the wafer was larger in the annealed wafer containing nitrogen than in the annealed wafer not containing nitrogen. Further, even in silicon not subjected to nitrogen doping, some are likely to be generated and some are hardly generated depending on the pulling conditions and oxygen concentration in the crystal. Therefore, it can be estimated that DNN defects generated after annealing are mainly caused by crystals. .
[0021]
By comparing the SP1 maps before and after the heat treatment, an attempt was made to clarify the DNN defect nuclei. However, even though the SP1 measurement was performed at the highest sensitivity, the core of the DNN defect was not found in the SP1 map before the heat treatment. The nucleus of the DNN defect is considered to be a very small grown-in defect which is very difficult to detect.
[0022]
A typical example of an extremely small grown-in defect other than the COP is an oxygen precipitate. However, it has been found that the grown-in oxygen precipitate existing at a depth of about 10 μm in the surface layer completely disappears when heat treatment at 1100 to 1300 ° C. is performed in a gas atmosphere such as hydrogen or argon. It was initially difficult to assume oxygen precipitates.
[0023]
During various investigations, it was found that when the oxygen concentration in the silicon crystal was increased, the number of DNN defects increased, suggesting that DNN defect nuclei were related to oxygen precipitation. Therefore, when cleaning was performed with hydrofluoric acid (HF) having a relatively high concentration before the heat treatment and then the heat treatment was performed, the number of DNN defects could be drastically reduced. From this, it can be said that the DNN defect nucleus is a special oxygen precipitate different from the oxygen precipitate which disappears in the heat treatment step.
[0024]
As a measure for reducing DNN defects, there is a method of reducing the oxygen concentration in the silicon crystal. However, it is difficult at present to eliminate DNN defects by adjusting crystal production conditions or the like in consideration of quality other than DNN defects, for example, slippage is likely to occur when the oxygen concentration is lowered in an annealed wafer.
[0025]
The method for producing an annealed wafer of the present invention is a method for producing an annealed wafer by heat-treating a silicon wafer, wherein oxygen precipitates on the surface of the silicon wafer before the heat treatment are performed, particularly oxygen precipitates which disappear in the heat treatment step. It is characterized by dissolving a special oxygen precipitate different from the substance.
[0026]
Conventionally, the cleaning performed before the heat treatment is performed using ammonia (NH) which is effective for removing particles. ₄ OH) and hydrogen peroxide (H ₂ O ₂ ), Hydrochloric acid (HCl) for removing metals and the like, and hydrogen peroxide (H). ₂ O ₂ ) Was generally used for cleaning. However, DNN defects could not be particularly reduced by such cleaning.
[0027]
Further, when heat treatment is performed in an argon gas atmosphere, cleaning with a thin hydrofluoric acid aqueous solution for the purpose of removing a natural oxide film may be used in the final step of cleaning in order to prevent the wafer surface from being contaminated with boron. (See Patent Document 5). However, DNN defects cannot be reduced by such thin hydrofluoric acid cleaning, and DNN defects cannot be reduced for the first time by performing hydrofluoric acid cleaning at a relatively high concentration for the purpose of dissolving oxygen precipitates. You can do it.
[0028]
[Patent Document 5]
International Publication No. 01/73838 pamphlet
[0029]
Wafers cut from nitrogen-doped crystals have various usefulness, such as small COP size and large grown-in oxygen precipitate size, as raw materials for annealed wafers. As a result, many DNN defects occurred, and this point became a problem. The cleaning with hydrofluoric acid before the heat treatment can also suppress the occurrence of such DNN defects in the nitrogen-doped crystal. That is, in the method of the present invention, it is possible to grow a silicon single crystal doped with nitrogen by the Czochralski method and use a silicon wafer cut out from the silicon single crystal as a raw material of the annealed wafer. Note that the doping amount of nitrogen is not particularly limited, but it is possible to reduce the COP size and the oxygen precipitate size by 5 × 10 5 ¹² ~ 1 × 10 ^Fifteen atoms / cm ³ Is desirable.
[0030]
Although the cause is not clear, a region where a silicon single crystal is grown by the Czochralski method is a silicon single crystal grown in a region excluding a region where an OSF (Oxidation Induced Stacking Fault) ring occurs. Good to be. When annealing is performed using a silicon single crystal in such a region (more precisely, a silicon wafer obtained by processing the silicon wafer), the number of DNN defects generated is small from the beginning, and the annealing with hydrofluoric acid cleaning significantly reduces DNN defects. Wafers can be manufactured.
[0031]
The heat treatment is preferably performed in an inert gas atmosphere such as a hydrogen gas or an argon gas at a temperature range of 1100 to 1300 ° C. for 30 minutes or more. Such a high-temperature heat treatment is necessary for improving the gettering ability and producing the defect-free layer (DZ). On the other hand, DNN defects are easily generated by high-temperature heat treatment, so that pretreatment by hydrofluoric acid cleaning can reduce the DNN defects, provide a defect-free region (DZ) sufficient, and produce a wafer having good gettering ability.
[0032]
The above hydrofluoric acid cleaning is desirably performed after mirror polishing of the wafer and before annealing. When combined with SC-1 cleaning or SC-2 cleaning, thin hydrofluoric acid cleaning to prevent boron contamination had to be performed at the end of the cleaning process, but hydrofluoric acid cleaning to reduce DNN defects can be incorporated at any position. Good. Further, it is desirable to wash the wafer using an aqueous solution having a hydrofluoric acid concentration (% by mass) of 0.5% to 50%. Hydrofluoric acid having such a concentration is easy to handle. In particular, cleaning conditions such as long-time cleaning when the hydrofluoric acid concentration is low and short-time cleaning when the hydrofluoric acid concentration is high are appropriately set, and oxygen precipitates which are considered to be nuclei of DNN defects generated after annealing, particularly disappear in the heat treatment step. The conditions are set such that a special oxygen precipitate different from the oxygen precipitate to be dissolved is sufficiently dissolved.
[0033]
In the case of the conventional method in which hydrofluoric acid cleaning for sufficiently dissolving such a special oxygen precipitate is not performed, although the DNN defect (≧ 0.12 μm) is small even in a crystal having a small DNN defect (≧ 0.12 μm), it depends on the manufacturing conditions of the single crystal. 2 to 0.5 pieces / cm ² Had occurred to a degree. On the other hand, if cleaning is performed with a hydrofluoric acid solution having a relatively high concentration before annealing, even the above-mentioned crystals have a concentration of 0.03 to 0.15 crystals / cm 2. ² Annealed wafers with reduced DNN defect density and even less DNN defects, especially 0.2 / cm ² The present inventors have obtained a new finding that the following annealed wafers can be manufactured, and have completed the present invention.
[0034]
Therefore, the annealed wafer of the present invention measures the surface of the wafer using a DNN measurement mode (≧ 0.12 μm) of a surfscan SP1-TBI particle counter manufactured by KLA-Tencor Corporation. The number of defects detected on the wafer surface is 0.2 / cm ² It is characterized by the following.
[0035]
In the above-mentioned annealed wafer, the DZ width on the wafer surface is 3 μm or more, and the BMD density inside the wafer is 1 × 10 ⁹ Pieces / cm ³ The above is preferable. The DZ width depends on the type of device and the device process, but is usually required to be 3 μm or more. According to the method for producing an annealed wafer of the present invention, a DZ layer having such a width can be easily obtained, and an annealed wafer having few DNN defects can be obtained. Although the upper limit of the DZ width is not particularly limited, about 30 μm is sufficient.
[0036]
The BMD density inside the wafer is 1 × 10 2 in consideration of the gettering ability. ⁹ Pieces / cm ³ That is all. The upper limit is not particularly limited, but considering the balance with the DZ width and the range required for the current device, 1 × 10 ¹¹ Pieces / cm ³ It is about. By using the method for producing an annealed wafer of the present invention, a wafer having such a BMD density can be easily obtained, and an annealed wafer having few DNN defects can be obtained.
[0037]
As a raw material wafer for the annealed wafer of the present invention, a silicon single crystal obtained by growing a silicon single crystal doped with nitrogen by the Czochralski method and cutting the silicon single crystal can be used.
[0038]
The annealed wafer of the present invention is suitably manufactured by the above-described method of manufacturing an annealed wafer of the present invention.
[0039]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it is needless to say that various modifications can be made without departing from the technical idea of the present invention. .
[0040]
The method for producing an annealed wafer of the present invention will be described. As shown in FIG. 1, the method for manufacturing an annealed wafer of the present invention comprises a single crystal growth step (step 100) of growing a silicon single crystal by the CZ method as in the conventional method of FIG. 3, and slicing the silicon single crystal. , Lapping, etching, surface grinding, chamfering, polishing, etc., a wafer processing step of performing processing such that at least one principal surface thereof is mirror-finished (step 102), and cleaning before heat treatment for cleaning the processed wafer It has a process (step 104) and a heat treatment process (step 106) for performing a heat treatment on the cleaned wafer. In particular, after the wafer polishing, a hydrofluoric acid treatment process (step 106) for cleaning with hydrofluoric acid before the heat treatment process (step 106) 103) is characterized.
[0041]
Although the production conditions of the silicon single crystal are not particularly limited, it is desirable to use a crystal having a small COP size in order to produce an annealed wafer having a wide DZ region. For this purpose, there is a method of using a crystal with a low pulling speed or a crystal that is rapidly cooled with a high pulling speed. It is known that doping a silicon single crystal with nitrogen reduces the COP size. In recent years, a nitrogen-doped product has been used as a silicon single crystal for annealing. In addition to reducing the COP size, nitrogen doping also has the effect of increasing the size of the grown-in oxygen precipitate, which makes the characteristics more desirable as a silicon single crystal for an annealed wafer.
[0042]
As described above, the silicon single crystal grown by the CZ method is processed into a wafer according to the usual method as shown in FIG. For example, after outer circumference grinding and orientation flat processing, slicing is performed by wafer cutting with an inner peripheral blade saw or wire saw, chamfering, lapping, chemical etching is performed to remove the damaged layer, and optical polishing by polishing. Finished to a mirror-polished wafer with high gloss. As shown in FIG. 3, a silicon wafer finished by mirror polishing is then subjected to a heat treatment to produce a conventional annealed wafer.
[0043]
An important aspect of the method for producing an annealed wafer of the present invention is that cleaning is performed using an aqueous solution containing hydrofluoric acid before performing the above-described heat treatment (annealing).
[0044]
The concentration of hydrofluoric acid in the aqueous solution used for washing is not particularly limited, but is desirably 0.5% to 50% by mass. Usually, the concentration of high-purity hydrofluoric acid used for semiconductors is about 50%, so that it can be used as an undiluted solution or water (H ₂ Use diluted with O). If the concentration of hydrofluoric acid is less than 0.5% at the time of dilution, the treatment time is prolonged, which is not practical. Particularly, treatment with 5% hydrofluoric acid for about 15 minutes greatly reduces DNN defects, which is preferable.
[0045]
After cleaning with an aqueous solution containing hydrofluoric acid, particles are likely to adhere to the wafer surface. Therefore, cleaning with an aqueous solution containing ammonia and hydrogen peroxide, which has an action of removing particles, so-called SC-1 cleaning, should be performed. desirable. Thereafter, if necessary, cleaning with an aqueous solution containing hydrochloric acid and a hydrogen peroxide solution having an action of removing metal impurities, so-called SC-2 cleaning may be performed.
[0046]
After the predetermined cleaning, annealing is performed on the surface of the silicon wafer. Although the annealing conditions are not particularly limited, heat treatment at a high temperature of 1100 ° C. or more for 30 minutes or more for the purpose of producing a gettering site and eliminating a COP is performed in an inert gas atmosphere such as a hydrogen gas or an argon gas. Is good. By such a high-temperature heat treatment, the COP on the wafer surface is completely eliminated, a DZ layer is formed on the wafer surface, and BMD is generated by oxygen precipitation inside the wafer to produce an annealed wafer having a high gettering effect. Further, since hydrofluoric acid cleaning is performed before annealing, the occurrence of DNN defects can be reduced.
[0047]
【Example】
The method for producing an annealed wafer of the present invention will be described in detail based on the following examples. However, the content of the present invention is not limited to these examples.
[0048]
(Example 1 and Comparative Example 1)
Nitrogen concentration in the crystal is 1 × 10 ^Thirteen atoms / cm ³ And grown by doping with nitrogen by the CZ method. Further, by changing manufacturing conditions such as a pulling speed, a silicon single crystal of six levels was grown.
[0049]
These crystals were sliced, and 12 wafers (wafer number: # 1 to 12) having a diameter of 300 mm and mirror-polished after chamfering, lapping and chemical etching were prepared.
[0050]
Six of the 12 wafers (# 7 to 12) were washed for 15 minutes using an aqueous solution containing 5% by mass HF (Example 1). On the other hand, for the remaining six sheets (# 1 to # 6), 4% by mass H containing no hydrofluoric acid was used. ₂ O ₂ -4% NH ₄ SC-1 washing with an aqueous solution of OH, and 4% by mass H ₂ O ₂ SC-2 washing with an aqueous solution of -4% by mass HCl was performed. The cleaning time of SC-1 cleaning and SC-2 cleaning was 10 minutes (Comparative Example 1).
[0051]
The surfaces of the 12 cleaned silicon wafers were subjected to a heat treatment at 1200 ° C. for 60 minutes in a 100% argon atmosphere. The heating rate is 2 ° C./min, and the cooling temperature is 2 ° C./min. As the heat treatment furnace, a vertical diffusion heat treatment furnace DD-1223V manufactured by Hitachi Kokusai Electric was used.
[0052]
Then, the number of DNN defects detected on the surface was measured using SP1. In SP1, a defect of 0.12 μm or more was detected in the DNN measurement mode, and was determined as a DNN defect.
[0053]
FIG. 2 is a map diagram showing the results of measuring the number of DNN defects detected on the surface after annealing in Example 1 and Comparative Example 1. The upper part (a) of FIG. 2 shows the result of Comparative Example 1 in which hydrofluoric acid cleaning was not performed before annealing (SC-1 + SC-2 cleaning). The lower part (b) of FIG. 2 shows the result of Example 1 in which hydrofluoric acid cleaning was performed before annealing. The wafers arranged above and below in FIGS. 2A and 2B are processed from silicon single crystals manufactured under the same pulling conditions. It is cut out from a single crystal grown in a region (V-rich region) where COP generation increases as going to the left side of FIG. 2. 600 wafers / wafer (0.85 wafers / cm ² ) (≧ 0.09 μm). 2 is a mirror-processed wafer cut from a single crystal grown in a region where the COP decreases toward the right side (a region where the OSF increases), and the number of COPs before the heat treatment is 80 in the rightmost wafer. Pieces / wafer (0.11 pieces / cm ² ) (DWN measurement mode, ≧ 0.09 μm).
[0054]
A comparison of the upper and lower stages of FIG. 2, ie, FIGS. 2A and 2B (Comparative Example 1 and Example 1), which are wafers processed from a silicon single crystal grown under the same manufacturing conditions, does not include hydrofluoric acid cleaning ( In the case of Comparative Example 1 (of SC-1 cleaning and SC-2 cleaning), 1.3 times better than in Example 1 in which cleaning was performed using an aqueous solution containing hydrofluoric acid (5% HF, 15 minutes). It can be seen that the number of DNN defects is about 6 times larger, and that the DNN defects are significantly reduced by hydrofluoric acid cleaning before annealing cleaning. In FIG. 2, the numerical values shown at the lower right of each wafer are actual measured values of DNN defects.
[0055]
The leftmost wafer in FIG. 2 is a wafer in which a large amount of COP has been generated. However, the number of defects is the smallest after the heat treatment, and the coordinates of the DNN defect shown in FIG. It can be seen that the COP has been completely erased by this heat treatment. Also, when the defects were similarly measured in the DWN mode and the DNN mode of SP1 after the fluoric acid cleaning and before the annealing, the number of defects did not change.
[0056]
As a result of confirming by cross-sectional TEM observation whether or not the defect after annealing was the one in which the COP existing before annealing remained, the defect had a form different from that of the COP. This defect (DNN defect) further increases as the heat treatment time is increased. This also indicates that the DNN defect is a defect having a property different from that of the COP.
[0057]
By performing hydrofluoric acid cleaning, DNN defects after annealing were reduced, but depending on crystal growth conditions, the number of DNN defects was large and could not be completely removed. Although the cause is not clear, it is expected that DNN defects are frequently generated in an area where OSF is likely to occur. Therefore, a good annealed wafer can be manufactured by manufacturing a crystal in such a region where the generation of OSF is small, subjecting it to hydrofluoric acid treatment, and further performing a heat treatment. The DZ width of the obtained annealed wafer was about 7 mm and the BMD density was about 5 × 10 ⁹ Pieces / cm ³ Met.
[0058]
(Example 2, Comparative Example 2)
A silicon single crystal doped with nitrogen under a growth condition considered to be outside the OSF ring generation region was pulled up. After this was processed into a wafer, heat treatment was performed on ten 300 mm diameter wafers in the same manner as in Example 1. The nitrogen concentration in the silicon single crystal is 1 × 10 ^Thirteen atoms / cm ³ Met.
[0059]
When these wafer surface defects were confirmed in the DWN measurement mode of SP1 before the heat treatment, about 800 wafers / wafer (1.13 wafers / cm) ² ) (≧ 0.09 μm). This is a small COP.
[0060]
Five of these wafers were annealed by hydrofluoric acid treatment (# 6 to # 10; Example 2), and five of the wafers were annealed without hydrofluoric acid treatment (# 1 to # 5). Comparative Example 2)
[0061]
As a result, in the wafer of Comparative Example 2 (# 1 to # 5) annealed without performing the hydrofluoric acid treatment, the average number of DNN defects was 240 / wafer (0.34 / cm). ² ) Degree was observed. On the other hand, in Example 2 (# 6 to # 10) in which annealing was performed by hydrofluoric acid treatment, the average number of DNN defects was 42 / wafer (0.06 / cm). ² ) And reduced to 1/6.
[0062]
The annealed wafers of Example 2 and Comparative Example 2 obtained at this time had a DZ width of 6 μm and a BMD density of 5 × 10 ⁹ Pieces / cm ³ Met.
[0063]
(Example 3, Comparative Example 3)
A silicon non-doped silicon single crystal was pulled under growth conditions considered to be outside the OSF ring generation region. After this was processed into a wafer, heat treatment was performed on ten 300 mm diameter wafers in the same manner as in Example 1.
[0064]
When these wafer surface defects were confirmed in the DWN measurement mode of SP1 before the heat treatment, about 400 wafers / wafer (0.57 wafers / cm ² ) (≧ 0.09 μm).
[0065]
Five of these wafers were annealed with hydrofluoric acid treatment (# 6 to # 10; Example 3), and five of the wafers were annealed without performing hydrofluoric acid treatment (# 1 to # 5). Comparative Example 3).
[0066]
As a result, in the wafer of Comparative Example 3 (# 1 to # 5) annealed without performing the hydrofluoric acid treatment, the average number of DNN defects was 150 / wafer (0.21 / cm). ² ) Degree was observed. On the other hand, in Example 3 (# 6 to # 10) in which annealing was performed by hydrofluoric acid treatment, the average number of DNN defects was 29 / wafer (0.04 / cm). ² ) And decreased to 1/5.
[0067]
At this time, the DZ width of the annealed wafers of Example 3 and Comparative Example 3 was 4 μm, and the BMD density was 3 × 10 ⁹ Pieces / cm ³ Met. When the annealed wafers subjected to the hydrofluoric acid cleaning and then subjected to the heat treatment as in Examples 2 and 3 were used for device manufacture, an improvement in the yield was observed.
[0068]
In the present invention, the form (characteristics) and the like of a defect newly generated or revealed after annealing (DNN defect in the present invention) is not accurately grasped. And a defect detected using a surfscan sp. 1-TB particle counter currently manufactured by KLA-Tencor Co., Ltd. (particularly, detected in a DNN mode after annealing). Defect). However, the present invention is not limited to this evaluation device, and the evaluation device is not particularly limited as long as it can measure a defect newly generated or revealed after such annealing with high sensitivity. For example, a device similar to the KLA-Tencor surfscan SP1-TBI particle counter is known as a KLA-Tencor surfscan without a grazing incidence laser system.・ Spy 1 ・ Particle counter or its family can be used.
[0069]
【The invention's effect】
As described above, according to the method for manufacturing an annealed wafer of the present invention, by performing cleaning using an aqueous solution containing hydrofluoric acid before annealing, it is possible to suppress the occurrence of DNN defects detected after the heat treatment, Particularly, even in the case of an annealed wafer made of a silicon single crystal grown by doping with nitrogen, the DNN defect can be effectively removed, and it can be performed without adding a new heat treatment process or changing heat treatment conditions. There is.
[0070]
Further, in the present invention, it is not necessary to further control the crystal growth conditions and the like, and a high-quality annealed wafer with few DNN defects can be provided.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating an example of a process sequence of a method for manufacturing an annealed wafer according to the present invention.
FIG. 2 is a map diagram showing the number of CNN defects in Example 1 and Comparative Example 1.
FIG. 3 is a flowchart showing an example of a process sequence of a conventional method for manufacturing an annealed wafer.
FIG. 4 is a flowchart illustrating an example of a process order of a wafer processing process.
FIG. 5 is a partial cross-sectional side view showing the structure of a surfscan S.B.1-T.B.I. Particle counter manufactured by KLA-Tencor Co., Ltd.
FIGS. 6A and 6B are similar drawings to FIGS. 5A and 5B, wherein FIG. 6A is a schematic view showing a measurement mechanism in a DWN mode, and FIG.
[Explanation of symbols]
10: Surf Scan Esp 1-TBI particle counter manufactured by KLA-Tencor Co., Ltd., 12: Sample stage, 14: First reflector, 16: Light collector, 18: First detection Device, 20: condenser lens, 22: second reflector, 24: second detector, W: sample wafer.

Claims (11)

A method for producing an annealed wafer by performing a heat treatment on a silicon wafer, wherein an oxygen precipitate on the surface of the silicon wafer is dissolved before performing the heat treatment. The method for producing an annealed wafer according to claim 1, wherein the oxygen precipitate is dissolved by washing the surface of the silicon wafer with an aqueous solution containing hydrofluoric acid at a concentration of 0.5% by mass to 50% by mass. . 3. The method for producing an annealed wafer according to claim 1, wherein a silicon single crystal doped with nitrogen by the Czochralski method is grown as the silicon wafer, and a silicon wafer cut out from the silicon single crystal is used. . The method for producing an annealed wafer according to claim 1, wherein the heat treatment is performed in a temperature range of 1100 to 1300 ° C. 5. The method for producing an annealed wafer according to any one of claims 1 to 4, wherein the heat treatment is performed for 30 minutes or more. The method for producing an annealed wafer according to claim 1, wherein the heat treatment is performed in a hydrogen gas or an inert gas atmosphere. The method for producing an annealed wafer according to any one of claims 1 to 6, wherein the dissolution of the oxygen precipitate on the surface of the silicon wafer is performed after mirror polishing of the silicon wafer. When the surface of the wafer is measured using the DNN measurement mode (≧ 0.12 μm) of a surf scan S.P.I.T.I.I. An annealed wafer, wherein the number of defects to be performed is 0.2 / cm ² or less. ^9. The annealed wafer according to claim 8, wherein the DZ width on the wafer surface is 3 μm or more, and the BMD density inside the wafer is 1 × 10 ⁹ / cm ³ or more. 10. The annealed wafer according to claim 8, wherein a silicon single crystal doped with nitrogen is grown by the Czochralski method, and a silicon wafer cut from the silicon single crystal is used as a raw material wafer. The annealing wafer according to claim 8, wherein the wafer is manufactured by the method according to claim 1.

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