JP2017175092A - Electronic component, anisotropic connecting structure, and method of designing electronic component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component, an anisotropic connection structure, and a method of designing the electronic component in which improvement in particle capture rate, prevention of short circuit, and improvement in adhesive strength are achieved while attaining a low profile of an electrode.SOLUTION: An electronic component 1 includes: a substrate 2; and bumps 3, 5 formed on one surface 2a of the substrate 2. In the bumps 3, 5, the areas of connecting surfaces 3a, 5a connected to electrodes 16, 17 of a connection object component 14 are larger than the areas of base portions 3b, 5b on the substrate 2 side.SELECTED DRAWING: Figure 1

Description

  The present technology relates to an electronic component connected on a circuit board via an anisotropic conductive adhesive, an anisotropic connection structure in which the electronic component is connected on the circuit board, and an electronic component design method.

  Conventionally, a connection body in which an electronic component such as an IC chip is connected to a circuit board of various electronic devices, or a connection body in which an electronic component such as a semiconductor package having an IC chip mounted on the substrate is connected to a circuit board of various electronic devices Is provided. In recent years, in various electronic devices, from the viewpoint of fine pitch, light weight, and thinning, as an electronic component, using an IC chip, an LSI chip, or a semiconductor package in which bumps that are protruding electrodes are arranged on the mounting surface, A so-called COB (chip on board), COG (chip on glass), or COF (chip on film) that directly mounts these electronic components such as an IC chip on a circuit board is employed.

  In COB connection or the like, COG connection, or COF connection, an electronic component such as an IC chip is thermocompression bonded onto a terminal portion of a circuit board via an anisotropic conductive film. An anisotropic conductive film is a film formed by mixing conductive particles in a thermosetting binder resin, and heat conduction is carried out between two conductors so that electrical conduction between the conductors can be achieved with the conductive particles. And the mechanical connection between the conductors is maintained by the binder resin. As an adhesive constituting the anisotropic conductive film, a photocurable resin or an adhesive using both thermosetting and photocuring is used in addition to a highly reliable thermosetting adhesive.

  For example, as shown in FIGS. 16A and 16B, the bumped IC chip 50 has input bumps 51 arranged in a line along one side edge 50a on the mounting surface of the circuit board, and one side edge 50a. The output bumps 53 are arranged in a zigzag pattern in two rows along the other side edge 50b opposite to. The input / output bumps 51 and 53 are generally formed in a rectangular shape with a longitudinal section having a conduction direction as a longitudinal direction by electrolysis or electroless plating using Au having excellent corrosion resistance and high connection reliability. The input / output bumps 51 and 53 can also be formed by solder balls using lead-free solder.

  In COG mounting, after the IC chip 50 is mounted on the electrode terminal 57 of the circuit board 56 via the anisotropic conductive film 55, the thermocompression bonding tool 58 is used from above the IC chip 50 via the buffer material 60. Heat and press. By the heat pressing by the thermocompression bonding tool 58, the binder resin of the anisotropic conductive film 55 is melted and flows from between the input / output bumps 51, 53 and the electrode terminals 57 of the circuit board 56, and each input / output. Conductive particles are sandwiched between the bumps 51 and 53 and the electrode terminal 57 of the circuit board 56, and in this state, the binder resin is thermally cured. As a result, the IC chip 50 is electrically and mechanically connected to the circuit board 56.

JP 2014-222701 A

  In recent years, electronic components on which electronic components are mounted and circuit boards on which electronic components are mounted have become smaller, thinner, and more integrated, and the mounting area for electronic components has been reduced, and input / output bumps such as IC chips have been developed. Also, the space between adjacent bumps is required to be narrowed. Even in such a case, it is required to maintain the capture rate of the conductive particles captured by the input / output bumps and to reduce the risk of shorting between the bumps due to the aggregation of the conductive particles in the space between the bumps. Further, in order to ensure the reliability of electrical connection of electronic components when an external stress is applied, improvement in adhesive strength is also desired.

  In addition, from the viewpoint of reducing the material for the input / output bumps, shortening the plating deposition time, reducing the thickness of the electronic component, and reducing the cost, there is a demand for a reduction in the height of the input / output bumps. However, if an attempt is made to reduce the height of the input / output bumps, the space between the bumps is further reduced, and there is a concern about the risk of a short between the bumps.

  The present technology has been made in view of such problems, and an electronic component and an anisotropic connection structure that are improved in particle capture rate, prevention of short circuit, and improvement in adhesive strength while reducing the height of the electrode. It aims at providing the design method of a body and an electronic component.

  In order to solve the above-described problem, an electronic component according to an embodiment of the present technology includes a substrate and a bump formed on one surface of the substrate, and the bump is connected to an electrode of a component to be connected. Is larger than the area of the base portion on the substrate side.

  Further, the anisotropic connection structure according to the present technology includes an anisotropic conductive adhesive in which the second electronic component including the bump of the electronic component and an electrode facing the bump is provided with conductive particles. Are anisotropically connected.

  The electronic component design method according to the present technology is a method for designing an electronic component including a substrate and a bump formed on one surface of the substrate. The bump is connected to an electrode of a connection target component. The area of the connection surface is larger than the area of the base portion on the substrate side.

  According to the present technology, it is possible to suppress the narrowing of the connection area per bump and improve the capture rate of the conductive particles. In addition, according to the present technology, since the space between the adjacent bumps extends toward the base portion, it is possible to suppress the occurrence of a short circuit between the bumps even when the conductive particles are densely packed and the height of the bump is reduced. it can. In addition, according to the present technology, since the binder resin is cured in a bowl shape from the connection surface of the bump to the base, the contact area between the bump and the binder resin is increased, and the anchor effect is exhibited by the binder resin filled to the base. By doing so, adhesive strength can be improved.

1A is a cross-sectional view showing a process of anisotropically connecting an IC chip to a circuit board, and FIG. 1B is a connection in which the IC chip is anisotropically conductively connected to the circuit board. It is sectional drawing which shows a body. FIG. 2 is a plan view showing the IC chip. 3A to 3I are perspective views showing examples of formation of input / output bumps. FIG. 4 is a view showing the output bump 3 through the substrate 2 from the other surface 2 b side of the substrate 2. FIG. 5 is a plan view of the semiconductor wafer. FIG. 6 is a cross-sectional view showing a part of a semiconductor wafer. FIG. 7A is a cross-sectional view showing a step of patterning a resist layer formed on an insulating film of a semiconductor wafer, and FIG. 7B is a cross-sectional view showing a step of forming a through hole in the resist layer. FIG. 7C is a cross-sectional view showing the step of forming the opening in the insulating film. FIG. 8A is a cross-sectional view showing the process of forming the metal layer, FIG. 8B is a cross-sectional view showing the process of removing the resist layer, and FIG. It is sectional drawing which shows the process in which the input-output bump to which this technique was applied was formed. FIG. 9 is a cross-sectional view showing a part of a semiconductor wafer on which input / output bumps are formed. FIG. 10A is a cross-sectional view showing the structure of the anisotropic conductive film, and FIG. 10B shows the structure of the anisotropic conductive film in which the conductive particle-containing layer and the insulating adhesive layer are laminated. It is sectional drawing shown. FIGS. 11A and 11B are diagrams showing an anisotropic conductive film in which conductive particles that are non-contact with each other and are independent of each other are irregularly distributed. FIG. 11A is a plan view and FIG. 11B is a cross-sectional view. 12A and 12B are diagrams showing an anisotropic conductive film in which conductive particles are regularly arranged in a lattice shape, where FIG. 12A is a plan view and FIG. 12B is a cross-sectional view. 13A and 13B are diagrams showing an anisotropic conductive film in which conductive particles are regularly arranged in a hexagonal lattice shape. FIG. 13A is a plan view and FIG. 13B is a cross-sectional view. 14A and 14B are diagrams showing an anisotropic conductive film in which conductive particles are randomly dispersed. FIG. 14A is a plan view and FIG. 14B is a cross-sectional view. FIG. 15 is a cross-sectional view showing a semiconductor device to which the present technology is applied. FIG. 16A is a plan view of an IC chip with bumps, and FIG. 16B is a cross-sectional view showing a connection process.

  Hereinafter, an electronic component, an anisotropic connection structure, and an electronic component design method to which the present technology is applied will be described in detail with reference to the drawings. In addition, this technique is not limited only to the following embodiment, Of course, a various change is possible in the range which does not deviate from the summary of this technique. Further, the drawings are schematic, and the ratio of each dimension may be different from the actual one. Specific dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Hereinafter, the IC chip 1 will be described as an example of the electronic component. As shown in FIGS. 1A and 1B, the connection body 20 has the IC chip 1 mounted on the circuit board 14 via an adhesive such as an anisotropic conductive film (ACF) 30, By heating and pressing the IC chip 1 with the thermocompression bonding tool 10 through the buffer material 15, the output bumps 3 and the input bumps 5 provided on the mounting surface of the IC chip 1 and the output terminals 16 provided on the circuit board 14 and The input terminal 17 is conductively connected.

[IC chip]
The IC chip 1 has a substrate 2, and one surface 2 a of the substrate 2 is a mounting surface on which input / output bumps are arranged and mounted on the circuit substrate 14 via the anisotropic conductive film 30, and is opposite to the one surface 2 a. The other surface 2 b is a pressing surface that is heated and pressed by the thermocompression bonding tool 10.

  The IC chip 1 is an element in which a semiconductor circuit is formed on a substrate 2 made of, for example, a silicon substrate, and input / output bumps 3 and 5 are formed on one surface of the substrate 2. A plurality of IC chips 1 are formed on a silicon wafer and are separated by dicing.

  As shown in FIG. 2, the substrate 2 has a substantially rectangular shape, and an output bump region 4 and an input bump in which output bumps 3 are arranged along a pair of side edges 2c and 2d facing each other in the length direction. An input bump region 6 in which 5 is arranged is formed. In the IC chip 1, the output bump region 4 is formed on one side edge 2 c side of the substrate 2, and the input bump region 6 is formed on the other side edge 2 d side of the substrate 2. Thereby, in the IC chip 1, the output bump region 4 and the input bump region 6 are formed apart from each other in the width direction of the mounting surface 2, and the inter-bump region in which no bump is formed at the center of the mounting surface 2. 7 is provided.

  In the output bump region 4, a plurality of output bumps 3 are arranged along the longitudinal direction of the substrate 2, for example, so that two output bump rows 3 </ b> A and 3 </ b> B are formed in order from one side edge 2 c side. . Further, the output bumps 3 of each of the output bump rows 3A and 3B are arranged in a staggered manner.

  In the input bump area 6, for example, an input bump row 5 </ b> A in which a plurality of input bumps 5 are arranged in a row along the longitudinal direction of the substrate 2 is formed. The input bump 5 is formed larger than the output bump 3. As a result, the IC chip 1 has an output bump area 4 and an input bump area 6 having an area difference and is asymmetrically arranged on the substrate 2. The input / output bumps 3 and 5 may be formed with the same size.

  As the input / output bumps 3 and 5, for example, copper bumps, gold bumps, or copper bumps plated with gold are suitably used. The input / output bumps 3 and 5 are provided in an arrangement corresponding to the input / output terminals 16 and 17 provided on the circuit board 14, and the IC chip 1 is aligned and connected to the circuit board 14. The input / output terminals 16 and 17 are connected through the anisotropic conductive film 30.

  In addition to the arrangement shown in FIG. 2, the input / output bumps 3 and 5 may be arranged in one or more rows on one side edge 2c and in one or more rows on the other side edge 2d. It may be a configuration. In addition, the input / output bumps 3 and 5 may have a plurality of rows in one row arrangement, and a portion of the plurality of rows may be one row. Further, the input / output bumps 3 and 5 may be formed in a straight array in which a plurality of rows are parallel and adjacent electrode terminals are parallel, or a plurality of rows of parallel and adjacent electrode terminals are It may be formed in a staggered arrangement that is shifted evenly.

  With recent downsizing, high functionality, and cost reduction of liquid crystal display devices and other electronic devices, electronic components such as IC chip 1 are also required to be downsized, low profile, and low cost. 3 and 5 are also low in height (although not particularly limited, for example, 3 to 15 μm).

  Here, the input / output bumps 3 and 5 to which the present technology is applied have the area of the connection surfaces 3a and 5a connected to the input / output terminals 16 and 17 of the circuit board 14 via the anisotropic conductive film 30 as the substrate. It is larger than the area of the base portions 3b and 5b on the two sides. The bases 3b and 5b refer to portions protruding from one surface 2a of the substrate 2 among the portions on the substrate 2 side of the bump connection surfaces 3a and 5a, and if there is a portion embedded in the substrate 2, Not included. The base portions 3b and 5b are closer to the substrate 2 than the connection surfaces 3a and 5a, and have a cross-sectional area narrower than the area of the connection surfaces 3a and 5a when the connection direction with the input / output terminals 16 and 17 is the vertical direction. The part which has. That is, the input / output bumps 3 and 5 to which the present technology is applied need only have a portion having a cross-sectional area smaller than the area of the connection surfaces 3a and 5a, and the upper surface standing on the pad 41 is the connection surface. In addition to the case where it is narrower than 3a and 5a, it is also included that a portion having a cross-sectional area larger than the area of the connection surfaces 3a and 5a is provided on the substrate 2 side of the connection surfaces 3a and 5a.

  Thereby, the IC chip 1 can suppress the narrowing of the connection area with the input / output terminals 16 and 17 per one of the input / output bumps 3 and 5 and can improve the capture rate of the conductive particles 32. Further, in the IC chip 1, the space between the adjacent input / output bumps 3, 5 is widened over the base portions 3 b, 5 b, so that the high density packing of the conductive particles 32 and the reduction in the height of the input / output bumps 3, 5 are advanced. Even in this case, the occurrence of a short circuit between the bumps can be suppressed.

  Further, the input / output bumps 3 and 5 are anisotropic because at least a part of the input / output bumps 3 and 5 is reduced inwardly toward the substrate 2 side in the longitudinal section when the connection direction with the input / output terminals 16 and 17 is the vertical direction. When the binder resin 33 of the conductive conductive film 30 is filled between the input / output terminals 16 and 17, it is cured in a bowl shape over the base portions 3b and 5b of the input / output bumps 3 and 5. Therefore, the IC chip 1 has an increased contact area between the input / output bumps 3 and 5 and the binder resin 33, and an anchor effect is exhibited by the binder resin 33 filled over the base portions 3 b and 5 b. The adhesive strength is improved. Further, the connection body 20 can prevent the electronic component from being peeled off and warped or lifted by increasing the filling amount of the binder resin 33 that relieves the stress between the IC chip 1 and the circuit board 14. .

  The input / output bumps 3 and 5 are pressed by the thermocompression bonding tool 10 when the area of the connection surfaces 3a and 5a is larger than the area of the bases 3b and 5b, and the bump height and the aspect of the bases 3b and 5b increase. Therefore, it is preferable to reduce the height of the metal parts that make up the I / O bumps 3 and 5, and to solve problems such as reducing the height of electronic components. become.

  Note that the input / output bumps 3 and 5 have at least a part of the vertical cross section and are reduced in diameter toward the inside of the bump toward the substrate 2 side, so that the area of the connection surfaces 3a and 5a and the area of the bases 3b and 5b are the same. In comparison, the amount of metal used for the input / output bumps 3 and 5 can be reduced, and the cost can be reduced.

  The shape of the input / output bumps 3 and 5 is not particularly limited, and various shapes such as a rectangular parallelepiped shape, a cone shape, and a pyramid shape can be adopted. FIG. 3 lists examples of shapes that the input / output bumps 3 and 5 can take. The input / output bumps 3 and 5 may have a symmetrical shape or a non-target shape when viewed in a longitudinal section. Further, the input / output bumps 3 and 5 may have a shape in which one side extending from the base portions 3b and 5b to the connection surfaces 3a and 5a is a straight line or a curve, or has a step when viewed in a longitudinal section. In addition, the input / output bumps 3 and 5 may have straight sides or non-straight lines, for example, curved lines.

  Further, the shape of the input / output bumps 3, 5 is preferably such that the cross-sectional area increases with regularity from the base portions 3b, 5b to the connection surfaces 3a, 5a. As a result, the IC chip 1 can easily form the input / output bumps 3 and 5, and can easily simulate the effect of pressurization at the time of heat pressing by the thermocompression bonding tool 10. For the same reason, the input / output bumps 3 and 5 may all have the same shape or different side surfaces. When the side shapes are different, it is preferable that the opposite side surfaces are symmetrical.

  In addition, the input / output bumps 3 and 5 may all have the same shape or different shapes in the bumps of the input / output bump rows 3A, 3B, and 5A. Manufacturing efficiency can be improved by making the bumps of the input / output bump rows 3A, 3B, and 5A all have the same shape. For example, the input / output bumps 3 and 5 are formed in the same direction by forming the bases 3b and 5b by cutting the side surfaces of the bumps by inserting cutters along the bump rows 3A and 5A from the side edges 2c and 2d of the substrate 2. The side shape seen from the side becomes the same.

  Further, when the bumps of the input / output bump rows 3A, 3B, 5A have different shapes, for example, when there are bump rows in a plurality of rows such as a staggered row, only the bump rows 3A, 5A on the side edges 2c, 2d side are the base. By forming 3b and 5b and making the areas of the connection surfaces 3a and 5a larger than the areas of the base portions 3b and 5b, the side surfaces of the bump row 3A and the bump row 3B viewed from the same direction can be made non-identical. This increases the degree of freedom in designing the bump layout. As a result, when the number of bumps varies depending on the input / output of the IC chip 1, an effect such as uniformizing the connection strength of the substrate 2 can be expected.

  In addition, when the bump arrangement exists in a plurality of rows such as the staggered arrangement as in the output bump rows 3A and 3B, the resin flow between the bump rows can be facilitated, and the occurrence of a short between the bumps can be suppressed. This means that when the bumps are dense, the space between the bumps is reduced by reducing the diameter of the surface with respect to the dense points. Moreover, if these are combined and the degree of diameter reduction is adjusted, the effect of inducing resin flow can be expected.

  For example, in the output bump rows 3A and 3B shown in FIG. 4, among the output bumps 3 arranged in a staggered manner, the side surfaces on the adjacent bump row side and the three bump side surfaces on the two side surfaces adjacent to the side surfaces are mutually connected. The distance between bumps is close. Therefore, the flow path of the binder resin 33 and the conductive particles 32 is widely provided by setting one or more of the three bump side surfaces to an inclined surface or a curved surface that is reduced in diameter toward the base 3b side, and the output bumps 3, It is possible to suppress the occurrence of a short circuit between the bumps by making it difficult to cause a stay between the three. FIG. 4 is a diagram showing the output bumps 3 that are transmitted through the substrate 2 from the other surface 2 b side of the substrate 2. Further, by allowing one or more of the three bump side surfaces, in which the inter-bump distance between the output bumps 3 arranged in a staggered manner is close, to enter the inside of the bump relatively deeper than the other side surfaces, the binder resin 33 and A wide flow path for the conductive particles 32 may be provided.

  Similarly, when each of a plurality of rows is formed in a straight array in which adjacent electrode terminals are parallel to each other, one or more of the three bump side surfaces including the side surfaces on the adjacent bump row side are directed toward the base 3b side. By providing an inclined surface or a curved surface with a reduced diameter, a wide flow path for the binder resin 33 and the conductive particles 32 is provided, so that the stay between the output bumps 3 and 3 is less likely to occur, and the occurrence of a short circuit between the bumps is suppressed. be able to.

[IC chip / bump formation method]
Next, an example of a bump forming method to which the present technology is applied will be described. First, as shown in FIGS. 5 and 6, a semiconductor wafer 40 is prepared. FIG. 5 is a plan view of the semiconductor wafer 40. The semiconductor wafer 40 constitutes the substrate 2 of the IC chip 1 by being cut into a plurality of semiconductor chips along a cutting line in a later process. The semiconductor chip is often cut into a rectangle, but the shape is not limited to this and may be, for example, a circle.

  The semiconductor wafer 40 has a plurality of pads 41 on which input / output bumps 3 and 5 are formed. The pad 41 becomes an electrode of an integrated circuit formed inside the semiconductor wafer 40. The pad 41 is formed for each region of the IC chip 1 to be separated. The pad 41 is formed on one surface of the semiconductor wafer 40 at the peripheral end (two or four sides) of the area of the IC chip 1 according to the arrangement position of the input / output bumps 3 and 5. The pad 41 is formed outside the region where the integrated circuit is formed (active region) on the surface of the semiconductor wafer 40, but may be formed in a region including the inside of the active region on the surface of the semiconductor wafer 40. .

  Next, input / output bumps 3 and 5 are formed on the pad 41 of the semiconductor wafer 40. The input / output bumps 3 and 5 can be formed by, for example, electrolytic plating, electroless plating, printing, or the like. In an example of the step of forming by an electroless plating method, as shown in FIGS. 7A and 7B, a resist layer 43 is provided over the insulating film 42 and the resist layer 43 is patterned. The resist layer 43 is provided so as to cover the entire surface of the semiconductor wafer 40 including the upper side of the pad 41. The resist layer 43 is set according to the height of the input / output bumps 3 and 5, and may be formed with a thickness of about 10 to 30 μm, for example.

  A portion of the resist layer 43 above the pad 41 is removed to form a through hole 44. The through hole 44 is formed by removing a portion above the pad 41 by applying a photolithography technique to a resist layer 43 formed using a resin that changes its properties in response to energy 45 such as ultraviolet rays. Can be formed. Further, the through hole 44 may be formed by etching the resist layer 43. Alternatively, the resist layer 43 may be formed by applying a resist material so as to directly pattern the through hole 44 by screen printing or an ink jet method.

  The through hole 44 is formed so as to overlap at least a part of the pad 41, and the insulating film 42 is exposed on the bottom surface. By forming the through hole 44 on the wall surface rising vertically with respect to the surface of the semiconductor wafer 40, bumps rising vertically are formed, and the area of the connection surfaces 3a, 5a is reduced to the base portion 3b on the substrate 2 side by cutting or the like. , 5b, the input / output bumps 3, 5 larger than the area can be formed. Further, by forming the through hole 44 on the wall surface whose diameter is enlarged from the bottom surface to the opening by anisotropic etching, the area of the connection surfaces 3a and 5a is larger than the area of the base portions 3b and 5b on the substrate 2 side. Output bumps 3 and 5 can be formed. The planar shape of the through hole 44 may be a rectangle, a circle, or another shape.

  Next, as shown in FIG. 7C, using the resist layer 43 in which the through holes 44 are formed as a mask, a part of the insulating film 42 is removed by etching to form an opening 46, and the pad 41 Expose at least a portion of The etching means may be any of chemical, physical or a combination of these properties. The etching characteristics may be anisotropic such as dry etching or isotropic such as wet etching.

  The opening 46 may be formed with a diameter equal to the diameter of the through hole 44, but may be formed with a smaller diameter. If the diameter of the opening 46 is made smaller than the diameter of the through hole 44, the surface of the pad 41 can be prevented from being exposed by forming the input / output bumps 3, 5 in the through hole 44. Alternatively, the diameter of the opening 46 may be formed to exceed the diameter of the through hole 44 by using, for example, wet etching.

  Note that the surface of the resist layer 43 may be cured by applying energy that causes a crosslinking reaction after or before the etching of the insulating film 42.

  Next, after performing a zincate process, as shown in FIG. 8A, a metal layer 47 (bump) is formed by using an electroless plating method or the like using a through hole 44. The metal layer 47 is composed of a single layer or a plurality of layers. The metal layer 47 may be formed from one or more of nickel, gold, copper, palladium, and tin, or formed from a metal containing at least one selected from Ag, Cu, Bi, and Zn in tin. You may form from several metals among these. For example, the metal layer is a nickel layer, a nickel and gold layer, a nickel and copper layer, a copper layer, a nickel and gold and copper layer, a nickel and copper and tin layer, a nickel and gold and copper and tin layer, The layer may be formed of any one of a layer of nickel, gold, copper, palladium, and tin, or a layer of nickel, palladium, copper, palladium, and tin, but the material is not limited to this. Silver tin or copper tin may be formed instead of tin. Of the plurality of layers, the lowermost layer may be formed of nickel, and the outermost layer may be formed of gold or tin.

  The metal layer 47 is laminated on the pad 41 through the opening 46 of the through hole 44 and is electrically connected. The metal layer 47 is formed so as not to be equal to or exceeding the height of the through hole 44 (thickness of the resist layer 43). The metal layer 47 may be a single layer as shown in the figure, or may be a plurality of layers.

  Next, as shown in FIG. 8C, the input / output bumps 3 and 5 in which the areas of the connection surfaces 3a and 5a are larger than the areas of the bases 3b and 5b on the substrate 2 side are formed. The base portions 3b and 5b having a cross section smaller than the area of the connection surfaces 3a and 5a can be formed on the vertically rising metal layer 47 by, for example, cutting or chemical or physical etching. In addition, you may perform the formation process of the base parts 3b and 5b by cutting, after dividing the semiconductor wafer 40 into each IC chip 1. FIG.

  Further, by forming the through hole 44 on the wall surface whose diameter is enlarged from the bottom surface to the opening by anisotropic etching, the area of the connection surfaces 3a and 5a is larger than the area of the base portions 3b and 5b on the substrate 2 side. The output bumps 3 and 5 may be formed.

  The input / output bumps 3, 5 may form a second metal layer on the surface of the metal layer 47. The second metal layer is formed so as to cover the surface including the side surface of the metal layer 47. Thereby, oxidation of the metal layer 47 (for example, nickel layer) can be prevented. The second metal layer is preferably composed of a single layer or a plurality of layers, and at least the surface thereof is preferably formed of gold or copper. The second metal layer can be formed using a known film formation technique such as electroless plating.

  The top surfaces of the input / output bumps 3 and 5 are connection surfaces 3 a and 5 a that are connected to the input / output terminals 16 and 17 of the circuit board 14 via the anisotropic conductive film 30. The connection surfaces 3a and 5a are formed substantially parallel to the substrate 2 (semiconductor wafer 40). Further, the input / output bumps 3 and 5 formed by plating deposition have unevenness on the connection surfaces 3a and 5a.

  Note that the input / output bumps 3 and 5 may be formed so that the connecting surfaces 3a and 5a are appropriately flat using a known film forming technique. Further, it is preferable that the connecting surface is flat so that the pressure applied to the IC chip 1 is evenly transmitted to the conductive particles 32. Here, “flat” includes unevenness of about 30% of the conductive particle diameter. That is, although there may be a height difference of 1 to 2 μm, it is more preferable that this height difference is smaller.

  FIG. 9 is a cross-sectional view of the semiconductor wafer 40 formed by the above steps. The semiconductor wafer 40 is cut into a plurality of IC chips 1.

[Dummy bump]
In addition, the IC chip 1 may be appropriately provided with so-called dummy bumps that are not used for input / output of signals or the like between the output bump area 4 and the input bump area 6 if restrictions on bump layout and manufacturing man-hours are allowed.

[Circuit board]
The circuit board 14 is selected according to the use of the connection body 20, and the type thereof is not limited, for example, a glass substrate, a glass epoxy substrate, a ceramic substrate, a flexible substrate, or the like. The circuit board 14 has input / output terminals 16 and 17 connected to the input / output bumps 3 and 5 provided on the IC chip 1. The input / output terminals 16 and 17 have the same arrangement as the arrangement of the input / output bumps 3 and 5. The circuit board 14 may be the IC chip 1. In this case, the connection body 20 is obtained by stacking the IC chips 1 in multiple layers.

[Alignment mark]
The IC chip 1 and the circuit board 14 are provided with an alignment mark (not shown) that aligns the IC chip 1 with the circuit board 14 by overlapping the IC chip 1 and the circuit board 14. As the substrate-side alignment mark and the IC-side alignment mark, various marks that can be aligned with the circuit board 14 and the IC chip 1 can be used. Since the wiring pitch of the input / output terminals of the circuit board 14 and the fine pitches of the input / output bumps 3 and 5 of the IC chip 1 are increasing, the IC chip 1 and the circuit board 14 are required to have high-precision alignment adjustment. There are many cases.

[adhesive]
As an adhesive for connecting the IC chip 1 to the circuit board 14, an anisotropic conductive film 30 can be suitably used. As shown in FIG. 10 (A), the anisotropic conductive film 30 is usually one in which a binder resin 33 containing conductive particles 32 is laminated on a base film 31 serving as a base material. As shown in FIG. 1, the anisotropic conductive film 30 connects the circuit board 14 and the IC chip 1 by interposing a binder resin 33 between the circuit board 14 and the IC chip 1. The conductive particles 32 are sandwiched between the bumps 3 and 5 and the input / output terminals 16 and 17 and are used for conduction.

  The adhesive composition of the binder resin 33 is composed of a normal binder component containing, for example, a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, and the like.

  As the film-forming resin, a resin having an average molecular weight of about 10,000 to 80,000 is preferable, and various resins such as an epoxy resin, a modified epoxy resin, a urethane resin, and a phenoxy resin are particularly mentioned. Among these, phenoxy resin is preferable from the viewpoint of film formation state, connection reliability, and the like.

  It does not specifically limit as a thermosetting resin, For example, a commercially available epoxy resin, an acrylic resin, etc. can be used.

  The epoxy resin is not particularly limited. For example, naphthalene type epoxy resin, biphenyl type epoxy resin, phenol novolac type epoxy resin, bisphenol type epoxy resin, stilbene type epoxy resin, triphenolmethane type epoxy resin, phenol aralkyl type epoxy resin. Naphthol type epoxy resin, dicyclopentadiene type epoxy resin, triphenylmethane type epoxy resin and the like. These may be used alone or in combination of two or more.

  There is no restriction | limiting in particular as an acrylic resin, According to the objective, an acrylic compound, liquid acrylate, etc. can be selected suitably. For example, methyl acrylate, ethyl acrylate, isopropyl acrylate, isobutyl acrylate, epoxy acrylate, ethylene glycol diacrylate, diethylene glycol diacrylate, trimethylolpropane triacrylate, dimethylol tricyclodecane diacrylate, tetramethylene glycol tetraacrylate, 2-hydroxy- 1,3-diacryloxypropane, 2,2-bis [4- (acryloxymethoxy) phenyl] propane, 2,2-bis [4- (acryloxyethoxy) phenyl] propane, dicyclopentenyl acrylate, tricyclo Examples include decanyl acrylate, tris (acryloxyethyl) isocyanurate, and urethane acrylate. In addition, what made acrylate the methacrylate can also be used. These may be used individually by 1 type and may use 2 or more types together.

  The latent curing agent is not particularly limited, and examples thereof include a heat curing type curing agent. The latent curing agent does not normally react, but is activated by various triggers selected according to applications such as heat, light, and pressure, and starts the reaction. The activation method of the thermal activation type latent curing agent includes a method of generating active species (cation, anion, radical) by a dissociation reaction by heating, etc., and it is stably dispersed in the epoxy resin near room temperature, and epoxy at high temperature There are a method of initiating a curing reaction by dissolving and dissolving with a resin, a method of initiating a curing reaction by eluting a molecular sieve encapsulated type curing agent at a high temperature, and an elution / curing method using microcapsules. Thermally active latent curing agents include imidazole, hydrazide, boron trifluoride-amine complexes, sulfonium salts, amine imides, polyamine salts, dicyandiamide, etc., and modified products thereof. The above mixture may be sufficient. As the radical polymerization initiator, a known one can be used, and among them, an organic peroxide can be preferably used.

  Although it does not specifically limit as a silane coupling agent, For example, an epoxy type, an amino type, a mercapto sulfide type, a ureido type etc. can be mentioned. By adding the silane coupling agent, the adhesion at the interface between the organic material and the inorganic material is improved.

[Conductive particles]
Examples of the conductive particles 32 contained in the binder resin 33 include any known conductive particles used in anisotropic conductive films. That is, as the conductive particles, for example, particles of various metals and metal alloys such as nickel, iron, copper, aluminum, tin, lead, chromium, cobalt, silver, gold, metal oxide, carbon, graphite, glass, ceramic Examples thereof include those in which the surface of particles such as plastic is coated with metal, or those in which the surface of these particles is further coated with an insulating thin film. In the case where the surface of the resin particle is coated with metal, examples of the resin particle include an epoxy resin, a phenol resin, an acrylic resin, an acrylonitrile / styrene (AS) resin, a benzoguanamine resin, a divinylbenzene resin, a styrene resin, and the like. Can be mentioned. The size of the conductive particles 32 is preferably 1 to 10 μm, but is not limited thereto.

  The adhesive composition constituting the binder resin 33 is not limited to the case where it contains a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, etc. You may make it comprise any material used as an adhesive composition.

Here, an example of the minimum melt viscosity range of the binder resin 33 is 10 to 1 × 10 ⁵ Pa · s. Of course, the minimum melt viscosity range of the binder resin 33 is not limited to this range. The minimum melt viscosity of the binder resin 33 is, for example, a rotary rheometer (TA instrument), a temperature rising rate of 10 ° C./min, a measurement pressure of 5 g, and a measurement plate having a diameter of 8 mm. Then, it can be obtained by measuring.

  The base film 31 that supports the binder resin 33 is coated with a release agent such as silicone on PET (Poly Ethylene Terephthalate), OPP (Oriented Polypropylene), PMP (Poly-4-methylpentene-1), PTFE (Polytetrafluoroethylene), and the like. Thus, the anisotropic conductive film 30 is prevented from drying and the shape of the anisotropic conductive film 30 is maintained.

  The anisotropic conductive film 30 may be produced by any method, but can be produced, for example, by the following method. An adhesive composition containing a film-forming resin, a thermosetting resin, a latent curing agent, a silane coupling agent, conductive particles 32 and the like is prepared. The adjusted adhesive composition is applied onto the base film 31 using a bar coater, a coating device, and the like, and dried by an oven or the like, whereby the anisotropic conductive film 30 in which the binder resin 33 is supported on the base film 31 is obtained. obtain.

  The shape of the anisotropic conductive film 30 is not particularly limited. For example, as shown in FIG. 10, the shape of the anisotropic conductive film 30 is a long tape shape that can be wound around the take-up reel 37, and is used by cutting a predetermined length. can do. The anisotropic conductive film 30 may be laminated with a release film (not shown) on the surface of the binder resin 33 that is not supported by the base film 31.

[Conductive particle non-contact ACF / arrangement type ACF]
Here, as the anisotropic conductive film 30, a film in which conductive particles 32 that exist independently of each other in a non-contact manner in a plan view are ubiquitous can be suitably used. This is preferably such that 95% or more of the total number of conductive particles are present independently, and more preferably 99% or more are present independently. A unit in which a plurality of conductive particles 32 are intentionally brought into contact is counted as one unit. Further, such a state in which the conductive particles 32 exist independently without being in contact with each other may be created by intentionally disposing the conductive particles 32 at predetermined positions.

  For example, as shown in FIGS. 11A and 11B, the conductive particles 32 that are not in contact with each other and independent of each other are ubiquitous in the binder resin 33 in a state in which the distance between the particles is irregular in a plan view. That is, it may exist at different distances depending on the direction. In addition, the conductive particles 32 are arranged in a predetermined arrangement pattern, and are regularly arranged in a tetragonal lattice pattern or a hexagonal lattice pattern as shown in FIGS. By arranging them regularly, they may be present independently of each other in a plan view. The arrangement pattern of the conductive particles 32 can be arbitrarily set.

  When the conductive particles 32 exist independently of each other in a non-contact manner with a distance between the conductive particles according to the bump area and layout in a plan view, the anisotropic conductive film 30 is formed as shown in FIGS. ), The conductive particles 32 are supplemented by the individual conductive particles 32 as compared with the case where the conductive particles 32 are randomly dispersed and the density of the conductive particles is reduced due to the formation of aggregates. Therefore, when the same highly integrated IC chip 1 is anisotropically connected, the blending amount of the conductive particles 32 can be reduced. As a result, when the conductive particles 32 are randomly dispersed, the number of conductive particles is required to be equal to or larger than a certain amount, so that aggregates and connections are generated in the spaces between adjacent input bumps 3 and output bumps 5. Although there was a concern, the occurrence of such a short circuit between the bumps can be suppressed by making them in a non-contact and independent state in plan view, and the input / output bumps 3 and 5 and the input / output terminals 16 and 17 can be suppressed. It is possible to reduce the number of conductive particles 32 that do not contribute to conduction between them.

  In addition, since the particle number density of the conductive particles 32 can be reduced, the IC chip 1 can reduce the height of the input / output bumps 3 and 5, realizing further downsizing and thinning, Resistance when pressed by the thermocompression bonding tool 10 can be improved. In other words, since the number density of the conductive particles 32 is low, the connection body 20 can reduce the risk of occurrence of a short circuit between the bumps even in the space between the narrow input / output bumps 3 and 5. it can. Accordingly, the connection body 20 can capture particles even between the input / output bumps 3 and 5 and the input / output terminals 16 and 17 that have been fine pitched, and can reduce the occurrence of a short circuit between the bumps.

  Further, as described above, since the space between the adjacent input / output bumps 3 and 5 spreads over the base portions 3b and 5b, the particle number density of the conductive particles 32 decreases, so that the input / output bumps 3 and 5 can be reduced. The occurrence of shorting between the bumps can be suppressed even when the profile is advanced, and the aspect between the bump height and the base portions 3b and 5b is reduced, so that the resistance when pressed by the thermocompression bonding tool 10 is reduced. Can be improved.

  Further, the anisotropic conductive film 30 has conductive particles 32 that are non-contact and independent from each other in a plan view, so that the conductive particles in the film plane can be obtained even when the binder resin 33 is filled with high density. 32 is prevented from occurring. Therefore, according to the anisotropic conductive film 30 in which the conductive particles 32 are arranged independently without being in contact with each other, the conductive particles are also present at the fine pitched input / output terminals 16 and 17 and the input / output bumps 3 and 5. The capture rate of 32 can be improved.

  Such an anisotropic conductive film 32 is obtained by, for example, applying a pressure-sensitive adhesive on a stretchable sheet, arranging the conductive particles 32 thereon as a single layer, and then stretching the sheet at a desired stretch ratio. A method of transferring to the binder resin 33, a method of transferring the conductive particles 32 to the binder resin 33 supported by the base film 31 after aligning the conductive particles 32 in a predetermined arrangement pattern on the substrate, or a base film 31. The conductive particles 32 can be manufactured by a method of supplying the conductive particles 32 on the binder resin 33 supported by the substrate through an array plate provided with openings corresponding to the array pattern.

[Laminated ACF]
Here, as shown in FIG. 10B, the anisotropic conductive film according to the present technology has a conductive resin composed of an insulating adhesive layer 34 made of only a binder resin 33 and a binder resin 33 containing conductive particles 32. It is preferable that the conductive particle content layer 35 is laminated. In the anisotropic conductive film 36 shown in FIG. 10B, an insulating adhesive layer 34 is laminated on the base film 31, and a conductive particle-containing layer 35 is laminated on the insulating adhesive layer 34. The layer 35 side is attached to the circuit board 14, and the IC chip 1 is mounted from the insulating adhesive layer 34 side. The anisotropic conductive film 36 is used by laminating a release film (not shown) on the conductive particle-containing layer 35 and winding it in a reel shape.

  In the anisotropic conductive film 36, the fluidity of the insulating adhesive layer 34 is such that, for example, the minimum melt viscosity of the insulating adhesive layer 34 is lower than the minimum melt viscosity of the conductive particle-containing layer 35. Higher than 35 fluidity. Therefore, when the anisotropic conductive film 36 is interposed between the circuit board 14 and the IC chip 1 and heated and pressed by the thermocompression bonding tool 10, first, the insulating adhesive layer 34 having a low melt viscosity is formed. And the IC chip 1 are filled. Since the conductive particle-containing layer 35 having a high melt viscosity has low fluidity, the flow of the conductive particles 32 is suppressed even when the binder resin 33 is melted between the circuit board 14 and the IC chip 1 by heating and pressing. The Moreover, the flow of the conductive particles 32 is also suppressed when the insulating adhesive layer 34 that has flowed first and filled between the circuit board 14 and the IC chip 1 starts a curing reaction. Therefore, the connection body 20 can reduce the occurrence of short between bumps without the conductive particles 32 aggregating between the adjacent output bumps 3 or between the input bumps 5.

As an example of the minimum melt viscosity range of the insulating adhesive layer 34, the conductive particle-containing layer 35, and the anisotropic conductive film 36, the minimum melt viscosity range of the insulating adhesive layer 34 is 1 to 1 × 10 ^4. Pa · s, the lowest melt viscosity range of the conductive particle-containing layer 35 is 10 to 1 × 10 ⁵ Pa · s, and the lowest melt viscosity range of the entire anisotropic conductive film 36 is 10 to 1 × 10 ⁵ Pa · s. . Of course, the minimum melt viscosity ranges of the insulating adhesive layer 34, the conductive particle-containing layer 35, and the anisotropic conductive film 36 are not limited to the ranges given here. The minimum melt viscosity of the insulating adhesive layer 34, the conductive particle-containing layer 35, and the anisotropic conductive film 36 can be obtained by measuring in the same manner as the binder resin 33 described above.

  The anisotropic conductive film 36 may be one in which only the conductive particle-containing layer 35 is laminated. In this case, the fluidity of each conductive particle-containing layer 35 may be the same or different.

  In addition, as shown in FIGS. 11 to 13, the anisotropic conductive film 36 was arranged by arranging the conductive particles 32 in the conductive particle-containing layer 35 independently in a non-contact manner in a plan view. Between the input / output bumps 3 and 5 and the input / output terminals 16 and 17 which are made fine pitch with the flow of the conductive particles 32 suppressed, the particle capture rate is improved and the output bumps 3 adjacent to the conductive particles 32 are also provided. The occurrence of a short between bumps can be reduced without agglomeration between the gaps and between the input bumps 5.

  In the above-described embodiment, as an anisotropic conductive adhesive, an example of an adhesive film obtained by forming a thermosetting resin composition appropriately containing conductive particles 32 in a binder resin 33 into a film shape has been described. The adhesive which concerns on this technique is not limited to this, For example, the insulating adhesive film which consists only of binder resin 33 may be sufficient. The anisotropic conductive adhesive is not limited to an adhesive film formed by such a film, but only from a conductive adhesive paste in which conductive particles 32 are dispersed in a binder resin composition, or only from a binder resin composition. It is good also as an insulating adhesive paste. The anisotropic conductive adhesive according to the present technology includes any of the forms described above.

[Connection process]
Next, a connection process for connecting the IC chip 1 to the circuit board 14 will be described. First, the anisotropic conductive film 30 is temporarily attached on the mounting surface of the circuit board 14 on which the input / output terminals 16 and 17 are formed. Next, the circuit board 14 is placed on the stage of the connection device, and the IC chip 1 is placed on the mounting surface of the circuit board 14 via the anisotropic conductive film 30.

  When the anisotropic conductive film 36 in which the conductive particle-containing layer 35 and the insulating adhesive layer 34 are laminated is used, the conductive particle-containing layer 35 side is attached to the circuit board 14 and the edge adhesive layer 34 is attached. The IC chip 1 is arranged from the side.

  Next, the thermocompression bonding tool 10 heated to a predetermined temperature for curing the binder resin 33 is heated at a predetermined pressure and time on the other surface 2b of the substrate 2 serving as a pressing surface of the IC chip 1 through the buffer material 15. Pressurize. As a result, the binder resin 33 of the anisotropic conductive film 30 exhibits fluidity and flows out from between the IC chip 1 and the circuit board 14, and the conductive particles 32 in the binder resin 33 form the output bumps 3 and the output terminals. 16 and between the input bump 5 and the input terminal 17 and are crushed.

  At this time, according to the IC chip 1 to which the present technology is applied, the binder resin 33 of the anisotropic conductive film 30 fills the base portions 3b and 5b of the input / output bumps 3 and 5 as well. In the anisotropic conductive film 36 in which the insulating adhesive layer 34 and the conductive particle-containing layer 35 are laminated, the low melt viscosity insulating adhesive layer 34 is first formed between the IC chip 1 and the circuit board 14. In addition to filling in between, the base portions 3b and 5b are filled to suppress the inflow of the conductive particles 32. As a result, the conductive particles 32 are captured between the input / output bumps 3 and 5 and the input / output terminals 16 and 17 that have been fine pitched, and are aggregated in the space between the adjacent input / output bumps 3 and 5. No short between bumps is prevented.

  As a result, the IC chip 1 and the circuit board 14 are electrically connected by sandwiching the conductive particles 32 between the input / output bumps 3 and 5 and the input / output terminals 16 and 17. The binder resin 33 heated by 10 is cured, and the connection body 20 is formed.

  In the connection body 20, conductive particles 32 that are not between the input / output bumps 3, 5 and the input / output terminals 16, 17 of the circuit board 14 are dispersed in the binder resin 33, and are maintained in an electrically insulated state. ing. Thereby, electrical continuity is achieved only between the output bumps 3 and the input bumps 5 of the IC chip 1 and the input / output terminals 16 and 17 of the circuit board 14. In addition, by using a fast curing type radical polymerization reaction system as the binder resin, the binder resin can be rapidly cured even with a short heating time. Further, the anisotropic conductive films 30 and 36 are not limited to the thermosetting type, and may be a photo-curing type or a photo-heat combined type adhesive as long as pressure connection is performed.

  In such a connection body 20, since the area of the connection surfaces 3a and 5a of the input / output bumps 3 and 5 is larger than the area of the base portions 3b and 5b, the connection area with the individual input / output terminals 16 and 17 is provided. It is possible to improve the capture rate of the conductive particles 32. Further, in the IC chip 1, the space between the adjacent input / output bumps 3, 5 is widened over the base portions 3 b, 5 b, so that the high density packing of the conductive particles 32 and the reduction in the height of the input / output bumps 3, 5 are advanced. Even in this case, the occurrence of a short circuit between the bumps can be suppressed.

  Further, the input / output bumps 3 and 5 are anisotropic because at least a part of the input / output bumps 3 and 5 is reduced inwardly toward the substrate 2 side in the longitudinal section when the connection direction with the input / output terminals 16 and 17 is the vertical direction. When the binder resin 33 of the conductive conductive film 30 is filled between the input / output terminals 16 and 17, it is cured in a bowl shape over the base portions 3b and 5b of the input / output bumps 3 and 5. Therefore, the IC chip 1 has an increased contact area between the input / output bumps 3 and 5 and the binder resin 33, and an anchor effect is exhibited by the binder resin 33 filled over the base portions 3 b and 5 b. The adhesive strength is improved.

  Further, the increase in the filling amount of the binder resin 33 further relaxes the stress between the circuit board 14 and the IC chip 1 due to the binder resin 33, and it is possible to prevent peeling of the electronic component, and prevention of warping and floating. . Therefore, when the circuit board 14 constitutes a transparent substrate of a display panel such as an LCD panel, for example, the influence of the warp on the display unit can be suppressed and display unevenness can be prevented.

  Further, by reducing the height of the input / output bumps 3 and 5, the bump height and the aspect of the base portions 3b and 5b can be reduced. Can be improved.

[Semiconductor device]
The connection body 20 to which the present technology is applied is a semiconductor device in which the IC chip 1 is mounted on a substrate on which a wiring pattern is formed, in addition to a circuit substrate of an electronic device such as an LCD panel to which the IC chip 1 is connected. Such electronic parts may be used.

  FIG. 15 is a diagram illustrating a semiconductor device 21 according to an example of the present embodiment. The semiconductor device 21 includes the IC chip 1 having the input / output bumps 3 and 5 described above, a substrate 23 on which the wiring pattern 22 is formed, and a plurality of external terminals 24.

  The IC chip 1 is face-down bonded to the substrate 23 as a flip chip. In that case, the wiring pattern 22 (land) formed on the substrate 23 and the input / output bumps 3, 5 are electrically connected via the anisotropic conductive film 30.

  The external terminal 24 is electrically connected to the wiring pattern 22 through a through hole (not shown). The external terminal 24 may be a solder ball. The external terminals 24 may be formed through a reflow process by printing solder or the like. Alternatively, the external terminals may be formed by the surface tension at the time of melting using solder cream applied to the mother board side when the mother board is mounted without actively forming the external terminals 24. This semiconductor device is a so-called land grid array type semiconductor device.

1 IC chip, 2 substrate, 2a one side, 2b other side, 2c, 2d side edge, 3 output bump, 4 output bump area, 5 input bump, 6 input bump area, 7 bump area, 9 depression, 9a non-through hole 9b Groove, 10 Non-electrode region, 14 Circuit board, 15 Buffer material, 16 Output terminal, 17 Input terminal, 20 Connector, 30 Anisotropic conductive film, 31 Base film, 32 Conductive particle, 33 Binder resin, 34 Insulating adhesive layer, 35 conductive particle-containing layer, 36 anisotropic conductive film, 40 thermocompression bonding tool

Claims (10)

A substrate, and a bump formed on one surface of the substrate,
The bump is an electronic component in which an area of a connection surface connected to an electrode of a component to be connected is larger than an area of a base portion on the substrate side.   The electronic component according to claim 1, wherein a cross-sectional area of the bump regularly increases from the base portion to the connection surface.   The electronic component according to claim 1, wherein a side of the bump has a straight side.   The electronic component according to claim 1, wherein a side of the side surface of the bump is non-linear.   The electronic component according to any one of claims 1 to 4, wherein a bump row in which a plurality of the bumps are arranged is formed.   The electronic component according to claim 5, wherein each bump in the bump row has the same side surface shape when viewed from the same direction.   The electronic component according to claim 5, wherein each bump in the bump row has a non-identical side shape when viewed from the same direction.   The electronic component according to claim 1, wherein the connection surface is substantially parallel to the substrate.   The bump of the electronic component according to claim 1 and the second electronic component including an electrode opposed to the bump are anisotropically connected by an anisotropic conductive adhesive including conductive particles. An anisotropic connection structure. In a method for designing an electronic component comprising a substrate and a bump formed on one surface of the substrate,
The bump is a method for designing an electronic component in which an area of a connection surface connected to an electrode of a component to be connected is larger than an area of a base portion on the substrate side.

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