JP2014179363A - Semiconductor chip, and semiconductor device comprising the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the strength of bonding between a semiconductor chip, which is flip-chip bonded to a wiring board, and the wiring board.SOLUTION: A semiconductor chip comprises: a bump electrode 110a arranged in the central region of a principal surface of a semiconductor chip 100; and bump electrodes 110b-110d arranged in an outer peripheral region of the principal surface of the semiconductor chip 100. The planar shape of the bump electrode 110a is square, and the planar shapes of the bump electrodes 110b-110d are circular. Because of the shapes, it is possible, with the bump electrodes 110b-110d in which stress concentration hardly occurs, to increase the strength of bonding between the semiconductor chip and a wiring board while maintaining electric characteristics of the bump electrode 110a.

Description

  The present invention relates to a semiconductor chip and a semiconductor device including the semiconductor chip, and more particularly, to a semiconductor chip provided with a bump electrode on a main surface and a semiconductor device including the semiconductor chip.

  Many semiconductor devices include a semiconductor chip and a package that accommodates the semiconductor chip. As one type of such a package, there is a package called a flip chip package (see Patent Document 1). In the flip chip package, a semiconductor chip is mounted on a rigid wiring board by a flip chip method. A semiconductor chip to be mounted needs to have bump electrodes formed in advance on its main surface in order to enable flip chip connection.

JP 2012-146733 A

  However, a semiconductor chip made of silicon or the like and a wiring board made of resin or the like have greatly different coefficients of thermal expansion, so that the wiring board warps when the temperature changes. When the wiring board is warped, some bump electrodes that are flip-chip connected may be peeled off from the wiring board. In order to prevent such a phenomenon, a method of designing the shape and size of each bump electrode so that separation is unlikely to occur can be considered, but the shape and size of the bump electrode is limited by electrical characteristics, arrangement pitch, etc. For this reason, it is difficult to design all the bump electrodes in a shape and size that are unlikely to peel off.

  A semiconductor chip according to an aspect of the present invention includes a first bump electrode disposed in a central region of a main surface and a second bump electrode disposed in an outer peripheral region of the main surface and having a planar shape different from that of the first bump electrode. And a bump electrode.

  A semiconductor chip according to another aspect of the present invention includes first and second sides extending in parallel to a first direction, and a third extending in parallel to a second direction intersecting the first direction. And a fourth surface, and a plurality of first and second bump electrodes provided on the main surface, wherein the plurality of first bump electrodes includes the third side. Between the substantially central portion in the second direction and the substantially central portion in the second direction of the fourth side, and the plurality of second bump electrodes are arranged in the first direction. The planar shapes of the plurality of first bump electrodes arranged in the first direction along the first or second side are the planar shapes of the plurality of second and third bump electrodes. It is characterized by being different.

  A semiconductor device according to the present invention includes the semiconductor chip described above and a wiring board on which the semiconductor chip is mounted. The wiring board is provided on one surface of the insulating base and the insulating base. A first connection electrode bonded to one bump electrode, a second connection electrode provided on the one surface of the insulating base material and bonded to the second bump electrode, and the other of the insulating base material And a plurality of external terminals electrically connected to at least the first connection electrode.

  According to the present invention, since the planar shape of the bump electrode differs depending on the formation position on the main surface, the planar shape of the bump electrode can be optimized according to the required characteristics.

1 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to an embodiment of the present invention. 3 is a schematic plan view for explaining a layout of bump electrodes 110 provided on a semiconductor chip 100. FIG. 2 is a schematic plan view showing a pad electrode 120. FIG. FIG. 3 is a schematic cross-sectional view along the line AA ′ shown in FIG. 2. It is a schematic plan view for explaining the shape of bump electrodes 110a to 110c. FIG. 6 is a schematic cross-sectional view along the line BB ′ shown in FIG. 5. It is a schematic sectional view showing the shape of a bump electrode 110X. It is a schematic sectional view for explaining a state in which a solder layer 113 is melted. It is a schematic sectional view showing the shape of a modified example of the bump electrode 110X. It is a schematic sectional drawing which shows the shape of another modification of bump electrode 110X. 4 is a schematic plan view for explaining a conductive pattern formed on one surface 210a of an insulating base 210. FIG. It is a figure which shows an example of the layout of the external terminal 260 provided in the other surface 210b of the insulating base material 210. FIG. 4 is a schematic diagram for explaining an example of a connection relationship between a semiconductor chip 100 and a wiring board 200. FIG. 6 is a schematic diagram for explaining another example of the connection relationship between the semiconductor chip 100 and the wiring substrate 200. FIG. 5 is a process diagram for explaining a production process of a bump electrode 110. FIG. 5 is a process diagram for explaining a production process of a bump electrode 110. FIG. 6 is a process diagram for explaining a process of flip-chip mounting the semiconductor chip 100 on the wiring board 200. FIG. It is a schematic sectional drawing for demonstrating the structure of the semiconductor chip 100a used in 2nd Embodiment. It is a schematic plan view for explaining the shape of bump electrodes 110a to 110c. FIG. 20 is a schematic cross-sectional view along the line CC ′ shown in FIG. 19. It is a typical top view for demonstrating the 1st example of the relationship between the pad electrode 120b and the uppermost wiring layer. It is a typical top view for explaining the 2nd example of the relation between pad electrode 120b and the uppermost wiring layer.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic cross-sectional view for explaining the structure of a semiconductor device 10 according to an embodiment of the present invention.

  As shown in FIG. 1, the semiconductor device 10 according to the present embodiment includes a semiconductor chip 100 and a wiring board 200 on which the semiconductor chip 100 is flip-chip mounted. The semiconductor chip 100 is a one-chip device in which a large number of elements such as transistors are integrated on a semiconductor substrate made of silicon (Si) or the like. The type of the semiconductor chip 100 is not particularly limited, and may be a memory device such as a DRAM (Dynamic Random Access Memory), or a logic device such as a CPU (Central Processing Unit), or a sensor. It may be an analog device such as.

  The wiring board 200 is formed on the insulating base 210 made of glass epoxy having a thickness of 0.2 mm, for example, the connection electrode 220 formed on one surface 210a of the insulating base 210, and the other surface 210b of the insulating base 210. The land pattern 230 is provided. The connection electrode 220 and the land pattern 230 are connected to each other via a wiring pattern 240 provided on the insulating substrate 210. The wiring pattern 240 may be formed on one or the other surface of the insulating base 210 or may be formed on the inner layer of the insulating base 210. Of the one surface and the other surface of the insulating base 210, a portion where the connection electrode 220 and the land pattern 230 are not formed is covered with the solder resist 250. The connection electrode 220 is an electrode to which the bump electrode 110 provided on the semiconductor chip 100 is bonded. The land pattern 230 is connected to an external terminal 260 made of a solder ball. An underfill 270 is filled between the wiring substrate 200 and the semiconductor chip 100, and a sealing resin 280 is provided so as to cover the semiconductor chip 100.

  In the present embodiment, four types of bump electrodes 110 are provided on the semiconductor chip 100. The first type of bump electrode 110 a is provided in a substantially central region of the semiconductor chip 100 and is electrically connected to the external terminal 260 via the wiring pattern 240. The second type of bump electrode 110 b is provided in the vicinity of the outer peripheral region of the semiconductor chip 100 and is electrically connected to the external terminal 260 through the wiring pattern 240. The third type of bump electrode 110 c is provided in the vicinity of the outer peripheral region of the semiconductor chip 100, but is not electrically connected to any external terminal 260. The fourth type of bump electrode 110 d is a dummy bump electrode provided in the vicinity of the outer peripheral region of the semiconductor chip 100 and is not electrically connected to any external terminal 260. As shown in FIG. 1, the pad electrode 120 is provided on the base of the bump electrodes 110a to 110c, but the pad electrode corresponding to the dummy bump electrode 110d is not provided, and the outermost layer of the semiconductor chip 100 is formed. It is formed on the upper surface of the covering protective film 130.

  FIG. 2 is a schematic plan view for explaining the layout of the bump electrodes 110 provided on the semiconductor chip 100. FIG. 3 is a schematic plan view showing the pad electrode 120 that is the base of the bump electrode 110. FIG. 4 is a schematic cross-sectional view taken along the line AA ′ shown in FIG.

  As shown in FIG. 2, the bump electrodes 110 a are arranged in two rows in the X direction at a substantially central portion in the Y direction of the semiconductor chip 100. More specifically, the main surface of the semiconductor chip 100 includes first and second sides L1 and L2 extending in parallel to the X direction and third and fourth sides extending in parallel to the Y direction. L3 and L4, and the first bump electrode 110a is 2 in the X direction between a substantially central portion in the Y direction of the third side L3 and a substantially central portion in the Y direction of the fourth side L4. Arranged in columns. The bump electrode 110a is used for signal input / output and external power supply potential supply. As shown in FIGS. 2 to 4, the pad electrode 120a corresponding to the bump electrode 110a has a slightly larger planar size than the bump electrode 110a.

  On the other hand, the bump electrodes 110 b to 110 d are arranged in the vicinity of the outer peripheral region of the semiconductor chip 100. That is, the bump electrodes 110b to 110d are arranged in the X direction along the first and second sides L1 and L2. The bump electrode 110b is used for supplying an external power supply potential, and the bump electrode 110c is used for connection to a bridge wiring described later. As shown in FIGS. 3 and 4, the pad electrodes 120b and 120c corresponding to the bump electrodes 110b and 110c have a slightly smaller planar size than the corresponding bump electrodes 110b and 110c. These bump electrodes 110b and 110c play a role of increasing the bonding strength between the semiconductor chip 100 and the wiring board 200 in addition to the functions described above.

  That is, the semiconductor chip 100 made of silicon or the like and the wiring board 200 made of resin or the like have greatly different coefficients of thermal expansion, so that the wiring board 200 is warped when the temperature changes, and the semiconductor chip 100 is peeled off from the wiring board 200. There is a fear. In order to prevent such a phenomenon, the bump electrodes 110b and 110c are disposed in the vicinity of the outer peripheral region of the semiconductor chip 100 where peeling is likely to occur, thereby increasing the bonding strength between the two. The dummy bump electrode 110d is used exclusively for the purpose of increasing the bonding strength. Therefore, as shown in FIGS. 3 and 4, the pad electrode corresponding to the dummy bump electrode 110d is unnecessary.

  FIG. 5 is a schematic plan view for explaining the shapes of the bump electrodes 110a to 110c, and FIG. 6 is a schematic cross-sectional view taken along the line BB 'shown in FIG.

  As shown in FIG. 5, the planar shape of the bump electrode 110a is a square, whereas the planar shape of the bump electrodes 110b and 110c is a circle. Although not shown, the dummy bump electrode 110d also has a circular planar shape. Here, the length of one side of the bump electrode 110a and the diameter of the bump electrodes 110b and 110c are designed to be substantially equal. For this reason, the bump electrode 110a has a larger cross-sectional area in the direction parallel to the main surface of the semiconductor chip 100 than the bump electrodes 110b and 110c. This means that the square bump electrodes 110a arranged at a predetermined interval (pitch) can be arranged with the closest density and lower resistance than the bump electrodes 110b and 110c.

  Further, the planar shape of the pad electrode 120a corresponding to the bump electrode 110a is also quadrangular, and its size is slightly larger than that of the bump electrode 110a. For this reason, the outer peripheral part of the pad electrode 120a is not covered with the bump electrode 110a. In contrast, the planar shape of the pad electrodes 120b and 120c corresponding to the bump electrodes 110b and 110c is a quadrangle, but the size is smaller than that of the bump electrodes 110b and 110c. For this reason, the pad electrodes 120b and 120c are entirely covered with the bump electrodes 110b and 110c. With the above configuration, the contact resistance between the bump electrode 110a and the pad electrode 120a is lower than the contact resistance between the bump electrodes 110b and 110c and the pad electrodes 120b and 120c. Can be supplied with low resistance.

  One reason that the area of the pad electrode 120a is designed to be large is to enable the probe of the tester to be contacted in order to perform a test in a wafer state. On the other hand, the pad electrodes 120b and 120c are designed to have a small area because they do not come into contact with the probe in the wafer state test. Further, as shown in FIG. 3, the pad electrodes 120b and 120c are arranged in the vicinity of the outer peripheral region of the semiconductor chip 100 which is not the pad area, and it is difficult to secure a large-area pad in the wiring layer. Is also present.

  As described above, the planar shape of the bump electrode 110a is a square, whereas the planar shape of the bump electrodes 110b to 110d is a circle. The reason why the planar shape of the bump electrode 110a is a quadrangle is that the cross-sectional area in the direction parallel to the main surface of the semiconductor chip 100 can be maximized when the plurality of bump electrodes 110a are arranged at a predetermined pitch. . This makes it possible to transmit and receive signals and supply power via the bump electrodes 110a with low resistance. On the other hand, the reason why the planar shape of the bump electrodes 110b to 110d is circular is to increase the bonding strength. That is, if the bump electrodes 110b to 110d have a quadrangular planar shape, when the wiring substrate 200 is warped, stress is concentrated on the corners of the bump electrodes, and peeling is likely to occur from here. On the other hand, when the planar shape of the bump electrodes 110b to 110d is circular, stress is not concentrated at a specific location, so that even if the wiring substrate 200 is warped, peeling is less likely to occur. For this reason, the planar shape of the bump electrodes 110a to 110d is designed as described above. Note that the planar shape of the bump electrodes 110b to 110d is not limited to a circular shape, and any shape is preferable as long as stress concentration hardly occurs. For example, a polygon having both obtuse angles such as a regular hexagon and a regular octagon is also preferable.

  Next, the cross-sectional shape of the bump electrode 110 will be described. As shown in FIG. 6, the bump electrodes 110 a to 110 c include UBM (under barrier metal) layers 111 that are in contact with the pad electrodes 120 a to 120 c, pillar portions 112 that are erected on the UBM layers 111, and pillar portions 112. And a solder layer 113 provided on the end face 112a. The UBM layer 111 is made of a laminated film of Ti and Cu, for example, and the pillar portion 112 is made of Cu, for example. The bump electrodes 110a to 110c shown in FIG. 6 have a quadrangular prism shape or a cylindrical shape, and therefore, the angle formed between the upper end surface 112a and the side surface 112b of the pillar portion 112 is substantially a right angle. Although not shown, the dummy bump electrode 110d has the same structure as the bump electrodes 110a to 110c shown in FIG. 6 except that the corresponding pad electrode 120 does not exist.

  In addition, when making the pillar part 112 of bump electrode 110a, 110b, 110c, 110d by plating, since these are formed simultaneously, bump electrode 110a, 110b, 110c formed on pad electrode 120a, 120b, 120c. The position of the upper end surface 112a of the pillar portion 112 of the insulating film bump electrode 110d is higher than the upper end surface 112a of the pillar portion 112. In this case, the pillar portion 112 of the bump electrode 110d is formed to have a smaller diameter than the pillar portions 112 of the other bump electrodes 110a, 110b, and 110c. Since the pillar portion 112 of the bump electrode 110d has a small diameter, the area of the upper end surface a of the pillar portion 112 is smaller than the area of the upper end portion a of the pillar portion 112 of the other bump electrodes 110a, 110b, and 110c. This is because the height of the solder bump formed thereon after reflow is reduced, and the height of the pillar portion 112 can be absorbed. As a result, the bump electrodes 110a, 110b, 110c, and 110d including the solder layer 113 after reflow have substantially the same height.

  FIG. 7 is a schematic cross-sectional view showing the shape of the improved bump electrode 110X. The bump electrode 110X shown in FIG. 7 has an inverted trapezoidal cross section, and therefore the angle formed by the upper end surface 112a and the side surface 112b of the pillar portion 112 is an acute angle. When the bump electrode 110X having such a shape is used, when the semiconductor chip 100 is flip-chip connected to the wiring substrate 200, the solder layer 113 melted by reflow does not easily go around the side surface 112b of the pillar portion 112. The molten solder layer 113 is deformed into a hemispherical shape as shown in FIG. 8 due to surface tension. However, when the solder layer 113 is thick, the molten solder layer 113 spills from the upper end surface 112a of the pillar portion 112, and the side surface 112b. May wrap around. However, if the angle formed by the upper end surface 112a and the side surface 112b is set to an acute angle, the solder layer 113 is unlikely to wrap around, so that connection failure or short circuit failure due to the spillage of the solder layer 113 can be prevented.

  In order to obtain the above effect, the side surface 112b of the pillar portion 112 does not need to be entirely inclined, and only the upper portion of the side surface 112b in contact with the upper end surface 112a is inclined as shown in FIG. The other parts may be vertical. Alternatively, as shown in FIG. 10, the upper side of the side surface 112 b that is in contact with the upper end surface 112 a is inclined so that the diameter increases as it goes upward, and the lower side of the side surface 112 b that is in contact with the UBM layer 111 is downward. The spindle shape may be inclined in the direction in which the diameter increases. In short, it is sufficient that the angle formed by the upper end surface 112a of the pillar portion 112 and the side surface 112b in the portion in contact with the pillar portion 112 is an acute angle.

  FIG. 11 is a schematic plan view for explaining a conductive pattern formed on one surface 210 a of the insulating base 210. A broken line 100 </ b> X illustrated in FIG. 11 is a mounting area of the semiconductor chip 100.

  As shown in FIG. 11, a plurality of connection electrodes 220, a plurality of wiring patterns 240, and two bridge wirings 290 are provided on one surface 210 a of the insulating base 210. More specifically, of the connection electrodes 220, the connection electrode 220 a bonded to the bump electrode 110 a is connected to the through-hole conductor 221 through the wiring pattern 240. The through-hole conductor 221 is a conductor provided through the insulating base 210 and is connected to the land pattern 230 and the external terminal 260 provided on the other surface 210 b of the insulating base 210.

  FIG. 12 is a diagram illustrating an example of the layout of the external terminals 260 provided on the other surface 210 b of the insulating base 210. As shown in FIG. 12, the other surface 210b of the insulating base 210 is provided with a wiring pattern 240 that connects the through-hole conductor 221 and the land pattern 230 (external terminal 260).

  Returning to FIG. 11, of the connection electrodes 220, the connection electrodes 220 c joined to the bump electrodes 110 c are commonly connected via the bridge wiring 290. The bridge wiring 290 is not connected to the other wiring pattern 240 and is therefore not connected to any external terminal 260. By such a bridge wiring 290, the plurality of bump electrodes 110c are electrically short-circuited with each other.

  The bump electrode 110b and the dummy bump electrode 110d are directly connected to the large-area power supply pattern 241 provided on one surface 210a of the insulating base 210.

  FIG. 13 is a schematic diagram for explaining a connection relationship between the semiconductor chip 100 and the wiring substrate 200.

  As shown in FIG. 13, the semiconductor chip 100 includes an internal voltage generation circuit 140 that generates an internal power supply potential VINT. The internal voltage generation circuit 140 receives external power supply potentials VDD and VSS supplied via the external terminal 260 and generates the internal power supply potential VINT based on the external power supply potentials VDD and VSS. Since the internal power supply potential VINT is a potential generated inside the semiconductor chip 100 and is not supplied from the outside, the capability of the internal voltage generation circuit 140 is designed based on the load of the circuit using the internal power supply potential VINT. . However, in the case where the circuits using the internal power supply potential VINT are dispersedly arranged in the semiconductor chip 100 or the internal power supply potential VINT is used in many circuits, the internal power supply depends on the planar position in the semiconductor chip 100. The potential drop of the potential VINT may increase. Such a potential drop is designed to be reduced as much as possible by constructing the power supply wiring network in the semiconductor chip 100 in a mesh shape. However, in the semiconductor chip 100 that has been increased in speed and functionality, the potential is reduced. The decrease may not be sufficiently suppressed.

  In the present embodiment, the wiring for supplying such an internal power supply potential VINT is bypassed by the bridge wiring 290. In other words, not only the power supply wiring network in the semiconductor chip 100 but also the bridge wiring 290 provided on the wiring substrate 200 is additionally used to reduce the impedance of the wiring for supplying the internal power supply potential VINT. In addition, since the bridge wiring 290 is a wiring provided on the wiring board 200 side, the film thickness thereof is much thicker than the wiring provided inside the semiconductor chip 100. For this reason, the bridge wiring 290 has a very low resistance. By using the bridge wiring 290 to bypass the wiring for supplying the internal power supply potential VINT, the potential drop of the internal power supply potential VINT can be greatly reduced. Is possible.

  However, the wiring bypassed using the bridge wiring 290 in the present invention is not limited to the wiring that supplies the internal power supply potential VINT. For example, as shown in FIG. 14, it is possible to connect a wiring for supplying the external power supply potential VSS to the bump electrode 110 c inside the semiconductor chip 100, thereby bypassing the wiring by a bridge wiring 290. This is because, for example, when circuits 150A that are easily affected by power supply noise are distributed and there are circuits 150B that can be a source of power supply noise, the power supply wiring is connected to the bump electrode 110c in the vicinity of each circuit 150A. Thus, if the power supply wiring is bypassed between the plurality of circuits 150A, the influence of noise can be reduced.

  Next, a manufacturing process of the bump electrode 110 will be described.

  FIGS. 15A to 15D and FIGS. 16A to 16C are process diagrams for explaining a manufacturing process of the bump electrodes 110a and 110c.

  First, as shown in FIG. 15A, the uppermost wiring layer included in the semiconductor chip 100 is patterned to form pad electrodes 120a and 120c. As a material for the pad electrodes 120a and 120c, aluminum is preferably used. Thereafter, the pad electrodes 120a and 120c are covered with a protective film 130 made of a passivation film or a polyimide film so that a part of the pad electrodes 120a and 120c is exposed. The reason why the sizes of the pad electrode 120a and the pad electrode 120c are different depends on whether or not it is necessary to contact the probe of the tester as already described. The test using the probe is performed in the state shown in FIG.

  Next, as shown in FIG. 15B, the UBM layer 111 is formed on the entire surface. The UBM layer 111 can be formed by sputtering Ti and Cu in this order. Next, as shown in FIG. 15C, a resist film 160 is formed on the surface of the UBM layer 111. The thickness of the resist film 160 is not particularly limited, but is, for example, about 20 μm.

  Next, as shown in FIG. 15D, a mask M in which an opening having a predetermined pattern is formed is placed on the semiconductor chip 100, and exposure and development are performed, whereby openings 160a, 160c is formed. Although a positive resist is illustrated here, a negative resist may be used. The openings 160a and 160c are provided at positions where the bump electrodes 110a and 110c are to be formed. In the example shown in FIG. 15D, the inner walls of the openings 160a and 160c are substantially vertical. However, the inner walls of the openings 160a and 160c can be inclined by adjusting the focus position during exposure.

  Next, as shown in FIG. 16A, the pillar portion 112 and the solder layer 113 are formed on the UBM layer 111 exposed at the openings 160a and 160c by performing electroplating. Then, after removing the resist film 160 as shown in FIG. 16B, the UBM layer 111 that is not covered by the pillar portion 112 is removed as shown in FIG. 110c is completed. When the inner walls of the openings 160a and 160c are inclined by adjusting the focus position, the bump electrodes 110a and 110c also have a cross-sectional shape reflecting this, and the bump electrode 110X shown in FIGS. 7 to 10 is manufactured. It becomes possible to do.

  In the above description, the bump electrodes 110a and 110c are formed simultaneously, but it goes without saying that the other bump electrodes 110b and 110d are formed at the same time. As already described, the dummy bump electrode 110d is formed on the protective film 130 because the corresponding pad electrode 120 does not exist. After the bump electrodes 110a to 110d are formed, when the semiconductor chip 100 is reflowed at a predetermined temperature, for example, about 240 ° C., the solder layer 113 is melted, and the solder layer 113 becomes hemispherical due to surface tension.

  The above process may be performed on each semiconductor chip 100, but is normally performed on a large number of semiconductor chips 100 in a wafer state. After the above steps are completed, the semiconductor chip 100 is separated into pieces by dicing the wafer. The separated semiconductor chip 100 is flip-chip mounted on the wiring board 200 as described below.

  FIG. 17A to FIG. 17E are process diagrams for explaining a process of flip-chip mounting the semiconductor chip 100 on the wiring substrate 200.

  First, as shown in FIG. 17A, a large-area insulating base 210X on which a plurality of semiconductor chips 100 can be mounted is prepared, and connection electrodes 220, land patterns 230, solder resists 250, and the like are formed on both surfaces thereof. . In addition, the broken line D shown to Fig.17 (a) is a dicing line cut | disconnected by a subsequent process. Next, as shown in FIG. 17B, the semiconductor chip 100 is bonded to the mounting region defined on the surface of the insulating base 210 by flip chip bonding.

  The flip chip bonding is performed in a state in which the bump electrode 110 provided on the semiconductor chip 100 and the connection electrode 220 provided on the insulating base 210 are joined to each other. Specifically, the back surface of the semiconductor chip 100 is sucked and held with a bonding tool (not shown), and the bump electrode 110 and the connection electrode 220 are joined while applying a load at a high temperature of about 240 ° C. Thereafter, the underfill 270 is filled in the gap between the wiring substrate 200 and the semiconductor chip 100. The underfill 270 is supplied to a position near the end of the semiconductor chip 100 by a dispenser (not shown), for example, so that the supplied underfill material is filled in a gap between the wiring substrate 200 and the semiconductor chip 100 by capillary action. The

  After the underfill 270 is filled, the underfill 270 is cured by curing at a predetermined temperature, for example, about 150 ° C., and a fillet as shown in FIG. 17B is formed. Instead of the underfill 270, NCP (Non Conductive Paste) may be used.

  Next, as shown in FIG. 17C, the entire surface of the wiring substrate 200 is covered with a sealing resin 280 so that the semiconductor chip 100 is embedded, and then, on the land pattern 230 as shown in FIG. External terminals 260 made of solder balls are mounted. Then, as shown in FIG. 17E, if the wiring board 200 is cut along the dicing line D, a plurality of semiconductor devices 10 can be obtained.

  In the above description, the underfill 270 is used to fill the gap between the wiring substrate 200 and the semiconductor chip 100 in advance. However, the gap is filled during molding using a technique such as mold underfill (MUF). Technology may be used.

  As described above, in the semiconductor device 10 according to the present embodiment, the planar shape of the bump electrode 110a disposed in the central region of the main surface of the semiconductor chip 100 is a quadrangle, and is disposed in the outer peripheral region of the main surface of the semiconductor chip 100. Since the planar shapes of the bump electrodes 110b to 110d thus formed are circular, it is possible to increase the bonding strength between the semiconductor chip 100 and the wiring substrate 200 while maintaining the electrical characteristics.

  Moreover, in the semiconductor device 10 according to the present embodiment, since the wiring wiring 200 is provided with the bridge wiring 290, the plurality of pad electrodes 120 c provided on the semiconductor chip 100 are bypassed by the bridge wiring 290. Thereby, the impedance of an arbitrary wiring connected to the pad electrode 120c, for example, a wiring to which an internal power supply potential is supplied can be greatly reduced.

  Next, a second embodiment of the present invention will be described.

  FIG. 18 is a schematic cross-sectional view for explaining the structure of the semiconductor chip 100a used in the second embodiment.

  As shown in FIG. 18, in the semiconductor chip 100a used in this embodiment, two minute pad electrodes 120b and 120c are assigned to the bases of the bump electrodes 110b and 110c, respectively. Since the other points are the same as those of the semiconductor chip 100 used in the first embodiment, the same elements are denoted by the same reference numerals, and redundant description is omitted. The wiring board 200 used in the present embodiment is the same as that in the first embodiment.

  FIG. 19 is a schematic plan view for explaining the shapes of the bump electrodes 110a to 110c, and FIG. 20 is a schematic cross-sectional view along the line CC 'shown in FIG.

  As shown in FIGS. 19 and 20, the planar shapes of the bump electrodes 110a, 110b, and 110c are the same as those in the first embodiment. However, the number of the pad electrodes 120a corresponding to the bump electrodes 110a is one, whereas the number of the pad electrodes 120b and 120c corresponding to the bump electrodes 110b and 110c is two. These two pad electrodes 120b and 120c are covered with corresponding bump electrodes 110b and 110c, respectively.

  FIG. 21 is a schematic plan view for explaining a first example of the relationship between the pad electrode 120b and the uppermost wiring layer.

  In the example shown in FIG. 21, power wirings 411 to 413 extending in the X direction are provided in the uppermost wiring layer. Among these, the power supply wirings 411 and 413 are wirings supplied with the power supply potential VDD, and the power supply wiring 412 is a wiring supplied with the ground potential VSS. As described above, the wiring to which the power supply potential VDD is supplied and the wiring to which the ground potential VSS is supplied are often arranged alternately.

  In the example shown in FIG. 21, a part of the power supply wiring 412 is used as two pad electrodes 120b. These two pad electrodes 120 b are arranged in the X direction along the power supply wiring 412. The wiring width of the power supply wiring 412 is not particularly enlarged at a portion corresponding to the pad electrode 120b. Therefore, the other power supply wirings 411 and 413 are not pressed by the pad electrode 120b. Moreover, since the two pad electrodes 120b are assigned to one bump electrode 110b, the connection resistance can be reduced even if the planar size of the pad electrode 120b is very small.

  FIG. 22 is a schematic plan view for explaining a second example of the relationship between the pad electrode 120b and the uppermost wiring layer.

  In the example shown in FIG. 22, power supply wirings 421 to 423 extending in the X direction are provided in the uppermost wiring layer. Among these, the power supply wirings 421 and 423 are wirings to which the ground potential VSS is applied, and the power supply wiring 422 is a wiring to which the power supply potential VDD is applied. Thus, also in this example, the wiring to which the power supply potential VDD is applied and the wiring to which the ground potential VSS is applied are alternately arranged.

  In the example shown in FIG. 22, a part of the power supply wiring 421 and a part of the power supply wiring 423 are used as the pad electrode 120b. These two pad electrodes 120b are arranged in the Y direction so as to straddle the power supply wiring 422. The power supply wirings 421 and 423 are not particularly expanded in the width corresponding to the pad electrode 120b. Therefore, the other power supply wiring 422 is not pressed by the pad electrode 120b. In this example, one bump electrode 110b can be assigned to two different power supply wirings 421 and 423. Here, the two different power supply wirings 421 and 423 are wirings to which the same potential is applied, but are wirings formed separately from each other in the uppermost wiring layer. Therefore, they are short-circuited in other wiring layers located in lower layers.

  Thus, according to this embodiment, since the two pad electrodes 120b are assigned to one bump electrode 110b, the connection resistance is reduced even if the planar size of the pad electrode 120b is very small. be able to. Further, as in the example shown in FIG. 22, one bump electrode 110b can be assigned to two different wirings.

  21 and 22, the relationship between the bump electrode 110b and the pad electrode 120b has been described, but the relationship between the bump electrode 110c and the pad electrode 120c is the same.

  As described above, in this embodiment, the same effects as those of the first embodiment described above can be obtained, and two pad electrodes 120b and 120c are assigned to one bump electrode 110b and 110c. Therefore, even if the planar size of these pad electrodes 120b and 120c is very small, the connection resistance can be reduced.

  In this embodiment, two pad electrodes 120b and 120c are assigned to the bump electrodes 110b and 110c, respectively, but three or more pad electrodes 120b and 120c may be assigned. Further, it is not essential to assign the plurality of pad electrodes 120b and 120c to all the bump electrodes 110b and 110c, and the plurality of pad electrodes 120b and 120c may be assigned only to some of the bump electrodes 110b and 110c.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above-described embodiment, the plurality of pad electrodes 120c are short-circuited via the bridge wiring 290, but it is not essential to provide such a bridge wiring 290 in the present invention.

  Moreover, in the said embodiment, although 3 types of bump electrodes 110b-110d are arrange | positioned in the outer peripheral area | region of the main surface of the semiconductor chip 100, this point is not essential in this invention. Therefore, only the dummy bump electrode 110 d may be disposed in the outer peripheral region of the main surface of the semiconductor chip 100.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 100 Semiconductor chip 100X Semiconductor chip mounting area 110a-110d, 110X Bump electrode 111 UBM layer 112 Pillar part 112a Pillar part upper end surface 112b Pillar part side surface 113 Solder layer 120a-120c Pad electrode 130 Protective film 140 Internal voltage Generation circuits 150A and 150B Circuit 160 Resist films 160a and 160c Openings 170a to 170d Back bumps 200 Wiring substrates 210 and 210X Insulating base material 210a Insulating base material one surface 210b Insulating base material other surface 220a and 220c Connection electrode 221 Through-hole conductor 230 Land pattern 240 Wiring pattern 241 Power supply pattern 250 Solder resist 260 External terminal 270 Underfill 280 Sealing resin 290 Bridge wiring 411 to 413 and 42 ～423 power lines D dicing line M mask TP test pad

Claims (14)

A first bump electrode disposed in a central region of the main surface;
A semiconductor chip comprising: a second bump electrode disposed in an outer peripheral region of the main surface and having a planar shape different from that of the first bump electrode.   2. The semiconductor chip according to claim 1, wherein the planar shape of the first bump electrode is a quadrangle, and the planar shape of the second bump electrode is a polygon or a circle having an obtuse internal angle. .   The cross-sectional area in a direction parallel to the main surface of the first bump electrode is larger than a cross-sectional area in a direction parallel to the main surface of the second bump electrode. The semiconductor chip described. A first pad electrode provided on the main surface and connected to a lower portion of the first bump electrode;
A second pad electrode provided on the main surface and connected to a lower portion of the second bump electrode,
The semiconductor chip according to claim 3, wherein an area of the first pad electrode is larger than an area of the second pad electrode.   The semiconductor chip according to claim 4, wherein two or more second pad electrodes are connected to a lower portion of the second bump electrode. One of the two or more second pad electrodes is provided in a first wiring formed in the uppermost wiring layer of the semiconductor chip,
The other one of the two or more second pad electrodes is formed in the uppermost wiring layer, and is formed at least in the uppermost wiring layer and separated from the first wiring. The semiconductor chip according to claim 5, wherein the semiconductor chip is provided on the wiring.   The semiconductor chip according to claim 6, wherein the first wiring and the second wiring are short-circuited via a wiring layer different from the uppermost wiring layer. A passivation film covering the main surface;
A first pad electrode connected to a lower portion of the first bump electrode through an opening provided in the passivation film,
The semiconductor chip according to claim 3, wherein the second bump electrode is provided on the passivation film.   The semiconductor chip according to claim 8, wherein the second bump electrode is not connected to any pad electrode provided on the main surface. Each of the first and second bump electrodes includes a pillar portion erected on the main surface, and a solder layer provided on an upper end surface of the pillar portion,
10. The semiconductor chip according to claim 1, wherein an angle formed by the upper end surface of the pillar portion and a side surface in contact with the upper end surface is an acute angle. A main surface having first and second sides extending parallel to the first direction, and third and fourth sides extending parallel to a second direction intersecting the first direction; ,
A plurality of first and second bump electrodes provided on the main surface,
The plurality of first bump electrodes may include the first side between the substantially central portion of the third side in the second direction and the substantially central portion of the fourth side in the second direction. Arranged in the direction of
The plurality of second bump electrodes are arranged in the first direction along the first or second side,
The semiconductor chip according to claim 1, wherein a planar shape of the plurality of first bump electrodes is different from a planar shape of the plurality of second and third bump electrodes.   12. The semiconductor chip according to claim 11, wherein at least some of the plurality of second bump electrodes are dummy bump electrodes that are not connected to an internal circuit. A semiconductor chip according to any one of claims 1 to 12,
A wiring board on which the semiconductor chip is mounted,
The wiring board is provided on an insulating base, a first connection electrode provided on one surface of the insulating base and joined to the first bump electrode, and on the one surface of the insulating base. A second connection electrode joined to the second bump electrode; and a plurality of external terminals provided on the other surface of the insulating base material and electrically connected to at least the first connection electrode. A semiconductor device.   The semiconductor device according to claim 13, wherein none of the plurality of external terminals is electrically connected to the second bump electrode.

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