JP2017152495A - Chip resistor for board inner layer and component built-in circuit board - Google Patents

Chip resistor for board inner layer and component built-in circuit board Download PDF

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JP2017152495A
JP2017152495A JP2016032409A JP2016032409A JP2017152495A JP 2017152495 A JP2017152495 A JP 2017152495A JP 2016032409 A JP2016032409 A JP 2016032409A JP 2016032409 A JP2016032409 A JP 2016032409A JP 2017152495 A JP2017152495 A JP 2017152495A
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resistor
chip resistor
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substrate
internal electrodes
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JP6715024B2 (en
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松本 健太郎
Kentaro Matsumoto
健太郎 松本
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Koa Corp
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Abstract

PROBLEM TO BE SOLVED: To provide a component built-in circuit board capable of reducing surface temperature rise incident to heat generation, while reducing resistance value change caused by flexure stress, and to provide a chip resistor for board inner layer that is built in such a circuit board.SOLUTION: In a component built-in circuit board, a chip resistor 3 is embedded in the resin layer 2 of a base substrate, and a connection via 5 formed in this resin layer 2 is connected with the external electrode of the chip resistor 3. The chip resistor 3 is built in the resin layer 2 while directing the first surface of an insulating substrate, on which a pair of internal electrode and a resistor and a protection film are formed, laterally, and the connection via 5 is connected with the external electrode formed on the second surface adjacent to the first surface and directing upward.SELECTED DRAWING: Figure 1

Description

本発明は、積層回路基板等に内蔵されて使用される基板内層用チップ抵抗器と、そのようなチップ抵抗器が絶縁性の樹脂層に埋め込まれている部品内蔵型回路基板に関するものである。   The present invention relates to a chip resistor for a substrate inner layer that is used by being embedded in a laminated circuit board or the like, and a component built-in circuit board in which such a chip resistor is embedded in an insulating resin layer.

近年、電子機器の小型・軽量化や回路構成の複雑化に伴って、チップ抵抗器を回路基板の表面だけでなく内層にも実装して部品実装密度を高めるようにした部品内蔵型回路基板が実用に供されている。   In recent years, with the reduction in size and weight of electronic devices and the complexity of circuit configurations, there is a component-embedded circuit board in which chip resistors are mounted not only on the surface of the circuit board but also on the inner layer to increase the component mounting density. It is used for practical use.

この種の部品内蔵型回路基板では、通常、絶縁性の樹脂層からなるベース基板にチップ抵抗器を埋め込んだ後、この樹脂層にレーザ光を照射してビアホールを形成すると共に、そのビアホール内に銅メッキ処理等からなる接続ビアを形成することにより、この接続ビアと内層されたチップ抵抗器の電極とを接続するようにしている。   In this type of component built-in circuit board, a chip resistor is usually embedded in a base substrate made of an insulating resin layer, and then a laser beam is irradiated to the resin layer to form a via hole, and the via hole is formed in the via hole. By forming a connection via made of a copper plating process or the like, the connection via is connected to the electrode of the chip resistor formed in the inner layer.

従来より、基板内層用チップ抵抗器の表面に広い面積を有する外部電極を形成し、この外部電極に向けてビアホールを形成することにより、内層されたチップ抵抗器を介してベース基板上の配線パターン間を導通させるようにした部品内蔵型回路基板が提案されている(例えば、特許文献1参照)。   Conventionally, an external electrode having a large area is formed on the surface of the chip resistor for the inner layer of the substrate, and a via hole is formed toward the external electrode, whereby a wiring pattern on the base substrate is formed via the inner layer of the chip resistor. There has been proposed a component-embedded circuit board that conducts between them (for example, see Patent Document 1).

上記特許文献1に開示されたチップ抵抗器は、直方体形状の絶縁基板の表面に所定間隔を存して形成された一対の内部電極と、これら内部電極間に形成された抵抗体と、内部電極の一部を露出させると共に抵抗体の全体を覆うように形成された保護膜と、内部電極の露出部分と保護膜の端部を覆うように形成された一対の外部電極とを備えて構成されている。   The chip resistor disclosed in Patent Document 1 includes a pair of internal electrodes formed on the surface of a rectangular parallelepiped insulating substrate at a predetermined interval, a resistor formed between these internal electrodes, and an internal electrode And a pair of external electrodes formed so as to cover the exposed portion of the internal electrode and the end portion of the protective film. ing.

このように構成された基板内層用チップ抵抗器をベース基板の樹脂層に内層して部品内蔵型回路基板を製造する場合、抵抗体や外部電極等が形成された一面を上に向けた姿勢でチップ抵抗器を樹脂層に埋め込んだ後、樹脂層の表面から内部に延びるビアホールを形成することにより、ベース基板上の配線パターンとチップ抵抗器の外部電極がビアホールを介して接続されるようになっている。その際、チップ抵抗器がビアホールと接続可能な広面積の外部電極を有しているため、ビアホールの形成位置が正規の位置に対して多少ずれたとしても、チップ抵抗器の外部電極とビアホールを確実に接続することができる。   When manufacturing a component-embedded circuit board by layering the chip resistor for the substrate inner layer configured as described above on the resin layer of the base substrate, the one side on which the resistor, the external electrode, etc. are formed faces up. After embedding the chip resistor in the resin layer, by forming a via hole extending from the surface of the resin layer to the inside, the wiring pattern on the base substrate and the external electrode of the chip resistor are connected via the via hole. ing. At that time, since the chip resistor has a large external electrode that can be connected to the via hole, even if the formation position of the via hole is slightly deviated from the normal position, the external electrode and the via hole of the chip resistor are It can be securely connected.

特開2011−91140号公報JP 2011-91140 A

特許文献1に開示された基板内層用チップ抵抗器は、ビアホールと接続される外部電極が抵抗体や内部電極と同一面上に形成されているため、抵抗体の形成面を上向きにした姿勢でチップ抵抗器を樹脂層に埋め込む必要がある。このため、抵抗体で発生した熱によって樹脂層の表面温度が上昇し易くなり、ベース基板上に表面実装された電子部品や、多層基板の場合は他の樹脂層に内層されたチップ部品に悪影響を及ぼしてしまうという問題があった。   In the chip resistor for the substrate inner layer disclosed in Patent Document 1, since the external electrode connected to the via hole is formed on the same surface as the resistor and the internal electrode, in a posture in which the formation surface of the resistor faces upward It is necessary to embed a chip resistor in the resin layer. For this reason, the surface temperature of the resin layer is likely to rise due to the heat generated by the resistor, which adversely affects electronic components surface-mounted on the base substrate and chip components inner layers of other resin layers in the case of multilayer substrates. There was a problem that would affect.

また、この種の部品内蔵型回路基板では、ベース基板の反り等によって樹脂層に埋め込まれたチップ抵抗器の絶縁基板に曲げ応力が加わることがあり、その場合、内部電極の間隔が拡がるような曲げ応力が加わると抵抗値は上昇し、その反対に内部電極の間隔が狭くなるような曲げ応力が加わると抵抗値は下降するため、絶縁基板に加わる曲げ応力によってチップ抵抗器の抵抗値が変化してしまうことになる。特に、樹脂層の内部に埋め込まれて使用される基板内層用チップ抵抗器は、絶縁基板を含めた全体の厚みが薄く形成されており、抵抗体の形成面を撓める方向の変形に対して非常に弱い構造となっているため、僅かな撓みで抵抗値が大きく変化してしまうという問題があった。   In addition, in this type of component-embedded circuit board, bending stress may be applied to the insulating substrate of the chip resistor embedded in the resin layer due to warpage of the base substrate, and in this case, the interval between the internal electrodes is increased. When bending stress is applied, the resistance value increases, and conversely, when bending stress is applied that reduces the distance between the internal electrodes, the resistance value decreases. Therefore, the resistance value of the chip resistor changes due to the bending stress applied to the insulating substrate. Will end up. In particular, the chip resistor for the inner layer of the substrate that is used by being embedded in the resin layer is formed with a thin overall thickness including the insulating substrate, so that the deformation in the direction in which the resistor forming surface is bent is prevented. Since the structure is very weak, there is a problem that the resistance value changes greatly with a slight deflection.

本発明は、上記した従来技術の実情に鑑みてなされたものであり、その第1の目的は、発熱に伴う表面温度の上昇を低減できると共に曲げ応力に起因する抵抗値変化を軽減できる部品内蔵型回路基板を提供することにある。また、本発明の第2の目的は、発熱に伴う表面温度の上昇を低減できると共に曲げ応力に起因する抵抗値変化を軽減できる基板内層用チップ抵抗器を提供することにある。   The present invention has been made in view of the above-described prior art, and a first object thereof is to incorporate a component that can reduce an increase in surface temperature due to heat generation and reduce a resistance value change caused by bending stress. To provide a mold circuit board. A second object of the present invention is to provide a chip resistor for an inner layer of a substrate that can reduce an increase in surface temperature due to heat generation and can reduce a change in resistance value caused by bending stress.

上記第1の目的を達成するために、本発明の部品内蔵型回路基板は、絶縁性の樹脂層からなるベース基板の内層にチップ抵抗器が埋め込まれており、前記ベース基板の表面から前記チップ抵抗器に達するビアホールが設けられている部品内蔵型回路基板において、前記チップ抵抗器は、直方体形状の絶縁基板と、この絶縁基板の一面である第1面に所定間隔を存して形成された一対の内部電極と、これら一対の内部電極間に形成された抵抗体と、この抵抗体を覆うように形成された絶縁性の保護膜と、前記絶縁基板の前記第1面に隣接する第2面に形成されて前記内部電極と接続する一対の外部電極とを備えており、前記第1面は前記ベース基板の表面と直交する面を向くように配置されており、前記ビアホールは前記ベース基板の表面と平行に配置された前記第2面上の前記外部電極と接続されているという構成にした。   In order to achieve the first object, in the component-embedded circuit board of the present invention, a chip resistor is embedded in the inner layer of the base substrate made of an insulating resin layer, and the chip chip is formed from the surface of the base substrate. In the component-embedded circuit board provided with via holes reaching the resistor, the chip resistor is formed on the rectangular parallelepiped insulating substrate and the first surface, which is one surface of the insulating substrate, with a predetermined interval. A pair of internal electrodes; a resistor formed between the pair of internal electrodes; an insulating protective film formed to cover the resistor; and a second adjacent to the first surface of the insulating substrate. A pair of external electrodes formed on a surface and connected to the internal electrode, wherein the first surface is disposed to face a surface orthogonal to the surface of the base substrate, and the via hole is formed on the base substrate Surface and flat And the configuration that is connected to the external electrodes on the arranged second surface to.

このように構成された部品内蔵型回路基板では、チップ抵抗器の絶縁基板を構成する6つの面のうち、外部電極の形成面である第2面がベース基板の表面と平行になるように樹脂層に埋め込まれ、この外部電極に対してビアホールが接続されていると共に、内部電極や抵抗体の形成面である第1面がベース基板の表面と直交する面を向くように配置されているため、抵抗体の発熱によって樹脂層の表面温度が上昇してしまうことを抑制できると共に、曲げ応力によって抵抗体の抵抗値が変化してしまうことを抑制できる。   In the component-embedded circuit board configured as described above, a resin is formed so that the second surface, which is the external electrode forming surface, is parallel to the surface of the base substrate among the six surfaces constituting the insulating substrate of the chip resistor. Since the via hole is connected to the external electrode and the first surface, which is the formation surface of the internal electrode and the resistor, is disposed so as to face the surface orthogonal to the surface of the base substrate. In addition, it is possible to suppress the surface temperature of the resin layer from increasing due to the heat generated by the resistor, and it is possible to suppress the resistance value of the resistor from changing due to bending stress.

上記の構成において、ベース基板にチップ抵抗器の第1面を包囲する放熱体が埋め込まれていると、第1面に形成された抵抗体の発熱が放熱体によって放熱されるため、樹脂層の表面温度の上昇をより効果的に抑えることができる。   In the above configuration, when the radiator that surrounds the first surface of the chip resistor is embedded in the base substrate, the heat generated by the resistor formed on the first surface is dissipated by the radiator. An increase in surface temperature can be suppressed more effectively.

また、上記第2の目的を達成するために、本発明の基板内層用チップ抵抗器は、直方体形状の絶縁基板と、この絶縁基板の一面である第1面に所定間隔を存して形成された一対の内部電極と、これら一対の内部電極間に形成された抵抗体と、この抵抗体を覆うように形成された絶縁性の保護膜と、前記絶縁基板の前記第1面に隣接する第2面に形成されて前記内部電極と接続する一対の外部電極とを備え、前記一対の外部電極の間隔が前記一対の内部電極の間隔よりも狭く設定されていることを特徴としている。   In order to achieve the second object, the chip resistor for an inner layer of the present invention is formed with a rectangular parallelepiped insulating substrate and a first surface which is one surface of the insulating substrate with a predetermined interval. A pair of internal electrodes, a resistor formed between the pair of internal electrodes, an insulating protective film formed to cover the resistor, and a first layer adjacent to the first surface of the insulating substrate. A pair of external electrodes formed on two surfaces and connected to the internal electrodes are provided, and an interval between the pair of external electrodes is set narrower than an interval between the pair of internal electrodes.

このように構成された基板内層用チップ抵抗器では、直方体形状の絶縁基板を構成する6つの面のうち、第1面に内部電極と抵抗体および保護膜が形成されると共に、第1面に隣接する第2面に外部電極が形成されており、この外部電極の電極間距離が内部電極よりも狭く設定されているため、第2面に広い面積を有する外部電極が延在している。したがって、絶縁基板の第2面がベース基板の表面と平行になるように樹脂層に埋め込むことにより、第2面上に広面積で形成された外部電極に対してビアホールを確実に接続することができる。また、このように第2面をベース基板の表面と平行になるように配置すると、内部電極や抵抗体が形成された第1面はベース基板の表面と直交する面を向くように配置されるため、抵抗体の発熱によって樹脂層の表面温度が上昇してしまうことを抑制できると共に、曲げ応力によって抵抗体の抵抗値が変化してしまうことを抑制できる。   In the chip resistor for the substrate inner layer configured as described above, the internal electrode, the resistor, and the protective film are formed on the first surface among the six surfaces constituting the rectangular parallelepiped insulating substrate, and the first surface is formed on the first surface. An external electrode is formed on the adjacent second surface, and the distance between the electrodes of the external electrode is set to be narrower than that of the internal electrode, so that the external electrode having a large area extends on the second surface. Therefore, by embedding the resin layer so that the second surface of the insulating substrate is parallel to the surface of the base substrate, the via hole can be reliably connected to the external electrode formed in a large area on the second surface. it can. Further, when the second surface is arranged so as to be parallel to the surface of the base substrate, the first surface on which the internal electrode and the resistor are formed is arranged so as to face a surface orthogonal to the surface of the base substrate. Therefore, it can suppress that the surface temperature of a resin layer raises by the heat_generation | fever of a resistor, and can suppress that the resistance value of a resistor changes with bending stress.

上記の構成において、絶縁基板の第1面と対向する別の第1面に、所定間隔を存して形成された一対の内部電極と、これら一対の内部電極間に形成された抵抗体と、この抵抗体を覆うように形成された絶縁性の保護膜とが形成されており、外部電極は2つの第1面に形成された内部電極とそれぞれ接続していると、チップ抵抗器の定格を高めることができる。   In the above configuration, a pair of internal electrodes formed on the first surface opposite to the first surface of the insulating substrate at a predetermined interval, and a resistor formed between the pair of internal electrodes, An insulating protective film formed so as to cover this resistor is formed, and when the external electrode is connected to the internal electrode formed on the two first surfaces, the rating of the chip resistor is set. Can be increased.

また、上記の構成において、保護膜は少なくとも抵抗体を覆っていれば良いが、保護膜が抵抗体と内部電極の全体を覆っていると、放熱効果を高めるためにベース基板の樹脂層にチップ抵抗器の第1面を包囲する放熱体を埋め込んだとしても、保護膜によって内部電極と放熱体との接触を防止することができる。   In the above configuration, the protective film only needs to cover at least the resistor, but if the protective film covers the entire resistor and the internal electrode, the chip is formed on the resin layer of the base substrate in order to enhance the heat dissipation effect. Even if the radiator that surrounds the first surface of the resistor is embedded, the contact between the internal electrode and the radiator can be prevented by the protective film.

本発明によれば、発熱に伴う表面温度の上昇を低減できると共に曲げ応力に起因する抵抗値変化を軽減できる部品内蔵型回路基板を提供することができ、また、発熱に伴う表面温度の上昇を低減できると共に曲げ応力に起因する抵抗値変化を軽減できる基板内層用チップ抵抗器を提供することができる。   According to the present invention, it is possible to provide a circuit board with a built-in component that can reduce a rise in surface temperature due to heat generation and reduce a resistance value change caused by bending stress, and can also increase a surface temperature due to heat generation. It is possible to provide a chip resistor for an inner layer of a substrate that can reduce the resistance value change caused by a bending stress.

本発明の第1実施形態例に係る部品内蔵型回路基板の断面図である。1 is a cross-sectional view of a component-embedded circuit board according to a first embodiment of the present invention. 該部品内蔵型回路基板に内蔵されるチップ抵抗器の斜視図である。It is a perspective view of the chip resistor built in this component built-in type circuit board. 該チップ抵抗器の断面図である。It is sectional drawing of this chip resistor. 図1の部品内蔵型回路基板に内蔵される他のチップ抵抗器の斜視図である。It is a perspective view of the other chip resistor built in the component built-in type circuit board of FIG. 本発明の第2実施形態例に係る部品内蔵型回路基板の断面図である。It is sectional drawing of the component built-in type circuit board based on 2nd Example of this invention. 該部品内蔵型回路基板の製造工程を示す平面図である。It is a top view which shows the manufacturing process of this component built-in type circuit board. 該部品内蔵型回路基板の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of this component built-in type circuit board. 本発明の第1実施形態例に係る基板内層用チップ抵抗器の斜視図である。It is a perspective view of the chip resistor for substrate inner layers concerning the example of a 1st embodiment of the present invention. 該チップ抵抗器の断面図である。It is sectional drawing of this chip resistor. 本発明の第2実施形態例に係る基板内層用チップ抵抗器の斜視図である。It is a perspective view of the chip resistor for substrate inner layers concerning the example of a 2nd embodiment of the present invention. 本発明の第3実施形態例に係る基板内層用チップ抵抗器の斜視図である。It is a perspective view of the chip resistor for substrate inner layers concerning the example of a 3rd embodiment of the present invention. 該チップ抵抗器の断面図である。It is sectional drawing of this chip resistor.

以下、発明の実施の形態について図面を参照しながら説明する。図1に示すように、本発明の第1実施形態例に係る部品内蔵型回路基板1は、絶縁性の樹脂層2からなるベース基板の内層にチップ抵抗器3が埋め込まれており、この樹脂層2の上面に設けられた配線パターン4が接続ビア5を介してチップ抵抗器3の後述する外部電極と接続されている。この接続ビア5は、樹脂層2にレーザ光を照射してビアホールを形成した後、そのビアホール内に銅メッキ等を施すことによって形成されたものである。   Hereinafter, embodiments of the invention will be described with reference to the drawings. As shown in FIG. 1, a component-embedded circuit board 1 according to a first embodiment of the present invention has a chip resistor 3 embedded in an inner layer of a base substrate made of an insulating resin layer 2, and this resin A wiring pattern 4 provided on the upper surface of the layer 2 is connected to an external electrode (described later) of the chip resistor 3 through a connection via 5. The connection via 5 is formed by irradiating the resin layer 2 with a laser beam to form a via hole and then performing copper plating or the like in the via hole.

図2,3に示すように、樹脂層2に内層されたチップ抵抗器3は、直方体形状の絶縁基板6と、絶縁基板6の一側面における長手方向両端部に設けられた一対の内部電極7と、これら内部電極7に接続するように設けられた長方形状の抵抗体8と、両内部電極7と抵抗体8を含めて絶縁基板6の一側面全体を覆う樹脂からなる保護膜9と、絶縁基板6の長手方向両端部に設けられた一対の外部電極10とによって主に構成されている。   As shown in FIGS. 2 and 3, the chip resistor 3 formed in the resin layer 2 includes a rectangular parallelepiped insulating substrate 6 and a pair of internal electrodes 7 provided at both ends in the longitudinal direction on one side surface of the insulating substrate 6. A rectangular resistor 8 provided so as to be connected to these internal electrodes 7, and a protective film 9 made of a resin covering the entire side surface of the insulating substrate 6 including both the internal electrodes 7 and the resistor 8, It is mainly constituted by a pair of external electrodes 10 provided at both ends in the longitudinal direction of the insulating substrate 6.

絶縁基板6はセラミックスからなり、この絶縁基板6を構成する6つの面のうち、最も面積の広い2つの対向面を第1面、これら第1面の長辺に連続する2つの対向面を第2面、第1面の短辺に連続する2つの対向面を第3面と呼ぶと、内部電極7と抵抗体8および保護膜9は一方の第1面に形成され、外部電極10は第1乃至第3面を覆うようにキャップ形状に形成されている。   The insulating substrate 6 is made of ceramics. Of the six surfaces constituting the insulating substrate 6, the two opposing surfaces having the largest area are the first surface, and the two opposing surfaces continuing to the long side of the first surface are the first surfaces. If two opposing surfaces that are continuous with the short sides of the two surfaces, the first surface, are referred to as a third surface, the internal electrode 7, the resistor 8 and the protective film 9 are formed on one first surface, and the external electrode 10 A cap shape is formed so as to cover the first to third surfaces.

一対の内部電極7はAg系ペーストをスクリーン印刷して乾燥・焼成させたものであり、これら内部電極7は絶縁基板6の第1面の長手方向端部に矩形状に形成されている。   The pair of internal electrodes 7 are obtained by screen-printing Ag-based paste, dried and fired, and these internal electrodes 7 are formed in a rectangular shape at the longitudinal ends of the first surface of the insulating substrate 6.

抵抗体8は酸化ルテニウム等の抵抗ペーストをスクリーン印刷して乾燥・焼成させたものであり、この抵抗体8の長手方向の両端部はそれぞれ内部電極7に重なっている。なお、図示省略されているが、抵抗体8には抵抗値を調整するためのトリミング溝が形成されている。   The resistor 8 is obtained by screen-printing a resistor paste such as ruthenium oxide, dried and fired, and both ends in the longitudinal direction of the resistor 8 overlap the internal electrode 7. Although not shown, the resistor 8 has a trimming groove for adjusting the resistance value.

保護膜9はエポキシ系樹脂ペーストをスクリーン印刷して加熱硬化させたオーバーコート層であり、図示省略されているが、保護膜9の下面側には抵抗体8を覆うアンダーコート層が形成されている。なお、このアンダーコート層はガラスペーストをスクリーン印刷して乾燥・焼成させたものである。保護膜9は両内部電極7と抵抗体8を含めて絶縁基板6の第1面全体を覆うように形成されているため、一対の内部電極7の3辺が絶縁基板6と保護膜9間から露出している。   The protective film 9 is an overcoat layer obtained by screen-printing an epoxy resin paste and heat-cured. Although not shown, an undercoat layer that covers the resistor 8 is formed on the lower surface side of the protective film 9. Yes. The undercoat layer is obtained by screen-printing glass paste, drying and firing. Since the protective film 9 is formed so as to cover the entire first surface of the insulating substrate 6 including both the internal electrodes 7 and the resistor 8, the three sides of the pair of internal electrodes 7 are between the insulating substrate 6 and the protective film 9. Is exposed from.

一対の外部電極10はAgペーストやCuペーストを絶縁基板6の第3面にディップ塗布して加熱硬化させたものであり、これら外部電極10は、一方の第1面に形成された保護膜9を含めて残りの第1面と両第2面の一部を覆うようにキャップ形状に形成されている。これにより、図2中の左側に位置する外部電極10は絶縁基板6と保護膜9間から露出する左側の内部電極7の端面と接続され、右側に位置する外部電極10は絶縁基板6と保護膜9間から露出する右側の内部電極7の端面と接続されている。なお、図示省略されているが、これら外部電極10の表面にはNi,Cu等の電解メッキが施されている。   The pair of external electrodes 10 is obtained by dip-coating Ag paste or Cu paste on the third surface of the insulating substrate 6 and heat-curing. These external electrodes 10 are protective films 9 formed on one first surface. Is formed in a cap shape so as to cover the remaining first surface and part of both second surfaces. Accordingly, the external electrode 10 located on the left side in FIG. 2 is connected to the end face of the left internal electrode 7 exposed from between the insulating substrate 6 and the protective film 9, and the external electrode 10 located on the right side is protected from the insulating substrate 6. It is connected to the end face of the right internal electrode 7 exposed from between the membranes 9. Although not shown, the surface of these external electrodes 10 is subjected to electrolytic plating such as Ni and Cu.

このように構成されたチップ抵抗器3は、図1に示すように、内部電極7や抵抗体8の形成面である第1面を横向きにすると共に、この第1面に隣接する第2面を上向きにした状態で樹脂層2に内層された後、上向きの第2面に形成された外部電極10に対して接続ビア5(ビアホール)が接続されるようになっている。このように抵抗体8の形成面である第1面がベース基板の表面と直交する面を向くように配置されているため、抵抗体8から樹脂層2の表面に至る熱の伝達経路が長くなり、抵抗体8の発熱に伴う樹脂層2の表面温度の上昇を抑制することができる。また、ベース基板(樹脂層2)の板面に対して抵抗体8の形成面である第1面が直交する向き(横向き姿勢)に配置されているため、ベース基板の反り等によってチップ抵抗器3の絶縁基板6に曲げ応力が加わったとしても、抵抗体8の抵抗値が変化してしまうことを抑制できる。   As shown in FIG. 1, the chip resistor 3 configured as described above has a first surface, which is a formation surface of the internal electrode 7 and the resistor 8, turned sideways and a second surface adjacent to the first surface. Then, a connection via 5 (via hole) is connected to the external electrode 10 formed on the second surface facing upward. Since the first surface, which is the formation surface of the resistor 8, is arranged so as to face the surface orthogonal to the surface of the base substrate, the heat transfer path from the resistor 8 to the surface of the resin layer 2 is long. Thus, an increase in the surface temperature of the resin layer 2 due to the heat generation of the resistor 8 can be suppressed. In addition, since the first surface, which is the formation surface of the resistor 8, is arranged in a direction (lateral orientation) perpendicular to the plate surface of the base substrate (resin layer 2), the chip resistor is caused by warpage of the base substrate or the like. Even if a bending stress is applied to the third insulating substrate 6, the resistance value of the resistor 8 can be prevented from changing.

図1に示す部品内蔵型回路基板1において、樹脂層2に内層されたチップ抵抗器3の代わりに図4に示すチップ抵抗器11を用いることも可能である。このチップ抵抗器11が図2,3に示すチップ抵抗器3と相違する点は、最も面積の広い2つの対向面を第2面、これら第2面の長辺に連続する2つの対向面を第1面、第2面の短辺に連続する2つの対向面を第3面とし、細長形状の一方の第1面に一対の内部電極7と抵抗体8および保護膜9が形成されていることにあり、それ以外の構成は基本的に同様である。   In the component-embedded circuit board 1 shown in FIG. 1, the chip resistor 11 shown in FIG. 4 can be used in place of the chip resistor 3 formed in the resin layer 2. The chip resistor 11 is different from the chip resistor 3 shown in FIGS. 2 and 3 in that the two opposing surfaces having the largest area are the second surface, and the two opposing surfaces that are continuous with the long sides of the second surface are provided. Two opposing surfaces that are continuous with the short sides of the first surface and the second surface are defined as a third surface, and a pair of internal electrodes 7, a resistor 8, and a protective film 9 are formed on one elongated first surface. In particular, the rest of the configuration is basically the same.

このように構成されたチップ抵抗器11は、図1に示す部品内蔵型回路基板1の樹脂層2に内層される場合、内部電極7や抵抗体8の形成面である第1面を横向きにすると共に、この第1面に隣接する第2面を上向きにした姿勢で樹脂層2に埋め込まれた後、上向きの第2面に形成された外部電極10に対して接続ビア5(ビアホール)が接続されるようになっている。この場合、抵抗体8の面積が小さくなるため、負荷特性は図2,3に示すチップ抵抗器3よりも劣るが、外部電極10の面積が大きくなるため、接続ビア5との接続信頼性が向上する。そして、この場合においても、抵抗体8の形成面である第1面がベース基板の表面と直交する面を向くように配置されているため、抵抗体8から樹脂層2の表面に至る熱の伝達経路が長くなり、抵抗体8の発熱に伴う樹脂層2の表面温度の上昇を抑制することができる。また、ベース基板(樹脂層2)の板面に対して抵抗体8の形成面である第1面が直交する向きに配置されているため、ベース基板の反り等によってチップ抵抗器3の絶縁基板6に曲げ応力が加わったとしても、抵抗体8の抵抗値が変化してしまうことを抑制できる。以上のように、絶縁基板6の各面の面積においては、接続信頼性や負荷特性などの求められる仕様により選択することが可能である。   When the chip resistor 11 configured as described above is formed in the resin layer 2 of the component-embedded circuit board 1 shown in FIG. 1, the first surface, which is the formation surface of the internal electrode 7 and the resistor 8, is turned sideways. At the same time, after being embedded in the resin layer 2 with the second surface adjacent to the first surface facing upward, the connection via 5 (via hole) is formed with respect to the external electrode 10 formed on the second surface facing upward. Connected. In this case, since the area of the resistor 8 is reduced, the load characteristic is inferior to the chip resistor 3 shown in FIGS. 2 and 3, but the area of the external electrode 10 is increased, and thus the connection reliability with the connection via 5 is improved. improves. Even in this case, since the first surface, which is the formation surface of the resistor 8, is arranged so as to face the surface orthogonal to the surface of the base substrate, the heat from the resistor 8 to the surface of the resin layer 2 can be obtained. The transmission path becomes longer, and an increase in the surface temperature of the resin layer 2 accompanying the heat generation of the resistor 8 can be suppressed. Further, since the first surface, which is the formation surface of the resistor 8, is arranged in a direction orthogonal to the plate surface of the base substrate (resin layer 2), the insulating substrate of the chip resistor 3 is caused by warpage of the base substrate. Even if bending stress is applied to 6, the resistance value of the resistor 8 can be prevented from changing. As described above, the area of each surface of the insulating substrate 6 can be selected according to required specifications such as connection reliability and load characteristics.

図5は本発明の第2実施形態例に係る部品内蔵型回路基板20の断面図であり、図1に対応する部分には同一符号を付してある。   FIG. 5 is a cross-sectional view of a component-embedded circuit board 20 according to the second embodiment of the present invention, and portions corresponding to those in FIG.

図5に示すように、第2実施形態例に係る部品内蔵型回路基板20では、ベース基板の樹脂層2にチップ抵抗器21と一緒に放熱体22が埋め込まれており、この放熱体22によってチップ抵抗器21の外側面が包囲されるようになっている。チップ抵抗器21は図2や図4に示すチップ抵抗器3,11と同様のものであり、抵抗体23の形成面である第1面がベース基板の表面と直交する面を向くように配置され、上向きに配置された第2面上の外部電極に対して接続ビア5が接続されている。放熱体22は熱伝導率の良い銅板等からなり、チップ抵抗器21の外形よりも大きめな貫通孔22aを有している。チップ抵抗器21は貫通孔22aの内部に配置されており、その第1面と第3面の計4つの外側面が貫通孔22aの内壁面と非接触状態で対向している。   As shown in FIG. 5, in the component-embedded circuit board 20 according to the second embodiment, a heat radiator 22 is embedded in the resin layer 2 of the base substrate together with the chip resistor 21. The outer surface of the chip resistor 21 is surrounded. The chip resistor 21 is the same as the chip resistors 3 and 11 shown in FIG. 2 and FIG. 4, and is arranged so that the first surface, which is the formation surface of the resistor 23, faces the surface orthogonal to the surface of the base substrate. The connection via 5 is connected to the external electrode on the second surface arranged upward. The radiator 22 is made of a copper plate or the like having a good thermal conductivity, and has a through hole 22 a larger than the outer shape of the chip resistor 21. The chip resistor 21 is disposed inside the through hole 22a, and a total of four outer surfaces of the first surface and the third surface face the inner wall surface of the through hole 22a in a non-contact state.

このように構成された部品内蔵型回路基板20においては、チップ抵抗器21の第1面を包囲している放熱体22がヒートシンクとして機能し、第1面に形成された抵抗体23の発熱が放熱体22によって放熱されるため、樹脂層2の表面温度の上昇をより効果的に抑えることができる。   In the component-embedded circuit board 20 configured as described above, the radiator 22 surrounding the first surface of the chip resistor 21 functions as a heat sink, and the resistor 23 formed on the first surface generates heat. Since heat is radiated by the heat radiating body 22, an increase in the surface temperature of the resin layer 2 can be more effectively suppressed.

次に、上記の如く構成された部品内蔵型回路基板20の製造方法について、図6と図7を参照しながら説明する。   Next, a method for manufacturing the component-embedded circuit board 20 configured as described above will be described with reference to FIGS.

まず、図6(a)と図7(a)に示すように、片面に粘着テープ24が付着された支持板25を準備し、この粘着テープ24に複数の貫通孔22aを有する放熱体22を貼り付ける。なお、図6は支持板25を上方から見た平面図、図7は図6のA−A線に沿った断面図を示している。   First, as shown in FIG. 6A and FIG. 7A, a support plate 25 having an adhesive tape 24 attached to one side is prepared, and a radiator 22 having a plurality of through holes 22a is provided in the adhesive tape 24. paste. 6 is a plan view of the support plate 25 as viewed from above, and FIG. 7 is a cross-sectional view taken along the line AA in FIG.

次に、図6(b)と図7(b)に示すように、放熱体22の貫通孔22aの内部にチップ抵抗器21を挿入し、このチップ抵抗器21の第2面を粘着テープ24に貼り付ける。その際、抵抗体23の形成面である第1面は側方を向いた姿勢で貫通孔22a内に挿入され、チップ抵抗器21と貫通孔22aの内壁面との間には両者を非接触状態に保つ隙間が確保される。しかる後、放熱体22の上から熱可塑性の樹脂シートを熱圧着することにより、図6(c)と図7(c)に示すように、放熱体22とチップ抵抗器21を覆う上側樹脂層26を形成する。その際、上側樹脂層26は貫通孔22aの内壁面とチップ抵抗器21間に確保された隙間にも充填される。   Next, as shown in FIGS. 6B and 7B, the chip resistor 21 is inserted into the through hole 22 a of the radiator 22, and the second surface of the chip resistor 21 is attached to the adhesive tape 24. Paste to. At that time, the first surface, which is the formation surface of the resistor 23, is inserted into the through hole 22a in a sideward orientation, and the chip resistor 21 and the inner wall surface of the through hole 22a are not in contact with each other. A gap to keep the state is secured. Thereafter, an upper resin layer covering the radiator 22 and the chip resistor 21 as shown in FIGS. 6C and 7C by thermocompression bonding a thermoplastic resin sheet on the radiator 22. 26 is formed. At that time, the upper resin layer 26 is also filled in a gap secured between the inner wall surface of the through hole 22 a and the chip resistor 21.

次に、図7(d)に示すように、粘着テープ24付きの支持板25を上側樹脂層26から剥離した後、上側樹脂層26の下面に熱可塑性の樹脂シートを熱圧着することにより、図7(e)に示すように、上側樹脂層26から露出する放熱体22とチップ抵抗器21を覆う下側樹脂層27を形成する。これにより上側樹脂層26と下側樹脂層27が一体化されて樹脂層2となり、この時点で樹脂層2の内部にチップ抵抗器21と放熱体22が埋め込まれた状態となる。   Next, as shown in FIG. 7D, after the support plate 25 with the adhesive tape 24 is peeled from the upper resin layer 26, a thermoplastic resin sheet is thermocompression bonded to the lower surface of the upper resin layer 26. As shown in FIG. 7E, a lower resin layer 27 that covers the heat radiator 22 and the chip resistor 21 exposed from the upper resin layer 26 is formed. As a result, the upper resin layer 26 and the lower resin layer 27 are integrated to form the resin layer 2, and at this time, the chip resistor 21 and the radiator 22 are embedded in the resin layer 2.

次に、図7(f)に示すように、樹脂層2の上面にレーザ光を照射してビアホール5aを形成し、このビアホール5aをチップ抵抗器21の第2面に形成された外部電極に接続させる。しかる後、無電解銅メッキ等によりビアホール5a内に接続ビア5を形成すると共に、樹脂層2の上面に配線パターン4を形成することにより、図5に示すような部品内蔵型回路基板20が完成する。   Next, as shown in FIG. 7 (f), the upper surface of the resin layer 2 is irradiated with laser light to form a via hole 5 a, and this via hole 5 a is formed on the external electrode formed on the second surface of the chip resistor 21. Connect. Thereafter, the connection via 5 is formed in the via hole 5a by electroless copper plating or the like, and the wiring pattern 4 is formed on the upper surface of the resin layer 2, thereby completing the component built-in circuit board 20 as shown in FIG. To do.

次に、本発明の第1実施形態例に係る基板内層用チップ抵抗器40を図8と図9に基づいて説明する。本実施形態例に係る基板内層用チップ抵抗器40は、図1や図5に示す部品内蔵型回路基板1,20の樹脂層2に内層されて使用されるものであり、絶縁基板6の第1面に形成された一対の内部電極7の間隔L1に対して、第2面に形成された一対の外部電極10の間隔L2を狭く設定した点に特徴があり、それ以外の構成は図4に示すチップ抵抗器11と基本的に同様である。   Next, the substrate inner layer chip resistor 40 according to the first embodiment of the present invention will be described with reference to FIGS. The chip resistor 40 for the substrate inner layer according to the present embodiment is used by being layered on the resin layer 2 of the component built-in circuit boards 1 and 20 shown in FIG. 1 and FIG. 4 is characterized in that the distance L2 between the pair of external electrodes 10 formed on the second surface is set narrower than the distance L1 between the pair of internal electrodes 7 formed on the one surface. This is basically the same as the chip resistor 11 shown in FIG.

すなわち、このチップ抵抗器40は、直方体形状の絶縁基板6と、絶縁基板6の一側面における長手方向両端部に設けられた一対の内部電極7と、これら内部電極7に接続するように設けられた長方形状の抵抗体8と、両内部電極7と抵抗体8を含めて絶縁基板6の一側面全体を覆う樹脂からなる保護膜9と、絶縁基板6の長手方向両端部に設けられた一対の外部電極10とによって主に構成されている。   That is, the chip resistor 40 is provided so as to be connected to the rectangular parallelepiped insulating substrate 6, a pair of internal electrodes 7 provided at both ends in the longitudinal direction on one side surface of the insulating substrate 6, and the internal electrodes 7. A rectangular resistor 8, a protective film 9 made of a resin covering the entire side surface of the insulating substrate 6 including both the internal electrodes 7 and the resistor 8, and a pair provided at both longitudinal ends of the insulating substrate 6 The external electrode 10 is mainly configured.

そして、絶縁基板6の6つの面のうち、最も面積の広い2つの対向面が第2面、これら第2面の長辺に連続する2つの対向面が第1面、第2面の短辺に連続する2つの対向面が第3面となっており、一対の内部電極7と抵抗体8および保護膜9は一方の第1面に形成されている。また、一対の外部電極10は第1面に形成された保護膜9を覆うように絶縁基板6の長手方向両端部に形成されており、これら外部電極10の間隔L2が内部電極7の間隔L1よりも狭く設定されているため、第2面に広い面積を有する一対の外部電極10が延在している。なお、保護膜9は第1面の全体を覆うように形成されているが、少なくとも抵抗体8を覆っていれば良い。   Of the six surfaces of the insulating substrate 6, the two opposing surfaces having the largest area are the second surface, the two opposing surfaces continuing to the long sides of the second surface are the first surface, and the short sides of the second surface The two opposing surfaces that are continuous with each other are the third surface, and the pair of internal electrodes 7, the resistor 8, and the protective film 9 are formed on one first surface. The pair of external electrodes 10 are formed at both ends in the longitudinal direction of the insulating substrate 6 so as to cover the protective film 9 formed on the first surface, and the interval L2 between the external electrodes 10 is the interval L1 between the internal electrodes 7. Therefore, the pair of external electrodes 10 having a large area extends on the second surface. Although the protective film 9 is formed so as to cover the entire first surface, it is sufficient that at least the resistor 8 is covered.

したがって、このように構成されたチップ抵抗器40においても、抵抗体8の形成面である第1面をベース基板の表面と直交する側面を向くように樹脂層に内層すれば、抵抗体8の発熱に伴う樹脂層の表面温度の上昇を抑制することができると共に、ベース基板の反り等によってチップ抵抗器40の絶縁基板6に曲げ応力が加わったとしても、抵抗体8の抵抗値が変化してしまうことを抑制できる。しかも、絶縁基板6の第2面に広い面積を有する一対の外部電極10が延在しているため、これら外部電極10に対してビアホールを確実に接続することができる。   Therefore, even in the chip resistor 40 configured as described above, if the first surface, which is the surface on which the resistor 8 is formed, is formed on the resin layer so as to face the side surface orthogonal to the surface of the base substrate, the resistor 8 The rise in the surface temperature of the resin layer due to heat generation can be suppressed, and even if bending stress is applied to the insulating substrate 6 of the chip resistor 40 due to warpage of the base substrate, the resistance value of the resistor 8 changes. Can be suppressed. Moreover, since the pair of external electrodes 10 having a large area extends on the second surface of the insulating substrate 6, via holes can be reliably connected to the external electrodes 10.

図10は本発明の第2実施形態例に係る基板内層用チップ抵抗器50の斜視図であり、このチップ抵抗器50が第1実施形態例に係る基板内層用チップ抵抗器40と相違する点は、絶縁基板6の相対向する2つの第1面が抵抗体8の形成面となっていることであり、それ以外の構成は基本的に同様である。   FIG. 10 is a perspective view of the substrate inner layer chip resistor 50 according to the second embodiment of the present invention. The chip resistor 50 is different from the substrate inner layer chip resistor 40 according to the first embodiment. Is that the two first surfaces facing each other of the insulating substrate 6 are the surfaces on which the resistor 8 is formed, and the other configurations are basically the same.

すなわち、このチップ抵抗器50は、絶縁基板6の相対向する2つの第1面にそれぞれ一対の内部電極7と抵抗体8および保護膜9が形成され、これら2つの第1面上の内部電極7と第2面に形成された外部電極10とを導通させることにより、定格の高いチップ抵抗器となっている。   That is, in the chip resistor 50, a pair of internal electrodes 7, a resistor 8, and a protective film 9 are formed on two opposing first surfaces of the insulating substrate 6, and the internal electrodes on these two first surfaces are formed. 7 and the external electrode 10 formed on the second surface are electrically connected to form a highly rated chip resistor.

図11は本発明の第3実施形態例に係る基板内層用チップ抵抗器60の斜視図、図12は該チップ抵抗器60の断面図であり、図8,9に対応する部分には同一符号を付してある。   FIG. 11 is a perspective view of a chip resistor 60 for an inner layer substrate according to a third embodiment of the present invention. FIG. 12 is a cross-sectional view of the chip resistor 60. Parts corresponding to those in FIGS. Is attached.

このチップ抵抗器60第1実施形態例に係る基板内層用チップ抵抗器40と相違する点は、絶縁基板6の第1面に形成された一対の内部電極7と抵抗体8の全体を保護膜9が覆っていると共に、これら内部電極7に接続する外部電極10が第2面にのみに形成されていることにあり、それ以外の構成は基本的に同様である。   The chip resistor 60 is different from the substrate inner layer chip resistor 40 according to the first embodiment in that the entire pair of internal electrodes 7 and the resistor 8 formed on the first surface of the insulating substrate 6 is a protective film. 9 is covered and the external electrodes 10 connected to the internal electrodes 7 are formed only on the second surface, and the other configurations are basically the same.

第3実施形態例に係るチップ抵抗器60においては、抵抗体8の形成面である第1面の外表面が絶縁性の保護膜9によって覆われていると共に、この第1面に対向するもう1つの第1面と一対の第3面が絶縁基板6の露出面となっているため、図5に示す部品内蔵型回路基板20のように、ベース基板の樹脂層2にチップ抵抗器60を包囲する放熱体22を内層した場合、仮に放熱体22がチップ抵抗器60の外側面に接触してしまっても、放熱体22と内部電極7が導通してしまうことを防止できる。   In the chip resistor 60 according to the third embodiment, the outer surface of the first surface, which is the formation surface of the resistor 8, is covered with the insulating protective film 9 and is opposed to the first surface. Since one first surface and a pair of third surfaces are exposed surfaces of the insulating substrate 6, a chip resistor 60 is provided on the resin layer 2 of the base substrate as in the component built-in circuit substrate 20 shown in FIG. In the case where the surrounding heat dissipating body 22 is formed as an inner layer, even if the heat dissipating body 22 contacts the outer surface of the chip resistor 60, the heat dissipating body 22 and the internal electrode 7 can be prevented from conducting.

1,20 部品内蔵型回路基板
2 樹脂層
3,11,21 チップ抵抗器
4 配線パターン
5 接続ビア
5a ビアホール
6 絶縁基板
7 内部電極
8,23 抵抗体
9 保護膜
10 外部電極
22 放熱体
22a 貫通孔
24 粘着テープ
25 支持板
26 上側樹脂層
27 下側樹脂層
40,50,60 基板内層用チップ抵抗器
DESCRIPTION OF SYMBOLS 1,20 Component built-in circuit board 2 Resin layer 3,11,21 Chip resistor 4 Wiring pattern 5 Connection via 5a Via hole 6 Insulating substrate 7 Internal electrode 8, 23 Resistor 9 Protective film 10 External electrode
22 Radiator 22a Through hole 24 Adhesive tape 25 Support plate 26 Upper resin layer 27 Lower resin layer 40, 50, 60 Chip resistor for substrate inner layer

Claims (5)

絶縁性の樹脂層からなるベース基板の内層にチップ抵抗器が埋め込まれており、前記ベース基板の表面から前記チップ抵抗器に達するビアホールが設けられている部品内蔵型回路基板において、
前記チップ抵抗器は、直方体形状の絶縁基板と、この絶縁基板の一面である第1面に所定間隔を存して形成された一対の内部電極と、これら一対の内部電極間に形成された抵抗体と、この抵抗体を覆うように形成された絶縁性の保護膜と、前記絶縁基板の前記第1面に隣接する第2面に形成されて前記内部電極と接続する一対の外部電極とを備えており、
前記第1面は前記ベース基板の表面と直交する面を向くように配置されており、前記ビアホールは前記ベース基板の表面と平行に配置された前記第2面上の前記外部電極と接続されていることを特徴とする部品内蔵型回路基板。
In a component-embedded circuit board in which a chip resistor is embedded in an inner layer of a base substrate made of an insulating resin layer, and via holes reaching the chip resistor from the surface of the base substrate are provided,
The chip resistor includes a rectangular parallelepiped insulating substrate, a pair of internal electrodes formed on a first surface, which is one surface of the insulating substrate, with a predetermined interval, and a resistor formed between the pair of internal electrodes. A body, an insulating protective film formed to cover the resistor, and a pair of external electrodes formed on a second surface adjacent to the first surface of the insulating substrate and connected to the internal electrodes With
The first surface is disposed so as to face a surface orthogonal to the surface of the base substrate, and the via hole is connected to the external electrode on the second surface disposed in parallel with the surface of the base substrate. A circuit board with built-in components.
請求項1の記載において、前記ベース基板に前記チップ抵抗器の前記第1面を包囲する放熱体が埋め込まれていることを特徴とする部品内蔵型回路基板。   2. The component-embedded circuit board according to claim 1, wherein a heat radiating body surrounding the first surface of the chip resistor is embedded in the base substrate. 直方体形状の絶縁基板と、この絶縁基板の一面である第1面に所定間隔を存して形成された一対の内部電極と、これら一対の内部電極間に形成された抵抗体と、この抵抗体を覆うように形成された絶縁性の保護膜と、前記絶縁基板の前記第1面に隣接する第2面に形成されて前記内部電極と接続する一対の外部電極とを備え、
前記一対の外部電極の間隔が前記一対の内部電極の間隔よりも狭く設定されていることを特徴とする基板内層用チップ抵抗器。
A rectangular parallelepiped insulating substrate, a pair of internal electrodes formed on the first surface, which is one surface of the insulating substrate, with a predetermined interval, a resistor formed between the pair of internal electrodes, and the resistor And a pair of external electrodes formed on a second surface adjacent to the first surface of the insulating substrate and connected to the internal electrodes.
A chip resistor for an inner layer of a substrate, wherein an interval between the pair of external electrodes is set narrower than an interval between the pair of internal electrodes.
請求項3の記載において、前記絶縁基板の前記第1面と対向する別の第1面に、所定間隔を存して形成された一対の内部電極と、これら一対の内部電極間に形成された抵抗体と、この抵抗体を覆うように形成された絶縁性の保護膜とが形成されており、前記外部電極は前記2つの第1面に形成された前記内部電極とそれぞれ接続していることを特徴とする基板内層用チップ抵抗器。   4. The method according to claim 3, wherein a pair of internal electrodes formed on the first surface opposite to the first surface of the insulating substrate at a predetermined interval are formed between the pair of internal electrodes. A resistor and an insulating protective film formed so as to cover the resistor are formed, and the external electrodes are connected to the internal electrodes formed on the two first surfaces, respectively. A chip resistor for an inner layer of a substrate. 請求項3または4の記載において、前記保護膜は前記抵抗体と前記内部電極の全体を覆っていることを特徴とする基板内層用チップ抵抗器。   5. The chip resistor for an inner layer of a substrate according to claim 3, wherein the protective film covers the resistor and the whole internal electrode.
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