JP2017135129A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which can supply sufficient power to a mounting semiconductor element thereby to enable normal operation of the mounted semiconductor element.SOLUTION: In a wiring board, land patterns 13 in a third wiring conductor 2 from the top are arranged outside a region and along the region which penetrates between positions on a third mat pattern 12-3 corresponding to second semiconductor element connection pads and a position on the third mat pattern 12-3 corresponding to a first through hole 6-1 so that a low-resistant current path without the intervening the land pattern 13 is ensured between the positions on the third mat pattern 12-3 corresponding to the second semiconductor element connection pads and the position on the third mat pattern 12-3 corresponding to the first through hole 6-1.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a wiring board for mounting a semiconductor element.

  FIG. 7 shows a conventional wiring substrate 40 used for mounting a semiconductor element S such as a semiconductor integrated circuit element. The wiring substrate 40 includes an insulating substrate 21 formed by laminating a plurality of build-up insulating layers 21b on the upper and lower surfaces of the core insulating layer 21a, and wiring conductors disposed inside and above and below the insulating substrate 21. 22 and a solder resist layer 23 deposited on the upper and lower surfaces of the insulating substrate 21 and the wiring conductor 22 thereon.

  A mounting portion 40 </ b> A is provided at the center of the upper surface of the wiring substrate 40. The mounting portion 40A is a quadrangular region for mounting the semiconductor element S. A large number of semiconductor element connection pads 24 are arranged two-dimensionally on the mounting portion 40A. The semiconductor element connection pad 24 is formed by exposing a part of the wiring conductor 22 deposited on the upper surface of the insulating substrate 21 from an opening provided in the solder resist layer 23. The electrode T of the semiconductor element S is connected to the semiconductor element connection pad 24 by flip chip connection.

  The lower surface of the wiring board 40 is a connection surface with the external electric circuit board. On the lower surface of the wiring board 40, a large number of external connection pads 25 are arranged two-dimensionally over substantially the entire area. The external connection pad 25 is formed by exposing a part of the wiring conductor 22 deposited on the lower surface of the insulating substrate 21 from an opening provided in the solder resist layer 23 on the lower surface side. The external connection pad 25 is connected to the wiring conductor of the external electric circuit board through, for example, a solder ball.

  A number of through holes 26 are formed in the insulating layer 21a. A through-hole conductor 27 is deposited in the through-hole 26. The wiring conductors 22 on the upper and lower surfaces of the insulating layer 21a are connected to each other through the through-hole conductor 27.

  A large number of via holes 28 are formed in each insulating layer 21b. A via hole conductor 29 is deposited in the via hole 28. Via the via-hole conductors 29, the wiring conductors 22 positioned above and below are connected with the insulating layer 21b interposed therebetween.

  The wiring conductor 22 including the semiconductor element connection pad 24 and the external connection pad 25 includes a signal, a ground, and a power source. Most of the signal semiconductor element connection pads 24 are arranged on the outer peripheral portion of the mounting portion 40A. Most of the grounding semiconductor element connection pads 24 and the power supply semiconductor element connection pads 24 are arranged in the center of the mounting portion 40A. Correspondingly, most of the signal external connection pads 25 are disposed on the outer peripheral portion of the lower surface of the insulating substrate 21. The grounding external connection pads 25 and the power supply external connection pads 25 are disposed at the center and the outer periphery of the lower surface of the insulating substrate 21.

  The signal semiconductor element connection pad 24 and the signal external connection pad 25 are connected to each other by a signal wiring conductor 22. The signal wiring conductor 22 has a belt-like pattern 30 extending from the region corresponding to the mounting portion 40A toward the outer peripheral portion of the insulating substrate 21 on the surface of the insulating layer 21b laminated on the upper surface side of the insulating layer 21a. . The strip pattern 30 and the signal semiconductor element connection pad 24 are connected via a via-hole conductor 29 in a region corresponding to the mounting portion 40A. The strip pattern 30 and the signal external connection pad 25 are connected to each other on the outer peripheral portion of the insulating substrate 21 through a through-hole conductor 27 and a via-hole conductor 29.

  The grounding semiconductor element connection pad 24 and the grounding external connection pad 25 are connected to each other by a grounding wiring conductor 22. The power supply semiconductor element connection pad 24 and the power supply external connection pad 25 are connected to each other by a power supply wiring conductor 22. The grounding wiring conductor 22 and the power supply wiring conductor 22 have a solid pattern 31 having a large area. Part of the solid pattern 31 is disposed on the left and right and top and bottom of the signal wiring conductor 22. The solid pattern 31 is formed on the surface of each insulating layer 21b stacked on both sides of the insulating layer 21a. The solid pattern 31 is formed over a wide region from the region corresponding to the mounting portion 40 </ b> A to the outer peripheral portion of the insulating substrate 21. The solid pattern 31 and the semiconductor element connection pad 24 for grounding or power supply are connected via a via-hole conductor 29 in a region immediately below the mounting portion 40A. Further, the solid pattern 31 and the external connection pad 25 for grounding or power supply are connected via a through-hole conductor 27 and a via-hole conductor 29 in a region extending from the central portion to the outer peripheral portion of the insulating substrate 21. .

  Here, a plan view of the main part of the uppermost wiring conductor 22 is shown in FIG. The conductor layer 22 has a signal semiconductor element connection pad 24S and a solid pattern 31 for grounding or power. A part of the solid pattern 31 forms a semiconductor element connection pad 24G (P) for grounding or power. In FIG. 6, a region corresponding to the mounting portion 40A is indicated by a two-dot chain line. Further, the grounding or power supply semiconductor element connection pads 24G (P) are indicated by dotted circles. Furthermore, the connection position of the via-hole conductor 29 to the lower wiring conductor 22 is indicated by a small cross. Furthermore, the position of the through hole 26 connected to the solid pattern 31 is indicated by a broken-line circle.

  Each of the signal semiconductor element connection pads 24S has an independent circular shape. These semiconductor element connection pads 24 </ b> S are electrically connected to signal strip patterns 30 described later via via-hole conductors 29.

  The solid pattern 31 is a wide area pattern that extends from the region corresponding to the mounting portion 40 </ b> A to the outer peripheral portion of the insulating substrate 21. The solid pattern 31 is provided with a plurality of mesh-like openings 31a for venting gas. The solid pattern 31 integrally has a plurality of semiconductor element connection pads 24G (P) in a region corresponding to the mounting portion 40A. The solid pattern 31 is electrically connected to the lower solid pattern 31 at a position corresponding to each semiconductor element connection pad 24G (P) and a position corresponding to the through hole 26.

  FIG. 9 is a plan view of the main part of the wiring conductor 22 in the second layer from the top. The wiring conductor 22 in this layer has a plurality of strip-like patterns 30 for signals and a solid pattern 31 for grounding or power. The region corresponding to the mounting portion 40A and the connection position of the via hole conductor 29 to the lower wiring conductor 22 and the position of the through hole 26 connected to the solid pattern 31 are shown in the same manner as in FIG. Further, the connection position of the via-hole conductor 29 from the upper wiring conductor 22 is indicated by a small black circle.

  A plurality of signal strip patterns 30 extend in parallel from right under the signal semiconductor element connection pads 24S to the outer peripheral portion of the insulating substrate 21 to the front of the through holes 26 connected to the solid pattern 31. Yes. A via hole conductor 29 from the semiconductor element connection pad 24S is connected to the end of each strip pattern 30 on the mounting portion 40A side, and a via hole connected to the lower wiring conductor 22 is connected to the end of the through hole 26 side. A conductor 29 is connected.

  The solid pattern 31 is a wide area pattern that extends from directly below the mounting portion 40A to the outer peripheral portion of the insulating substrate 21, and surrounds the belt-shaped pattern 30 for each signal. A plurality of via-hole conductors 29 from the semiconductor element connection pads 24G (P) are connected to the solid pattern 31 in a region corresponding to the mounting portion 40A, and an upper solid pattern is also formed at a position corresponding to the through hole 26. A plurality of via-hole conductors 29 from 31 are connected.

  FIG. 10 is a plan view showing the third wiring conductor 22 from the top. The wiring conductor 22 of this layer has a signal land 32 and a solid pattern 31. The region corresponding to the mounting portion 40A, the connection position of the via-hole conductor 29, and the position of the through hole 26 connected to the solid pattern 31 are shown in the same manner as in FIGS.

  Each land 32 has an independent circular shape. These lands 32 are arranged immediately below the end portions on the through hole 26 side of the respective band-like patterns 30. Via holes 29 from the belt-like pattern 30 are connected to the lands 32.

  The solid pattern 31 is a wide-area pattern that extends from directly below the mounting portion 40 </ b> A to the outer peripheral portion of the insulating substrate 21, and surrounds each land 32. A plurality of via-hole conductors 29 from the upper solid pattern 31 are connected to the solid pattern 31 in a region corresponding to the mounting portion 40 </ b> A, and from the upper solid pattern 31 to a position corresponding to the through hole 26. A plurality of via-hole conductors 29 are connected.

  FIG. 11 is a plan view of the main part of the fourth wiring conductor 22 from the top. The wiring conductor 22 of this layer has a plurality of strip-like patterns 30 for signals, a solid pattern 31 for grounding or power, and a land 33 for grounding or power. The region corresponding to the mounting portion 40A, the connection position of the via hole conductor 29, and the position of the through hole 26 connected to the solid pattern 31 are shown in the same manner as in FIGS.

  The signal strip pattern 30 extends so that the interval between the signal strip pattern 30 increases from directly below the signal land 32 toward the outer periphery of the insulating substrate 21. A via-hole conductor 29 from the land 32 is connected to the end portion of each strip pattern 30 on the land 32 side, and the end portion on the outer peripheral side of the insulating substrate 21 is not shown in the signal through-hole conductor 27 (not shown). They are electrically connected via via-hole conductors 29.

  The land 33 is a circle having four protrusions. The land 33 is disposed immediately above the through hole 26. A via-hole conductor 29 from the upper solid pattern 31 is connected to the land 33.

  The solid pattern 31 is a wide-area pattern that extends from directly below the mounting portion 40A to the outer peripheral portion of the insulating substrate 21, and surrounds the periphery of the belt-like pattern 30 for each signal and the periphery of the land 33. The solid pattern 31 of this layer is connected to a ground or power supply potential having a potential different from that of the solid pattern 30 of the upper layer.

  However, according to this conventional wiring board 40, as shown in FIG. 12, in the third wiring conductor 22 from the top, the signal land 32 is located between the mounting portion 40A and the grounding or power supply through hole 26. Therefore, the electrical resistance value of the current path between the through hole 26 and the mounting portion 40A in the solid pattern 31 becomes large. As a result, when the semiconductor element S having a low operating voltage and a large operating current is mounted, sufficient power supply to the semiconductor element S cannot be performed, and the semiconductor element S may not be normally operated.

JP 2011-249734 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring board that can supply sufficient power to a semiconductor element to be mounted and can normally operate the semiconductor element to be mounted.

  The wiring board of the present invention is formed by laminating a plurality of build-up insulating layers having a plurality of via holes of at least four layers on the upper and lower surfaces of a core insulating layer having a plurality of through-holes. An insulating substrate having a rectangular mounting portion on which a semiconductor element is mounted and a lower surface serving as a connection surface with an external electric circuit substrate; upper and lower surfaces of the core insulating layer; and a surface of the build-up insulating layer A wiring conductor attached to the through hole, and a through hole conductor that is attached to the through hole and electrically connects the wiring conductors positioned above and below the insulating layer for the core, and the via hole And a via-hole conductor that electrically connects the wiring conductors positioned above and below with the insulating layer for buildup interposed therebetween, and the wiring conductor in the uppermost layer has the mounting portion. A plurality of semiconductor element connection pads including a signal semiconductor element connection pad, a ground semiconductor element connection pad, and a power supply semiconductor element connection pad are arranged adjacent to each other along the outer periphery of the mounting portion. Having a grid-like array having a plurality of rows including a side row and an inner circumferential side row, and having a first solid pattern for grounding or power supply extending from the mounting portion to the outer peripheral portion of the insulating substrate, The outer peripheral side row includes a first semiconductor element connection pad group in which a plurality of signal semiconductor element connection pads are arranged adjacent to each other, and the inner peripheral side row includes the first solid pattern and A plurality of integrated second semiconductor element connection pad groups for grounding or power supply are adjacent to the first semiconductor element pad group, and the wiring conductor in the second layer from the top has one end portion The first The first solid pattern is electrically connected to the signal semiconductor element connection pad of the conductor element connection pad group via the via-hole conductor, and the other end portion is directed toward the outer peripheral portion of the insulating substrate. A plurality of strip-like patterns extending in parallel up to a position before the first through-hole connected to the substrate, and a position corresponding to the second semiconductor element connection pad group and the first through-hole The second solid pattern is connected to the first solid pattern via the via-hole conductor at a position where the second solid pattern for grounding or power supply surrounds the plurality of strip-shaped patterns. The wiring conductor in the layer is provided at a position corresponding to the other end of each strip pattern, and a plurality of run conductors each electrically connected to the strip pattern via the via hole conductor. And a pattern corresponding to the second semiconductor element connection pad group and a position corresponding to the first through hole to the second solid pattern via the via-hole conductor, A wiring board having a third solid pattern for grounding or power supply surrounding the plurality of land patterns, wherein the land pattern corresponds to the second semiconductor element connection pad group. And a position corresponding to the first through-hole, and is disposed along the region outside the region that can be seen through.

  According to the wiring board of the present invention, the land pattern in the third wiring conductor from the top corresponds to the position corresponding to the second semiconductor element connection pad group and the position corresponding to the first through hole in the third solid pattern. Are disposed along the region outside the region foreseeing between the first and second regions, so that the position corresponding to the second semiconductor element connection pad group and the position corresponding to the first through hole in the third solid pattern A low-resistance current path with no land pattern interposed therebetween is ensured. Therefore, a sufficient power supply can be supplied from the first through hole to the second semiconductor element connection pad group via the third solid pattern, thereby enabling the mounted semiconductor element to operate normally. Can be provided.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a schematic top view of the main part showing the uppermost wiring conductor in the wiring board shown in FIG. FIG. 3 is a schematic top view showing the main part of the wiring conductor in the second layer from the top in the wiring board shown in FIG. FIG. 4 is a schematic top view of a main part showing a third-layer wiring conductor from the top in the wiring board shown in FIG. FIG. 5 is a schematic top view of the main part showing the fourth-layer wiring conductor from the top in the wiring board shown in FIG. FIG. 6 is a schematic top view of a main part showing a current path in the third wiring conductor from the top in the wiring board shown in FIG. FIG. 7 is a schematic sectional view showing a conventional wiring board. FIG. 8 is a schematic top view of the main part showing the uppermost wiring conductor in the conventional wiring board. FIG. 9 is a schematic top view of a main part showing a second-layer wiring conductor from the top in a conventional wiring board. FIG. 10 is a schematic top view of a main part showing a third-layer wiring conductor from the top in a conventional wiring board. FIG. 11 is a schematic top view of a main part showing a fourth-layer wiring conductor from the top in a conventional wiring board. FIG. 12 is a schematic top view of a main part showing a current path in a third-layer wiring conductor from the top in a conventional wiring board.

  Next, an example of an embodiment of the wiring board of the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing a wiring board 20 which is an example of an embodiment of the present invention. In FIG. 1, 1 is an insulating substrate, 2 is a wiring conductor, 3 is a solder resist layer, 4 is a semiconductor element connection pad, and 5 is an external connection pad.

  The wiring board 20 of this example includes an insulating substrate 1 in which a plurality of build-up insulating layers 1b are stacked on the upper and lower surfaces of the core insulating layer 1a, and the upper and lower surfaces of the insulating layer 1a and the insulating layers 1b. The wiring conductor 2 is attached, and the outermost insulating layer 1b and the solder resist layer 3 deposited on the wiring conductor 2 are provided.

  A mounting portion 20 </ b> A is provided at the center of the upper surface of the wiring substrate 20. The mounting portion 20A is a quadrangular region for mounting the semiconductor element S. A large number of semiconductor element connection pads 4 are arranged two-dimensionally on the mounting portion 20A. The semiconductor element connection pad 4 is formed by exposing a part of the wiring conductor 2 deposited on the upper surface of the insulating substrate 1 from an opening provided in the solder resist layer 3. The electrode T of the semiconductor element S is connected to the semiconductor element connection pad 4 by flip chip connection. The diameter of the semiconductor element connection pad 4 is about 50 to 100 μm. The arrangement pitch of the semiconductor element connection pads 4 is about 100 to 250 μm.

  The lower surface of the wiring board 20 is a connection surface with the external electric circuit board. A large number of external connection pads 5 are arranged two-dimensionally on the lower surface of the wiring board 20 over substantially the entire area. The external connection pad 5 is formed by exposing a part of the wiring conductor 2 deposited on the lower surface of the insulating substrate 1 from an opening provided in the solder resist layer 3 on the lower surface side. The external connection pad 5 is connected to the wiring conductor of the external electric circuit board through, for example, a solder ball. The diameter of the external connection pad 5 is about 300 to 500 μm. The arrangement pitch of the external connection pads 5 is about 600 to 1000 μm.

  The insulating layer 1a constituting the insulating substrate 1 is a core member in the wiring substrate 20 of this example. The insulating layer 1a is formed, for example, by impregnating a glass fabric in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The thickness of the insulating layer 1a is about 0.1 to 1 mm. A number of through holes 6 are formed in the insulating layer 1a from its upper surface to its lower surface. The diameter of the through hole 6 is about 0.1 to 1 mm. A through-hole conductor 7 is deposited in the through-hole 6. The wiring conductors 2 on the upper and lower surfaces of the insulating layer 1a are connected to each other through the through-hole conductors 7.

  Such an insulating layer 1a is manufactured by thermally curing an insulating sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling the insulating sheet from the upper surface to the lower surface. The wiring conductors 2 on the upper and lower surfaces of the insulating layer 1a are formed in a predetermined pattern by attaching copper foil to the entire upper and lower surfaces of the insulating sheet for the insulating layer 1a and etching the copper foil after the sheet is cured. The The through-hole conductor 7 in the through-hole 6 is formed by depositing a copper plating film on the inner surface of the through-hole 6 by electroless plating and electrolytic plating after providing the through-hole 6 in the insulating layer 1a.

  Further, the inside of the through hole 6 to which the through hole conductor 7 is attached is filled with a hole filling resin 8. The hole filling resin 8 is made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The hole-filling resin 8 is for making it possible to form the wiring conductor 2 and each insulating layer 1b directly above and below the through-hole 6 by closing the through-hole 6. The hole-filling resin 8 is formed by filling an uncured paste-like thermosetting resin into the through-hole 6 by screen printing, thermally curing it, and then polishing its upper and lower surfaces substantially flatly. The

  Each insulating layer 1b laminated on the upper and lower surfaces of the insulating layer 1a is made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. As for the thickness of the insulating layer 1b, each thickness is about 20-60 micrometers. The insulating layer 1b has a plurality of via holes 9 from the upper surface to the lower surface of each layer. The diameter of the via hole 9 is about 30 to 100 μm. A via hole conductor 10 is filled in the via hole 9. The upper wiring conductor 2 and the lower wiring conductor 2 are connected to each other through the via-hole conductor 10.

  Each such insulating layer 1b is formed by sticking an insulating film made of an uncured thermosetting resin having a thickness of about 20 to 60 μm on the upper or lower surface of the insulating layer 1a or the lower insulating layer 1b, and thermosetting it. And via holes 9 are formed by laser processing. The wiring conductor 2 on the surface of each insulating layer 1b and the via-hole conductor 10 in the via hole 9 are formed by depositing copper plating on the surface of each insulating layer 1b and in the via hole 9 each time each insulating layer 1b is formed. The A well-known semi-additive method is used for copper plating deposition.

  The solder resist layer 3 is made of a thermosetting resin having photosensitivity such as an acrylic-modified epoxy resin. The thickness of the solder resist layer 3 is about 10 to 50 μm. The solder resist layer 3 protects the wiring conductor 2 on the outermost layer and enables connection between the semiconductor element connection pad 4 and the external connection pad 5 and the semiconductor element S and the external electric circuit board through the opening.

  Such a solder resist layer 3 is formed by applying or sticking a photosensitive resin paste or resin film to the surfaces of the uppermost layer and the lowermost insulating layer 1b and using a photolithography technique to expose and develop a predetermined pattern. Then, it is formed by ultraviolet curing and heat curing.

  In the wiring board 20 of this example, the wiring conductor 2 including the semiconductor element connection pads 4 and the external connection pads 5 includes signals, grounds, and power supplies. Most of the signal semiconductor element connection pads 4 are arranged on the outer peripheral portion of the mounting portion 20A. Most of the grounding semiconductor element connection pads 4 and the power supply semiconductor element connection pads 4 are arranged at the center of the mounting portion 20A. Correspondingly, most of the signal external connection pads 5 are arranged on the outer peripheral portion of the lower surface of the insulating substrate 1. The grounding external connection pad 5 and the power supply external connection pad 5 are disposed at the center and the outer periphery of the lower surface of the insulating substrate 1.

  The signal semiconductor element connection pad 4 and the signal external connection pad 5 are connected to each other by a signal wiring conductor 2. The signal wiring conductor 2 has a strip-like pattern 11 extending from the region corresponding to the mounting portion 20A toward the outer peripheral portion of the insulating substrate 1 on the surface of the insulating layer 2b laminated on the upper surface side of the insulating layer 1a. . The strip pattern 11 and the signal semiconductor element connection pad 4 are connected via a via-hole conductor 10 in a region corresponding to the mounting portion 20A. Further, the strip pattern 11 and the signal external connection pad 5 are connected to each other on the outer peripheral portion of the insulating substrate 1 through the through-hole conductor 7 and the via-hole conductor 10.

  The grounding semiconductor element connection pad 4 and the grounding external connection pad 5 are connected to each other by a grounding wiring conductor 2. The power supply semiconductor element connection pad 4 and the power supply external connection pad 5 are connected to each other by a power supply wiring conductor 2. The grounding wiring conductor 2 and the power supply wiring conductor 2 have a solid pattern 12 having a large area. Part of the solid pattern 12 is arranged on the left and right and top and bottom of the signal wiring conductor 2. The solid pattern 12 is formed on the surface of the insulating layer 1b laminated on both sides of the insulating layer 1a. The solid pattern 12 is formed over a wide region from the region corresponding to the mounting portion 20 </ b> A to the outer peripheral portion of the insulating substrate 1. The solid pattern 12 and the semiconductor element connection pad 4 for grounding or power supply are connected via a via-hole conductor 10 immediately below the mounting portion 20A. The solid pattern 12 and the external connection pad 5 for grounding or power supply are connected via a through-hole conductor 7 and a via-hole conductor 10 in a region extending from the central portion to the outer peripheral portion of the insulating substrate 1. .

  Here, a plan view of the main part of the uppermost wiring conductor 2 is shown in FIG. The conductor layer 2 has a signal semiconductor element connection pad 4S and a first solid pattern 12-1 for grounding or power. A part of the first solid pattern 12-1 forms a semiconductor element connection pad 4G (P) for grounding or power. In FIG. 2, a region corresponding to the mounting portion 20A is indicated by a two-dot chain line. Further, the grounding or power supply semiconductor element connection pads 4G (P) are indicated by dotted circles. Furthermore, the connection position of the via-hole conductor 10 to the lower wiring conductor 2 is indicated by a small cross. Furthermore, the position of the first through hole 6-1 connected to the first solid pattern 12-1 is indicated by a broken-line circle.

  The semiconductor element connection pads 4 are arranged in a grid having a plurality of rows including an outer circumferential row and an inner circumferential row arranged adjacent to each other along the outer periphery of the mounting portion 20A. The signal semiconductor element connection pads 4 </ b> S have a first semiconductor element connection pad group in which a plurality of signal semiconductor element connection pads 4 </ b> S are arranged adjacent to each other on the outer peripheral side row of the semiconductor element connection pads 4. Each semiconductor element connection pad 4S has an independent circular shape. These semiconductor element connection pads 4S are electrically connected to a signal strip pattern 11 described later via via-hole conductors 10.

  The first solid pattern 12-1 is a wide area pattern that extends from the region corresponding to the mounting portion 20 </ b> A to the outer peripheral portion of the insulating substrate 1. The first solid pattern 12-1 is provided with a plurality of mesh-like openings 12a for venting gas. The first solid pattern 12-1 integrally has a plurality of semiconductor element connection pads 4G (P) in a region corresponding to the mounting portion 20A. The semiconductor element connection pads 4G (P) have a second semiconductor element connection pad group in which a plurality of semiconductor element connection pads 4G (P) are arranged adjacent to each other in the inner row of the array of semiconductor element connection pads 4. The second semiconductor element connection pad group is disposed adjacent to the first semiconductor element connection pad group for signals. The first solid pattern 12-1 is a lower second solid pattern 12- described below at a position corresponding to each semiconductor element connection pad 4G (P) and a position corresponding to the first through hole 6-1. The second and third solid patterns 12-3 are electrically connected.

  FIG. 3 is a plan view of the main part of the wiring conductor 2 in the second layer from the top. The wiring conductor 2 of this layer has a plurality of strip patterns 11 for signals and a second solid pattern 12-2 for grounding or power. The region corresponding to the mounting portion 20A and the connection position of the via-hole conductor 10 to the lower wiring conductor 2 and the position of the first through hole 6-1 connected to the second solid pattern 12-2 are shown in FIG. As well as. Further, the connection position of the via-hole conductor 10 from the upper wiring conductor 2 is indicated by a small black circle.

  A plurality of signal strip patterns 11 extend in parallel from directly under the signal semiconductor element connection pads 4S to the outer periphery of the insulating substrate 1 to the front of the first through holes 6-1. The band-shaped pattern 11 is outside the region in which the end portion side on the first through hole 6-1 side sees between the position corresponding to the second semiconductor element pad group and the position corresponding to the first sou hole 6-1. It is bent to spread. The end of the belt-like pattern 11 on the first through-hole 6-1 side is outside the region that can be seen between the position corresponding to the second semiconductor element pad group and the position corresponding to the first soot hole 6-1. , And are arranged along this area. A via-hole conductor 10 from the semiconductor element connection pad 4S is connected to the end of each strip pattern 11 on the mounting portion 20A side, and a lower-layer wiring conductor is connected to the end of the first through-hole 6-1 side. A via-hole conductor 10 connected to 2 is connected.

  The second solid pattern 12-2 is a wide-area pattern that extends from directly under the mounting portion 20A to the outer peripheral portion of the insulating substrate 1, and surrounds the periphery of the belt-like pattern 11 for each signal. In the second solid pattern 12-2, a plurality of via-hole conductors 10 from the semiconductor element connection pads 4G (P) are connected to the region corresponding to the mounting portion 20A, and the first through-holes 6-1 are connected. A plurality of via-hole conductors 10 from the first solid pattern 12-1 in the upper layer are also connected to corresponding positions.

  FIG. 4 shows a plan view of the main part of the third wiring conductor 2 from the top. The wiring conductor 2 of this layer has a signal land 13 and a third solid pattern 12-3. The region corresponding to the mounting portion 20A, the connection position of the via-hole conductor 10, and the position of the first through hole 6-1 connected to the third solid pattern 12-3 are shown in the same manner as in FIGS. Yes.

  Each land 13 has an independent circular shape. These lands 13 are arranged immediately below the end portion of each strip pattern 11 on the first through-hole 6-1 side. That is, the lands 13 are arranged so as to be lined up along the region outside the region foreseeing between the position corresponding to the second semiconductor element pad group and the position corresponding to the first Sue hole 6. Via holes 10 from the belt-like pattern 11 are connected to the lands 13.

  The third solid pattern 12-3 is a wide-area pattern that extends from directly below the mounting portion 20A to the outer peripheral portion of the insulating substrate 1 and surrounds each land 13. A plurality of via-hole conductors 10 from the upper second solid pattern 12-2 are connected to the third solid pattern 12-3 in a region corresponding to the mounting portion 20A, and the first through-hole 6 Also, a plurality of via-hole conductors 10 from the upper second solid pattern 12-2 are connected to the position corresponding to -1.

  FIG. 5 is a plan view of the main part of the fourth wiring conductor 2 from the top. The wiring conductor 2 of this layer has a plurality of strip-like patterns 11 for signals, a fourth solid pattern 12-4 for grounding or power supply, and a land 14 for grounding or power supply. In addition, the area | region corresponding to 20 A of mounting parts, the connection position of the via-hole conductor 10, and the position of the 1st through-hole 6-1 are shown similarly to FIGS.

  The land 14 has a circular shape having four protrusions. The land 14 is disposed immediately above the first through hole 6-1. The via hole conductor 10 from the upper third solid pattern 12-3 is connected to the land 14.

  The fourth solid pattern 12-4 is a wide area pattern that extends from directly below the mounting portion 20A to the outer peripheral portion of the insulating substrate 1, and surrounds the periphery of the belt-like pattern 11 for each signal and the periphery of the land 14. . The fourth solid pattern 12-4 is connected to a ground or power supply potential different from that of the first to third solid patterns 12-1 to 12-3.

  In the wiring board 20 of this example, as described above, the land pattern 13 in the third wiring conductor 2 from the top corresponds to the second semiconductor element connection pad group in the third solid pattern 12-3. And the third through pattern 12-as shown in FIG. 6 because it is arranged along this region outside the region that can be seen between the first through hole 6-1 and the position corresponding to the first through hole 6-1. 3, a low-resistance current path in which the land pattern 13 is not interposed is ensured between the position corresponding to the second semiconductor element connection pad group 3 and the position corresponding to the first through hole 6-1. Therefore, sufficient power can be supplied from the first through hole 6-1 to the second semiconductor element connection pad group via the third solid pattern 12-3, and the mounted semiconductor element S operates normally. The wiring board 20 that can be made to be provided can be provided.

1. Insulating substrate 1a ... Core insulating layer 1b ... Build-up insulating layer 2 .... Wiring conductor 4 ....・ ・ ・ Semiconductor element connection pad 4G (P) ・ ・ ・ Semiconductor element connection pad for grounding or power supply 4S ・ ・ ・ ・ ・ ・ Semiconductor element connection pad for signal 5 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ External connection pad 6 .... Through hole 6-1 ... First through hole 7 ... ... Through hole conductor 9 ... Via hole 10 ... Via-hole conductor 11... Strip pattern 12-1... First solid pattern 12-2... Second solid pattern 12-3. Solid pattern 12 ... Solid pattern 17 ... Degassing opening 20 And wiring substrate 20A · · · · · · mounting portion S · · · · · · · semiconductor element

Claims (1)

  A plurality of build-up insulating layers having at least four or more via holes are laminated on the upper and lower surfaces of a core insulating layer having a plurality of through holes, and a semiconductor element is mounted at the center of the upper surface. An insulating substrate having a rectangular mounting portion and having a lower surface serving as a connection surface with an external electric circuit substrate, and a wiring conductor attached to the upper and lower surfaces of the core insulating layer and the surface of the build-up insulating layer And a through-hole conductor that is electrically connected between the wiring conductors located above and below the insulating layer for the core, and is attached in the via hole, A via-hole conductor that electrically connects the wiring conductors positioned above and below with the insulating layer for buildup interposed therebetween, and the wiring conductor in the uppermost layer has a signal semiconductor element on the mounting portion. A plurality of semiconductor element connection pads including a connection pad, a semiconductor element connection pad for grounding, and a semiconductor element connection pad for power supply are arranged adjacent to each other along the outer periphery of the mounting portion. And having a first solid pattern for grounding or power supply extending from the mounting portion to the outer peripheral portion of the insulating substrate, and having a plurality of rows including a plurality of rows, and in the outer peripheral side row, A plurality of signal semiconductor element connection pads have a first semiconductor element connection pad group arranged adjacent to each other, and a plurality of signal lines integrated with the first solid pattern are formed on the inner circumferential side row. A second semiconductor element connection pad group for grounding or power supply is adjacent to the first semiconductor element pad group, and the wiring conductor in the second layer from the top has one end at the first semiconductor element. Connection pad The signal semiconductor element connection pad is connected via the via-hole conductor, and the other end is electrically connected to the first solid pattern toward the outer periphery of the insulating substrate. A plurality of strip-like patterns extending in parallel to a position before one through hole, and a position corresponding to the second semiconductor element connection pad group and a position corresponding to the first through hole. The first wiring is connected to the first solid pattern via the via-hole conductor, has a second solid pattern for grounding or power supply surrounding the plurality of strip-shaped patterns, and the wiring in the third layer from the top The conductor has a plurality of land patterns that are electrically connected to the belt-like pattern via the via-hole conductors at positions corresponding to the other end portions of the belt-like patterns. Both are connected to the second solid pattern via the via-hole conductor at a position corresponding to the second semiconductor element connection pad group and a position corresponding to the first through hole. A wiring board having a third solid pattern for grounding or power supply surrounding the periphery of the pattern, wherein the land pattern has a position corresponding to the second semiconductor element connection pad group and the first pattern. A wiring board, wherein the wiring board is disposed along an area outside the area that can be seen through to a position corresponding to the through hole.

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