JP2017152449A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board that can prevent the wet spread of sealing resin while the wiring conductor is protected.SOLUTION: A wiring board 20 includes: a first insulating layer 1a including a mount part 20A where a semiconductor element S is mounted in a central part of an upper surface; a first wiring conductor 2a which is formed on an upper surface of the first insulating layer 1a and has a first solid pattern 12a surrounding the mount part 20A and a plurality of semiconductor element connection pads 4 arranged in the mount part 20A; and a solder resist layer 3a that is formed on the first insulating layer 1a and the first wiring conductor 2a, exposes the semiconductor element connection pad 4, and covers completely the first solid pattern 12a. The first solid pattern 12a includes a frame-shaped first opening 14a that surrounds the mount part 20A, and the solder resist layer 3a is formed so that a concave part 13 following the first opening 14a surrounds the mount part 20A.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a wiring board for mounting a semiconductor element.

  A wiring board for mounting a semiconductor element has a multilayer structure in which a plurality of insulating layers and wiring conductors are alternately stacked, and a solder resist layer is deposited on the outermost layer. A mounting portion on which a semiconductor element is mounted is formed at the center of the upper surface of the wiring board. In the mounting portion, a plurality of semiconductor element connection pads made of a part of the wiring conductor are arranged in a grid. The lower surface of the wiring board is a connection surface with an external electric circuit board. A plurality of external connection pads made of a part of the wiring conductor are arranged in a grid on the connection surface. A predetermined number of semiconductor element connection pads and external connection pads are electrically connected to each other via a wiring conductor inside the wiring board. The semiconductor element electrode pads are flip-chip connected to the electrode terminals of the semiconductor element. The external connection pads and the external electric circuit board are connected by solder balls. The solder resist layer covers the remaining portion of the wiring conductor in the same layer as the semiconductor element connection pad and the wiring conductor in the same layer as the external connection pad.

  In the flip-chip connection, the electrode terminals formed on the lower surface of the semiconductor element and the semiconductor element connection pads are connected via solder bumps. A gap is formed between the flip-chip connected semiconductor element and the wiring board. This gap is filled with a sealing resin called underfill. In order to fill the sealing resin, a method of injecting an uncured liquid thermosetting resin into the gap between the semiconductor element and the wiring substrate and then thermosetting is employed. However, when or after the liquid resin is injected, a part of the resin may be greatly spread around the mounting portion.

  Therefore, it has been proposed to provide grooves and protrusions in the solder resist layer around the mounting portion to prevent wetting and spreading of the sealing resin. When the groove is provided, the wiring conductor is exposed on the bottom surface of the groove, and the protection to the wiring conductor becomes insufficient. In addition, when the protrusion is provided, an extra process is required to provide the protrusion, and the productivity of the wiring board is reduced.

JP 2004-349399 A

  The problem to be solved by the present invention is to provide a wiring board that does not require an extra step and that can prevent the sealing resin from spreading while protecting the wiring conductor.

  The wiring board of the present invention is attached to the first insulating layer having a mounting portion on which the semiconductor element is mounted at the center of the upper surface and the upper surface of the first insulating layer, and is arranged in the mounting portion. A plurality of semiconductor element connection pads and a first wiring conductor having a first solid pattern surrounding the mounting portion; and being deposited on the first insulating layer and the first wiring conductor, A wiring board comprising a solder resist layer that exposes a semiconductor element connection pad and completely covers the first solid pattern, and the first solid pattern surrounds the mounting portion. The solder resist layer has a frame-shaped first opening, and a recess that follows the first opening is formed so as to surround the mounting portion. It is.

  According to the wiring board of the present invention, the solder resist layer completely covers the first solid pattern, and the first solid pattern has a frame-shaped opening that surrounds the mounting portion. In addition, the solder resist layer is formed so that the recess that follows the opening of the first solid pattern surrounds the mounting portion, so that no extra process is required and the wiring conductor is protected. It is possible to provide a wiring board capable of preventing the sealing resin from spreading and getting wet.

FIG. 1 is a schematic cross-sectional view showing an example of an embodiment of a wiring board according to the present invention. FIG. 2 is a schematic top view of the main part showing the uppermost wiring conductor in the wiring board shown in FIG. FIG. 3 is a schematic top view showing the main part of the wiring conductor in the second layer from the top in the wiring board shown in FIG. FIG. 4 is a schematic top view of a main part showing a third-layer wiring conductor from the top in the wiring board shown in FIG. FIG. 5 is a schematic top view of the main part showing the fourth-layer wiring conductor from the top in the wiring board shown in FIG. FIG. 6 is a schematic cross-sectional view showing a semiconductor device in which a semiconductor element is mounted on the wiring board shown in FIG.

  Next, an example of an embodiment of the wiring board according to the present invention will be described in detail with reference to FIGS. FIG. 1 is a schematic cross-sectional view showing a wiring board 20 which is an example of an embodiment of the present invention. In FIG. 1, 1 is an insulating substrate, 2 is a wiring conductor, 3 is a solder resist layer, 4 is a semiconductor element connection pad, and 5 is an external connection pad.

  In the wiring board 20 of this example, the insulating substrate 1 includes a plurality of insulating layers 1a to 1i. The wiring conductor 2 includes a plurality of wiring conductors 2a to 2j. The solder resist layer 3 includes upper and lower solder resist layers 3a and 3b.

  A mounting portion 20 </ b> A is provided at the center of the upper surface of the insulating substrate 1. The mounting portion 20A is a quadrangular region for mounting the semiconductor element S. A large number of semiconductor element connection pads 4 are arranged two-dimensionally on the mounting portion 20A. The semiconductor element connection pad 4 is formed by exposing a part of the wiring conductor 2a from an opening provided in the solder resist layer 3a. The electrode terminal T of the semiconductor element S is connected to the semiconductor element connection pad 4 by flip chip connection.

  The lower surface of the insulating substrate 1 is a connection surface with the external electric circuit substrate. A large number of external connection pads 5 are arranged two-dimensionally on the lower surface of the insulating substrate 1 over substantially the entire region. The external connection pad 5 is formed by exposing a part of the wiring conductor 2j from an opening provided in the solder resist layer 3b. The external connection pad 5 is connected to the wiring conductor of the external electric circuit board through, for example, a solder ball.

  The insulating layer 1e constituting the insulating substrate 1 is a core member in the wiring substrate 20 of this example. The insulating layer 1e is formed, for example, by impregnating a glass fabric in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The thickness of the insulating layer 1e is about 0.1 to 1 mm. A number of through holes 6 are formed in the insulating layer 1e from the upper surface to the lower surface. A through-hole conductor 7 is deposited in the through-hole 6. The wiring conductors 2e and 2f on the upper and lower surfaces of the insulating layer 1e are connected through the through-hole conductor 7.

  Such an insulating layer 1e is manufactured by thermally curing an insulating sheet in which a glass fabric is impregnated with an uncured thermosetting resin, and then drilling the insulating sheet from the upper surface to the lower surface. The wiring conductors 2e and 2f on the upper and lower surfaces of the insulating layer 1a are formed into a predetermined pattern by attaching a copper foil to the entire upper and lower surfaces of the insulating sheet for the insulating layer 1e and etching the copper foil after the sheet is cured. It is formed. The through-hole conductor 7 in the through-hole 6 is formed by depositing a copper plating film on the inner surface of the through-hole 6 by electroless plating and electrolytic plating after providing the through-hole 6 in the insulating layer 1e. The thickness of the wiring conductors 2e and 2f is about 20 to 40 μm.

  Further, the inside of the through hole 6 to which the through hole conductor 7 is attached is filled with a hole filling resin 8. The hole filling resin 8 is made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin. The hole-filling resin 8 is used to form the wiring conductors 2 e and 2 f and the insulating layers 1 d and 1 f immediately above and below the through-hole 6 by closing the through-hole 6. The hole-filling resin 8 is formed by filling an uncured paste-like thermosetting resin into the through-hole 6 by screen printing, thermally curing it, and then polishing its upper and lower surfaces substantially flatly. The

  The insulating layers 1a to 1d and 1f to 1i laminated on the upper and lower surfaces of the insulating layer 1e are made of a thermosetting resin such as an epoxy resin. The thicknesses of the insulating layers 1a to 1d and 1f to 1i are about 20 to 60 μm, respectively. The insulating layers 1a to 1d and 1f to 1i have a plurality of via holes 9 from the upper surface to the lower surface of each layer. A via hole conductor 10 is filled in the via hole 9. The upper wiring conductors 2 a to 2 d and 2 g to 2 i and the lower wiring conductors 2 b to 2 e and 2 h to 2 j are connected to each other through the via-hole conductor 10.

  Each of the insulating layers 1a to 1d and 1f to 1i is made of an insulating film made of an uncured thermosetting resin having a thickness of about 20 to 60 [mu] m, or an insulating layer 1b to 1d and 1f to 1h. It is formed by sticking to the surface, thermosetting it, and drilling the via hole 9 by laser processing. The wiring conductors 2a to 2d and 2h to 2j on the surfaces of the insulating layers 1a to 1d and 1f to 1i and the via-hole conductor 10 in the via hole 9 are formed each time the insulating layers 1a to 1d and 1f to 1i are formed. It is formed by depositing copper plating on the surfaces 1a to 1d and 1f to 1i and the via holes 9. A well-known semi-additive method is used for copper plating deposition. The thickness of the wiring conductors 2a to 2d and 2h to 2j is about 10 to 30 μm.

  The solder resist layers 3a and 3b are made of a thermosetting resin having photosensitivity such as an acrylic-modified epoxy resin. The thickness of the solder resist layers 3a and 3b is about 10 to 50 μm. The solder resist layers 3a and 3b protect the wiring conductor 2 in the outermost layer, and enable connection between the semiconductor element connection pad 4 and the external connection pad 5 and the semiconductor element S and the external electric circuit board through the opening. .

  Such solder resist layers 3a and 3b are formed by applying or pasting a photosensitive resin paste or resin film to the surfaces of the insulating layers 1a and 1i, and using a photolithography technique to expose and develop a predetermined pattern. It is formed by UV curing and heat curing.

  In the wiring board 20 of this example, the wiring conductor 2 including the semiconductor element connection pads 4 and the external connection pads 5 includes signals, grounds, and power supplies. Most of the signal semiconductor element connection pads 4 are arranged on the outer peripheral portion of the mounting portion 20A. Most of the grounding semiconductor element connection pads 4 and the power supply semiconductor element connection pads 4 are arranged at the center of the mounting portion 20A. Correspondingly, most of the signal external connection pads 5 are arranged on the outer peripheral portion of the lower surface of the insulating substrate 1. The grounding external connection pad 5 and the power supply external connection pad 5 are disposed at the center and the outer periphery of the lower surface of the insulating substrate 1.

  The signal semiconductor element connection pad 4 and the signal external connection pad 5 are connected to each other by a signal wiring conductor 2. The signal wiring conductor 2 has a belt-like pattern 11 extending from the region corresponding to the mounting portion 20 </ b> A toward the outer peripheral portion of the insulating substrate 1 on the surface of the insulating layers 1 b to 1 d. The strip pattern 11 and the signal semiconductor element connection pad 4 are connected via a via-hole conductor 10 in a region corresponding to the mounting portion 20A. Further, the strip pattern 11 and the signal external connection pad 5 are connected to each other on the outer peripheral portion of the insulating substrate 1 through the through-hole conductor 7 and the via-hole conductor 10.

  The grounding semiconductor element connection pad 4 and the grounding external connection pad 5 are connected to each other by a grounding wiring conductor 2. The power supply semiconductor element connection pad 4 and the power supply external connection pad 5 are connected to each other by a power supply wiring conductor 2. The grounding wiring conductor 2 and the power supply wiring conductor 2 have a solid pattern 12 having a large area. Part of the solid pattern 12 is arranged on the left and right and top and bottom of the signal wiring conductor 2. The solid pattern 12 is formed on the surfaces of the insulating layers 1a to 1i. The solid pattern 12 is formed over a wide region from the region corresponding to the mounting portion 20 </ b> A to the outer peripheral portion of the insulating substrate 1. The solid pattern 12 and the semiconductor element connection pad 4 for grounding or power supply are connected via a via-hole conductor 10 immediately below the mounting portion 20A. The solid pattern 12 and the external connection pad 5 for grounding or power supply are connected via a through-hole conductor 7 and a via-hole conductor 10 in a region extending from the central portion to the outer peripheral portion of the insulating substrate 1. .

  In the wiring board 20 of this example, the recess 13 is formed in the solder resist layer 3a around the mounting portion 20A. The concave portion 13 is formed in a frame shape surrounding the mounting portion 20A. The recess 13 has a width of about 1 to 3 mm and a depth of about 20 to 30 μm. The recess 13 is formed by providing a frame-shaped opening 14 surrounding the mounting portion 20A in the solid pattern 12 of the wiring conductor 2a. By providing such an opening 14, the solder resist layer 3 a follows the opening 14 to form a recess 13.

  Here, the principal part top view of the wiring conductor 2a of the uppermost layer is shown in FIG. The wiring conductor 2a has a semiconductor element connection pad 4S for signals and a solid pattern 12a for grounding or power supply. A part of the solid pattern 12a forms a grounding or power supply semiconductor element connection pad 4G (P). In FIG. 2, a region corresponding to the mounting portion 20A is indicated by a two-dot chain line. Further, the grounding or power supply semiconductor element connection pads 4G (P) are indicated by dotted circles. Furthermore, the connection position of the via-hole conductor 10 to the lower wiring conductor 2b is indicated by a small cross. Furthermore, the position of the through hole 6a connected to the solid pattern 12a is indicated by a broken-line circle.

  The semiconductor element connection pads 4 are arranged in a grid having a plurality of rows including an outer circumferential row and an inner circumferential row arranged adjacent to each other along the outer periphery of the mounting portion 20A. The signal semiconductor element connection pads 4 </ b> S have a first semiconductor element connection pad group in which a plurality of signal semiconductor element connection pads 4 </ b> S are arranged adjacent to each other on the outer peripheral side row of the semiconductor element connection pads 4. Each semiconductor element connection pad 4S has an independent circular shape. These semiconductor element connection pads 4S are electrically connected via a via-hole conductor 10 to a signal strip pattern 11b described later.

  The solid pattern 12 a is a wide area pattern that extends from the region corresponding to the mounting portion 20 </ b> A to the outer peripheral portion of the insulating substrate 1. The solid pattern 12a is provided with a plurality of mesh-like gas vent openings 15a. The solid pattern 12a integrally has a plurality of semiconductor element connection pads 4G (P) in a region corresponding to the mounting portion 20A. The semiconductor element connection pads 4G (P) have a second semiconductor element connection pad group in which a plurality of semiconductor element connection pads 4G (P) are arranged adjacent to each other in the inner row of the array of semiconductor element connection pads 4. The second semiconductor element connection pad group is disposed adjacent to the first semiconductor element connection pad group for signals. The solid pattern 14a is electrically connected to a lower solid pattern 12b and a solid pattern 12c, which will be described later, at a position corresponding to each semiconductor element connection pad 4G (P) and a position corresponding to the through hole 6a.

  Further, the solid pattern 12a has a square frame-shaped opening 14a surrounding the mounting portion 20A. By having this opening part 14a, the square-shaped recessed part 13 in which the solder resist layer 3a which covers the solid pattern 14a follows the opening part 14a and surrounds the mounting part 20A is formed. If the width of the opening 14a is less than 1 mm, the solder resist layer 3a hardly follows the opening 14a, and if it exceeds 3 μm, the risk of the function as a solid pattern being impaired increases. Therefore, the width of the opening 14a is preferably in the range of 1 to 3 mm.

  FIG. 3 is a plan view of the main part of the second wiring conductor 2b from the top. The wiring conductor 2b has a plurality of strip patterns 11b for signals and a solid pattern 12b for grounding or power. In addition, the region corresponding to the mounting portion 20A and the connection position of the via-hole conductor 10 to the lower wiring conductor 2c and the position of the through-hole 6a connected to the solid pattern 12b are shown in the same manner as in FIG. Further, the connection position of the via-hole conductor 10 from the upper wiring conductor 2a is indicated by a small black circle.

  A plurality of signal strip-like patterns 11 b extend in parallel from directly below the signal semiconductor element connection pads 4 </ b> S toward the outer peripheral portion of the insulating substrate 1. A via-hole conductor 10 from the semiconductor element connection pad 4S is connected to the end of each band-like pattern 11b on the mounting portion 20A side, and a via-hole conductor 10 connected to the lower wiring conductor 2c is connected to the outer end. Is connected.

  The solid pattern 12b has a rectangular frame-shaped opening 14b that overlaps the opening 14a of the upper solid pattern 12a. By having the opening 14b, the insulating layer 1a stacked on the solid pattern 12b is recessed in a frame shape following the opening 14a. As a result, the depth of the recess 13 of the solder resist layer 3a deposited thereon is further increased. In the solid pattern 12b, a plurality of via-hole conductors 10 from the semiconductor element connection pads 4G (P) are connected to a region corresponding to the mounting portion 20A, and an upper-layer solid pattern is formed at a position corresponding to the through hole 6a. A plurality of via-hole conductors 10 from 12a are connected.

  FIG. 4 is a plan view of the main part of the third wiring conductor 2c from the top. The wiring conductor 2c has a signal land 16 and a solid pattern 12c. The region corresponding to the mounting portion 20A, the connection position of the via-hole conductor 10, and the position of the through hole 6a connected to the solid pattern 12c are shown in the same manner as in FIGS.

  Each land 16 has an independent circular shape. These lands 16 are arranged directly below the outer peripheral end of each upper belt-like pattern 11b. The via holes 10 from the upper layer strip pattern 11b are connected to the lands 16 respectively.

  The solid pattern 12 c is a wide area pattern that extends from directly below the mounting portion 20 </ b> A to the outer peripheral portion of the insulating substrate 1, and surrounds each land 16. A plurality of via-hole conductors 10 from the upper solid pattern 12b are connected to the solid pattern 12c in a region corresponding to the mounting portion 20A, and also from the upper solid pattern 12b to a position corresponding to the through hole 6a. A plurality of via-hole conductors 10 are connected.

  FIG. 5 is a plan view of the main part of the fourth wiring conductor 2d from the top. The wiring conductor 2d has a plurality of strip patterns 11d for signals, a solid pattern 12d for grounding or power supply, and a land 17 for grounding or power supply. The region corresponding to the mounting portion 20A, the connection position of the via-hole conductor 10, and the position of the through hole 6a are shown in the same manner as in FIGS.

  The signal strip pattern 11 d extends from directly below the upper land 16 toward the outer periphery of the insulating substrate 1. As a result, the belt-like pattern 11 d is developed under the upper layer opening 14 b to the outer peripheral portion of the insulating substrate 1. The via hole conductor 10 from the land 16 is connected to the land 16 side end of the belt-shaped pattern 11d, and the via hole conductor 10 connected to the lower conductor layer 2e is connected to the outer peripheral side end.

  The land 17 is a circle having four protrusions. The land 17 is disposed immediately above the through hole 6a. The via hole conductor 10 from the upper solid pattern 12c is connected to the land 17.

  The solid pattern 12d is a wide area pattern that extends from directly under the mounting portion 20A to the outer peripheral portion of the insulating substrate 1 and surrounds the periphery of the belt-like pattern 11 for each signal and the periphery of the land 17. The solid pattern 12d is connected to a ground or power supply potential having a potential different from that of the upper solid patterns 12a to 12c.

  In the wiring board 20 of this example, as shown in FIG. 6, the electrode terminal T of the semiconductor element S is flip-chip connected, and a sealing resin called underfill is formed in the gap between the semiconductor element S and the wiring board 20. By filling U, the product becomes a semiconductor device. At this time, according to the wiring board 20 of this example, the solid pattern 12a in the uppermost wiring conductor 2a is completely covered with the solder resist layer 3a, and thus is well protected. Moreover, since the frame-shaped recessed part 13 surrounding the mounting part 20A is formed in the solder resist layer 3a, wetting and spreading of the sealing resin U is effectively prevented. Furthermore, since the recess 13 is formed following the opening 14a of the solid pattern 12a, it does not require an extra step and can be manufactured with high productivity.

1a... 1st insulation layer 1b... 2nd insulation layer 2a... 1st wiring conductor 2b.・ ・ ・ ・ ・ Solder resist layer 4... Semiconductor element connection pad 12 a... First solid pattern 12 b. ... Depression 14a... First opening 14b... Second opening 20. .... Semiconductor elements

Claims (2)

  A first insulating layer having a mounting portion on which a semiconductor element is mounted at the center of the upper surface; and a plurality of semiconductor element connection pads arranged on the upper surface of the first insulating layer and arranged in the mounting portion; A first wiring conductor having a first solid pattern that surrounds the mounting portion, and the first wiring conductor is deposited on the first insulating layer and the first wiring conductor, and exposes the semiconductor element connection pads. And a first solder resist layer that completely covers the first solid pattern, wherein the first solid pattern has a frame-shaped second surrounding the mounting portion. 1. The wiring board according to claim 1, wherein the solder resist layer is formed such that a recess that follows the first opening surrounds the mounting portion.   On the second insulating layer on which the second wiring conductor having the second solid pattern in which the second opening overlapping the first opening is formed on the upper surface is deposited, the first 2. The wiring according to claim 1, wherein an insulating layer is laminated, and the first insulating layer is formed so that a recess that follows the second opening surrounds the mounting portion. substrate.

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