JP2017129437A5 - - Google Patents

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Publication number
JP2017129437A5
JP2017129437A5 JP2016008448A JP2016008448A JP2017129437A5 JP 2017129437 A5 JP2017129437 A5 JP 2017129437A5 JP 2016008448 A JP2016008448 A JP 2016008448A JP 2016008448 A JP2016008448 A JP 2016008448A JP 2017129437 A5 JP2017129437 A5 JP 2017129437A5
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Japan
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scan
circuit
signal
mode
sub
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JP2016008448A
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English (en)
Japanese (ja)
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JP2017129437A (ja
JP6731733B2 (ja
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Priority to US15/411,259 priority patent/US10215808B2/en
Publication of JP2017129437A publication Critical patent/JP2017129437A/ja
Publication of JP2017129437A5 publication Critical patent/JP2017129437A5/ja
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JP2016008448A 2016-01-20 2016-01-20 スキャンテスト回路、スキャンテスト方法およびスキャンテスト回路の設計方法 Expired - Fee Related JP6731733B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016008448A JP6731733B2 (ja) 2016-01-20 2016-01-20 スキャンテスト回路、スキャンテスト方法およびスキャンテスト回路の設計方法
US15/411,259 US10215808B2 (en) 2016-01-20 2017-01-20 Scan test circuit, scan test method, and method of designing scan test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016008448A JP6731733B2 (ja) 2016-01-20 2016-01-20 スキャンテスト回路、スキャンテスト方法およびスキャンテスト回路の設計方法

Publications (3)

Publication Number Publication Date
JP2017129437A JP2017129437A (ja) 2017-07-27
JP2017129437A5 true JP2017129437A5 (https=) 2019-01-31
JP6731733B2 JP6731733B2 (ja) 2020-07-29

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JP2016008448A Expired - Fee Related JP6731733B2 (ja) 2016-01-20 2016-01-20 スキャンテスト回路、スキャンテスト方法およびスキャンテスト回路の設計方法

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US (1) US10215808B2 (https=)
JP (1) JP6731733B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10775432B2 (en) * 2018-05-30 2020-09-15 Seagate Technology Llc Programmable scan compression
JP7147372B2 (ja) * 2018-08-27 2022-10-05 富士通株式会社 半導体装置及び半導体装置の試験方法
US11663382B1 (en) * 2018-09-24 2023-05-30 Architecture Technology Corporation Systems and methods for hardware trojan detection and mitigation
CN115841090A (zh) * 2022-12-07 2023-03-24 上海华大九天信息科技有限公司 一种以旁路电路形式插入扫描单元的方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1089083A1 (en) 1999-09-03 2001-04-04 Sony Corporation Semiconductor circuits having scan path circuits
JP2001141791A (ja) 1999-09-03 2001-05-25 Sony Corp スキャンパス回路を有する半導体回路
WO2001039254A2 (en) * 1999-11-23 2001-05-31 Mentor Graphics Corporation Continuous application and decompression of test patterns to a circuit-under-test
US7058869B2 (en) * 2003-01-28 2006-06-06 Syntest Technologies, Inc. Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuits
JP3828502B2 (ja) * 2003-03-26 2006-10-04 株式会社東芝 集積回路
JP2006349548A (ja) 2005-06-17 2006-12-28 Matsushita Electric Ind Co Ltd 組み込み自己検査回路
JP2008234782A (ja) 2007-03-22 2008-10-02 Matsushita Electric Ind Co Ltd 半導体集積回路およびその検査方法
US7823034B2 (en) * 2007-04-13 2010-10-26 Synopsys, Inc. Pipeline of additional storage elements to shift input/output data of combinational scan compression circuit
JP4802139B2 (ja) * 2007-05-15 2011-10-26 株式会社東芝 半導体集積回路モジュール
US8195995B2 (en) * 2008-07-02 2012-06-05 Infineon Technologies Ag Integrated circuit and method of protecting a circuit part of an integrated circuit
US8065651B2 (en) * 2009-01-29 2011-11-22 Synopsys, Inc. Implementing hierarchical design-for-test logic for modular circuit design
US7996741B2 (en) * 2009-08-24 2011-08-09 Syntest Technologies, Inc. Method and apparatus for low-pin-count scan compression
US8856601B2 (en) * 2009-08-25 2014-10-07 Texas Instruments Incorporated Scan compression architecture with bypassable scan chains for low test mode power
US8479067B2 (en) * 2010-04-16 2013-07-02 Synopsys, Inc. Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry
KR101709071B1 (ko) * 2010-05-19 2017-02-22 삼성전자주식회사 컴프레션 모드 스캔 테스트를 위한 집적 회로
JP6054597B2 (ja) * 2011-06-23 2016-12-27 ラピスセミコンダクタ株式会社 半導体集積回路
JP2013036903A (ja) 2011-08-09 2013-02-21 Renesas Electronics Corp 故障箇所推定システム、故障箇所推定方法及び故障箇所推定用プログラム
US8645778B2 (en) * 2011-12-31 2014-02-04 Lsi Corporation Scan test circuitry with delay defect bypass functionality

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