JP2017120940A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce area for a sense amplifier.SOLUTION: A semiconductor memory comprises: a memory cell array 10 having a plurality of memory cells 11; a plurality of bit line pairs provided so as to correspond to each column of the memory cell array 10; and a plurality of sense amplifiers 12 provided so as to correspond to the plurality of bit line pairs, and to amplify potential difference of the bit line pairs. Each sense amplifier comprises: precharge transistors PCT, PCN, and EQ having a diffusion layer 41 and for precharging bit line pairs; and switch transistors YT and YN having a diffusion layer 41a integrally formed with the diffusion layer 41a of the precharge transistors PCT, PCN, and EQ, and selectively connecting the plurality of bit line pairs to a common bus line.SELECTED DRAWING: Figure 23

Description

  The present invention relates to a semiconductor memory.

  Patent Document 1 discloses a semiconductor memory device. The semiconductor memory device of Patent Document 1 includes a memory cell, a bit line pair, a sense amplifier, and a column switch. The sense amplifiers and column switches are laid out at a pitch that is less than twice the pitch of the bit line pairs.

JP-A-8-279602

  In the semiconductor memory, further reduction in area is required.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, in the semiconductor memory, the switching transistor and the precharging transistor have a common diffusion layer, or the sense amplifier pitch and the pitch of the precharge unit 22 and the Y switch unit 23 are different. Is.

  According to the embodiment, the circuit area can be reduced.

It is a figure which shows the structure of a semiconductor memory typically. It is a figure which shows the structure of a semiconductor memory typically. It is a figure which shows the structure of a semiconductor memory typically. It is a figure which shows the structure of a semiconductor memory typically. It is a figure which shows the circuit diagram of a sense amplifier. It is a layout diagram showing a normal sense amplifier. It is a conceptual diagram which shows the structure of the sense amplifier concerning this embodiment. It is a conceptual diagram which shows another structure of the sense amplifier concerning this embodiment. FIG. 3 is a layout diagram of the sense amplifier according to the first embodiment. FIG. 5 is a layout diagram illustrating an example of transistor arrangement in an amplifier region provided in a sense amplifier. FIG. 5 is a layout diagram illustrating an example of transistor arrangement in an amplifier region provided in a sense amplifier. FIG. 5 is a layout diagram illustrating an example of transistor arrangement in an amplifier region provided in a sense amplifier. It is a figure which shows typically the example of arrangement | positioning of the column selection of a Y switch part. It is a figure which shows typically the example of arrangement | positioning of the column selection of a Y switch part. It is a figure which shows typically the example of arrangement | positioning of the column selection of a Y switch part. 6 is a layout diagram illustrating an example of transistor arrangement in a Y switch section of a sense amplifier according to a second embodiment; FIG. 6 is a layout diagram illustrating an example of transistor arrangement in a Y switch section of a sense amplifier according to a second embodiment; FIG. 6 is a layout diagram illustrating an example of transistor arrangement in a Y switch section of a sense amplifier according to a second embodiment; FIG. 6 is a layout diagram illustrating an example of transistor arrangement in a Y switch section of a sense amplifier according to a second embodiment; FIG. FIG. 10 is a layout diagram illustrating a transistor arrangement example of a precharge portion of a sense amplifier according to a third embodiment. FIG. 10 is a layout diagram illustrating a transistor arrangement example of a precharge unit of a sense amplifier according to Modification 1 of Embodiment 3. 10 is a layout diagram illustrating a transistor arrangement example of a precharge portion of a sense amplifier according to a second modification of the third embodiment. FIG. 9 is a layout diagram illustrating a transistor arrangement example of a sense amplifier according to a fourth embodiment. FIG. 10 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE unit according to Modification 1 of Embodiment 4; FIG. 10 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE portion according to a second modification of the fourth embodiment. FIG. 10 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE unit according to a fifth embodiment. FIG. 10 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE unit according to Modification 1 of Embodiment 5. FIG. 10 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE portion according to a second modification of the fifth embodiment. FIG. 10 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE section according to a sixth embodiment; FIG. 29 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE portion according to Modification 1 of Embodiment 6; FIG. 29 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE portion according to Modification 2 of Embodiment 6; FIG. 29 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE section according to Modification 3 of Embodiment 6; FIG. 10 is a layout diagram illustrating a transistor arrangement example of a Y switch unit according to a seventh embodiment; FIG. 10 is a layout diagram illustrating a transistor arrangement example of a precharge unit according to a seventh exemplary embodiment; FIG. 10 is a layout diagram illustrating a transistor arrangement example of a YSW / PRE section according to a seventh embodiment;

  For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

  A DRAM (Dynamic Random Access Memory) sense amplifier (hereinafter also referred to as “SA”) region has a large area ratio next to a memory cell, and is a portion that is strongly desired to be reduced for cost reduction. However, with the recent reduction in the size of memory cells, the SA pitch is becoming narrower, making it difficult to reduce the SA height. Furthermore, memories that meet the demands for speeding up random access have been developed, such as DRAM, LLDRAM (Low Latency DRAM), and RLDRAM (Reduced Latency DRAM) incorporated in a system LSI. These have shortened the bit lines for speeding up, and the SA area ratio tends to increase.

  On the other hand, miniaturization of logic products such as recent MCU (Microcontroller) and system LSI (Large Scale Integration) is also progressing. The main part of miniaturization is area reduction and high performance of the MOS transistor which is a basic element constituting the logic circuit. The following (1) to (4) are technical trends in area reduction and higher performance.

(1) The transistor structure is reduced in the gate length direction, such as between contacts as viewed from the gate, between diffusion layers, and between adjacent gates.
(2) The resistance of the entire diffusion layer is reduced by the salicide technique that metalizes the surface of the diffusion layer of the source and drain to maintain the reduction in the number of contacts.
(3) Even in a low power supply voltage trend, the gate length L can be reduced and the device structure can be improved to improve the transistor capability and reduce the gate width W.
(4) Miniaturization of transistors and improvement in performance have been focused on standard gate-shaped elements.

  As a method for forming a transistor, various technologies such as substrate embedding and tertiary solid shape have been developed and put into practical use. However, a memory cell transistor has a condition that hates leakage current extremely. On the other hand, logic transistors tend to be combined with different transistor technologies because the first requirement is to increase the switching capability. This means that the SA area where the layout pitch is limited by the memory cell size is designed based on the logic transistor device reference.

  Due to such device technology trends, there are cases where the reduction ratio of memory cells and SA does not show a constant trend for each generation. This tendency is particularly noticeable in DRAMs with built-in logic, but the tendency is spreading also in general-purpose DRAMs. According to the present embodiment, it is possible to provide an SA layout optimum reduction technique from a new viewpoint in consideration of such a situation.

(Memory cell pitch and sense amplifier configuration)
The semiconductor memory according to the present embodiment has a memory cell array and a sense amplifier. Hereinafter, the relationship between the sense amplifier pitch (hereinafter referred to as SA pitch) of the sense amplifier and the memory cell will be described with reference to FIG. FIG. 1 is a diagram schematically showing a configuration of a semiconductor memory, and here shows a configuration of a folded type memory cell. Although the semiconductor memory is described as a DRAM, it is not limited to a DRAM. For example, the semiconductor memory may be an SRAM (Static Random Access Memory).

  As shown in FIG. 1, the semiconductor memory includes a memory cell array 10 and a sense amplifier 12. The memory cell array 10 includes a plurality of memory cells 11, a plurality of word lines WL, and a plurality of bit lines BL. The plurality of memory cells 11 are arranged in a matrix. The plurality of word lines WL are provided corresponding to each row of the memory cell array 10. The word line WL is formed along the horizontal direction (left-right direction) of the drawing. The plurality of bit lines BL are provided corresponding to each column of the memory cell array 10. The bit line BL is formed along the vertical direction (vertical direction) of the drawing. The sense amplifier 12 detects information stored in the memory cell 11 via the bit line BL. The sense amplifier 12 detects information according to the potential difference between the pair of bit lines BL.

  Here, two sense amplifiers 12 are provided for the four bit lines BL. Sense amplifiers 12 are arranged at the upper and lower ends of the memory cell array 10, respectively. Therefore, one sense amplifier 12 is arranged for a bit line pair having a pair of bit lines BL.

  When one of the four word lines WL is selected, one of the upper and lower bit line pairs is connected to the memory cell 11, and the other one becomes the reference potential. The sense amplifier 12 amplifies the potential difference between the bit line pair.

  The sense amplifier 12 includes a latch FF 13 and a YSW (Y switch unit) / PRE (precharge unit) unit 14. The latch FF 13 includes a latch-type flip-flop transistor that amplifies the bit line BL to VDD (power supply voltage) and GND (ground). The YSW / PRE unit 14 includes a column selection switch YSW that is connected to an external data bus line, and a precharge unit PRE that sets the bit line to the precharge voltage HVDD in the initial state. The precharge voltage HVDD is, for example, VDD / 2.

  Here, the width of the sense amplifier 12 in the direction of the word line WL, that is, in the horizontal direction of the paper surface is defined as SA pitch Psa. The SA pitch has a width corresponding to four bit lines BL, that is, a width corresponding to four memory cells 11. When the ratio of the number of bit lines or the number of memory cells to the SA pitch Psa is n (n is an integer of 2 or more), n = 4 in FIG. That is, the SA pitch Psa is n times the pitch of the memory cells 11.

  2 to 4 show other memory cell configurations. FIG. 2 is a diagram illustrating a configuration in which the transfer switch 15 is provided and the sense amplifier 12 is shared. Memory cell arrays 10 are provided above and below the sense amplifier 12. A transmission switch 15 is disposed between the sense amplifier 12 and the memory cell array 10. The transmission switches 15 respectively disposed above and below the sense amplifier 12 are selectively turned ON / OFF. Thereby, one memory cell array 10 is connected to the sense amplifier 12.

  FIG. 2 shows a state in which the upper memory cell array 10 is connected to the sense amplifier 12. In some cases, the precharge element PRE is arranged on the bit line BL side outside the transfer switch 15. In FIG. 2, four bit lines BL correspond to one sense amplifier 12, and n = 4. That is, the SA pitch Psa is n times the pitch of the memory cells 11. Thus, the SA pitch Psa is defined by an integer multiple of the pitch of the memory cells 11.

  FIG. 3 shows an open bit type memory cell configuration. Sense amplifiers 12 are arranged above and below the memory cell array 10. One sense amplifier 12 is connected to the upper memory cell 11 and the lower memory cell 11. Of the four bit lines BL of the memory cell array 10, two are connected to the upper sense amplifier 12, and the other two are connected to the lower sense amplifier 12. When the bit line BL of the memory cell array 10 disposed on the sense amplifier 12 is connected to the memory cell 11 by the word line selection, the bit line BL of the memory cell array 10 disposed below the sense amplifier 12 is set to the reference potential. Become the side. Alternatively, when the bit line BL of the memory cell array 10 disposed below the sense amplifier 12 is connected to the memory cell 11 by word line selection, the bit line BL of the memory cell array 10 disposed above the sense amplifier 12 is On the reference potential side.

  When the word line WL is selected, the two bit lines BL are connected to the memory cell 11, so that the bit line BL from the non-selected memory cell 11 serves as a reference potential. In FIG. 3, two bit lines BL correspond to one sense amplifier 12, and n = 2. That is, the SA pitch Psa is defined by an integer multiple of the pitch of the memory cells 11.

  FIG. 4 shows a configuration used when the sense amplifier 12 cannot be arranged with respect to the two pitches of the bit lines BL in the open bit type. The sense amplifier 12 has a two-stage configuration for the four bit lines BL. That is, two sense amplifiers 12 are arranged in two upper and lower stages between two memory cells 10 adjacent in the vertical direction. A passing wiring 17 passes through the sense amplifier 12 adjacent to the memory cell array 10. Then, the second-stage sense amplifier 12 is connected to the bit line BL via the passage wiring 17. In this case, the sense amplifier can be in the same state as in FIG. That is, in the case of FIG. 4, four bit lines BL correspond to one sense amplifier 12, and n = 4. The configuration shown in FIG. 4 is disclosed in Japanese Patent Laid-Open No. 7-254650. Furthermore, another configuration is disclosed in Japanese Patent Laid-Open No. 2001-266569. In Japanese Patent Laid-Open No. 2001-266569, in order to cause another circuit (element) to interrupt the SA row with respect to a large number of SAs, the SAs are shifted little by little. However, the idea that the SA pitch Psa is n times the bit line is common.

  As shown in FIGS. 1 to 4, there are various layouts in the sense amplifier 12, and in any case, the SA pitch Psa is an integer of the pitch of the memory cell 11 with respect to the bit line BL period of the memory cell 11. The basic idea that has been doubled has not changed. In an actual DRAM, n = 4 is often obtained. The DRAM is configured by repeating the same layout.

(Sense amplifier circuit diagram)
Next, the circuit of the sense amplifier 12 will be described with reference to FIG. FIG. 5 is a circuit diagram showing a general sense amplifier 12 and a memory cell array 10. FIG. 5 shows a circuit configuration of the sense amplifier 12 corresponding to a pair of bit lines. Therefore, in the DRAM, the memory cell array 10 and the sense amplifier 12 shown in FIG. 5 are repeatedly arranged. That is, a plurality of memory cell arrays 10 and sense amplifiers 12 are arranged side by side in the horizontal direction.

  As described above, the memory cell array 10 includes a plurality of memory cells 11, and word lines WL and bit lines BL connected to the plurality of memory cells 11. FIG. 5 shows two memory cells 11, two word lines WL0 and WL1, and two bit lines BT and BN. The two bit lines BT and BN form a bit line pair for reading information from one memory cell 11. For example, when the word line WL0 is selected, the bit line BT is connected to the memory cell 11, and the bit line BN becomes a reference potential line for the sense amplifier 12. In this manner, the bit lines BT and BN are paired to read data.

  The sense amplifier 12 includes an amplifier unit 21, a precharge unit 22, and a Y switch unit 23. The amplifier unit 21 is a region where a circuit corresponding to the latch FF 13 shown in FIGS. 1 to 4 is provided. The amplifier unit 21 includes a PMOS pair 25 and an NMOS pair 26. The PMOS pair 25 includes an amplifying PMOS transistor SPT and an amplifying PMOS transistor SPN. The NMOS pair 26 includes an amplifying NMOS transistor SPN and an amplifying NMOS transistor SNN. As described above, the amplifier unit 21 is configured by a flip-flop including two pairs of the PMOS pair 25 and the NMOS pair 26.

  The sources of the amplification PMOS transistors SPT and SPN are connected to a common source line SAP. The sources of the amplification NMOS transistors SNT and SNN are connected to a common source line SAN. The drain of the amplifying PMOS transistor SPT and the drain of the amplifying NMOS transistor SNT are connected to the bit line BT. The gate of the amplifying PMOS transistor SPT and the gate of the amplifying NMOS transistor SNT are connected to the bit line BN. The drain of the amplifying PMOS transistor SPN and the drain of the amplifying NMOS transistor SNN are connected to the bit line BN. The gate of the amplification PMOS transistor SPN and the gate of the amplification NMOS transistor SNN are connected to the bit line BT. The common source line SAP is connected to the power supply voltage VDD via the transistor SEP. The common source line SAN is grounded via the transistor SEN. The transistors SEP and SEN drive the common source lines SAP and SAN, so that the amplifier unit 21 performs an amplification operation.

  The precharge unit 22 performs precharge before the amplifier operation. The precharge unit 22 corresponds to a region where the precharge unit PRE shown in FIGS. 1 to 4 is provided. The precharge unit 22 includes precharge transistors PCT and PCN, which are NMOS transistors, and an equalize transistor EQ. A precharge signal line PDL is connected to the gates of the precharging transistors PCT and PCN and the equalizing transistor EQ. In the precharge state before the amplifier operation, a precharge signal is supplied to the precharge signal line PDL. The precharging transistors PCT and PCN are potential fixing transistors for fixing to a precharge potential. The equalizing transistor EQ is a transistor for equalizing the bit line pair.

  When the precharge signal is supplied, the precharging transistors PCT and PCN and the equalizing transistor EQ are turned on. When the precharge transistor PCT is turned on, the bit line BL is set to the precharge voltage HVDD. When the precharge transistor PCN is turned on, the bit line BN is set to the precharge voltage HVDD. Note that the precharge voltage HVDD is, for example, half the power supply voltage VDD. The equalizing transistor EQ is arranged between the bit line BT and the bit line BN. When the equalizing transistor EQ is turned on, the bit line BT and the bit line BN are connected. That is, the equalizing transistor EQ equalizes the bit line pair BT and BN by the precharge signal. As described above, the precharge operation is performed by the three precharge transistors PCT and PCN and the equalizing transistor EQ.

  The Y switch unit 23 performs column selection. That is, the Y switch unit 23 corresponds to the region where the column selection switch YSW shown in FIGS. The Y switch unit 23 selects the sense amplifier 12 connected to the common bus line DBUS from a large number of the sense amplifiers 12 arranged in succession. The Y switch unit 23 selectively connects a plurality of bit line pairs to the common bus line DBUS.

  The Y switch unit 23 includes switching transistors YT and YN which are NMOS transistor pairs. The common bus line DBUS includes a common bus line DT and a common bus line DN. The switching transistor YT is disposed between the bit line BT and the common bus line DT. The switching transistor YN is disposed between the bit line BN and the common bus line DN. A column selection signal Y is input to the gates of the switching transistors YT and YN. A column selection signal is supplied to the gates of the switching transistors YT and YN via the column selection signal line Y.

  In response to a column selection signal from the column selection signal line Y, the switching transistors YT and YN are turned ON. When the switching transistor YT is turned on, the bit line BT is connected to the common bus line DT. When the switching transistor YN is turned on, the bit line BN is connected to the common bus line DN. For example, during reading, when the Y switch unit 23 connects the bit lines BT and BN to the common bus lines DT and DN, the bit line signal amplified by the amplifier unit 21 is supplied to the common bus line DBUS. At the time of writing, the Y switch unit 23 transmits write information from the common bus line DBUS to the bit lines BT and BN. By combining the selection by the word line WL and the column selection of the Y switch unit 23, it becomes possible to select an address from the memory matrix. The circuit configuration shown in FIG. 5 is an example of the sense amplifier 12, and the sense amplifier 12 having a different circuit configuration may be used.

(Two-dimensional layout of general sense amplifier)
FIG. 6 is a layout diagram illustrating a transistor arrangement example of a general sense amplifier 12. In FIG. 6, two adjacent sense amplifiers 12 are shown. In FIG. 6, the vertical direction (vertical direction) of the drawing is the bit line direction. In the following layout description, the direction perpendicular to the bit line direction is defined as the horizontal direction. The horizontal direction is the word line direction. In SA, each transistor has a diffusion layer 41 and a gate g. The gate g of each transistor is disposed so as to straddle the diffusion layer 41. In each transistor, the diffusion layers 41 on both sides of the gate g serve as a source and a drain. That is, each transistor is formed in the diffusion layer 41.

  Two sense amplifiers 12 are juxtaposed in the horizontal direction. Here, the bit lines BT and BN of the left sense amplifier 12 are referred to as bit lines BT0 and BN0, respectively, and the bit lines BT and BN of the right sense amplifier 12 are referred to as bit lines BT1 and BT1, respectively. Bit lines BT0 and BN0 form a bit line pair. Bit lines BT1 and BN1 form a bit line pair. Similarly, the column selection signal line Y is set to column selection signal lines Y0 and Y1. The column addresses selected by the column selection signal lines Y0 and Y1 are shown.

  A PMOS pair 25 is arranged in the SA pitch Psa. The PMOS pair 25 is provided with two gates g. One of the two gates g corresponds to the amplifying PMOS transistor SPT, and the other corresponds to the amplifying PMOS transistor SPN. Two gates g are arranged in the bit line direction. That is, the gates g of the amplification PMOS transistors SPT and SPN have the bit line direction as the longitudinal direction. The channel width direction of the amplification PMOS transistors SPT and SPN is the bit line direction. The amplifying PMOS transistor SPT and the amplifying PMOS transistor SPN share the diffusion layer 41. That is, the gate g of the amplifying PMOS transistor SPT and the gate g of the amplifying PMOS transistor SPN are disposed so as to straddle the integrally formed diffusion layer 41. A common source line SAP is connected to the diffusion layer 41 between the two linear gates g. Therefore, the amplification PMOS transistor SPT and the amplification PMOS transistor SPN share the diffusion layer 41 on the common source line SAP side.

  Similarly, the NMOS pair 26 is arranged in the SA pitch Psa. The NMOS pair 26 is provided with two gates g. One of the two gates g corresponds to the amplification NMOS transistor SNT, and the other also corresponds to the amplification NMOS transistor SNN. Two gates g are arranged in the bit line direction. That is, the gate g of the amplification NMOS transistors SNT and SNN has the bit line direction as the longitudinal direction. The channel width direction of the amplification NMOS transistors SNT and SNN is the bit line direction. The diffusion layer 41 is shared by the amplification NMOS transistor SNT and the amplification NMOS transistor SNN. That is, the gate g of the amplifying NMOS transistor SNT and the gate g of the amplifying NMOS transistor SNN are disposed so as to straddle the integrally formed diffusion layer 41. A common source line SAN is connected to the diffusion layer 41 between the two linear gates g. Therefore, the diffusion layer 41 on the common source line SAN side is shared by the amplification NMOS transistor SNT and the amplification NMOS transistor SNN. Within each SA pitch, the transistor layout of the PMOS pair 25 and the NMOS pair 26 is the same.

  Similarly, an NMOS pair of the Y switch unit 23 is provided in the SA pitch Psa. Two gates g are provided in the SA pitch Psa. One of the two gates g corresponds to the switching transistor YT, and the other corresponds to the switching transistor YN. Two gates g are arranged in the bit line direction. That is, the gates g of the switching transistors YT and YN have the bit line direction as the longitudinal direction. The channel width direction of the switching transistors YT and YN is the bit line direction. The switching transistor YN shares the diffusion layer 41 with two adjacent SAs. The switching transistor YT shares the diffusion layer 41 with two adjacent SAs.

  The PMOS pair 25, the NMOS pair 26, and the Y switch unit 23 are arranged in parallel in the bit line direction. That is, the NMOS pair 26 is arranged between the PMOS pair 25 and the Y switch unit 23 in the bit line direction (vertical direction). Further, a precharge unit 22 is disposed under the Y switch unit 23. Accordingly, in FIG. 6, the PMOS pair 25, the NMOS pair 26, the Y switch unit 23, and the precharge unit 22 are arranged in this order from the top. The three precharging transistors PCT, PCN, and EQ included in the precharge unit 22 are modified transistors using a T-type gate g. The diffusion layer 41 is shared by the precharging transistors PCT, PCN, and EQ.

(Sense amplifier configuration concept)
The concept of the SA layout according to this embodiment will be described below. For the amplifier unit 21 configured with the SA pitch Psa being n times as large as the bit line BL, a layout having a repetitive pitch such as twice or half of n is employed in other circuit regions. By doing so, the integration of the precharge portion 22 and the Y switch portion 23 constituting the SA and the adjacent SA can be promoted. Therefore, the layout can be performed efficiently, and the height of the SA can be reduced. Note that the SA height means the size of the SA in FIG. 6 in the vertical direction, that is, the bit line direction. The layout reduction means by integration can be realized by sharing gate signals continuously or sharing diffusion layers.

  Further, the gate shape of some or all of the transistors included in these SAs may be linear. By doing so, it becomes possible to use a fine reference around the transistor, so that further compression of the SA height is realized. At the same time, since there is no special shape transistor, it is possible to obtain a reduction effect in device development that requires a special cost. Only standard shape transistors can be used, leading to improved yield.

  Note that the standard shape transistor is a transistor having a linear gate. A special shape transistor is a transistor whose gate is not linear. The special shape transistor is, for example, a transistor whose gate is bent in an L shape, a T shape, a U shape, an O shape, or the like.

  FIG. 7 shows a conceptual diagram of the overall configuration. FIG. 7 shows two sense amplifiers 12, latch FFs 13, and two YSW / PRE units 14 that are repeatedly arranged. The latch FF13 and YSW / PRE unit 14 corresponding to the bit line pair BT0 and BN0 are shown as FF0 and YSW0 / PRE0, respectively. Latch FF13 and YSW / PRE unit 14 corresponding to bit line pair BT1 and BN1 are shown as FF1 and YSW1 / PRE1, respectively.

  The width of one latch FF 13 defines the SA pitch Psa of the sense amplifiers 12 that are repeatedly arranged in the horizontal direction. That is, the width of the latch FF 13 in the horizontal direction matches the SA pitch Psa. The SA pitch Psa of the sense amplifier 12 is an integral multiple of the memory cell pitch Pcell. Psa = n (n is an integer) × Pcell. The SA pitch Psa has a width corresponding to the bit line pair BT0, BN0. That is, the SA pitch Psa is a width corresponding to one bit line pair. The latch FF13 connected to the bit line pair BT0, BN0 and the latch FF13 connected to the bit line pair BT1, BN1 are juxtaposed in the horizontal direction.

  The width Pt of the YSW / PRE portion 14 is twice the SA pitch Psa. The width Pt of the YSW / PRE unit 14 is made wider than the SA pitch Psa which is the width of the latch FF 13. Two YSW / PRE units 14 corresponding to two SAs are arranged in parallel in the bit line direction. That is, YSW0 / PRE0 corresponding to the bit line pair BT0 and BN0 and YSW1 / PRE1 corresponding to the bit line pair BT1 and BN1 are arranged in two upper and lower stages.

  Moreover, another conceptual diagram of the whole structure of FIG. 8 is shown. The width of one latch FF 13 defines the SA pitch Psa. The width of the latch FF 13 in the horizontal direction matches the SA pitch Psa. The SA pitch Psa of the sense amplifier 12 is an integral multiple of the memory cell pitch Pcell. That is, Psa = m (m is an integer) × Pcell. The SA pitch Psa has a width corresponding to the bit line pair BT0, BN0, the bit line pair BT1, and the bit line BN1. That is, the SA pitch Psa is a width corresponding to two bit line pairs. The latch FF 13 corresponding to the rabbit line pair BT0 and BN0 and the latch FF 13 corresponding to the bit line pair BT1 and BN1 are arranged in two upper and lower stages.

  On the other hand, the width Pt of the YSW / PRE portion 14 is half of the SA pitch Psa. The width Pt of the YSW / PRE unit 14 is made narrower than the SA pitch Psa which is the width of the latch FF 13. Two YSW / PRE units 14 are juxtaposed in the horizontal direction. That is, YSW0 / PRE0 corresponding to the bit line pair BT0 and BN0 and YSW1 / PRE1 corresponding to the bit line pair BT1 and BN1 are juxtaposed in the horizontal direction.

  In the semiconductor memory, the configuration of FIG. 7 or FIG. 8 is repeatedly arranged in the horizontal direction. That is, the latch FF 13 is repeatedly arranged in the horizontal direction with the SA pitch Psa and the width Pt as a pitch. The YSW / PRE unit 14 is repeatedly arranged in the horizontal direction with the width Pt as a pitch. In other words, the circuit layout of the semiconductor memory can also be expressed as follows. The semiconductor memory has a configuration in which a reference layout as a reference is repeatedly arranged in the horizontal direction. That is, the reference layout of the latch FF 13 is repeatedly arranged in the horizontal direction. Similarly, the reference layout of the YSW / PRE unit 14 is repeatedly arranged in the horizontal direction. A plurality of sense amplifiers 12 are configured by a reference layout arranged in the horizontal direction.

  In one sense amplifier 12, the pitch widths of the YSW / PRE unit 14 and the latch FF 13 are different. The repetition pitch of the YSW / PRE unit 14 is set to be twice or half the repetition pitch of the latch FF 13. By doing so, the area can be reduced and the performance can be improved.

  As described above, the pitch of the latch FF 13 in the horizontal direction is different from the pitch of the YSW / PRE unit 14. The repetition pitch of the layout between the latch FF 13 and the YSW / PRE unit 14 is doubled or halved. Therefore, when a predetermined number of sense amplifiers 12 are considered, the number of repetitions of the reference layout corresponding to the latch FF 13 is different from the number of repetitions of the reference layout corresponding to the YSW / PRE unit 14. That is, the number of latch FFs 13 repeatedly arranged in the horizontal direction is different from the number of YSW / PRE units 14 repeatedly arranged in the horizontal line direction. For example, when the width of the latch FF 13 is twice the width of the YSW / PRE unit 14, the number of repetitions of the latch FF 13 is half the number of repetitions of the YSW / PRE unit 14. Conversely, when the width of the latch FF 13 is half the width of the YSW / PRE unit 14, the number of repetitions of the latch FF 13 is twice the number of repetitions of the YSW / PRE unit 14. By doing so, the area can be reduced and the performance can be improved.

Embodiment 1 FIG.
(Sense amplifier layout)
Hereinafter, a circuit layout according to the present embodiment will be described with reference to the drawings. FIG. 9 is a layout diagram of the sense amplifier 12 according to the present embodiment. The basic circuit configuration of the sense amplifier 12 is the same as the configuration shown in FIG. Therefore, description of the same contents as those in FIG. 5 will be omitted as appropriate. The layout of the amplifier unit 21 is also the same as that shown in FIG. The amplifier unit 21 corresponds to the latch FF 13 in FIGS.

  As described above, in the lateral direction, the width of the pair amplification transistor of the amplifier unit 21 defines the SA pitch Psa. As shown in FIG. 7, the pitch Pt of the precharge unit 22 and the Y switch unit 23 is twice the SA pitch Psa.

  In FIG. 9, the Y switch unit 23 and the precharge unit 22 are provided with a total of four gates g. In the Y switch unit 23 and the precharge unit 22, linear gates g are arranged in four stages. In the following description, the gate g on the upper side (NMOS pair 26 side in FIG. 9) is defined as the first-stage gate g1, and the second-stage gate g2 and the third-stage gates g3, 4 as it goes downward. This will be described as the stage gate g4. Each of the gates g1 to g4 extends to the adjacent sense amplifier pitch. That is, each of the gates g1 to g4 is formed so as to protrude to the adjacent sense amplifier pitch. One gate g is formed across two SA pitches Psa.

  The Y switch unit 23 includes switching transistors YT and YN that selectively connect a plurality of bit line pairs to the common bus line DBUS. That is, the Y switch unit 23 is provided with two switching transistors YT and two switching transistors YN corresponding to the bit line pair BT0, BN0 and the bit line pair BT1, BN1. Here, the switching transistors YT, YN corresponding to the bit line pair BT0, BN0 are the switching transistors YT0, YN0, and the switching transistors YT, YN corresponding to the bit line pair BT1, BN1 are the switching transistors YT1, YN1. Identify. When the bit line pair is not specified, it is described as switching transistors YT and YN. The precharging transistors PCT and PCN and the equalizing transistor EQ are also identified in the same manner.

  When the bit line pair BT0, BN0 is connected to the common bus lines DT, DN, respectively, the switching transistors YT0, YN0 are turned on by the column selection signal of the column selection signal line Y0. When the bit line pair BT1, BN1 is connected to the common bus lines DT, DN, the switching transistors YT1, YN1 are turned on by the column selection signal of the column selection signal line Y1. In this way, by turning on one of the switching transistors YT0 and YN0 or one of the switching transistors YT1 and YN1, a bit line pair connected to the common bus line DBUS is selected.

  In the Y switch portion 23, two gates g1 and g2 are arranged. In the Y switch unit 23, the gates g1 and g2 have a two-stage configuration. A column selection signal line Y0 for selecting the bit line pair BT0, BN0 is connected to the first stage gate g1, and a column selection signal for selecting the bit line pair BT1, BN1 is connected to the second stage gate g2. Line Y1 is connected. The respective gates g1 and g2 of the Y switch portion 23 are formed along the horizontal direction. That is, the direction perpendicular to the bit line direction is the gate width W direction. In addition, the two gates g1 and g2 of the Y switch unit 23 are spaced apart from each other in the bit line direction. The two gates g1 and g2 of the Y switch unit 23 are linearly formed along the horizontal direction and have substantially the same shape.

  Specifically, the lateral direction of the gates g1 of the first-stage switching transistors YT0 and YN0 is the longitudinal direction. The gate width direction of the switching transistors YT0 and YN0 of the Y switch unit 23 is the horizontal direction. The gates g1 of the switching transistors YT0 and YN0 are a common electrode. That is, in one linear gate g1, the portion straddling the diffusion layer 41a becomes the gate of the switching transistor YT0, and the portion straddling the diffusion layer 41b becomes the gate of the switching transistor YN0.

  The diffusion layer 41a and the diffusion layer 41b are separated. The diffusion layer 41a is arranged in the SA amplifier pitch Psa of the bit line pair BT0, BN0, and the diffusion layer 41b is arranged in the SA amplifier pitch Psa of the bit line pair BT1, BN1. The gates g of the switching transistors YT0 and YN0 are continuous so as to straddle the two diffusion layers 41a and 41b. In other words, the gates g of the switching transistors YT0 and YN0 pass through the diffusion layers 41a and 41b.

  The switching transistor YT1 and the gate g2 of the switching transistor YT1 are provided in the second stage. Similarly to the gate g1 of the switching transistors YT0 and YN0, the switching transistor YT1 and the gate g2 of the switching transistor YN1 are one linear electrode. Similarly, the gates g2 of the switching transistors YT1 and YN1 penetrate through the diffusion layers 41a and 41b. Therefore, the gates g1 and g2 to which the column selection signal lines Y0 and Y1 are connected are formed across the two SA amplifiers Psa.

  Here, the diffusion layer 41a is shared by the switching transistor YT0 and the switching transistor YT1. The common part of the diffusion layers 41a of the two switching transistors YT0 and YT1 is connected to the common bus line DT. The switching transistors YT0 and YT1 are connected to the common bus line DT through the same contact of the diffusion layer 41a. Similarly, the diffusion layer 41b is shared by the switching transistor YN0 and the switching transistor YN1. A common portion of the diffusion layers 41b of the two switch transistors YN0 and YT1 is connected to the common bus line DN. The switching transistors YN0 and YN1 are connected to the common bus line DN through the same contact of the diffusion layer 41b.

  With such a configuration, the pitch Pt of the Y switch unit 23 is twice the SA pitch Psa. For example, the length of the electrodes serving as the gates g1 and g2 is larger than the SA pitch Psa and is about twice as long as Psa. Since the height is determined only by the shape of two continuous standard transistors, and the gate does not protrude up and down outside the active element region, the height can be easily reduced. Up to now, the gate width W is limited to the SA pitch Psa, which is not general. However, with the progress of miniaturization, the transistor capability increases and the above configuration can be adopted.

  Next, the precharge unit 22 will be described. The precharge unit 22 includes precharge transistors PCT0 and PCT1, precharge transistors PCN0 and PCN1, and equalization transistors EQ0 and EQ1. The precharge unit 22 includes six diffusion layers 41c to 41h corresponding to six transistors. The diffusion layers 41c, 41d, and 41e correspond to the precharging transistor PCT0, the precharging transistor PCN0, and the equalizing transistor EQ0, respectively. The diffusion layers 41f, 41g, and 41h correspond to the equalizing transistor EQ1, the precharging transistor PCN1, and the precharging transistor PCT1, respectively.

  The precharge portion 22 is provided with two linear gates g3 and g4 extending in the horizontal direction. The two gates g3 and g4 are spaced apart from each other in the vertical direction. That is, two gates g3 and g4 are arranged in two upper and lower stages. The third-stage gate g3 is disposed so as to straddle the diffusion layers 41c, 41e, and 41g, and the fourth-stage gate g4 is disposed so as to straddle the diffusion layers 41d, 41f, and 41h. Note that the first-stage and second-stage gates g1 and g2 are provided in the Y switch section 23 as described above.

  Three transistors, a precharging transistor PCT0, an equalizing transistor EQ0, and a precharging transistor PCN1, are arranged side by side in the horizontal direction. The third-stage gate g3 corresponds to three transistors: a precharging transistor PCT0, an equalizing transistor EQ0, and a precharging transistor PCN1. Therefore, the gate g3 is common to the precharging transistor PCT0, the equalizing transistor EQ0, and the precharging transistor PCN1. In other words, the three precharging transistors PCT0, the equalizing transistor EQ0, and the gate g3 of the precharging transistor PCN1 are integrally formed of the same wiring layer. Three precharging transistors PCT0, equalizing transistor EQ0, and gate g3 of precharging transistor PCN1 are formed by one electrode pattern in the same layer.

  Similarly to the precharging transistor PCT0, the equalizing transistor EQ0, and the precharging transistor PCN0, the precharge transistor PCT1, the equalizing transistor EQ1, and the precharging transistor PCN0 have the same gate g4. In other words, the fourth-stage gate g4 is shared by the precharging transistor PCT1, the equalizing transistor EQ1, and the precharging transistor PCN0. The three precharging transistors PCT1, the equalizing transistor EQ1, and the gate g4 of the precharging transistor PCN1 are integrally formed of the same wiring layer. Three precharging transistors PCT1, an equalizing transistor EQ1, and a gate g4 of the precharging transistor PCN1 are formed by one electrode pattern in the same layer.

  The pair transistors including the precharging transistor PCN0 and the precharging transistor PCT0 are arranged vertically within the SA pitch Psa on the left side. The pair transistors including the precharging transistor PCN1 and the precharging transistor PCT1 are arranged vertically within the SA pitch Psa on the right side. On the other hand, the equalizing transistor EQ0 is required to have a higher driving capability than the precharging transistor PCN0 and the precharging transistor PCT0, and thus has a large gate width W. That is, the equalizing transistor EQ0 that directly shorts the bit line pair BT0 and BN0 determines the precharge speed, and therefore tends to be larger than the precharging transistors PCT0 and PCN0. Therefore, the equalizing transistor EQ0 does not fit in the left SA pitch Psa. The pitch Pt of the precharge unit 22 is twice the SA amplifier pitch Psa.

  In the layout shown in FIG. 6, the increase in the gate width W of the equalizing transistor EQ directly increases the SA height, but in the layout in FIG. 9, a large gate width W can be obtained by using up to the adjacent SA region. Since the gate signal is common to the adjacent SA element, there is little loss of gate isolation, contact region, etc., and a large element can be obtained only by diffusion layer isolation. Since the height is equivalent to two independent transistors in the standard shape, the distance is determined by the design standard, and can be easily reduced as the size is reduced. In FIG. 9, all transistors in the sense amplifier 12 are standard shape transistors. Therefore, only a standard shape transistor can be used, leading to an improvement in yield. That is, the arrangement direction of the gate g is unified by using only the linear gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. Furthermore, the area in the vertical direction can be reduced.

  A common bus line DBUS is provided corresponding to m (m is an integer of 2 or more) SAs. Then, the column selection is performed by selectively turning on the m SA switching transistors Y and connecting one bit line pair of the m bit line pairs to the common bus line DBUS. Further, the column addresses of the columns located on both sides of the column at the boundary portion of adjacent I / O are the same. The gates of the switching transistors YT and YN are formed across the boundary of adjacent I / O. In this way, the capabilities of the switching transistors YT and YN can be improved, and the reliability of the memory can be improved. Furthermore, since a space for signal separation between adjacent I / Os can be reduced, efficient layout can be achieved.

(Amplifier area transistor arrangement example)
The amplifier unit 21 is a part responsible for an analog operation for amplifying the minute voltage of the sense amplifier 12. Therefore, it is necessary to set the gate length L of the amplifying PMOS transistors SPT and SPN and the amplifying NMOS transistors SNT and SNN to be large in consideration of random variation, or to design the transistor arrangement and shape symmetry. There is. Hereinafter, a layout example of the amplifier unit 21 will be described with reference to FIGS. 10 to 12 are diagrams showing examples of transistor-shaped layouts of the amplifier unit 21 that determines the SA pitch Psa. 10 to 12 show layout examples of the PMOS pair 25. The NMOS pair 26 can have the same configuration as that shown in FIGS.

  In FIG. 10, the gate g of the amplification PMOS transistor SPT and the gate g of the amplification PMOS transistor SPN are linear in the vertical direction. The amplification PMOS transistor SPT has two gates g. Similarly, the amplification PMOS transistor SPN has two gates g. The diffusion layer 41a of the amplification PMOS transistor SPT and the diffusion layer 41b of the amplification PMOS transistor SPN are arranged separately. The gate g of the amplifying PMOS transistor SPT and the amplifying PMOS transistor SPN are arranged in two upper and lower stages.

  In FIG. 11, the gate g is U-shaped, and the amplifying PMOS transistor SPT and the amplifying PMOS transistor SPN are arranged in two upper and lower stages. The gate g may be O-shaped instead of U-shaped, and the amplifying PMOS transistor SPT and the amplifying PMOS transistor SPN may be arranged in two upper and lower stages. The amplifying PMOS transistor SPT, the amplifying PMOS transistor SPN, and the amplifying PMOS transistor SPT are integrally formed with a diffusion layer 41a.

  In FIG. 12, the amplifying PMOS transistor SPT and the amplifying PMOS transistor SPN are arranged in two upper and lower stages while keeping the gate g straight. The diffusion layer 41a of the amplification PMOS transistor SPT and the diffusion layer 41b of the amplification PMOS transistor SPN are arranged separately. In the horizontal direction, the diffusion layer 41a and the diffusion layer 41b are shifted from each other. The diffusion layers 41a and 41b are wider than the SA pitch Psa. The diffusion layers 41a and 41b extend to the adjacent SA pitch. Amplifying PMOS transistors SPT of adjacent bit line pairs share a diffusion layer 41a. Similarly, amplification PMOS transistors SPN of adjacent bit line pairs share the diffusion layer 41b.

  10 to 12, a pair transistor having a long gate length L is arranged in the vicinity. Therefore, the SA pitch Psa is determined by the size of the pair transistor. 10 to 12 may be used for the PMOS pair 25 and the NMOS pair 26. Furthermore, you may use the structure of FIGS. 10-12 for the layout mentioned later.

(Assignment of column selection)
Next, a column selection arrangement example of the Y switch unit 23 will be described with reference to FIG. FIG. 13 is a diagram for explaining the case where the number of columns is four. That is, an example in which one bit line pair is selected from four bit line pairs and column selection is performed in each I / O will be described. Here, column addresses Y0 to Y3 are assigned to one I / O. As described above, a switch transistor pair of switching transistors YT and YN is connected to each of Y0 to Y3. The switching transistors YT and YN for Y0 to Y3 share a common bus line DBUS.

  In I / O = 0 and I / O = 2, SAs are arranged in the order of addresses Y0, Y1, Y2, and Y3 from the left. In I / O = 1, SAs are arranged in the order of addresses Y2, Y3, Y0, and Y1 from the left. FIG. 13 schematically shows the gates g of the switching transistors YT and YN.

  In the arrangement of FIG. 13, the Y0 and Y1 transistor pairs are not arranged between the Y2 and Y3 transistor pairs with I / O = 0 and the Y2 and Y3 transistor pairs with I / O = 1. Therefore, Y2 and Y3 transistor pairs can be physically adjacent to each other at the boundary portion between adjacent I / Os. Specifically, in the boundary part of adjacent I / O, both sides of Y3 are Y2, and both sides of Y2 are Y3. Thereby, the gates of the Y2 and Y3 transistor pairs can be shared by I / O = 0 and I / O = 1. Similarly, the gates g of the Y0 and Y1 transistor pairs can be shared by adjacent I / O = 2 and I / O = 1. In other words, the gate g over four SA pitches Psa is provided.

  In this way, the gate g can be made common to the four SAs existing at the boundary portions of adjacent I / O. For example, in two Y2 SAs and two Y3 SAs, an integrated gate g is used for the switching transistors YT and YN. By using the column selection arrangement of FIG. 13 in the layout of FIG. 9, the gate g can be shared over four times the SA pitch. That is, the gates g of the switching transistors YT and YN straddle the adjacent I / O boundary. As described above, by adjusting the order of Y0 to Y4 with the adjacent I / O, the repetition of the gate signal can be further shared. Since no element isolation or contact is required at the I / O boundary, the gate width W of the switching transistors YT and YN can be increased. Therefore, the capability of the switching transistors YT and YN can be improved.

  Here, in order to avoid that the same selected column address (Y) of adjacent I / O is selected by the physically adjacent SA, the decoder signal is set so that Y2 is adjacent to Y2 and Y0 is adjacent to Y1. The input order is set. The same column address is not continued at the boundary portion between adjacent I / Os. In adjacent I / O, column selection signals with the same address are prevented from continuing. This has the effect of reducing the test failure rate due to the bit line interference appearing differently, and reducing the rate of simultaneous failure at one location due to soft errors caused by cosmic ray irradiation.

  FIG. 14 shows an example in which the number of columns is six as an example of four or more columns. That is, column addresses Y0 to Y5 are assigned to each I / O. Hereinafter, a layout example for selecting one column from six columns will be described. When I / O = 0, the Y switch unit 23 is arranged in the order of Y0, Y1, Y2, Y3, Y4, and Y5 from the left. In I / O = 1, the Y switch unit 23 is arranged in the order of Y4, Y5, Y2, Y3, Y0, and Y1 from the left. In this configuration, the gates g of the Y4 and Y5 transistor pairs can be shared between adjacent I / Os. Although not shown, the gates g of the Y0 and Y1 transistor pairs can be shared at the boundary between I / O = 1 and I / O = 2. Therefore, the gate width W of the switching transistors YT and YN can be increased.

  FIG. 15 shows an example in which the number of columns is two. That is, column addresses Y0 and Y1 are assigned to each I / O. Hereinafter, a layout example for selecting one column from two columns will be described. In FIG. 15, Y0 and Y1 are alternately arranged. Therefore, the gate g can be shared for all the I / Os. Thereby, the gate g can be penetrated significantly. Since element isolation and contact are not required,

  13 to 15, the gate g straddles the boundary of adjacent I / O. At the boundary between adjacent I / Os, four or more switching transistors share the gate g. The gate width W of the switching transistors YT and YN can be increased. Thereby, the layout can be performed efficiently and the area can be reduced. Of course, the number of columns in each I / O is not limited to 2, 4, and 6, and can be any value.

Embodiment 2. FIG.
(Example of transistor arrangement of the Y switch unit 23)
The configuration of the semiconductor memory according to this embodiment will be described with reference to FIG. FIG. 16 is a diagram showing a layout of the Y switch unit 23. Since the configuration other than the Y switch unit 23 is the same as that of the first embodiment, the description thereof is omitted. Further, since the basic configuration of SA is the same as that of the first embodiment, the description overlapping with that of the first embodiment is omitted. In FIG. 16, two SA pitches Psa are shown.

  In FIG. 16, the gate width W of the switching transistors YT and YN is expanded to twice the SA pitch Psa. Therefore, four gates g extending in the horizontal direction are arranged in the Y switch portion 23. That is, the gates g are arranged in four stages. The first-stage gate g1 corresponds to the switching transistor YT0, and the second-stage gate g2 corresponds to the switching transistor YT1. The third-stage gate g3 corresponds to the switching transistor YN0, and the fourth-stage gate g4 corresponds to the switching transistor YN1.

  Further, the Y switch portion 23 is provided with two stages of diffusion layers 41a and 41b. The switching transistor YT0 and the switching transistor YT1 share the diffusion layer 41a connected to the common bus line DT. A common part of the diffusion layer 41a is used as a signal contact of the common bus line DT. Gates g1 and g2 are arranged on both upper and lower sides of the signal contact of the common bus line DT. The switching transistor YN0 and the switching transistor YN1 share the diffusion layer 41b connected to the common bus line DN. A common part of the diffusion layer 41b is used as a signal contact of the common bus line DN. Gates g3 and g4 are arranged on both upper and lower sides of the signal contact of the common bus line DN. The diffusion layers 41a and 41b are formed so as to protrude from the adjacent SA pitch Psa. That is, the diffusion layers 41a and 41b are wider than the SA pitch Psa, and are formed over the two SA pitches Psa. The pitch of the Y switch section 23 is twice the SA pitch Psa.

  As described above, the switching transistor YT0 and the switching transistor YT1 have a two-stage upper and lower transistor arrangement sharing the diffusion layer 41a. The switching transistor YN0 and the switching transistor YN1 have a transistor arrangement with a two-stage configuration in which the diffusion layer 41b is shared. Each transistor in each stage has a gate g along the word line direction.

  In this layout, the size in the height direction is larger than in the layout of FIG. 9, but the gate width W of the switching transistors YT and YN can be increased to about twice the pitch Psa. The gate width W of the switching transistors YT and YN can be increased, and the capability can be improved. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected.

(Modification 1 of Y switch part 23)
Next, a modified example 1 of the layout of the Y switch unit 23 will be described with reference to FIG. FIG. 17 shows the Y switch section 23 of the memory cell in the open bit format. FIG. 17 shows the Y switch unit 23 for the four bit line pairs of the bit line pair BT0, BN0, the bit line pair BT1, BN1, the bit line pair BT2, BN2, and the bit line pair BT3, BN3.

  A case where four bit lines BT0 to BT3 enter from the upper memory cell 11 and four bit lines BN0 to BN3 enter from the lower memory cell 11 with respect to twice the SA pitch Psa. Assumed. Also in this case, each of the gates g1 to g4 is formed along the horizontal direction. The electrodes of the gates g1 to g4 are twice as long as the SA pitch Psa.

  The Y switch unit 23 is provided with four diffusion layers 41a to 41d. The diffusion layers 41a to 41d are arranged in 2 × 2 in the vertical direction. The diffusion layer 41 is separated by the transistor pair of each address. For example, the diffusion layer 41a of the switching transistor YT0 and the diffusion layer 41b of the switching transistor YN0 are separated. Further, the diffusion layer 41a is shared by the switching transistor YT1 of the switching transistor YT0. The same applies to the diffusion layers 41d of the switching transistors YT2 and YT3. The same applies to the diffusion layers 41c of the switching transistors YN2 and YN3. The diffusion layer 41a and the diffusion layer 41d are arranged diagonally, and the diffusion layer 41b and the diffusion layer 41c are arranged diagonally.

  The four gates g1 to g4 are arranged in four upper and lower stages. Even with such a configuration, the pitch of the Y switch section 23 becomes twice the SA pitch Psa. The above effects can be obtained. Only the linear gates g1 to g4 are used to unify the arrangement direction of the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected.

(Modification 2 of the Y switch section 23)
A modified example 2 of the layout of the Y switch unit 23 will be described with reference to FIG. Further, FIG. 18 shows a region three times the SA pitch Psa. In other words, the Y switch section 23 for three bit line pairs of the bit line pair BT0, BN0, the bit line pair BT1, BN1, and the bit line pair BT2, BN2 is shown. In the layout shown in FIG. 18, both ends of the lateral gate g are U-shaped bent at a right angle. Since the basic configuration other than the shape of the gate g is the same as that of the first embodiment, description thereof will be omitted as appropriate.

  In this configuration, it is not necessary to dispose the protruding portion of the gate g and the connection contact with the column selection signal line Y at the end of the diffusion layer 41 in the horizontal direction. Thereby, the gate width W of the transistor of the Y switch section 23 can be increased. Although an increase in height occurs due to the upper and lower gate protruding portions, an optimal layout can be obtained from a combination of design criteria and transistor size. Further, the gate common region is shifted by the SA pitch between the upper and lower switching transistors YT1 and YN2. That is, the protruding position of the gate g in the lateral direction is shifted between the upper and lower gates g. This is a layout in consideration of the ease of signal wiring connecting from the bit line to the diffusion layer 41.

(Modification 3 of Y switch part 23)
Next, a third modification of the layout of the Y switch unit 23 will be described with reference to FIG. FIG. 19 shows the Y switch unit 23 for the four bit line pairs of the bit line pair BT0, BN0, the bit line pair BT1, BN1, the bit line pair BT2, BN2, and the bit line pair BT3, BN3. Further, FIG. 19 shows an area that is four times the SA pitch Psa.

  In FIG. 19, the gate g is formed in a U-shape as in the configuration of FIG. The diffusion layer 41b is formed wider than the SA pitch Psa and protrudes from the adjacent SA pitch Psa. Further, the diffusion layer 41b connected to the common bus line DN is added to the upper and lower sides, and is shared between the left and right adjacent SAs. That is, the diffusion layer 41b connected to the common bus line DN connected to the switching transistors YN0 to YN3 is common. By doing so, the diffusion layer 41b common to the four switching transistors YN can be used. Although not shown, the diffusion layers 41a and 41c connected to the common bus line DT are also shared between adjacent SAs. The separation region of the diffusion layer 41 can be reduced. The gate width W of the switching transistors YT and YN can be made larger than that in FIG. For example, since the element isolation region and the contact are not necessary, the diffusion layer 41 can be enlarged and the gate width W can be increased.

  The layout of the Y switch unit 23 shown in FIG. 9 can be changed to the layout shown in any of FIGS. The layout of the Y switch unit 23 shown in FIGS. 16 to 19 and the layout of the PMOS pair 25 shown in FIGS. 10 to 12 may be combined.

Embodiment 3 FIG.
(Example of transistor arrangement in the precharge unit 22)
The configuration of the semiconductor memory according to the third embodiment will be described with reference to FIG. FIG. 20 is a layout diagram of the transistors of the precharge unit 22. The layout of the precharge unit 22 according to the present embodiment can be used in the first embodiment. Note that description of the same contents as those in Embodiments 1 and 2 is omitted.

  In FIG. 20, the equalizing transistor EQ and the precharging transistor PCT share the diffusion layer 41 with respect to the layout of the first embodiment. In FIG. 20, a diffusion layer 41a is formed for the bit line pair BT0, BN0, and a diffusion layer 41b is formed for the bit line pair BT1, BN1.

  The diffusion layer 41a is shared by the bit line BT0 side of the equalizing transistor EQ0 and the bit line BT0 side of the precharging transistor PCT0. The diffusion layer 41a is commonly used by the HVDD side of the precharging transistor PCN0 and the HVDD side of the precharging transistor PCT0.

  In the precharge unit 22, four gates g1 to g4 are arranged along the horizontal direction. The first-stage and third-stage gates g1 and g4 have a length that is at least twice the SA pitch Psa. In the second stage, two gates g2 and g3 are provided. The first-stage gate g1 corresponds to the equalizing transistor EQ0 and the precharging transistor PCN1. The third-stage gate g4 corresponds to the equalizing transistor EQ1 and the precharging transistor PCN0. One gate g2 in the second stage corresponds to the precharging transistor PCT0, and the other gate g3 corresponds to the precharging transistor PCT1.

  The equalizing transistor EQ0, the precharging transistor PCT0, and the precharging transistor PCN0 are arranged at a distance in the bit line direction. The gate g1 of the equalizing transistor EQ0, the gate g2 of the precharging transistor PCT0, and the gate g4 of the precharging transistor PCN0 are different gates. Similarly, for the bit line pair BT1, BN1, the gate 4 of the equalizing transistor EQ1, the gate g3 of the precharging transistor PCT1, and the gate g1 of the precharging transistor PCN1 are different gates. The equalizing transistor EQ0 and the precharging transistor PCN1 are a common gate g1. The equalizing transistor EQ1 and the precharging transistor PCN0 are a common gate g4. The gate g2 of the precharging transistor PCT0 is independent. The gate g3 of the precharging transistor PCT1 is independent.

  The diffusion layers 41a and 41b are formed so as to protrude from the adjacent SA pitch Psa. That is, the diffusion layers 41a and 41b are wider than the SA pitch Psa, and are formed over the two SA pitches Psa. The diffusion layers 41a and 41b have extending portions 411 and 412 respectively. Accordingly, the diffusion layers 41a and 41b are each formed in an L shape, and the portions extending in the bit direction are extended portions 411 and 412, respectively. The diffusion layer 41a is laid out rotationally symmetrical with respect to the diffusion layer 41b. In the diffusion layer 41a, the extending portion 411 extending in the vertical direction constitutes the precharging transistor PCT0 and the precharging transistor PCN0. In the diffusion layer 41b, the extending portion 412 extending in the bit line direction constitutes the precharging transistor PCT1 and the precharging transistor PCN1.

  The gate g1 of the precharging transistor PCN1 extends so as to straddle the diffusion layer 41a. The first-stage gate g1 straddles the diffusion layer 41a and the extending portion 412. For two times the SA pitch Psa, the equalizing transistor EQ0 and the precharging transistor PCN1 can form a common gate g1. The gate g4 of the precharging transistor PCN0 extends so as to straddle the diffusion layer 41b. The third-stage gate g4 straddles the diffusion layer 41b and the extending portion 411. Similarly, a common gate g4 can be formed by the precharging transistor PCN0 and the equalizing transistor EQ1.

  As a result, the gate width W can be increased. Further, extending portions 411 and 412 are provided in the diffusion layers 41 a and 41 b, and precharging transistors PCN 0 and PCN 1 are disposed in the extending portions 411 and 412. As a result, the gate width of the equalizing transistor EQ that requires high capability can be made wider than that of the precharging transistor PCN. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The pitch of the precharge unit 22 is twice the SA pitch Psa. Therefore, the area can be reduced as described above.

(Modification 1 of the precharge unit 22)
FIG. 21 is a layout showing a first modification of the transistor arrangement of the precharge unit 22. In FIG. 21, three diffusion layers 41a to 41c are provided. The diffusion layer 41b is narrower than the diffusion layers 41a and 41c. The precharge portion 22 is provided with two linear gates g1 and g2. In FIG. 21, since the diffusion layer 41 is not separated in the vertical direction and the gates g1 and g2 have a two-stage configuration, the circuit height can be reduced.

  The diffusion layer 41a corresponds to the precharging transistor PCT0 and the equalizing transistor EQ0. The diffusion layer 41b corresponds to the precharging transistor PCN0 and the precharging transistor PCT1. The diffusion layer 41c corresponds to the precharging transistor PCN1 and the equalizing transistor EQ1. The transistor layout is rotationally symmetric.

  The upper gate g1 is common to the equalizing transistor EQ0, the precharging transistor PCN0, the equalizing transistor EQ1, and the precharging transistor PCN1. The lower gate g2 is common to the precharging transistor PCT0, the equalizing transistor EQ0, the precharging transistor PCT1, and the equalizing transistor EQ1.

  Therefore, the equalizing transistor EQ0 is a parallel connection of two transistors provided in the diffusion layer 41a. The equalizing transistor EQ0 is formed by two transistors, a transistor having a gate width W substantially equal to that of the precharging transistors PCT and PCN and a transistor having a gate width W wider than that of the precharging transistors PCT and PCN. In the equalizing transistor EQ0, a transistor having a wide gate width W is provided in the upper stage, and a transistor having a narrow gate width W is provided in the lower stage. Similarly, the equalizing transistor EQ1 is a parallel connection of two transistors provided in the diffusion layer 41c. In the equalizing transistor EQ1, a transistor having a narrow gate width W is provided in the upper stage, and a transistor having a wide gate width W is provided in the lower stage.

  The precharging transistor PCN0 and the precharging transistor PCT1 are assigned to the diffusion layer 41b. Precharging transistors PCN0 and PCT1 are arranged in two upper and lower stages. The diffusion layers 41b to which the precharge potential HVDD is supplied are commonly used in the two precharge transistors PCN0 and PCT1. Further, the precharging transistor PCT has a gate width W substantially equal to that of the precharging transistor PCN. The gate width W of the precharging transistors PCN and PCT is approximately the same as that of the narrower one of the two upper and lower equalizing transistors EQ0.

  By doing so, the gate width W of the equalizing transistor EQ can be made wider than the SA pitch Psa. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The pitch of the precharge unit 22 is twice the SA pitch Psa. Therefore, the area can be reduced as described above.

(Modification 2 of the precharge unit 22)
FIG. 22 is a layout showing a second modification of the transistor arrangement of the precharge unit 22. In FIG. 22, two diffusion layers 41a and 41b are provided. The diffusion layers 41a and 41b are arranged in two upper and lower stages. Further, a vertical gate 51 formed along the bit line direction is provided. In the present embodiment, the upper and lower two-stage gates g 1 and g 2 are connected by the vertical gate 51. The vertical gate 51 extends from the diffusion layer 41 to the diffusion layer 41b in the bit line direction. The vertical gate 51 is disposed in the vicinity of the left end of the diffusion layers 41a and 41b.

  The vertical gate 51 becomes the gate of the precharging transistors PCN0 and PCN1. Of the first-stage gate g1, the left side of the vertical gate 51 is the gate of the precharging transistor PCT0. Of the second-stage gate g2, the portion on the left side of the vertical gate 51 is the gate of the precharging transistor PCN1. The gates g1 and g2 on the right side of the vertical gate 51 are the gates of the equalizing transistors EQ0 and EQ1, respectively. Since the position of the vertical gate 51 is asymmetrical, the gate width of the equalizing transistor EQ can be made wider than that of the precharging transistors PCT and PCN. That is, the gate width W of the equalizing transistor EQ becomes larger than the SA pitch Psa, and can be expanded to nearly twice the SA pitch Psa.

  In the layout of FIG. 22, the gate corresponding to the diffusion layer 41a is T-shaped. Similarly, the gate corresponding to the diffusion layer 41a is T-shaped. The two gates g1 and g2 in the horizontal direction are connected by the vertical gate 51. By providing the vertical gate 51, the gate can be formed into a T-shaped pattern. Therefore, the area does not increase due to the protruding gate in the height direction. Further, in FIG. 22, the diffusion layer 41 is not separated in the bit line direction, and the gates g1 and g2 have a two-stage configuration, so that the height in the bit line direction can be reduced.

  The layout of the precharge unit 22 shown in FIG. 9 can be changed to the layout shown in any of FIGS. The layout of the precharge unit 22 shown in FIGS. 20 to 22 may be combined with the layout of the PMOS pair 25 shown in FIGS. 10 to 12 and the layout of the Y switch unit 23 shown in FIGS. . The pitch of the precharge unit 22 is twice the SA pitch Psa. Therefore, the area can be reduced as described above.

Embodiment 4 FIG.
(Sense amplifier layout)
The configuration of the semiconductor memory according to the fourth embodiment will be described with reference to FIG. FIG. 23 shows the layout of the sense amplifier 12. In addition, description is abbreviate | omitted about the content which overlaps with Embodiment 1-3.

  FIG. 23 shows a layout in which the precharge unit 22 and the Y switch unit 23 are integrated. In the following description, a portion where the precharge unit 22 and the Y switch unit 23 are integrated is referred to as a YSW / PRE unit 27. The PMOS pair 25, the NMOS pair 26, and the YSW / PRE unit 27 are arranged side by side in the bit line direction. FIG. 23 shows a transistor layout with two SA pitches Psa. Note that the PMOS pair 25 and the NMOS pair 26 are the same as those in FIG.

  For example, in the low VDD generation with VDD ≦ 1.2V, since the precharge voltage HVDD is ½VDD, the gate-drain (or source) voltage when the precharge transistors PCT and PCN and the equalizing transistor EQ are on. Vg becomes ½ VDD, and the ON capability is remarkably insufficient. There are the following measures for reliably carrying out DRAM bit line precharge.

  One is a method of boosting the potential of the precharge signal line VDL from the power supply voltage VDD. In this case, there is a high voltage transistor that increases the gate oxide film thickness of the precharge transistors PCT and PCN and the equalizing transistor EQ. Needed. However, recently, it has become possible to use a core transistor equivalent to the switching transistors YT and YN. The other method is a GND potential precharge circuit system, and in this case, boosting of the potential of the precharge signal line VDL becomes unnecessary. Since both can use the same core transistor as the switching transistors YT and YN, the integrated layout design technique is important.

  In FIG. 23, the YSW / PRE unit 27 is provided with two diffusion layers 41a and 41b. In the YSW / PRE portion 27, a diffusion layer 41a is provided in the left SA pitch Psa, and a diffusion layer 41b is provided in the right SA pitch Psa. The left SA pitch Psa corresponds to the SA of the bit line pair BT0, BN0, and the right SA pitch Psa corresponds to the SA of the bit line pair BT1, BN1. The diffusion layer 41a has a rotationally symmetric layout with respect to the diffusion layer 41b. A common diffusion layer 41a is used by the precharging transistor PCT0, the equalizing transistor EQ0, and the precharging transistor PCN1 and the switching transistors YT0 and YT1. That is, the integrally formed diffusion layer 41a corresponds to the precharging transistors PCT0 and PCT1, the equalizing transistor EQ0, and the switching transistors YT0 and YT1. Similarly, a common diffusion layer 41b is used for the precharging transistors PCN1, PCN0, the equalizing transistor EQ1, and the switching transistors YN0, YN1.

  In the YSW / PRE unit 27, four gates g1 to g4 are arranged. In order from the upper stage, that is, the gate g on the NMOS pair 26 side, the gate is g1, the gate g2, the gate g2, and the gate g4. The gate g1 is connected to the precharge signal line PDL of the bit line pair BT0, BN0. A column selection signal line Y0 is connected to the gate g2. The column selection signal line Y1 is connected to the gate g3. The gate g4 is connected to the precharge signal line PDL of the bit line pair BT1, BN1. Each of the four gates g1 to g4 is a linear electrode along the horizontal direction. Each gate g1 to gate g4 extends to the adjacent sense amplifier pitch Psa. That is, each gate g1 to gate g4 is formed so as to protrude to the adjacent sense amplifier pitch Psa. Each of the gates g1 to g4 is formed from the diffusion layer 41a to the diffusion layer 41b. The gates g1 to g4 have a length about twice the SA pitch Psa and straddle the diffusion layers 41a and 41b.

  The switching transistors YT0 and YT1 are arranged in the SA pitch Psa on the left side. The switching transistors YN0 and YN1 are arranged in the right SA pitch Psa. The gate g2 is formed across the diffusion layers 41a and 41b in the horizontal direction, and a common column selection signal is supplied to the switching transistors YT0 and YN0. The gate g3 is formed across the diffusion layers 41a and 41b in the horizontal direction, and a common column selection signal is supplied to the switching transistors YT1 and YN1.

  The precharging transistor PCT0 and the equalizing transistor EQ0 are arranged in the left SA pitch Psa. The precharging transistor PCN0 is disposed within the SA pitch Psa on the right side. The precharging transistors PCT0 and PCN0 and the equalizing transistor EQ0 share one linear gate g1. Similarly, the precharging transistor PCN1 and the equalizing transistor EQ1 are arranged within the right SA pitch Psa. The precharging transistor PCT1 is disposed within the SA pitch Psa on the left side. The precharging transistors PCT1 and PCN1 and the equalizing transistor EQ1 share one linear gate g4.

  The gates g2 of the switching transistors YT0 and YN0 and the gates g3 of the switching transistors YT1 and YN1 are arranged at the same position in the horizontal direction and are separated in the bit line direction. The gate g1 of the precharging transistors PCT0 and PCN0 and the equalizing transistor EQ0 and the gate g4 of the precharging transistors PCT1 and PCN1 and the equalizing transistor EQ1 are arranged at the same position in the horizontal direction and are spaced apart in the bit line direction. doing. The four gates g1 to g4 are arranged at the same position in the horizontal direction and are separated in the bit line direction. In the bit line direction, the two gates g2 and 3 of the switching transistor are arranged between the two gates g1 and g4 of the precharging transistor.

  In the bit line direction, the diffusion layer to which the common bus line of the switching transistor YT0 is connected and the diffusion layer to which the common bus line of the switching transistor YT1 is connected are shared. A common bus line DT is connected to the shared diffusion layer 41a. Similarly, the diffusion layer connected to the switching transistor YN0 common bus line and the diffusion layer connected to the switching transistor YN1 common bus line in the bit line direction are shared. A common bus line DT is connected to the shared diffusion layer 41b.

  The precharge transistors PCT and PCN and the equalizing transistor EQ are arranged with the diffusion layers 41a and 41b extending vertically. For example, a precharging transistor PCT0 and an equalizing transistor EQ0 are disposed above the switching transistor YT0, and a precharging transistor PCT1 is disposed below the switching transistor YT1. In the switching transistors YT0 and YT1, the precharging transistors PCT0 and PCT1, and the equalizing transistor EQ0, a shared diffusion layer is used. Specifically, the diffusion layer 41a is shared by the diffusion layer to which the bit line BT0 of the switching transistor YT0 is connected and the diffusion layer to which the precharge transistor PCT0 and the equalization transistor EQ0 are connected to BT0. It has become. The diffusion layer 41a is shared by the diffusion layer to which the bit line BT1 of the switching transistor YT1 is connected and the diffusion layer to which BT1 of the precharging transistor PCT1 is connected. The diffusion layer 41b has a similar layout. Therefore, the shared diffusion layer 41a is used in the switching transistors YT0 and YT1, the precharging transistors PCT0 and PCN1, and the equalizing transistor EQ0.

  In this way, ten transistors provided in two SAs can be laid out in two diffusion layers 41a and 41b. Thereby, the element isolation region of the diffusion layer 41 can be reduced, and the gate width W can be widened with a small area. Furthermore, since the four linear gates g1 to g4 carry 10 transistors provided in the two SAs, it is possible to suppress the SA height expansion. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The pitch of the YSW / PRE unit 27 is twice the SA pitch Psa. Therefore, the area can be reduced as described above. Further, the diffusion layer 41 is integrated with the switching transistor and the precharging transistor. This allows efficient layout. The area can be reduced. By making the diffusion layer 41 common between the bit line side of the equalizing transistor EQ and the bit line side of the switching transistor, the layout can be efficiently performed. Further, by sharing the gate g with a plurality of transistors, the number of connection points between the gate g and the connection wiring can be reduced. Further, by sharing the diffusion layer 41, the element isolation region can be reduced. Thereby, the layout can be performed efficiently and the area can be reduced.

(Layout variation 1 of YSW / PRE unit 27)
Modification 1 of the YSW / PRE unit 27 in which the precharge unit and the Y switch unit are integrated will be described with reference to FIG. FIG. 24 is a diagram showing a layout example of transistors in the YSW / PRE unit 27. In FIG. Note that description of portions common to FIG. 23 is omitted as appropriate. FIG. 24 shows an example where the bit lines are arranged in an open bit format so that four bit lines are supplied to the YSW / PRE unit 27 from the top and bottom. FIG. 24 shows an example in which four pairs of bit line pairs BT0 and BN0 to bit line pairs BT3 and BN3 are arranged at twice the SA pitch Psa.

  In FIG. 24, in the YSW / PRE section 27, diffusion layers 41a and 41b are arranged in a range twice as large as the SA pitch Psa. A diffusion layer 41a is disposed in the left SA pitch Psa. A diffusion layer 41b is disposed in the right SA pitch Psa. The diffusion layer 41a has a rotationally symmetric layout with respect to the diffusion layer 41b. The SA pitch Psa on the left corresponds to the SA of the bit line pair BT0, BN0 and the bit line pair BT2, BN2. The SA pitch Psa on the right side corresponds to the SA of the bit line pair BT1, BN1 and the bit line pair BT3, BN3.

  In addition, eight gates g are arranged in the YSW / PRE unit 27. The gate g1, gate g2, gate g3, gate g4, gate g5, gate g6, gate g7, and gate g8 are sequentially formed from the upper gate g. The gate g1 is connected to the precharge signal line PDL of the bit line pair BT0, BN0. The gate g2 is connected to the column selection signal line Y0. The gate g3 is connected to the column selection signal line Y1. The gate g4 is connected to the precharge signal line PDL of the bit line pair BT1, BN1. The gate g5 is connected to the precharge signal line PDL of the bit line pair BT2, BN2. The gate g6 is connected to the column selection signal line Y2. The gate g7 is connected to the column selection signal line Y3. The gate g8 is connected to the precharge signal line PDL of the bit line pair BT3, BN3.

  In the layout of FIG. 24, two diffusion layers 41a and 41b are used for four SAs. That is, the diffusion layer 41 of the YSW / PRE portion 27 is integrally formed by the upper and lower SA amplifiers. Therefore, the height can be reduced more than when the layout of FIG. 23 is simply arranged in two stages. That is, the element isolation regions can be omitted for the upper and lower SA diffusion layers 41, and the layout can be efficiently performed.

  For example, the switching transistors YT0 to YT3 correspond to the diffusion layer 41a formed integrally. Four precharging transistors PCT are arranged in the diffusion layer 41a. Equalizing transistors EQ0 and EQ2 are arranged in diffusion layer 41a. Similarly, the switching transistors YN0 to YN3 are disposed in the diffusion layer 41b formed integrally. Four precharging transistors PCN are arranged in the diffusion layer 41b. Equalizing transistors EQ1 and EQ3 are arranged in the diffusion layer 41b. One diffusion layer 41 carries 10 transistors.

  A gate g4 to which the precharge signal line PDL of the bit line pair BT1 and BN1 is supplied and a gate g5 to which the precharge signal line PDL of the bit line pair BT2 and BN2 is supplied are continuously arranged. The precharge transistor PCT1 and the precharge transistor PCT2 share a diffusion layer to which the precharge voltage HVDD is supplied. Similarly, the precharge transistor PCN1 and the precharge transistor PCN2 commonly use a diffusion layer to which the precharge voltage HVDD is supplied. Thereby, the number of connection contacts of the precharge voltage HVDD can be reduced, and the height can be reduced. Further, the equalizing transistor EQ2 is provided in the diffusion layer 41a, and the equalizing transistor EQ1 is provided in the diffusion layer 41b.

  Further, the gate width W of the equalizing transistor EQ and the precharging transistor PCT is set so as to be within the gate width W of the switching transistor YT. For example, the total width of the gate width W of the precharging transistor PCT2 and the equalizing transistor EQ2 falls within the gate width W of the switching transistor YT2. In addition to the precharge transistor PCT, the gate width W of the switch transistor YT has a space equivalent to the equalization transistor EQ. Similarly, the gate width W of the equalizing transistor EQ and the precharging transistor PCN is set to be within the gate width W of the switching transistor YN. Therefore, the equalizing transistor EQ can be arranged in the lateral direction of the precharging transistor PCT or the precharging transistor PCN.

  By adopting such a layout, a compact layout with a very high element density is possible. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The pitch of the YSW / PRE unit 27 is twice the SA pitch Psa. Therefore, the area can be reduced as described above.

(Layout variation 2 of YSW / PRE unit 27)
Modification 2 of the YSW / PRE unit 27 in which the precharge unit and the Y switch unit are integrated will be described with reference to FIG. FIG. 25 is a diagram showing a layout example of transistors in the YSW / PRE unit 27. In FIG. In FIG. 25, the arrangement of the equalizing transistors EQ is changed with respect to the configuration of FIG. Note that description of portions common to FIG. 23 is omitted as appropriate.

  In FIG. 25, an equalizing transistor EQ1 is provided in the diffusion layer 41a. An equalizing transistor EQ1 is provided below the switching transistor YT1. Similarly, an equalizing transistor EQ0 is provided in the diffusion layer 41b. An equalizing transistor EQ0 is provided below the switching transistor YN0. The equalizing transistor EQ0 of the diffusion layer 41a and the equalizing transistor EQ0 of the diffusion layer 41b are connected in parallel. The equalizing transistor EQ1 of the diffusion layer 41a and the equalizing transistor EQ1 of the diffusion layer 41b are connected in parallel. By doing so, the substantial gate width W of the equalizing transistor EQ can be increased. Therefore, the ability of the equalizing transistor EQ can be improved.

  23, a connection point between the bit line BT0 and the diffusion layer 41b and a connection point between the bit line BN1 and the diffusion layer 41a are added. Compared with FIG. 23, the signal connection is complicated, but the capacity of the equalizing transistor EQ can be increased without increasing the height of SA. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected.

Embodiment 5. FIG.
Also in the present embodiment, as in the fourth embodiment, the precharge unit and the Y switch unit are integrated. In addition, description is abbreviate | omitted about the content which overlaps with Embodiment 1-4. In the fifth embodiment, a layout that can easily draw out the reduction in the SA height accompanying the miniaturization of the design standard of the device is used.

  The transistor layout of the YSW / PRE unit 27 according to the present embodiment will be described with reference to FIG. In addition, description is abbreviate | omitted suitably about the structure similar to Embodiment 1-4. For example, for the PMOS pair 25 and the NMOS pair 26, any one of FIGS. 9 to 12 can be used, and thus detailed description thereof is omitted.

  The YSW / PRE unit 27 will be described with reference to FIG. Note that a description of the same contents as those in the above embodiment is omitted. In FIG. 26, eight gates g1 to g8 are arranged. Each gate g1-g8 is formed in the linear form along the horizontal direction. The gates g1, g2, g3, g4, g5, g6, g7, and g8 are designated in order from the upper gate g. The gate g1 is connected to the column selection signal line Y0. The gate g2 is connected to the precharge signal line PDL. The gate g3 is connected to the precharge signal line PDL. The gate g4 is connected to the column selection signal line Y0. The gate g5 is connected to the column selection signal line Y1. The gate g6 is connected to the precharge signal line PDL. The gate g7 is connected to the precharge signal line PDL. The gate g8 is connected to the column selection signal line Y1.

  Also, two SA transistors are provided in the diffusion layer 41a formed integrally. Therefore, the diffusion layer 41a is formed across the two SA pitches Psa. The diffusion layer 41a is wider than the SA pitch Psa and is formed so as to protrude from the adjacent SA pitch Psa. The diffusion layer 41a has a rotationally symmetric shape. The transistor layout is also rotationally symmetric.

  The switching transistor YT0 and the switching transistor YN0 correspond to the gates g at different stages. The first-stage gate g1 corresponds to the switching transistor YT0, and the fourth-stage gate g4 corresponds to the switching transistor YN0. Similarly, the switching transistor YT1 and the switching transistor YN1 correspond to gates g at different stages. The fifth-stage gate g5 corresponds to the switching transistor YN1, and the eighth-stage gate g8 corresponds to the switching transistor YT1. As described above, since the switching transistor YT and the switching transistor YN are not arranged in the lateral direction, the gate width W of the switching transistors YT and YN can be increased. Here, the switching transistors YT and YN have a gate width W that is approximately twice the SA pitch Psa. As a result, the capabilities of the switching transistors YN and YN can be improved.

  Between the gate g1 of the switching transistor YT0 and the gate g4 of the switching transistor YN0, the equalizing transistor EQ0 and the gates g2 and g3 of the precharging transistors PCT0 and PCN0 are arranged. The precharging transistor PCT0 and the equalizing transistor EQ0 are arranged in the horizontal direction. An equalizing transistor EQ0 and a precharging transistor PCT0 are arranged side by side in a range twice the SA pitch Psa. The equalizing transistor EQ1 and the gates g6 and g7 of the precharging transistors PCT1 and PCN1 are similarly arranged between the fifth-stage gate g5 and the eighth-stage gate g8. Therefore, the capabilities of the precharging transistors PCT and PCN and the equalizing transistor EQ can be improved. The gate width W of the equalizing transistor EQ is wider than the gates W of the precharging transistors PCT and PCN. Thereby, the capability of the equalizing transistor EQ can be improved.

  Further, the switching transistor YN0 and the switching transistor YN1 share the common bus line DN. Thereby, the number of contacts can be reduced. Further, since the integral diffusion layer 41a is used for the two SAs, the element isolation region can be reduced. Thereby, the size in the height direction can be further reduced. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The pitch of the YSW / PRE unit 27 is twice the SA pitch Psa. Therefore, the area can be reduced as described above.

(Modification 1 of YSW / PRE unit 27)
Modification 1 of the YSW / PRE unit 27 will be described with reference to FIG. The description overlapping with the above layout will be omitted. In FIG. 27, eight gates g1 to g8 are arranged. Each gate g1-g8 is formed in the linear form along the horizontal direction. In the uppermost stage, two gates g1 and g2 are arranged in the horizontal direction. In the lowermost stage, two gates g7 and g8 are arranged in the horizontal direction. Therefore, eight gates g1 to g8 are arranged in six stages. A precharge signal line PDL is connected to one gate g1 of the first stage, and a column selection signal line Y0 is connected to the other gate g2. The gate g3 is connected to the precharge signal line PDL. The gate g4 is connected to the column selection signal line Y0. The gate g5 is connected to the column selection signal line Y1. The gate g6 is connected to the precharge signal line PDL. A precharge signal line PDL is connected to one gate g7 in the sixth stage, and a column selection signal line Y1 is connected to the other gate g8.

  In FIG. 27, three diffusion layers 41a to 41c are provided in two SA pitches Psa. The diffusion layers 41a to 41c are formed in a rectangular shape. The diffusion layers 41a and 41b are disposed within the SA pitch Psa corresponding to the bit line pair BT0 and BN0. That is, the width of the diffusion layers 41a and 41b in the lateral direction is smaller than the SA pitch Psa. The diffusion layer 41c is formed wider than the SA pitch and protrudes to the adjacent SA pitch. The diffusion layer 41c is arranged over two SA pitches Psa. The width of the diffusion layer 41c in the horizontal direction is larger than the SA pitch Psa.

  The diffusion layer 41a corresponds to the precharging transistors PCT0 and PCN0. The precharging transistors PCT0 and PCN0 share a diffusion layer 41a to which the precharge voltage HVDD is connected. The diffusion layer 41b corresponds to the precharging transistors PCT1 and PCN1. The precharging transistors PCT1 and PCN1 share a diffusion layer 41b to which the precharge voltage HVDD is connected. The diffusion layer 41a and the diffusion layer 41b are arranged in two upper and lower stages.

  The diffusion layer 41c is larger than the total area of the diffusion layer 41a and the diffusion layer 41b. The gates g2, g3, g4, g5, g6, and g8 straddle the diffusion layer 41c. The gates g1 and g3 straddle the diffusion layer 41a. Gates g6 and g7 straddle the diffusion layer 41b. The gate g2 corresponds to the switching transistor YT0. The gate g3 corresponds to the equalizing transistor EQ0. The gate g4 corresponds to the switching transistor YN0. The gate g5 corresponds to the switching transistor YN1. The gate g6 corresponds to the equalizing transistor EQ1. The gate g8 corresponds to the switching transistor YT1. The diffusion layer 41c to which the common bus line DN of the switching transistor YN0 and the switching transistor YN1 is connected is made common.

  In this configuration, the diffusion layer 41c extends to the adjacent SA pitch. Therefore, the gate width W of the equalizing transistor EQ and the switching transistors YT and YN can be made wider than the SA pitch Psa. Furthermore, since the layout can be performed efficiently, the area can be reduced. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The pitch of the YSW / PRE unit 27 is twice the SA pitch Psa. Therefore, the area can be reduced as described above.

(Modification 2 of YSW / PRE unit 27)
Modification 2 of the YSW / PRE unit 27 will be described with reference to FIG. The description overlapping with the above layout will be omitted. In FIG. 28, ten gates g1 to g10 are arranged. Each gate g is formed in a straight line along the horizontal direction. In each stage, two gates g are arranged in the horizontal direction. Therefore, ten gates g1 to g10 are arranged in five stages.

  One gate g1 in the first stage is connected to the precharge signal line PDL, and the other gate g2 is connected to the column selection signal line Y0. One gate g3 in the second stage is connected to the precharge signal line PDL, and the other gate g4 is connected to the column selection signal line Y1. One gate g5 in the third stage is connected to the precharge signal line PDL, and the other gate g6 is connected to the precharge signal line PDL. One gate g7 in the fourth stage is connected to the column selection signal line Y0, and the other gate g8 is connected to the precharge signal line PDL. One gate g9 in the fifth stage is connected to the column selection signal line Y1, and the other gate g10 is connected to the precharge signal line PDL.

  The gate g1 corresponds to the precharging transistor PCN0, and the gate g2 corresponds to the switching transistor YT0. The gate g3 corresponds to the precharging transistor PCT0, and the gate g4 corresponds to the switching transistor YT1. The switching transistor YT1 and the switching transistor YT0 share a diffusion layer connected to the common bus line DT. The precharge transistor PCT0 and the precharge transistor PCN0 share a diffusion layer connected to the precharge voltage HVDD.

  The gate g5 corresponds to the equalizing transistor EQ0, and the gate g6 corresponds to the equalizing transistor EQ1. The gate g7 corresponds to the switching transistor YN0, and the gate g8 corresponds to the precharging transistor PCN1. The gate g9 corresponds to the switching transistor YN01, and the gate g10 corresponds to the precharging transistor PCT1. The switching transistor YN0 and the switching transistor YN1 share a diffusion layer connected to the common bus line DN. The precharge transistor PCT1 and the precharge transistor PCN1 share a diffusion layer connected to the precharge voltage HVDD.

  Two diffusion layers 41a and 41b are disposed within a range twice the SA pitch Psa. The diffusion layer 41a is mainly disposed within the SA pitch Psa on the bit line pair BT0, BN0 side, and has a wide portion 414 partially extending to the SA pitch Psa on the bit line pair BT1, BN1 side. The diffusion layer 41b is mainly disposed within the SA pitch Psa on the bit line pair BT1, BN1 side, and is a wide portion 416 that partially extends to the SA pitch Psa on the bit line pair BT0, BN0 side. The diffusion layer 41a has a rotationally symmetric layout with respect to the diffusion layer 41b. The transistor layout is also rotationally symmetric.

  One gate g of each stage straddles the diffusion layer 41a, and the other gate g straddles the diffusion layer 41b. The narrow portion 413 of the diffusion layer 41a and the wide portion 416 of the diffusion layer 41b are arranged in the horizontal direction, and the narrow portion 415 of the diffusion layer 41b and the wide portion 414 of the diffusion layer 41a are arranged in the horizontal direction. The widths of the wide portions 414 and 416 in the horizontal direction are wider than the SA pitch Psa. The widths of the narrow portions 413 and 415 in the horizontal direction are narrower than the SA pitch Psa.

  The gates g1, g3, and g5 of the precharging transistors PCN0 and PCT0 and the equalizing transistor EQ0 straddle the narrow portion 413. The gates g10, g8, and g6 of the precharging transistors PCN1 and PCT1 and the equalizing transistor EQ1 straddle the narrow portion 415. The gates g2 and g4 of the switching transistors YT0 and YT1 straddle the wide portion 416. The gates g7 and g9 of the switching transistors YN0 and YN1 straddle the wide portion 414.

  In this way, the gate width W of the switching transistors YT and YN can be made wider than the SA pitch Psa. Further, two SA YSW / PRE units 27 can be realized at a height of five stages of the gate g. Therefore, the size in the height direction can be reduced. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The pitch of the YSW / PRE unit 27 is twice the SA pitch Psa. Therefore, the area can be reduced as described above.

Embodiment 6 FIG.
Also in the present embodiment, the precharge unit and the Y switch unit are integrated as in the fourth and fifth embodiments. In addition, description is abbreviate | omitted about the content which overlaps with Embodiment 1-5. The sixth embodiment is an example in which a gate shape other than a straight line is used for the transistor, which is disadvantageous in terms of device standards, but is a condition that can promote the shared integration of diffusion layers and gate signals.

  The transistor layout of the YSW / PRE unit 27 according to the present embodiment will be described with reference to FIG. In addition, description is abbreviate | omitted suitably about the structure similar to Embodiment 1-5. For example, for the PMOS pair 25 and the NMOS pair 26, any one of FIGS. 9 to 12 can be used, and thus detailed description thereof is omitted.

  In FIG. 29, the gates g of the precharging transistors PCN and PCT and the equalizing transistor EQ are integrated into a T shape. In FIG. 29, upper and lower four-stage gates g1 to g4 are provided. The second and third gates g2 and g3 are connected by two vertical gates 51a and 51b. The diffusion layer portion corresponding to the precharge voltage HVDD has a layout surrounded by gates. The first-stage gate g1 is connected to the column selection signal line Y0. The second-stage and third-stage gates g2, 3 and the vertical gates 51a, 51b are connected to the precharge signal line PDL. The fourth-stage gate g4 is connected to the column selection signal line Y1.

  The YSW / PRE unit 27 is provided with four diffusion layers 41a to 41d. The diffusion layers 41a and 41b are arranged in two upper and lower stages within the SA pitch Psa on the bit line pair BT0 and BN0 side. The diffusion layers 41c and 41d are arranged in two upper and lower stages within the SA pitch Psa on the bit line pair BT1 and BN1 side. The diffusion layers 41a to 41d have a rotationally symmetric layout. Further, the transistor layout of the YSW / PRE unit 27 is rotationally symmetric.

  The first-stage gate g1 is arranged from the diffusion layer 41a to the diffusion layer 41c. That is, the first-stage gate g1 is longer than the SA pitch Psa and straddles the two SA pitches Psa. The second-stage gate g2 is disposed so as to straddle the diffusion layer 41a. The third-stage gate g3 is disposed so as to straddle the diffusion layer 41d. The fourth-stage gate g4 is arranged from the diffusion layer 41b to the diffusion layer 41d. That is, the fourth-stage gate g4 is longer than the SA pitch Psa and straddles two SA pitches Psa. The vertical gate 51a corresponds to the diffusion layer 41a. The other vertical gate 51b corresponds to the diffusion layer 41d. A T-shaped gate is formed by providing the vertical gates 51a and 51b.

  Of the first-stage gate g1, the portion straddling the diffusion layer 41a becomes the gate g of the switching transistor YT0, and the portion straddling the diffusion layer 41d becomes the gate g of the switching transistor YN0. The left side of the vertical gate 51a of the second stage gate g2 is the gate g of the equalizing transistor EQ0, and the right side is the gate g of the precharging transistor PCT0. The vertical gate 51a becomes the gate of the precharging transistor PCN0. Thus, the second-stage gate g2 and the vertical gate 51a extending thereunder constitute the T-type gates of the precharging transistors PCN0 and PCT0 and the equalizing transistor EQ0.

  Similarly, the portion on the right side of the vertical gate 51b of the third stage gate g3 is the gate of the equalizing transistor EQ1, and the portion on the left side is the gate of the precharging transistor PCN1. The vertical gate 51b becomes the gate of the precharging transistor PCT1. Thus, the third-stage gate g3 and the vertical gate 51b extending thereon constitute the T-type gates of the precharging transistors PCN1 and PCT1 and the equalizing transistor EQ1. Two sets of T-shaped transistors are lined upside down in the opposite direction. Of the fourth-stage gate g4, the portion straddling the diffusion layer 41a becomes the gate of the switching transistor YT1, and the portion straddling the diffusion layer 41d becomes the gate of the switching transistor YN1.

  The switching transistor YT0, the equalizing transistor EQ0, and the precharging transistor PCT0 share the bit line BT0 side. The switching transistor YN1, the equalizing transistor EQ1, and the precharging transistor PCN0 share the bit line BN1 side. In a frame-shaped region surrounded by the two vertical gates 51a and 51b, the second-stage gate g2, and the third-stage gate g3, a precharge voltage HVDD connecting the diffusion layer 41a and the diffusion layer 41 is provided. Connection lines are provided.

  With such a layout, the same effect as described above can be obtained. For example, the pitch of the YSW / PRE unit 27 is twice the SA pitch Psa, so the area can be reduced. Furthermore, since the number of stages of the gate g can be reduced, the vertical size can be reduced.

(Modification 1 of YSW / PRE unit 27)
Modification 1 of the YSW / PRE unit 27 will be described with reference to FIG. Note that a description of the same contents as those in the above embodiment is omitted. In FIG. 30, a vertical gate 51 is used for the layout of FIG. The gates g of the precharging transistors PCN and PCT and the equalizing transistor EQ are integrated into a T shape.

  In FIG. 30, four stages of upper and lower gates g are provided. In the second stage, two gates g2 and g3 are provided. In the third stage, two gates g4 and g5 are provided. Therefore, a total of six lateral gates g1 to g6 are arranged. Then, one gate g2 at the second stage and one gate g4 at the third stage are connected by the vertical gate 51.

  In FIG. 30, four diffusion layers 41a to 41d are provided in a region twice the SA pitch Psa. The diffusion layers 41c and 41d are wider than the SA pitch Psa and protrude to the adjacent SA pitch Psa. The diffusion layers 41a and 41b are arranged in two upper and lower stages and have substantially the same lateral width. Diffusion layers 41a and 41b are arranged in the SA pitch Psa on the left side. The diffusion layers 41c and 41c are arranged in two upper and lower stages, and the diffusion layers 41c and 41c are arranged in two upper and lower stages and have substantially the same lateral width. The diffusion layers 41c and 41d protrude from the left SA pitch Psa to the right SA pitch Psa. Therefore, the width of the diffusion layers 41c and 41d in the lateral direction is wider than that of the diffusion layers 41a and 41b.

  The first-stage gate g1 is connected to the column selection signal line Y0. The first-stage gate g1 is disposed so as to straddle the diffusion layer 41c. One gate g2 in the second stage is connected to the precharge signal line PDL, and the other gate g3 is connected to the column selection signal line Y1. One gate g2 in the second stage is disposed so as to straddle the diffusion layer 41a, and the other gate g3 corresponds to the diffusion layer 41c. One gate g4 in the third stage is connected to the precharge signal line PDL, and the other gate g5 is connected to the column selection signal line Y0. One gate g4 in the third stage corresponds to the diffusion layer 41b, and the other gate g5 is disposed so as to straddle the diffusion layer 41d. The fourth-stage gate g6 is connected to the column selection signal line Y1. The fourth-stage gate g6 is disposed so as to straddle the diffusion layer 41d.

  The first-stage gate g1 corresponds to the switching transistor YT0. One gate g2 in the second stage corresponds to the precharging transistor PCT0, and the other gate g3 corresponds to the switching transistor YT1. One gate g4 in the third stage corresponds to the precharging transistor PCN1, and the other gate g5 corresponds to the switching transistor YN0. The fourth-stage gate g6 corresponds to the switching transistor YN1. The vertical gate 51 is disposed so as to straddle the diffusion layer 41a and the diffusion layer 41b.

  The diffusion layer 41a corresponds to the precharging transistors PCT0 and PCN0 and the equalizing transistor EQ0. In the diffusion layer 41a, the portion above the gate g2 of the vertical gate 51 is the gate of the equalizing transistor EQ0, and the portion below is the gate of the precharging transistor PCN0. Thus, the vertical gate 51 and the second-stage gate g2 extending laterally form the T-type gates of the precharging transistors PCN0 and PCT0 and the equalizing transistor EQ0.

  The diffusion layer 41b corresponds to the precharging transistors PCT1 and PCN1 and the equalizing transistor EQ1. In the diffusion layer 41b, the part above the gate g4 of the vertical gate 51 is the gate of the precharging transistor PCT1, and the part below is the gate of the equalizing transistor EQ1. As described above, the vertical gate 51 and the third-stage gate g4 extending laterally form the T-type gates of the precharging transistors PCN1 and PCT1 and the equalizing transistor EQ1. In the SA pitch Psa of the bit line pair BT0 and BN0, two sets of T-shaped transistors are arranged in the vertical direction. The T-shaped gate is mirror-symmetric with respect to the horizontal straight line.

  With this layout, the switching transistors YT and YN can be aligned on the right side. Further, the precharging transistors PCT and PCN and the equalizing transistor EQ can be aligned on the left side. Further, the vertical gate 51 penetrating the two diffusion layers 41a and 41b in the vertical direction corresponds to the precharging transistor PCN0, the equalizing transistor EQ0, the equalizing transistor EQ1, and the precharging transistor PCT1. As a result, the gate width W of the equalizing transistor EQ can be easily increased, and the ability of the equalizing transistor EQ can be improved. In addition, the same effect as described above can be obtained. For example, the pitch of the YSW / PRE unit 27 is twice the SA pitch Psa, so the area can be reduced.

(Modification 2 of YSW / PRE unit 27)
Modification 2 of the YSW / PRE unit 27 will be described with reference to FIG. Note that a description of the same contents as those in the above embodiment is omitted. In FIG. 31, a vertical gate 51 is used for the layout of FIG. One diffusion layer 41a is provided for an area four times the SA pitch Psa. That is, the integrally formed diffusion layer 41a is formed over the four SA pitches Psa.

  FIG. 31 shows the layout of the YSW / PRE unit 27 for the four bit line pairs BT0 to BT3 and BN0 to BN3. In order from the SA pitch Psa on the left side, the bit line pair BT0, BN0, the bit line pair BT1, the BN1 bit line pair BT2, BN2, and the bit line pair BT3, BN3. The entire layout is mirror-symmetric with respect to the boundary line between the second and third SA pitches Psa from the left, and therefore the description of the layout of the two right SA pitches Psa is omitted. That is, the layout related to the bit line pair BT0, BN0 and the bit line pair BT1, BN1 is mirror-symmetric with the layout related to the bit line pair BT2, BN2 and the bit line pair BT3, BN3. Therefore, the description of the layout regarding the bit line pair BT2, BN2 and the bit line pair BT3, BN3 is omitted. Further, the entire layout is mirror-symmetric with respect to a horizontal straight line.

Gates g are arranged in six stages. In the region 4 times the SA pitch Psa, the first to sixth stages are each provided with two gates. The first stage gate g is referred to as gates g1 and g2. Similarly, the second stage gate g is referred to as gates 3 and g4. The third-stage gate g is gates g5 and g6, and the fourth-stage gate g is gates g7 and g8. The fifth-stage gate g is referred to as gates 9 and 10, and the sixth-stage gate g is referred to as gates 11 and 12.
The second-stage gate g3 and the fifth-stage gate g9 are connected by the vertical gate 51a. The first-stage gate g1 and the third-stage gate g5 are connected by a vertical gate 52a to form a U shape. The fourth-stage gate g7 and the sixth-stage gate g11 are connected by a vertical gate 53c and have a U-shape.

  The second-stage gate g3, the fifth-stage gate g9, and the vertical gate 51a are connected to the precharge signal line PDL. The gates g of the precharging transistors PCN and PCT and the equalizing transistor EQ are integrated into a T shape. The first-stage gate g1, the third-stage gate g7, and the vertical gate 52a are connected to the column selection signal line Y0. The fourth-stage gate g7, the sixth-stage gate g11, and the vertical gate 52c are connected to the column selection signal line Y1.

  The first-stage gate g1 corresponds to the switching transistor YT0. The second stage gate g3 corresponds to the equalizing transistor EQ0. The third-stage gate g5 corresponds to the switching transistor YN0. The fourth-stage gate g7 corresponds to the switching transistor YN1. The fifth-stage gate g9 corresponds to the equalizing transistor EQ1. The sixth-stage gate g11 corresponds to the switching transistor YT1. The vertical gate 51a corresponds to the precharging transistor PCT0, the precharging transistor PCN0, the precharging transistor PCN1, and the precharging transistor PCT1 in order from the top.

  The first-stage gate g1 and the third-stage gate g5 are connected via a vertical gate 52a, and the fourth-stage gate g7 and the sixth-stage gate g11 are connected via a vertical gate 52c. Yes. The vertical gates 52a and 52b are arranged so as to straddle the opening 54 of the diffusion layer 41a. Therefore, each of the switching transistors YT and YN has an L-shaped gate g.

  The diffusion layer 41a extends to the adjacent SA pitch. Therefore, the isolation region of the diffusion layer 41a can be reduced. The common bus line DN can be shared by the two left SA pitches Psa and the two right SA pitches Psa. That is, the common bus line DN is shared by the four switching transistors YT0 to YT3. In other words, the contacts of the diffusion layer 41a are the same in the four switching transistors YT0 to YT3. Further, the common bus line DT is shared by the switching transistor YT0 and the switching transistor YT2. The common bus line DT is shared by the switching transistor YT1 and the switching transistor YT3. Further, the common bus line DT is shared by the SA pitch Psa on both sides (not shown). Therefore, the number of contacts can be reduced. The diffusion layer 41a can be shared with the adjacent pattern, and the size of the switching transistors YT and YN can be further increased. Therefore, the layout can be performed efficiently and the area can be reduced. Since the pitch of the YSW / PRE portion 27 is larger than the SA pitch Psa, the area can be further reduced.

  In the layout so far, the total number of transistors included in the precharge unit 22 and the Y switch unit 23 (here, the precharge transistors PCT and PCN, the equalize transistor EQ, and the switch transistors YT and YN are five). More than half of the transistors have a gate whose longitudinal direction is perpendicular to the bit line direction. At least one of the precharge unit 22 and the switch unit 23 is repeatedly arranged at a pitch wider than the sense amplifier pitch.

  Further, in the layout so far, the longitudinal direction of the gate g is a vertical direction perpendicular to the bit line direction. In the longitudinal direction of the gate g, the channels of the two transistors are continuously arranged. That is, the channel width direction of the two switching transistors sharing the gate g is the longitudinal direction of the gate g. For example, one gate g corresponds to the switching transistors YT0 and YT1, and the channel width direction of the switching transistors YT0 and YT1 is the longitudinal direction of the gate g. Thus, two or more switching transistor channels are continuous in the longitudinal direction of the switching transistor gate. For example, the gate g extending in the vertical direction corresponds to the switching transistor YT0 and the switching transistor YT1. That is, the switching transistor YT0 and the switching transistor YT1 share the gate g. Thereby, the electrode pattern of the gate g can be laid out efficiently and the area can be reduced. Further, with the configuration shown in FIGS. 13 to 15, four or more switching transistors can share the gate g at the boundary portion between adjacent I / Os. Similarly, two or more precharging transistors can share one gate g. Thereby, the area can be further reduced.

(Modification 3 of YSW / PRE unit 27)
Modification 3 of the YSW / PRE unit 27 will be described with reference to FIG. The description overlapping with the above layout will be omitted. In FIG. 32, the gates g are arranged in the vertical direction. That is, in the YSW / PRE portion 27, the longitudinal direction of the gate g of the transistor is the bit line direction. The switching transistors YT and YN, the precharging transistors PCT and PCN, and the equalizing transistor EQ are realized in an integrated transistor shape.

  The YSW / PRE portion 27 is provided with two stages of diffusion layers 41a and 41b. The first-stage diffusion layer 41a corresponds to the transistors of the bit line pair BT0 and BN0, and the second-stage diffusion layer 41b corresponds to the transistors of the bit line pair BT1 and BN1. The layout related to the bit line pair BT0 and BN0 and the layout related to the bit line pair BT1 and BN1 are mirror-symmetric with respect to the horizontal straight line. Therefore, the description of the layout relating to the bit line pair BT1, BN1 is omitted.

  The diffusion layers 41a and 41b are formed wider than the SA pitch Psa, and are formed over two SA pitches Psa. The YSW / PRE unit 27 is provided with five gates g1 to g5. The diffusion layer 41a corresponds to the three gates g1 to g3. The diffusion layer 41b corresponds to the three gates g4, g2, and g5. The three gates g1 to g3 are arranged in the horizontal direction. The left gate g1 corresponds to the switching transistor YT, and the right gate g3 corresponds to the switching transistor YN0. The intermediate gate g2 corresponds to the equalizing transistor EQ0 and the precharging transistors PCT0 and PCN0. The gate g2 branches in the middle, and one of the branches corresponds to the precharging transistor PCT0 and the other corresponds to the precharging transistor PCN0. Further, the part where the gate g2 is not branched corresponds to the equalizing transistor EQ0. The intermediate gate g2 extends from the diffusion layer 41a to the diffusion layer 41b. That is, the intermediate gate g2 is formed from the diffusion layer 41a to the diffusion layer 41b and supplied with a common precharge signal.

  The left diffusion layer 41a of the left gate g1 is connected to the common bus line DT. The right diffusion layer 41a of the right gate g3 serves as a common bus line DN. A diffusion layer 41a between the left gate g1 and the intermediate gate g2 is connected to the bit line BT0. Accordingly, the switching transistor YT0, the equalizing transistor EQ0, and the precharging transistor PCT0 share the diffusion layer 41a of the bit line BT0. A diffusion layer 41a between the right gate g3 and the intermediate gate g2 is connected to the bit line BN0. Therefore, the diffusion transistor 41a on the bit line BN0 side is shared by the switching transistor YN0, the equalizing transistor EQ0, and the precharging transistor PCN0.

  In this way, the diffusion transistors 41a integrated by the switching transistors YT0 and YN0 for the bit line pair BT0 and BN0, the precharging transistors PCT0 and PCN0, and the equalizing transistor EQ0 are shared. The diffusion layer 41a and the diffusion layer 41b are arranged above and below to correspond to the two columns Y0 and Y1. As shown in FIG. 7, the switching transistors YT0 and YN0, the precharging transistors PCT0 and PCN0, and the equalizing transistor EQ0 in one column are configured to be twice the SA pitch Psa. Thereby, the area can be reduced without reducing the gate width W.

  Further, the diffusion layers 41a and 41b of the common bus lines DT and DN at the left and right ends can be shared with the adjacent SA region pattern. For example, the leftmost diffusion layer of the diffusion layer 41a can be integrated with the diffusion layer of the common bus line DN of the bit line pair BT2, BN2 (not shown). Similarly, the leftmost diffusion layer of the diffusion layer 41b can be integrated with the diffusion layer of the common bus line DN of the bit line pair BT3, BN3 (not shown). Therefore, the integrated transistor shape can be enlarged, and the area efficiency can be improved.

  As described above, the layouts of the fourth to sixth embodiments include the diffusion layer 41a in which the switching transistors YT0 and YN0, the precharging transistors PCT0 and PCN0, and the equalizing transistor EQ0 are integrally formed. That is, the diffusion layer 41a included in the precharging transistors PCT0 and PCN0 and the equalizing transistor EQ0 is formed integrally with the diffusion layer 41a included in the switching transistors YT0 and YN0. With such a layout, it becomes possible to arrange the transistors close to the diffusion layer separation. Thereby, the area can be reduced without reducing the gate width W.

  In the layout of FIG. 33, the total number of transistors included in the precharge unit 22 and the Y switch unit 23 (here, the precharge transistors PCT and PCN, the equalize transistor EQ, and the switch transistors YT and YN are five). More than half of the transistors have a gate whose longitudinal direction is the bit line direction. At least one of the precharge unit 22 and the switch unit 23 is repeatedly arranged at a pitch wider than the sense amplifier pitch.

  In the layouts of the first to sixth embodiments, the pitches of the precharge unit 22 and the Y switch unit 23 are different from the SA pitch Psa. The number of repetitions of the precharge unit 22 is different. Here, the number of repetitions of the sense amplifier 12 is twice that of the Y switch unit 23 and the precharge unit 22. Furthermore, it is possible to use a YSW / PRE unit 27 in which the Y switch unit 23 and the precharge unit 22 are integrated.

Embodiment 7 FIG.
A layout according to this embodiment will be described with reference to FIGS. FIG. 33 is a diagram showing a layout of the Y switch unit 23, and FIG. 34 is a diagram showing a layout of the precharge unit 22. In addition, about the content which overlaps with Embodiment 1-6, description is abbreviate | omitted. In the first to sixth embodiments, as shown in FIG. 7, the pitch of the precharge unit 22 and the Y switch unit 23 is double the SA pitch Psa, but in the seventh embodiment, the pitch is shown in FIG. 8. Thus, the layout is such that the pitch of the precharge unit 22 and the Y switch unit 23 is half of the SA pitch Psa.

  FIG. 33 shows a layout of the Y switch unit 23 of the semiconductor memory according to the present embodiment. FIG. 33 shows the Y switch unit 23 in the open bit configuration. Therefore, NMOS pairs 26 are arranged above and below the Y switch unit 23, respectively. That is, the Y switch unit 23 is disposed between the NMOS pairs 26 that are separated in the vertical direction. In FIG. 33, Y switch portions 23 of four bit line pairs are arranged in a region twice the SA pitch Psa. In FIG. 33, the precharge unit 22 is omitted.

  The pair amplification transistors of the bit line pair BT0 and BN0 correspond to the upper left NMOS pair 26, and the pair amplification transistors of the bit line pair BT1 and BN1 correspond to the lower left NMOS pair 26. The pair amplification transistors of the bit line pair BT2 and BN2 correspond to the upper right NMOS pair 26, and the pair amplification transistors of the bit line pair BT3 and BN3 correspond to the lower right NMOS pair 26. Each NMOS pair 26 has the same configuration as that shown in FIG. The layout of the Y switch section 23 in FIG. 33 is the same as the layout in which the layout in FIG. 17 is rotated by 90 °.

  The Y switch unit 23 has four diffusion layers 41a to 41d. Diffusion layers 41a and 41b are arranged in two stages in the left SA pitch Psa. In the right SA pitch Psa, diffusion layers 41c and 41d are arranged in two stages. The upper left diffusion layer 41a and the lower left diffusion layer 41b correspond to the bit line pair BT0, BN0 and the bit line pair BT1, BN1. The upper right diffusion layer 41c and the lower right diffusion layer 41d correspond to the bit line pair BT2, BN2 and the bit line pair BT3, BN3.

  Since the layout is substantially the same between the left SA pitch Psa and the right SA pitch Psa, description of the right SA pitch Psa is omitted. That is, the transistor layout of the bit line pair BT2, BN2 is the same as the transistor layout of the bit line pair BT0, BN0, and the transistor layout of the bit line pair BT3, BN3 is the same as the transistor layout of the bit line pair BT1, BN1. is there.

  In the Y switch unit 23, four gates g1 to g4 are provided. Two gates g1 and g2 are provided in the SA pitch Psa on the left side. Two gates g3 and g4 are arranged in the SA pitch Psa on the right side. The respective gates g1 to g4 are arranged in parallel with the bit line direction. In other words, the gates g1 to g4 are vertical gates along the bit line direction. Each of the gates g1 to g4 has a linear shape whose longitudinal direction is the bit line direction. Therefore, the bit line direction is parallel to the gate width W. Further, the two gates g1 and g2 are arranged apart from each other in the horizontal direction. Here, the two gates g provided in the left SA pitch Psa are identified as the left gate g1 and the right gate g2. The left gate g1 is connected to the column selection signal line Y0, and the right gate g2 is connected to the column selection signal line Y1. The respective gates g1 and g2 are arranged so as to straddle the diffusion layers 41a and 41b. That is, the gates g1 and g2 are formed from the diffusion layer 41a to the diffusion layer 41b.

  The diffusion layer 41a corresponds to the switching transistors YT0 and YT1, and the diffusion layer 41b corresponds to the switching transistors YN0 and YN1. On the left side of the gate g1, the diffusion layer 41a is connected to the bit line BT0, and on the left side of the gate g1, the diffusion layer 41b is connected to the bit line BN0. The diffusion layer 41a is connected to the bit line BT1 on the right side of the gate g2, and the diffusion layer 41b is connected to the bit line BN1 on the right side of the gate g2. Between the gate g1 and the gate g2, the diffusion layer 41a is connected to the common bus line DT. Similarly, the diffusion layer 41b is connected to the common bus line DN between the gate g1 and the gate g2. Therefore, the switching transistors YT0 and YN0 share the gate g1. Similarly, the switching transistors YT1 and YN1 share the gate g2. The switching transistor YT0 and the switching transistor YT1 share the diffusion layer 41a on the common bus line DT side. The switching transistor YN0 and the switching transistor YN1 share the diffusion layer 41a on the common bus line DN side.

  Thus, the left half of the diffusion layers 41a and 41b corresponds to the elements of the bit line pair BT0 and BN0, and the right half corresponds to the elements of the bit line pair BT1 and BN1. Further, the upper and lower switching transistors YT0 and YN0 use a common gate g, and the upper and lower switching transistors YT1 and YN1 use a common gate g. A diffusion layer corresponding to the column selection signal line Y can be shared by the two switching transistors YT and YN arranged in the vertical direction.

  Therefore, since the number of contacts can be reduced, it becomes possible to dispose the transistor close to the diffusion layer separation. Thereby, the area can be reduced without reducing the gate width W. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The Y switch unit 23 is repeatedly arranged at a pitch that is ½ of the SA pitch Psa. Thereby, the layout can be performed efficiently and the area can be reduced.

  Next, the layout of the precharge portion 22 of the semiconductor memory according to the present embodiment will be described with reference to FIG. FIG. 34 is a diagram showing a layout of the precharge unit 22 of the semiconductor memory according to the present embodiment. The layout shown in FIG. 34 has an open bit configuration as in FIG. 33, and shows an area twice the SA pitch Psa. In FIG. 34, precharge portions 22 of four bit line pairs are arranged in a region twice the SA pitch Psa. In this configuration, one SA precharge portion 22 is arranged at a width of ½ of the SA pitch Psa. NMOS pairs 26 are arranged above and below the precharge unit 22, respectively. A precharge unit 22 is disposed between the NMOS pairs 26 spaced in the vertical direction. The arrangement of the NMOS pair 26 is the same as that shown in FIG.

  In an area twice the SA pitch Psa, the transistor layout is mirror-symmetric with a vertical line as an axis. The SA pitch Psa on the left corresponds to the bit line pair BT0, BN0 and the bit line pair BT1, BN1. The SA pitch Psa on the right side corresponds to the bit line pair BT2, BN2 and the bit line pair BT3, BN3. Further, the transistor layout is mirror-symmetrical about the vertical straight line within each of the left and right SA pitches Psa.

  The precharge unit 22 has nine diffusion layers 41a to 41f. Diffusion layers 41a, 41b, 41c and 41e are arranged in the left SA pitch Psa. Diffusion layers 41f, 41g, 41h, 41i are arranged in the right SA pitch Psa. The diffusion layer 41d is disposed over the left and right SA pitch Psa. The diffusion layer 41a and the diffusion layer 41f have a mirror symmetrical layout. The diffusion layer 41b and the diffusion layer 41g have a mirror-symmetric layout. Similarly, the diffusion layer 41c and the diffusion layer 41i have a mirror-symmetric layout, and the diffusion layer 41e and the diffusion layer 41h have a mirror-symmetric layout. The diffusion layer 41d has a mirror-symmetric shape with respect to the boundary line of the left and right SA pitch Psa.

  Four gates g1 to g4 are arranged in a region twice the SA pitch Psa. Each of the gates g1 to g4 is formed in parallel with the bit line direction. In other words, the gates g1 to g4 are vertical gates along the bit line direction. Each of the gates g1 to g4 has a linear shape whose longitudinal direction is the bit line direction. Therefore, the bit line direction is parallel to the gate width W. Further, the four gates g1 to g4 are arranged apart from each other in the horizontal direction. Two gates g1 and g2 are arranged in the left SA pitch Psa, and two gates g3 and g4 are arranged in the right SA pitch Psa.

  The gate g1 is connected to the column selection signal line Y0. The column selection signal line Y0 and the gate g2 are connected to the column selection signal line Y1. The gate g3 is connected to the column selection signal line Y2. The gate g4 is connected to the column selection signal line Y3. Each of the gates g <b> 1 to g <b> 4 is disposed so as to straddle the three diffusion layers 41. For example, the gate g1 is disposed over the diffusion layers 41a, 41b, and 41c. The gate g2 is disposed over the diffusion layers 41d, 41b, and 41e. The gate g3 is disposed over the diffusion layers 41d, 41g, and 41h. The gate g4 is disposed over the diffusion layers 41f, 41g, and 41i.

  The diffusion layer 41a corresponds to the precharging transistor PCN0, and the diffusion layer 41c corresponds to the equalizing transistor EQ0. The diffusion layer 41e corresponds to the equalizing transistor EQ1. The diffusion layer 41b corresponds to the precharging transistors PCT0 and PCN1. In the diffusion layer 41b, the precharging transistors PCT0 and PCN1 share the precharge voltage HVDD. The diffusion layer 41d corresponds to the precharging transistors PCT1 and PCN2. In the diffusion layer 41d, the precharge transistors PCT1 and PCN2 share the precharge voltage HVDD.

  Similarly, the diffusion layer 41h corresponds to the equalizing transistor EQ2, and the diffusion layer 41i corresponds to the equalizing transistor EQ3. The diffusion layer 41f corresponds to the precharging transistor PCT3. The diffusion layer 41g corresponds to the precharging transistors PCT2 and PCN3. In the diffusion layer 41g, the precharging transistors PCT2 and PCN3 share the precharge voltage HVDD. The diffusion layers 41a and 41f may share the precharge voltage HVDD in the SA pitch Psa that is further adjacent to the outside.

  As described above, the gate g having the longitudinal direction in the bit line direction is shared by the precharging transistors PCN and PCT and the equalizing transistor EQ. Therefore, the precharge signal line PDL can be shared by the three precharge transistors PCN and PCT and the equalize transistor EQ arranged in the vertical direction. Since the number of contacts can be reduced, it is possible to dispose the transistor close to the diffusion layer separation. Thereby, the area can be reduced without reducing the gate width W.

  Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The precharge unit 22 is repeatedly arranged at a pitch that is ½ of the SA pitch Psa. Thereby, the layout can be performed efficiently.

(Modification of Embodiment 7)
A layout according to a modification of the seventh embodiment will be described with reference to FIG. FIG. 35 is a diagram showing a layout of a modified example. In FIG. 35, the YSW / PRE unit 27 in which the precharge unit 22 and the Y switch unit 23 are integrated as shown in the fourth to sixth embodiments is provided. Similarly to FIGS. 33 and 34, the YSW / PRE unit 27 is laid out at half of the SA pitch Psa. In FIG. 35, one SA pitch Psa is shown.

  NMOS pairs 26 are arranged above and below the YSW / PRE unit 27, respectively. That is, the YSW / PRE unit 27 is disposed between two NMOS pairs 26 that are spaced apart from each other in the vertical direction. The upper NMOS pair 26 becomes a pair amplification transistor of the bit line pair BT0, BN0, and the lower NMOS pair 26 becomes a pair amplification transistor of the bit line pair BT1, BN1. The configuration of the NMOS pair 26 is the same as that shown in FIG.

  In the YSW / PRE portion 27, upper and lower diffusion layers 41a and 41b are provided. The diffusion layer 41a has a rotationally symmetric layout with respect to the diffusion layer 41b. The transistor layout is also rotationally symmetric. The diffusion layers 41a and 41b are formed wider than the SA pitch Psa. Therefore, the diffusion layers 41a and 41b protrude to the adjacent SA pitch Psa.

  The YSW / PRE unit 27 is provided with four gates g1 to g4. Each of the gates g1 to g4 is formed in parallel with the bit line direction. In other words, the gates g1 to g4 are vertical gates along the bit line direction. Each of the gates g1 to g4 has a linear shape whose longitudinal direction is the bit line direction. Therefore, the bit line direction is parallel to the gate width W. Further, the four gates g1 to g4 are arranged apart from each other in the horizontal direction.

  The gate g1 is connected to the column selection signal line Y0. The gate g2 is connected to the precharge signal line PDL. The gate g3 is connected to the precharge signal line PDL. The gate g4 is connected to the column selection signal line Y1. Each gate g1-g4 is arrange | positioned so that the diffusion layer 41a and the diffusion layer 41b may be straddled. That is, the respective gates g1 to g4 are arranged from the diffusion layer 41a to the diffusion layer 41b.

  The gate g1 corresponds to the switching transistors YT0 and YN0. The gate g4 corresponds to the switching transistors YT1 and YN1. The gate g2 corresponds to the precharging transistors PCN0 and PCT0 and the equalizing transistor EQ0. The gate g3 corresponds to the precharging transistors PCN1 and PCT1 and the equalizing transistor EQ1.

  The diffusion layer 41a corresponds to the switching transistors YT0 and YT1, the precharging transistors PCT0 and PCT1, and the equalizing transistor EQ0. That is, the switching transistors YT0 and YT1, the precharging transistors PCT0 and PCT1, and the equalizing transistor EQ0 share the integrated diffusion layer 41a. The diffusion layer 41b corresponds to the switching transistors YN0 and YN1, the precharging transistors PCN0 and PCN1, and the equalizing transistor EQ1. That is, the switching transistors YN0 and YN1, the precharging transistors PCN0 and PCN1, and the equalizing transistor EQ1 share the integrated diffusion layer 41b.

  On the left side of the gate g1, the diffusion layers 41a and 41b are connected to the common bus line DT. The diffusion layers 41a and 41b of the common bus line DT can be shared with the SA pitch Psa adjacent to the left side. Similarly, the diffusion layers 41a and 41b are connected to the common bus line DN on the right side of the gate g4. The diffusion layers 41a and 41b of the common bus line DN can be shared with the SA pitch Psa adjacent to the right side. Thereby, the element isolation region can be reduced, and the layout can be performed efficiently.

  Between the gate g2 and the gate g3, the diffusion layers 41a and 41b are connected to the precharge voltage HVDD. In the diffusion layer 41a, the precharge transistor PCT0 and the precharge transistor PCN0 share the same precharge voltage HVDD side. Similarly, in the diffusion layer 41b, the precharge transistor PCT1 and the precharge transistor PCN1 share the same precharge voltage HVDD side.

  Between the gate g1 and the gate 2, the diffusion layer 41a is connected to the bit line BT0. A precharging transistor PCT0 and an equalizing transistor EQ0 are arranged in parallel by the gate g2. The three precharging transistors PCT0 and PCN0 and the equalizing transistor EQ0 share one vertical gate g2. As a result, the precharge signal can be shared by the three precharge transistors PCT0 and PCN0 and the equalizing transistor EQ0. An increase in the number of contacts can be prevented, and an increase in area can be suppressed.

  Similarly, the diffusion layer 41b is connected to the bit line BN1 between the gate g3 and the gate g4. A precharging transistor PCN1 and an equalizing transistor EQ1 are arranged in parallel by the gate g3. Therefore, the three precharging transistors PCT1 and PCN1 and the equalizing transistor EQ1 share one vertical gate g3. As a result, the precharge signal can be shared by the three precharge transistors PCT1 and PCN1 and the equalizing transistor EQ1. An increase in area due to an increase in the number of contacts can be suppressed.

The precharge transistor PCT1 and the precharge transistor PCT0 share the diffusion layer 41a on the precharge voltage HVDD side. The precharge transistor PCN1 and the precharge transistor PCN0 share the diffusion layer 41b on the precharge voltage HVDD side. The equalizing transistor EQ0 and the precharging transistor PCT0 share the diffusion layer 41b on the bit line BT0 side. The equalizing transistor EQ1 and the precharging transistor PCN1 share the diffusion layer 41b on the bit line BN1 side. The equalizing transistor EQ0 and the switching transistor YT0 share the diffusion layer 41a on the bit line BT0 side. The equalizing transistor EQ1 and the switching transistor YN1 share the diffusion layer 41b on the bit line BN1 side.
Therefore, an increase in area due to an increase in the number of contacts can be suppressed. Four linear gates g1 to g4 arranged in the SA pitch Psa are arranged. Two SAs can be realized by the transistor arrangement of the four gates g1 to g4. Gates g1 and g2 correspond to Y0, and gates g3 and g4 correspond to Y1. Therefore, one YSW / PRE unit 27 can be realized with 1/2 of the SA pitch Psa. Since the number of contacts can be reduced, it is possible to dispose the transistor close to the diffusion layer separation. Thereby, the area can be reduced without reducing the gate width W.

  Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. Only the linear gate g is used to unify the gate g. Therefore, the layout can be easily stabilized against variations in device manufacturing, and a high yield can be expected. The YSW / PRE unit 27 is repeatedly arranged at a pitch that is ½ of the SA pitch Psa. Thereby, the layout can be performed efficiently.

  Similar to the layouts of FIGS. 33 and 34, the precharge signals between the vertically arranged elements are shared. Therefore, it is possible to minimize the element separation distance. Thereby, an area can be reduced.

  In the seventh embodiment, the total number of transistors included in the precharge unit 22 and the Y switch unit 23 (here, five transistors of the precharge transistors PCT and PCN, the equalizing transistor EQ, and the switching transistors YT and YN) More than half of the transistors have a gate whose longitudinal direction is the bit line direction. In the vertical direction perpendicular to the bit line direction, the SA pitch Psa of the sense amplifier is defined by the widths of the PMOS pair 25 and the NMOS pair 26. In the vertical direction, the sense amplifiers 12 are repeatedly arranged at the SA pitch Psa. At least one of the precharge unit 22 and the Y switch unit 23 is repeatedly arranged at a pitch narrower than the SA pitch Psa. For example, the precharge unit 22 and the Y switch unit 23 are repeatedly arranged at a pitch of 1/2 of the SA pitch Psa.

  In the layouts of FIGS. 32 to 35, the longitudinal direction of the gate g is the bit line direction. In the longitudinal direction of the gate g, the channels of the two transistors are continuously arranged. That is, the gate width direction of the two switching transistors that share the gate g is the longitudinal direction of the gate g. For example, one gate g corresponds to the switching transistors YT0 and YT1, and the channel width direction of the switching transistors YT0 and YT1 is the longitudinal direction of the gate g. Thus, two or more switching transistor channels are continuous in the longitudinal direction of the switching transistor gate. For example, the gate g extending in the bit line direction corresponds to the switching transistor YT0 and the switching transistor YT1. That is, the switching transistor YT0 and the switching transistor YT1 share the gate g. Thereby, the layout can be performed efficiently.

  In the first to seventh embodiments, if the SA pitch Psa is defined by an integral multiple of the memory cell pitch Pcell, in the vertical direction perpendicular to the bit line direction, at least one of the precharge unit 22 and the Y switch unit 23 is SA. It is repeatedly arranged at a pitch different from the pitch Psa. Further, since the pitch of the precharge unit 22 and the Y switch unit 23 is different from the SA pitch Psa, the number of repetitions of the sense amplifier 12 in the horizontal direction and the number of repetitions of the Y switch unit 23 and the precharge unit 22 are different. Is different. Here, the number of repetitions of the sense amplifier 12 is half that of the Y switch unit 23 and the precharge unit 22. Furthermore, it is possible to use a YSW / PRE unit 27 in which the Y switch unit 23 and the precharge unit 22 are integrated.

  In the first to seventh embodiments, the connection wiring for connecting to the gate g and the diffusion layer 41 can be formed without crossing. Therefore, the connection wiring can be formed with only one wiring layer. That is, the number of conversions of the wiring layer can be reduced in the connection wiring formed by a wiring layer different from the gate g.

  In the first to third embodiments, the precharge portion 22 and the Y switch portion 23 are provided in the separated diffusion layer 41. In the present embodiment, the above-described layout may be employed only for the precharge unit 22, and the above-described layout may be employed only for the Y switch unit 23. Of course, the above-described layout may be adopted for both the precharge unit 22 and the Y switch unit 23.

  In the fourth to seventh embodiments, the diffusion layer 41 is integrated with the precharge unit 22 and the Y switch unit 23, and the precharge unit 22 and the Y switch unit 23 are used as the YSW / PRE unit 27. Here, when the gate voltage of the column selection signal line Y is a power supply voltage, the gate voltages of the precharging transistors PCT and PCN and the equalizing transistor EQ may be boosted to be higher than the power supply voltage. In addition, you may use combining the arbitrary layouts in Embodiment 1-7. Similarly, in the modified examples of the respective embodiments, the layouts of the other embodiments and the modified examples can be arbitrarily combined. In addition, among the first to seventh embodiments, the contents described in the other embodiments are omitted as appropriate, but the same effects can be achieved for the same layout as the other embodiments. Of course.

A part or all of the above embodiment can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1)
A memory cell array having a plurality of memory cells;
A plurality of bit line pairs provided corresponding to each column of the memory cell array;
A plurality of sense amplifiers that are provided corresponding to the plurality of bit line pairs and amplify a potential difference between the bit line pairs;
The sense amplifier is
A precharging transistor having a diffusion layer and precharging the bit line pair;
A semiconductor memory comprising: a switching transistor having a diffusion layer formed integrally with the diffusion layer of the precharging transistor and selectively connecting the plurality of bit line pairs to a common bus line.
(Appendix 2)
The semiconductor memory according to appendix 1, wherein the gate of the switching transistor has a longitudinal direction perpendicular to the bit line direction.
(Appendix 3)
An amplifying unit including at least two transistors connected to the bit line pair and amplifying a potential difference between the bit line pair;
In the vertical direction, the sense amplifier pitch of the sense amplifier is defined by the width of the amplification unit,
In the vertical direction, the sense amplifiers are repeatedly arranged at the sense amplifier pitch,
The semiconductor memory according to appendix 2, wherein a gate of the switching transistor extends to the adjacent sense amplifier pitch.
(Appendix 4)
The gate of the precharging transistor has the vertical direction as a longitudinal direction;
4. The semiconductor memory according to appendix 3, wherein the gate of the precharging transistor extends to the adjacent sense amplifier pitch.
(Appendix 5)
The precharging transistor includes an equalizing transistor for equalizing the bit line pair,
The semiconductor memory according to appendix 2, wherein a diffusion layer to which the bit line in the equalizing transistor is connected and a diffusion layer to which the bit line in the switching transistor is connected are common.
(Appendix 6)
The precharging transistor includes an equalizing transistor that equalizes the bit line pair and a fixing transistor that is fixed to a precharge potential.
The semiconductor memory according to appendix 2, wherein a diffusion layer to which the bit line in the equalizing transistor is connected and a diffusion layer to which the bit line in the fixing transistor is connected are common.
(Appendix 7)
4. The semiconductor memory according to appendix 3, wherein the diffusion layer extends to the adjacent sense amplifier pitch.
(Appendix 8)
The semiconductor memory according to appendix 7, wherein the diffusion layer is integrally formed in the two sense amplifiers adjacent in the vertical direction.
(Appendix 9)
9. The semiconductor memory according to appendix 8, wherein the common bus line is commonly connected to the diffusion layer in the two sense amplifiers adjacent in the vertical direction.
(Appendix 10)
A plurality of the sense amplifiers share the common bus line,
By selectively turning on the switching transistors of the plurality of sense amplifiers, one bit line pair of the plurality of bit line pairs is connected to the common bus line, thereby performing column selection.
The column addresses of the columns located on both sides of the adjacent I / O boundary column are the same,
The semiconductor memory according to appendix 2, wherein a gate of the switching transistor is formed across a boundary between the adjacent I / Os.
(Appendix 11)
The semiconductor memory according to claim 1, wherein the gate of the switching transistor has a bit line direction as a longitudinal direction.
(Appendix 12)
The precharging transistor includes an equalizing transistor for equalizing the bit line pair,
12. The semiconductor memory according to appendix 11, wherein the diffusion layer is shared by the bit line side of the equalizing transistor and the bit line side of the switching transistor.
(Appendix 13)
The precharging transistor includes an equalizing transistor that equalizes the bit line pair and a fixing transistor that is fixed to a precharge potential.
12. The semiconductor memory according to appendix 11, wherein the diffusion layer is shared by the bit line side of the equalizing transistor and the bit line side of the fixing transistor.
(Appendix 14)
The semiconductor memory according to appendix 1, wherein a gate voltage of the precharge transistor is equal to or higher than a gate voltage of the switch transistor.
(Appendix 15)
A memory cell array having a plurality of memory cells;
A plurality of bit line pairs provided corresponding to each column of the memory cell array;
An amplifier unit that is provided corresponding to each of the plurality of bit line pairs, amplifies a potential difference between the bit line pairs, a switch unit that switches connection between the bit line pairs and the data bus lines, and a pre-set of the bit line pairs. A plurality of sense amplifiers including a precharge unit for charging,
The plurality of sense amplifiers are arranged in a vertical direction perpendicular to the extending direction of the bit lines,
The number of repetitions of the layout pattern of the amplifier unit of the plurality of sense amplifiers arranged in the vertical direction, and the layout pattern of the switch unit or the precharge unit of the plurality of sense amplifiers arranged in the vertical direction A semiconductor memory characterized in that the number of repetitions is different.

(Appendix 16)
The gate of the switch transistor constituting the switch section has the vertical direction as a longitudinal direction, and extends to the adjacent sense amplifier pitch with respect to the sense amplifier pitch defined by the width of the amplifier section. The semiconductor memory according to appendix 15.
(Appendix 17)
The gate of the precharging transistor constituting the precharging unit has the vertical direction as a longitudinal direction,
18. The semiconductor memory according to appendix 16, wherein the gate of the precharging transistor extends to the adjacent sense amplifier pitch.
(Appendix 18)
16. The semiconductor memory according to appendix 15, wherein the precharge transistor constituting the precharge portion and the switch transistor constituting the switch portion share a diffusion layer.
(Appendix 19)
A memory cell array having a plurality of memory cells;
A plurality of bit line pairs provided corresponding to each column of the memory cell array;
A plurality of amplification transistors provided corresponding to the plurality of bit line pairs, for amplifying a potential difference between the bit line pairs; and a switching transistor for selectively connecting the plurality of bit line pairs to a common bus line. ,
A semiconductor memory in which a channel width direction of two or more switching transistors having a common gate is a longitudinal direction of the gate.
(Appendix 20)
A vertical direction perpendicular to the bit line direction of the gate is a longitudinal direction,
Item 20. The semiconductor memory according to appendix 19, wherein, at a boundary portion between adjacent I / Os, the switching transistor shares the gate with the switching transistor of an adjacent I / O.
(Appendix 21)
The semiconductor memory according to any one of appendices 16 to 18, wherein at least one of the precharge unit and the switch unit is repeatedly arranged at a pitch wider than a sense amplifier pitch defined by the width of the amplifier unit. .
(Appendix 22)
A memory cell array having a plurality of memory cells;
A plurality of bit line pairs provided corresponding to each column of the memory cell array;
A plurality of sense amplifiers that are provided corresponding to the plurality of bit line pairs and amplify a potential difference between the bit line pairs;
The sense amplifier is
An amplifier section having a pair amplification transistor connected to the bit line pair;
A precharge unit having one or more precharge transistors for precharging the bit line pair;
A switch unit having one or more switching transistors for selectively connecting a plurality of bit line pairs to a common bus line,
More than half of the total number of transistors included in the precharge portion and the switch portion have a gate whose longitudinal direction is the bit line direction,
In the vertical direction perpendicular to the bit line direction, the sense amplifier pitch of the sense amplifier is defined by the width of the pair amplification transistor,
In the vertical direction, the amplifier unit is repeatedly arranged at the sense amplifier pitch,
A semiconductor memory in which at least one of the precharge unit and the switch unit is repeatedly arranged at a pitch different from the sense amplifier pitch.
(Appendix 23)
23. The semiconductor memory according to appendix 22, wherein at least one of the precharge unit and the switch unit is repeatedly arranged at a pitch narrower than the sense amplifier pitch.
(Appendix 24)
A memory cell array having a plurality of memory cells;
A plurality of bit line pairs provided corresponding to each column of the memory cell array;
A plurality of sense amplifiers that are provided corresponding to the plurality of bit line pairs and amplify a potential difference between the bit line pairs;
The sense amplifier is
An amplifier section having a pair amplification transistor connected to the bit line pair;
A precharge unit having one or more precharge transistors for precharging the bit line pair;
A switch unit having one or more switching transistors for selectively connecting a plurality of bit line pairs to a common bus line,
In the vertical direction perpendicular to the bit line direction, the sense amplifier pitch of the sense amplifier, which is an integral multiple of the pitch of the memory cells, is defined by the width of the pair amplification transistor,
In the vertical direction, the amplifier unit is repeatedly arranged at the sense amplifier pitch,
A semiconductor memory in which at least one of the precharge unit and the switch unit is repeatedly arranged at a pitch different from the sense amplifier pitch in the vertical direction.
(Appendix 25)
A memory cell array having a plurality of memory cells;
A plurality of bit line pairs provided corresponding to each column of the memory cell array;
A plurality of sense amplifiers that are provided corresponding to the plurality of bit line pairs and amplify a potential difference between the bit line pairs;
The sense amplifier is
An amplifier section having a pair amplification transistor connected to the bit line pair;
A precharge unit having one or more precharge transistors for precharging the bit line pair;
A switch unit having one or more switching transistors for selectively connecting a plurality of bit line pairs to a common bus line,
In the vertical direction perpendicular to the bit line direction, the sense amplifier pitch of the sense amplifier is defined by the width of the pair amplification transistor,
In the vertical direction, the amplifier unit is repeatedly arranged at the sense amplifier pitch,
In the vertical direction, the precharge unit and the switch unit are repeatedly arranged,
A semiconductor memory in which the number of repetitions of at least one of the precharge unit and the switch unit is different from the number of repetitions of the amplifier unit.
(Appendix 26)
24. The semiconductor memory according to any one of appendices 19 to 23, wherein the precharge transistor and the switching transistor share a diffusion layer.
(Appendix 27)
24. The semiconductor memory according to any one of appendices 18 to 23, wherein the diffusion layer extends to the adjacent sense amplifier pitch.
(Appendix 28)
28. The semiconductor memory according to appendix 27, wherein in the two sense amplifiers adjacent in the vertical direction perpendicular to the bit line direction, the diffusion layer is integrally formed.
(Appendix 29)
29. The semiconductor memory according to appendix 28, wherein a common bus line is commonly connected to the diffusion layer in the two sense amplifiers adjacent in the vertical direction.
(Appendix 30)
The gate of the switching transistor has a longitudinal direction as a longitudinal direction perpendicular to the bit line direction,
30. The semiconductor memory according to any one of appendices 19 to 29, wherein a gate of the switching transistor extends to an adjacent sense amplifier pitch.
(Appendix 31)
The gate of the precharging transistor has a vertical direction perpendicular to the bit line direction as a longitudinal direction,
31. The semiconductor memory according to any one of appendices 19 to 30, wherein a gate of the precharging transistor extends to an adjacent sense amplifier pitch.
(Appendix 32)
The precharging transistor includes an equalizing transistor that equalizes the bit line pair.
32. The semiconductor memory according to any one of appendices 15 to 31, wherein a diffusion layer is shared between the bit line side of the equalizing transistor and the bit line side of the switching transistor.
(Appendix 33)
The precharging transistor includes an equalizing transistor that equalizes the bit line pair and a fixing transistor that is fixed to the precharge potential.
33. The semiconductor memory according to any one of appendices 15 to 32, wherein a diffusion layer is shared between the bit line side of the equalizing transistor and the bit line side of the fixing transistor.
(Appendix 34)
34. The semiconductor memory according to any one of appendices 15 to 33, wherein the precharge portion is repeatedly arranged at a pitch that is approximately twice or approximately half the sense amplifier pitch.
(Appendix 35)
35. The semiconductor memory according to any one of appendices 15 to 34, wherein the switch unit is repeatedly arranged at a pitch that is approximately twice or approximately half the sense amplifier pitch.
(Appendix 36)
Multiple sense amplifiers share a common bus line,
By selectively turning on the switching transistors of the plurality of sense amplifiers, one bit line pair among the plurality of bit line pairs is connected to the common bus line, thereby performing column selection,
The column addresses of the columns located on both sides of the adjacent I / O boundary column are the same,
34. The semiconductor memory according to any one of appendices 1 to 35, wherein a gate of the switching transistor is formed across a boundary between the adjacent I / Os.
(Appendix 37)
37. The semiconductor memory according to any one of appendices 1 to 36, wherein a gate voltage of the precharging transistor is equal to or higher than a gate voltage of the switching transistor.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

10 memory cell array 11 memory cell 12 sense amplifier 13 latch FF
14 YSW / PRE
DESCRIPTION OF SYMBOLS 15 Transfer switch 21 Amplifier part 22 Precharge part 23 Y switch part 25 PMOS pair 26 NMOS pair 27 YSW / PRE part 41 Diffusion layer 411 Extension part 412 Extension part 413 Narrow part 414 Wide part 415 Narrow part 416 Wide part BT bit line BN bit line Y, Y0 to Y3 Column selection signal line (column address)
BL, BT0 to BT3, BN0 to BN3 Bit line WL Word line DT Common bus line DN Common bus line YT Switch transistor YN Switch transistor PCT Precharge transistor PCN Precharge transistor EQ Equalize transistor SPT Amplification PMOS transistor SPN Amplifying PMOS transistor SNT Amplifying NMOS transistor SNN Amplifying NMOS transistor PDL Precharge signal line g Gate

Claims (18)

A memory cell array having a plurality of memory cells;
A plurality of bit line pairs provided corresponding to each column of the memory cell array;
A plurality of sense amplifiers that are provided corresponding to the plurality of bit line pairs and amplify a potential difference between the bit line pairs;
The sense amplifier is
An amplifier section having a pair amplification transistor connected to the bit line pair;
A precharge unit having one or more precharge transistors for precharging the bit line pair;
A switch unit having one or more switching transistors for selectively connecting a plurality of bit line pairs to a common bus line,
More than half of the total number of transistors included in the precharge portion and the switch portion have a gate whose longitudinal direction is the bit line direction,
In the vertical direction perpendicular to the bit line direction, the sense amplifier pitch of the sense amplifier is defined by the width of the pair amplification transistor,
In the vertical direction, the amplifier unit is repeatedly arranged at the sense amplifier pitch,
A semiconductor memory in which at least one of the precharge unit and the switch unit is repeatedly arranged at a pitch different from the sense amplifier pitch. The semiconductor memory according to claim 1, wherein at least one of the precharge unit and the switch unit is repeatedly arranged at a pitch narrower than the sense amplifier pitch. A memory cell array having a plurality of memory cells;
A plurality of bit line pairs provided corresponding to each column of the memory cell array;
A plurality of sense amplifiers that are provided corresponding to the plurality of bit line pairs and amplify a potential difference between the bit line pairs;
The sense amplifier is
An amplifier section having a pair amplification transistor connected to the bit line pair;
A precharge unit having one or more precharge transistors for precharging the bit line pair;
A switch unit having one or more switching transistors for selectively connecting a plurality of bit line pairs to a common bus line,
In the vertical direction perpendicular to the bit line direction, the sense amplifier pitch of the sense amplifier is defined by the width of the pair amplification transistor,
In the vertical direction, the amplifier unit is repeatedly arranged at the sense amplifier pitch,
In the vertical direction, the precharge unit and the switch unit are repeatedly arranged,
A semiconductor memory in which the number of repetitions of at least one of the precharge unit and the switch unit is different from the number of repetitions of the amplifier unit.   4. The semiconductor memory according to claim 1, wherein a sense amplifier pitch of the sense amplifier defined in the vertical direction is an integral multiple of a pitch of the memory cells.   4. The semiconductor memory according to claim 1, wherein a diffusion layer is shared by the precharging transistor and the switching transistor.   6. The semiconductor memory according to claim 5, wherein the diffusion layer extends to the adjacent sense amplifier pitch.   The semiconductor memory according to claim 6, wherein the diffusion layer is integrally formed in two sense amplifiers adjacent in a vertical direction perpendicular to the bit line direction.   The semiconductor memory according to claim 7, wherein a common bus line is commonly connected to the diffusion layer in the two sense amplifiers adjacent in the vertical direction. The gate of the switching transistor has a longitudinal direction as a longitudinal direction perpendicular to the bit line direction,
4. The semiconductor memory according to claim 1, wherein a gate of the switching transistor extends to an adjacent sense amplifier pitch. The gate of the precharging transistor has a vertical direction perpendicular to the bit line direction as a longitudinal direction,
4. The semiconductor memory according to claim 1, wherein a gate of the precharging transistor extends to an adjacent sense amplifier pitch. The precharging transistor includes an equalizing transistor that equalizes the bit line pair.
4. The semiconductor memory according to claim 1, wherein a diffusion layer is shared between the bit line side of the equalizing transistor and the bit line side of the switching transistor. The precharging transistor includes an equalizing transistor that equalizes the bit line pair and a fixing transistor that is fixed to the precharge potential.
4. The semiconductor memory according to claim 1, wherein a diffusion layer is shared between the bit line side of the equalizing transistor and the bit line side of the fixing transistor. 4. The semiconductor memory according to claim 1, wherein the precharge portions are repeatedly arranged at a pitch that is approximately twice or half the sense amplifier pitch. 4. The semiconductor memory according to claim 1, wherein the switch portions are repeatedly arranged at a pitch that is approximately twice or half the sense amplifier pitch. Multiple sense amplifiers share a common bus line,
By selectively turning on the switching transistors of the plurality of sense amplifiers, one bit line pair among the plurality of bit line pairs is connected to the common bus line, thereby performing column selection,
The column addresses of the columns located on both sides of the adjacent I / O boundary column are the same,
4. The semiconductor memory according to claim 1, wherein a gate of the switching transistor is formed across a boundary between the adjacent I / Os. 4. The semiconductor memory according to claim 1, wherein a gate voltage of the precharging transistor is equal to or higher than a gate voltage of the switching transistor. _ The plurality of bit line pairs have first and second bit line pairs;
The sense amplifier includes a first sense amplifier corresponding to the first bit line pair, and a second sense amplifier corresponding to the second bit line pair;
3. The semiconductor memory according to claim 2, wherein switch portions of the first and second sense amplifiers are arranged at the sense amplifier pitch. The plurality of bit line pairs have first and second bit line pairs;
The sense amplifier includes a first sense amplifier corresponding to the first bit line pair, and a second sense amplifier corresponding to the second bit line pair;
3. The semiconductor memory according to claim 2, wherein precharge portions of the first and second sense amplifiers are arranged at the sense amplifier pitch.

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