JP2010061760A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device achieving high speed operation and low power consumption. <P>SOLUTION: For example, a DRAM includes sense amplifier outside bit lines BL0T and BL0B connected to a memory cell, sense amplifier inside bit lines BIT and BIB connected to a sense amplifier, and a transfer gate which connects and separates BL0T and BL0B to and from BIT and BIB in accordance with a transfer gate control signal TG0. When a word line WL is activated (ACT), memory cell information is amplified by the sense amplifier, and TG0 is then deactivated, to separate BL0T and BL0B from BIT and BIB, thereby inactivating the sense amplifier. In reading (RD), TG0 is activated to activate the sense amplifier using common source lines CSP and CSN to perform read from the sense amplifier, and thereafter, TG0 and the sense amplifier are deactivated again. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a technique that is useful when applied to a semiconductor memory device such as a DRAM for portable equipment that requires low power supply voltage, high-speed operation, and low power consumption.

  For example, in a DRAM (Dynamic Random Access Memory), it is necessary to lower the power supply voltage in order to maintain miniaturization and maintain the reliability of internal elements. In particular, in DRAMs for portable devices, it is necessary to lower the power supply voltage to reduce power consumption during operation and in a self-refresh state.

  FIG. 19 is a circuit diagram showing a configuration example of the sense amplifier SA in the conventional semiconductor memory device studied as a premise of the present invention. The sense amplifier SA includes a precharge circuit PCC, a cross couple CC, a read / write port (column switch) IOP, and a transfer gate TGC. FIG. 20 is an operation waveform diagram showing an operation example of FIG. In the memory array in the standby state, in the precharge circuit PCC, the bit line precharge signal PC is activated to the power supply voltage VPP at a boost level higher than the power supply voltage VCC, and the paired bit lines BL0T and BL0B are equalized. And precharged to the bit line precharge level. Normally, the power supply voltage VDL as the bit line voltage is set to the same level as the power supply voltage VCC from the outside of the chip or a level obtained by stepping down the same. The bit line precharge level is set to this midpoint (VDL / 2). At this time, the transfer gate TGC is turned on because both the transfer gate control signals TG0 and TG1 are at the VPP level, and the pair of sense amplifier internal bit lines BIT and BIB and the pair of sense amplifier external bit lines (BL0T, BL0B and BL1T, BL1B) are all precharged to VDL / 2.

  When an activate command (ACT) is input from the outside of the chip, the PC is deactivated to 0 V, the precharge is released, and TG1 is deactivated, and the upper memory array in FIG. Disconnected. Further, local I / O lines LIOT and LIOB are precharged from VDL / 2 level to power supply voltage VCL at the peripheral circuit voltage level. Thereafter, word line WL is activated to VPP level, and a signal is generated on bit line BL0T and sense amplifier internal bit line BIT. Subsequently, in the sense amplifier, the N-side common source line CSN is driven from VDL / 2 to 0 V, and the P-side common source line CSP is driven from VDL / 2 to VDL. Then, the potential difference between the sense amplifier internal bit lines BIT and BIB and the sense amplifier external bit lines BL0T and BL0B is amplified, and BL0T becomes VDL and BL0B becomes 0V as shown in FIG.

  Thereafter, when a read command (RD) is input, the column selection line YS is activated to the VCL level, and when the read / write port (column switch) IOP is turned on, a potential difference is generated between the local I / O lines LIOT and LIOB. This is transmitted to the main amplifier through main I / O lines MIOT and MIOB (not shown), amplified to the VCL level amplitude, and then output to the outside of the chip.

In relation to such a circuit configuration around the sense amplifier SA, for example, in Patent Document 1 (Japanese Patent Laid-Open No. 2000-251474), a subthreshold leak that flows from a VDL memory cell to a VSS bit line during active standby is disclosed. Techniques for reducing are shown. Specifically, two cross couples are prepared on both sides of the transfer gate, the transfer gate is cut during active standby, the cross couple (sense amplifier) on the bit line side is deactivated, and the bit line is pre-charged to VDL / 2. Charge. At this time, the memory cell information is held by the other activated cross couple (latch circuit). Further, for example, Patent Document 2 (Japanese Patent Laid-Open No. 8-241594) discloses a method for writing a voltage (VDL / 3) smaller than VDL in a memory cell at high speed. Specifically, the transfer gate controlled by ΦT is arranged between the sense amplifier internal bit line and the sense amplifier external bit line, and the transfer gate controlled by ΦS is arranged between the sense amplifier internal bit line and the gate terminal of the cross couple. Place between. During the sensing operation, ΦT is turned off and the sense amplifier is once amplified to VDL, then ΦS is turned off and ΦT is connected to VDL / 3 while the gate terminal of the sense amplifier is kept at VDL.
JP 2000-251474 A JP-A-8-241594

  For example, in a DRAM or the like, there is a problem that when the write voltage to the memory cell, that is, the power supply voltage of the sense amplifier is lowered, the time for the sense amplifier to amplify a minute signal read from the memory cell becomes long. In order to avoid this, it is effective to lower the threshold value of the MOS transistor constituting the cross couple in the sense amplifier, but the current consumption in the active standby (in the state where data is held in the sense amplifier) increases. There's a problem.

Specifically, in FIG. 19, the currents flowing through the NMOS transistors M1 and M2 in the cross couple CC are I _L1 and I _L2 . FIG. 21 will be described with the total of I _L1 and I _L2 of the entire sense amplifiers (for example, 128k) activated in the entire chip being I _L. In FIG. 21, a leak current I _LS is an I _L that flows in an active standby state (Active-Standby) after a peak current flows during a sensing operation after receiving an ACT command. Since this is a subthreshold current of the MOS transistor, it rapidly increases when the threshold V _{T of the} MOS transistor is lowered. Here, the threshold V _T of the MOS transistor is defined as a gate-source voltage at which a drain current flows 100 nA / μm when 0.8 V is applied between the drain and the source at 25 ° C.

FIG. 21 shows the relationship between I _LS and the threshold values V _T of M1 and M2 when the power supply voltage VDL is lowered to 0.8V. If V _T is equal to or higher than 0.4V, the leakage current of the NMOS transistors M1, M2 are small, are determined overall leakage current leakage current of the PMOS transistor M3, M4. On the other hand, the entire chip of total reducing a leak current _{V T} until 0.3V is reached 300 .mu.A, rapidly increased since. If specifications of the leak current in the active standby as DRAM for mobile devices is tight, because the order of 300μA is considered the limit value of the leakage current in the sense amplifier, the lower limit value of V _T of the NMOS transistor in the cross-couple 0 .3V.

FIG. 22 shows the relationship between the sense time t _S and the threshold values V _T of M1 and M2. The sense time is defined in that the potential difference between the bit lines is amplified to 60% of VDL from the start of sensing. The sense time exceeds 10 ns at the point of V _T = 0.35 V obtained by adding 0.05 V to the threshold value of 0.3 V. In order to satisfy the specifications of a normal DRAM, the sense time needs to be 3 to 4 ns or less, but this cannot be satisfied. Therefore, it is very important to realize a sense amplifier system that achieves both high speed operation and low standby current when the power supply voltage is lowered to 0.8V. Under such circumstances, the methods of Patent Document 1 and Patent Document 2 described above do not attempt to reduce the leakage current of the sense amplifier (cross couple) in the active standby state, and it is difficult to save power.

  The present invention has been made in view of the above, and the above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of a typical embodiment will be briefly described as follows. The memory array voltage in the DRAM is lowered to, for example, 1 V or less, and the threshold voltage of the MOS transistors constituting the sense amplifier cross-couple is lowered to, for example, about 0.1 V, and the threshold voltage is reduced. The current consumption in the sense amplifier is not increased significantly by lowering. In other words, in order to reduce the leakage current when the word line is activated (active standby), after sensing the signal and amplifying the bit line, the transfer gate provided between the bit line and the sense amplifier is turned off, After separating the line from the sense amplifier, the sense amplifier is deactivated. At this time, the memory cell information is held by the bit line. When reading or writing is performed, the transfer gate is turned on, the bit line and the sense amplifier are connected, and then the sense amplifier is activated.

  The effects obtained by the typical embodiments of the invention disclosed in this application will be briefly described. A semiconductor memory device capable of saving power while maintaining high-speed operation can be realized. Specifically, for example, the leakage current can be reduced to 300 μA or less during operation with a memory array voltage of 1 V or less, and the sense time can be suppressed to about 3 ns.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. In the drawings, the PMOS transistor is distinguished from the NMOS transistor by adding an arrow symbol to the gate. Further, in the drawing, the connection of the substrate potential of the MOS transistor is not specified, but the connection method is not particularly limited as long as the MOS transistor can operate normally. Further, in the following embodiments, a MOS (Metal Oxide Semiconductor) transistor is used as an example of a MIS (Metal Insulator Semiconductor) transistor.

FIG. 1 is a circuit diagram showing a configuration example of a sense amplifier when a folded bit line array is used in a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of a sense amplifier when an open bit line array is used in the semiconductor memory device according to the embodiment of the present invention. As shown in FIG. 1, when the folded bit line array is used, the sense amplifier SA has a circuit configuration similar to that of the sense amplifier shown in FIG. 19, but the NMOS transistors M1 and M2 constituting the cross-coupled LVTCC and The threshold voltage V _T of the PMOS transistors M3 and M4 is lowered to about 0.1V. Here, _{V T} of the MOS transistor, the drain in the same way 25 ° C. and described in FIG. 19 or the like - is defined as the source voltage - drain current 100 nA / [mu] m through gate when applying the 0.8V between the source . When the lower bit lines BL0T and BL0B of the sense amplifier SA are selected, the transfer gate control signal TG1 is deactivated to 0 V in order to deactivate the upper transfer gate TGC, and the upper bit line BL1T is deactivated. , BL1B are separated. A signal is generated on either bit line BL0T or BL0B, and these bit lines are amplified as a pair.

On the other hand, the sense amplifier SA in the case of using an open bit line array, as with FIG. 1, 0.1 V threshold _{V T} of the NMOS transistors M1, M2 and the PMOS transistor M3, M4 constituting the cross-coupled LVTCC It is characterized by being lowered to the extent. In the sense amplifier SA, a signal is generated on the lower bit line BL0T or the upper bit line BL0B. A general open-type bit line array sense amplifier does not require a transfer gate TGC for separating these bit lines and the sense amplifier, but this embodiment is also characterized in that they are provided. Since the upper and lower transfer gates TGC are simultaneously activated and deactivated, both are controlled by the transfer gate control signal TG0.

  FIG. 3 is a waveform diagram showing an operation example of the sense amplifier of FIGS. 1 and 2. The sense amplifier of FIG. 1 and the sense amplifier of FIG. However, since TG1 does not exist in the open-type bit line array sense amplifier of FIG. 2, it is ignored. 3, in the memory array in the standby state, in the precharge circuit PCC, the bit line precharge signal PC is activated to the power supply voltage VPP at a boost level higher than the power supply voltage VCC, and the paired bit lines BL0T, BL0B is equalized and precharged to the bit line precharge level. Normally, the power supply voltage VDL as the bit line voltage is set to the same level as the power supply voltage VCC from the outside of the chip or a level obtained by stepping down the same. The bit line precharge level is set to this midpoint (VDL / 2). At this time, since both the transfer gates TGC are at the VPP level and are in the ON state, the sense amplifier internal bit line pair BIT, BIB and the sense amplifier external bit line pairs (BL0T, BL0B and BL1T, BL1B) are all present. Precharged to VDL / 2.

  When an activate command (ACT) is input from the outside of the chip, the PC is deactivated to 0 V, the precharge is released, and TG1 is deactivated, and the upper memory array in FIG. Disconnected. Further, local I / O lines LIOT and LIOB are precharged from VDL / 2 level to power supply voltage VCL at the peripheral circuit voltage level. Thereafter, word line WL is activated to VPP level, and a signal is generated on sense amplifier external bit line BL0T and sense amplifier internal bit line BIT. Subsequently, in the sense amplifier SA, the N-side common source line CSN is driven from VDL / 2 to 0 V, and the P-side common source line CSP is driven from VDL / 2 to VDL. Then, the potential difference between the complementary bit lines is amplified in the sense amplifier internal bit lines BIT and BIB and the sense amplifier external bit lines BL0T and BL0B, and BL0T becomes VDL and BL0B becomes 0V as shown in FIG.

In the sense amplifier SA in FIG. 1 and FIG. 2, down since the lower the threshold _{V T} of the MOS transistors constituting the cross-coupled LVTCC about 0.1 V, the VDL as shown in FIG. 22 to 0.8V However, there is a feature that high-speed sensing of about 3 ns is possible. Further, when it lowered the threshold V _T of the MOS transistors constituting the cross-coupled LVTCC, it can be reduced than other peripheral circuits channel impurity amount. For this reason, there is an advantage that variation in threshold value due to variation in impurity amount can be reduced. If the variation in threshold value is small, the power supply voltage can be further reduced.

Subsequently, in the sense amplifier SA of FIGS. 1 and 2, in the subsequent active standby state (Active-Standby), the transfer gate control signal TG0 is lowered, and the sense amplifier internal bit lines BIT and BIB and the sense amplifier external bit line BL0T. , BL0B are separated. As a result, information (power supply voltage VDL or ground voltage VSS) is dynamically held in the sense amplifier external bit lines BL0T, BL0B and the storage node of the memory cell. Thereafter, when driving of CSN and CSP is stopped (for example, when sense amplifier enable signals SAP1B and SAN in the CS line driver CSD in FIG. 14 and the like to be described later are deactivated), a low threshold MOS transistor constituting the cross couple LVTCC CSN, CSP and BIT, BIB rapidly approach VDL / 2 due to the leakage current. CSN, becomes the CSP and BIT, BIB approximately VDL / 2, no leak current flows, the leakage current _{I LS} in active standby state is negligibly small.

Note that when CSN and CSP become VDL / 2, there is a concern about leakage current in the CS line driver CSD of FIG. 14 and the like to be described later. However, MOS transistors constituting the CSD have a standard V _T (eg, 0.3 V or more). ), There is no particular problem. Further, for example, CSN and CSP may be driven to VDL / 2 by using a CS line precharge circuit SEQ shown in FIG. 14 and the like which will be described later. However, the control becomes complicated and excessive current associated with this precharge is also consumed. Therefore, it is sufficient to deactivate the sense amplifier enable signals SAP1B and SAN and open the CSN and CSP.

  As described above, when the sense amplifier SA according to the present embodiment is used, it is possible to realize a high-speed sensing operation even when the power supply voltage (VDL) is lowered, and at the same time, to realize a small active standby current in the entire chip. . In addition, the MOS transistor constituting the driver for driving CSN and CSP has a larger amount of channel impurities to increase the threshold value than the MOS transistor constituting the cross-coupled LVTCC. Then, the threshold variation due to the impurity amount variation is larger than that of the cross-coupled LVTCC. However, since the gate voltage is driven by the power supply voltage in the driver, the influence of the threshold variation on the circuit operation is small. Absent.

  Next, the read operation will be described. When the read command (RD) is input, the transfer gate control signal TG0 is activated again, and the sense amplifier internal bit lines BIT and BIB and the sense amplifier external bit lines BL0T and BL0B are connected. Then, a potential difference occurs between the sense amplifier internal bit lines BIT and BIB due to the electric charge flowing from the sense amplifier external bit lines BL0T and BL0B. Since the sense amplifier external bit lines BL0T and BL0B have a large parasitic capacitance, this potential difference is more than half of VDL. Therefore, when the N-side common source line CSN is driven from VDL / 2 to 0 V and the P-side common source line CSP is driven from VDL / 2 to VDL, the potential difference is amplified at high speed. Subsequently, when the column selection line YS is activated to the VCL level and the read / write port (column switch) IOP is turned on, a potential difference is generated between the local I / O lines LIOT and LIOB. This is transmitted to the main amplifier via main I / O lines MIOT and MIOB (not shown), amplified to the VCL amplitude, and then output to the outside of the chip. At the time of reading, the LIOT and LIOB are driven by the NMOS transistors M1 and M2 constituting the cross-coupled LVTCC. However, since the driving power is increased by reducing the threshold of these MOS transistors, the sense amplifier power supply voltage (VDL) is Even if it becomes low, high-speed reading becomes possible.

  Thereafter, after the column selection line YS is deactivated, the transfer gate control signal TG0 is again lowered in the active standby state (Active-Standby), and the sense amplifier internal bit lines BIT, BIB and the sense amplifier external bit lines BL0T, BL0B And the N-side common source line CSN is returned from 0 V to VDL / 2, the P-side common source line CSP is returned from VDL to VDL / 2, and the leakage current of the cross-coupled LVTCC is cut off. Therefore, in the sense amplifier of this embodiment, even if the power supply voltage is reduced, it is possible to realize high-speed data reading and at the same time to realize a small active standby current in the entire chip.

  The write operation is not shown, but the control of the memory array is the same. TG0, CSN, and CSP are activated before the column selection line YS is activated, and then data is written from the LIOT and LIOB to the sense amplifier internal bit lines BIT and BIB and the sense amplifier external bit lines BL0T and BL0B. Is called. In particular, when writing inverted data, TG0, CSN, and CSP are deactivated after waiting for a sufficient time for the storage node of the memory cell to sufficiently invert.

  After the precharge command (PRE) is input, the word line WL is deactivated, the precharge signal PC and the transfer gate control signals TG0 and TG1 are activated, and the sense amplifier external bit lines (BL0T, BL0B and BL1T, BL1B) is equalized and recharged to VDL / 2. Further, the local I / O lines LIOT and LIOB are also restored from VCL to VDL / 2.

  In the above operation, the memory cell information is dynamically held by the charge on the external bit line of the sense amplifier. Therefore, if there is a leakage current path in this bit line, the bit line amplitude decreases and the information is destroyed. There is a fear. FIG. 4 is a cross-sectional view showing a configuration example around the memory cell in the semiconductor memory device according to the embodiment of the present invention, and shows an example of a leak current path of the bit line.

As shown in FIG. 4, each DRAM memory cell has an NMOS transistor (memory cell transistor) formed on a semiconductor substrate (P well) PW and a stack capacitor formed on the bit line BL. It has become. In FIG. 4, two word lines WL are arranged on the active region AT in the semiconductor substrate PW separated by the insulating film SiO ₂ , and the two word lines WL are used as the gates of the memory cell transistors. An N type diffusion layer region N to be a source / drain is formed in the semiconductor substrate PW.

  A contact CB is disposed on the N-type diffusion layer region N between the two word lines WL, and a bit line contact BC is disposed thereon. A bit line BL formed in a direction orthogonal to the extending direction of the word line is disposed on the bit line contact BC. On the other hand, a contact CB is disposed on each of the N-type diffusion layer regions N outside the two word lines WL, and a storage node contact SC is disposed thereon. A concave (cylinder-shaped) storage node SN formed on the inner wall of a hole in an interlayer insulating film (not shown) is disposed above the storage node contact SC, and a plate electrode PL is embedded inside the storage node SN. These constitute the capacitor Cs with the capacitive insulating film CI interposed therebetween. FIG. 5 is a plan view showing a layout configuration example of the DRAM memory array of FIG. Here, an example of an open bit line array in which DRAM memory cells are provided at the intersections of all the bit lines BL and word lines WL is shown.

  In FIG. 4 (and FIG. 5), the first path (LP1) is a leakage current of the N-type diffusion layer region N that makes contact between the bit line BL and the MOS transistor. Judging from the refresh characteristics of the memory cell, this is about 100 fA per diffusion layer at the maximum. However, considering the frequency of occurrence, the probability that a plurality of leak paths will occur on one bit line is low. The second pass (LP2) is a short-circuit between the word line and the bit line due to the breaking of the side wall of the word line WL when the bit line contact CB is formed by the self-alignment process. The third pass (LP3) is a short circuit between the storage node and the bit line due to the breaking of the side wall of the bit line BL when the storage node contact SC is formed by the self-alignment process.

  Defects during the wafer process such as the second and third passes can be ignored because the probability of occurrence is low at the stage of mass production. Further, in the early stage of mass production, when such a defect is included, the influence of the leak path can be ignored by replacing the array with a defect-free array. On the other hand, the first pass is caused by random defects in the Si crystal, and it is difficult to completely remove even if mass production progresses. FIG. 6 is an explanatory diagram showing the voltage change of the bit line during active standby in the DRAM memory cell of FIG. 4, and shows the influence of the first path in FIG.

In FIG. 6, the vertical axis represents the voltage of the bit line BL in the floating state, and the horizontal axis represents the active standby time (t). When the leak path of the current to _{I LP,} the bit line capacitance and _{C B,} the voltage decrease ΔV of the bit line is represented by _{I LP} × t / _{C B.} In the current DRAM, I _LP = about 100 fA and C _B = about 100 fF. In general-purpose DRAMs, the maximum time (tRAS (max)) from when the sense amplifier is activated upon receipt of the ACT command to when the PRE line is received and the bit line is precharged is determined by the specifications. It is about 70 μs. Therefore, the bit line voltage decrease ΔV during this period is about 70 μV at the maximum from the above formula, and is negligibly small compared to the voltage (for example, 0.8 V) of the bit line BL. Although the probability is small, even if there are 10 defects in one bit line BL, the voltage decrease is 0.7 mV, which is negligibly small.

Another problem is leakage through the transfer gate TGC from the bit line (sense amplifier external bit line) BL to the sense amplifier. The threshold V _T of the NMOS transistor constituting the transfer gate TGC To prevent this it is necessary to sufficiently high. When the _{V T} of the MOS transistor is defined as 100 nA / [mu] m flow gate voltage at 25 ° C., the channel width of the transfer gate TGC is 0.1 [mu] m, the subthreshold swing 0.1 V / dec, the decrease amount of _{V T} due to temperature rise 0 Since the voltage is about 1 V, the necessary threshold value is 0.5 V when the leak current is allowed up to 1 pA. Therefore, it is desirable that the threshold value of the transfer gate TGC be 0.5 V or more. At this time, the value of VPP is preferably set to be higher than the bit line voltage VDL + 0.5 V so that a high-level voltage can be written to the bit line even if the threshold value of the transfer gate TGC is increased.

  By the way, when tRAS (max) is made very long depending on how the chip is used, it is necessary to recover the voltage decrease of the bit line. For this purpose, it is preferable to periodically perform a bit line refresh operation. FIG. 7 is a waveform diagram showing an example of the bit line refresh operation in the semiconductor memory device according to one embodiment of the present invention. After receiving the activate command (ACT) and amplifying the signal on the bit line by the sense amplifier, when the transfer gate control signal TG0 and the sense amplifier are deactivated, the sense amplifier external bit lines BL0T and BL0B are in the floating state and the memory cell information Hold.

  After a certain period of time, TG0 is activated again based on, for example, a timer circuit in the DRAM chip or a command from outside the chip, and the sense amplifier internal bit lines BIT and BIB and the sense amplifier external bit line BL0T, BL0B is connected. Then, a potential difference is generated in the sense amplifier internal bit line due to the charge flowing from the sense amplifier external bit line. Since the sense amplifier external bit line has a large parasitic capacitance, this potential difference is more than half of VDL. Therefore, when the N-side common source line CSN is driven from VDL / 2 to 0 V and the P-side common source line CSP is driven from VDL / 2 to VDL, the potential difference is amplified at a high speed, and the bit line returns to VDL and VSS. Thereafter, TG0 is lowered, the sense amplifier internal bit lines BIT and BIB and the sense amplifier external bit lines BL0T and BL0B are separated, the N-side common source line CSN is returned from 0 V to VDL / 2, and the P-side common source line CSP is changed. The VDL is returned to VDL / 2, and the leakage current of the cross couple LVTCC is cut off.

  By such an operation, even if the bit line is left in a floating state for a long time and the bit line voltage decreases, the voltage written in the bit line and the memory cell can be recovered. When a timer circuit is used, this circuit measures, for example, the time after the word line WL is activated.

  FIG. 8 is a waveform diagram showing an example of the second precharge operation in the semiconductor memory device according to the embodiment of the present invention. Note that the operation in FIG. 8 can be said to be a second bit line refresh operation different from that in FIG. In FIG. 8, when the activation command (ACT) is received and the signal on the bit line is amplified by the sense amplifier and then the transfer gate control signal TG0 and the sense amplifier are deactivated, the bit line holds the memory cell information in the floating state. . When the precharge command (PRE) is input, TG0 is activated again, and the sense amplifier internal bit lines BIT and BIB and the sense amplifier external bit lines BL0T and BL0B are connected. Then, a potential difference is generated in the sense amplifier internal bit line due to the charge flowing from the sense amplifier external bit line. Since the sense amplifier external bit line has a large parasitic capacitance, this potential difference is more than half of VDL. Therefore, when the N-side common source line CSN is driven from VDL / 2 to 0 V and the P-side common source line CSP is driven from VDL / 2 to VDL, the potential difference is amplified at a high speed, and the bit line returns to VDL and VSS.

  After that, after deactivating the word line WL, the precharge signal PC and the transfer gate control signal TG1 are activated, the sense amplifier external bit lines (BL0T, BL0B and BL1T, BL1B) are equalized, and precharged to VDL / 2. Recharge. Further, the local I / O lines LIOT and LIOB are also restored from VCL to VDL / 2. When the operation of FIG. 8 is used, since the bit line is refreshed immediately before the word line WL is deactivated, information of a sufficient voltage level can be written back to the memory cells on the word line. Therefore, even if the bit line is left floating for a long time and the bit line voltage decreases, the voltage written in the bit line and the memory cell can be sufficiently recovered as a whole. Further, since the operation of FIG. 8 is performed by using a precharge command (PRE), it can be said that the operation is easier than the operation of FIG.

  FIG. 9 is a plan view showing an example of the chip configuration of the semiconductor memory device according to the embodiment of the present invention, where (a) is a configuration example of the entire chip, and (b) is the memory in (a). The structural example of a block is shown. The memory chip CHIP shown in FIG. 9A is roughly divided into a control circuit CNTL, an input / output circuit DQC, and a memory block BLK. A clock, an address, and a control signal are input to the control circuit CNTL from outside the memory chip CHIP, and an operation mode of the memory chip CHIP is determined, an address is predecoded, and the like. The input / output circuit DQC includes an input / output buffer and the like, and receives write data from the outside of the memory chip CHIP and outputs read data to the outside of the memory chip CHIP.

  In the memory block BLK, for example, as shown in FIG. 9B, a memory array ARY arranged in a plurality of arrays is arranged, and a sense amplifier array SAA, a sub word driver array SWDA, and a cross area XP are arranged around the memory array ARY. Be placed. On the outer periphery of the memory block BLK, a column decoder YDEC and a main amplifier column MAA are arranged in parallel with the sense amplifier column SAA, and a row decoder XDEC and an array control circuit ACC are arranged in parallel with the sub word driver column SWDA.

  FIG. 10 is a plan view showing an example of a detailed arrangement relationship between the sense amplifier row and the sub word driver row in the memory block of FIG. The sense amplifiers SA in the sense amplifier array SAA are alternately arranged above and below the memory array ARY and commonly connected to the bit lines BL in the upper and lower memory arrays. Similarly, the sub word drivers SWD in the sub word driver array SWDA are alternately arranged on the left and right with respect to the memory array, and are commonly connected to the word lines WL in the left and right memory arrays. By arranging in this way, the pitch between the sense amplifiers in the sense amplifier row can be increased to twice the pitch between the bit lines in the memory array, and between the sub word drivers in the sub word driver row. Can be increased to twice the pitch between the word lines in the memory array, so that miniaturization is facilitated. A local I / O line LIO is arranged in the sense amplifier row, and the local I / O line is connected to the main I / O line MIO via the switch SW in the cross area XP.

  11 and 12 are circuit diagrams showing detailed configuration examples in the memory array in the memory block of FIG. As shown in FIGS. 11 and 12, the memory array ARY includes a plurality of memory cells MC. Each memory cell MC is a DRAM memory cell, and includes one MOS transistor (memory cell transistor) and one capacitor Cs. In FIG. 11, a folded bit line type array is used, and memory cells MC are arranged at half the intersections of all the word lines and bit lines. The bit lines BLmT and BLmB adjacent to the left and right are connected to the sense amplifier SA as a bit line pair. One of the source and drain of the memory cell transistor is connected to BLmT or BLmB, the other of the source and drain is connected to the storage node SN, and the gate is connected to the word line WL. One terminal of capacitor Cs is connected to storage node SN, and the other terminal is connected to plate electrode PL. The configuration example of FIG. 1 is applied to the sense amplifier SA in this case.

  On the other hand, in FIG. 12, an open bit line type array is used, and memory cells MC are arranged at the intersections of all the word lines and bit lines. This has the effect of reducing the memory cell size. Bit lines BLmT and BLmB in the upper and lower separate arrays are connected to the sense amplifier SA as a bit line pair. The configuration example of FIG. 2 is applied to the sense amplifier SA in this case. The configuration of the memory cell MC is the same as that in FIG. Further, the bit lines BLmT and BLmB in the memory array ARY are alternately connected to different sense amplifier arrays SAA, and the sense amplifiers SA are shared by the bit lines in the memory array adjacent to both sides. Accordingly, in each sense amplifier array SAA, adjacent sense amplifiers SA are arranged with a space for one bit line interposed therebetween. By adopting such an arrangement, the pitch between the sense amplifiers SA is relaxed, which facilitates the layout and enables miniaturization.

  FIG. 13 is a circuit diagram showing an example of a configuration of a sub word driver column in the memory block of FIG. The sub word driver array SWDA is composed of a plurality of sub word drivers SWD. As shown in FIG. 10, the sub word driver array SWDA is arranged around the memory array ARY, and one sub word driver SWD drives the word lines WL in the memory arrays arranged on the left and right. Further, since the sub word driver columns are alternately arranged with respect to the memory array, every other word line in the memory array is connected to the left and right sub word drivers.

  The sub word driver SWD includes two NMOS transistors and one PMOS transistor. One NMOS transistor has a gate connected to the main word line MWLB, a drain connected to the word line WL, and a source connected to the voltage VKK. The other NMOS transistor has a gate connected to the complementary sub word driver select line FXB, a drain connected to the word line WL, and a source connected to the voltage VKK. Here, VKK is a standby word line voltage, which is a negative voltage lower than the ground potential. The PMOS transistor has a gate connected to the main word line MWLB, a drain connected to the word line WL, and a source connected to the sub word driver selection line FX. Four sets of sub word driver selection lines FX0 to FX3 are wired on one sub word driver column, and each of FX0 to FX3 is one of four sub word drivers SWD selected by one main word line MWLB. One is selected and one word line WL is activated.

  FIG. 14 is a circuit diagram showing an example of a cross area configuration in the memory block of FIG. The cross area XP includes a first local I / O line precharge circuit LEQ1, a second local I / O line precharge circuit LEQ2, a read / write gate RGC, a CS line driver CSD, and a CS line precharge circuit SEQ. BLEQ signal driver EQD, FX line driver FXD, and transfer gate control signal driver TGD are arranged.

  The first local I / O line precharge circuit LEQ1 precharges the local I / O lines LIOT and LIOB to VDL / 2 when the precharge signal PC is in an active state (the complementary precharge signal BLEQB is at the “L” level). Charge. The second local I / O line precharge circuit LEQ2 surrounds the local I / O lines LIOT and LIOB when the read equalization signal (LIOPC2) is in the active state (the complementary read equalization signal LIOPC2B is at the “L” level). Precharge to the power supply voltage VCL for the circuit. The read / write gate RGC connects the local I / O lines LIOT, LIOB and the main I / O lines MIOT, MIOB when the gate signals IOS, IOSB are activated.

  The CS line driver CSD drives the N-side common source line CSN to the ground voltage VSS when the N-side sense amplifier enable signal SAN is active, and the P-side when the P-side sense amplifier enable signal SAP1B is active. The common source line CSP is driven to the power supply voltage VDL. In order to reduce the leakage current in the active standby state and the precharge state, the threshold value of the MOS transistor constituting this CSD is set to 0.3 V or more as described in FIG. The CS line precharge circuit SEQ is a circuit for precharging the P-side and N-side common source lines CSP and CSN to VDL / 2 when the precharge signal PC is in an active state (the complementary precharge signal BLEQB is at the “L” level). It is. The BLEQ signal driver EQD receives a complementary precharge signal BLEQB, which is a complementary signal of the precharge signal PC, and outputs an inverted signal thereof. The FX line driver FXD receives signals from the complementary sub word driver selection lines FXB0 to FXB3 and outputs the inverted signal to the sub word driver selection lines FX0 to FX3.

  FIG. 15 is a circuit diagram showing another configuration example of the cross area in the memory block of FIG. The cross area XP shown in FIG. 15 is different only in that the read / write gate RGC in FIG. 14 is changed to the sub-amplifier SUBA. At the time of writing, the read enable signal RSAN is deactivated to VSS, IOS is activated to VCL, IOSB is activated to VSS, and the local I / O lines LIOT and LIOB are connected to the main I / O lines MIOT and MIOB. When reading, IOS is deactivated to VSS and IOSB is deactivated to VCL, RSAN is activated to VCL, and the voltage difference between the local I / O lines LIOT and LIOB is amplified at high speed, and the main I / O lines MIOT and MIOB are amplified. Is output.

  16A to 16D are circuit diagrams showing configuration examples of the timing generation circuit in the semiconductor memory device according to the embodiment of the present invention. 17A to 17C are waveform diagrams showing an operation example of FIG. The timing generation circuit shown in FIG. 16 is arranged, for example, in the control circuit CNTL or the array control circuit ACC in the semiconductor memory device of FIG. FIG. 16A shows a row-related signal generation circuit and shows a method for generating various signals from the activation signal RACT. FIG. 17A shows a timing chart. RACT is a one-shot pulse, which is delayed by the delay circuit DLY to generate the precharge deactivation signal TPCD, which is further delayed to generate the word line activation signal TWLE, which is further delayed. N-side sense amplifier activation signal TSANE and P-side sense amplifier activation signal TSAPE are generated.

  This is further delayed by an additional delay circuit AD having a delay tAD, which will be described later, to generate a transfer gate deactivation signal TTG0D, which is further delayed to inactivate the N side sense amplifier deactivation signal TSAND and the P side sense amplifier. Signal TSAPD is generated. By inputting these signals to the set / reset flip-flop shown in FIG. 16 (d), a transfer gate activation signal TTG0, a precharge activation signal TPC, a word line activation signal TWL, N-side sense amplifier activation signals TSAN, P A side sense amplifier activation signal TSAP1B is generated. While each signal is activated, the transfer gate control signal TG0, the precharge signal PC, the word line WL, the N-side sense amplifier enable signal SAN, and the P-side sense amplifier enable signal SAP1B are activated.

  FIG. 16B shows a column-related signal generation circuit, and shows a method for generating various signals from the column clock CCLK generated at the time of reading and writing. FIG. 17B shows a timing chart. CCLK is a one-shot pulse, which is delayed by a delay circuit DLY to generate a transfer gate activation signal TTG0E, which is delayed to produce an N-side sense amplifier activation signal TSANE and a P-side sense amplifier activation signal TSAPE. Is generated. Thereafter, a column selection line activation signal TYSE and a column selection line deactivation signal TYSD are sequentially generated via a delay. Subsequently, a transfer gate deactivation signal TTG0D is generated by being delayed by an additional delay circuit AD having a delay tAD, which will be described later, and this is delayed so that the N side sense amplifier deactivation signal TSAND and the P side sense amplifier non-delay An activation signal TSAPD is generated. By inputting these signals to the set / reset flip-flop shown in FIG. 16D, a transfer gate activation signal TTG0, an N-side sense amplifier activation signal TSAN, a P-side sense amplifier activation signal TSAP1B, and a column selection line activation signal TYS is generated. While the respective signals are activated, the transfer gate control signal TG0, the N-side sense amplifier enable signal SAN, the P-side sense amplifier enable signal SAP1B, and the column selection line YS are activated.

  FIG. 16C is a precharge signal generation circuit, and shows a method for generating various signals from the precharge control signal RPRE. FIG. 17C shows a timing chart. RPRE is a one-shot pulse, which is delayed by delay circuit DLY to generate word line deactivation signal TWLD, which is delayed to generate precharge activation signal TPCE and transfer gate activation signal TTG0E. The By inputting these signals to the set / reset flip-flop shown in FIG. 16D, a word line start signal TWL, a precharge start signal TPC, and a transfer gate start signal TTG0 are generated. While each signal is activated, the word line WL, the precharge signal PC, and the transfer gate control signal TG0 are activated.

  FIG. 18 shows the additional delay circuit AD in FIG. 16, wherein (a) is a circuit diagram showing a configuration example thereof, and (b) is a waveform diagram showing an operation example of (a). In the additional delay circuit AD shown in FIG. 18A, for example, a delay circuit DLY that generates a reset signal RST from a one-shot pulse signal from an input terminal IN and a logic gate GT1, and this RST is input to one of two inputs. It is composed of a plurality of stages of logic gates (AND circuits) GT2 in which the output of the previous stage is input to the other of the two inputs. IN is connected to the other of the two inputs in the first stage logic gate GT2, and the output of the last stage logic gate GT2 is connected to the output terminal OUT.

As shown in FIG. 18B, when a one-shot pulse of “H” level is input to the input terminal IN, an RST having an “L” pulse width of the delay circuit DLY is generated, and each logic gate GT2 Reset the output to 'L' level. Thereafter, when the RST returns to the “H” level, a one-shot “H” pulse signal is generated at the output (N1) of the first stage GT2 by AND logic with the “H” level from the IN. Are sequentially transmitted toward OUT. On the other hand, if a one-shot pulse signal is input again from IN during the transmission, the output of each logic gate GT2 is reset to the “L” level by RST, and the “H” pulse signal during the transmission disappears. The transmission of the “H” pulse signal starts again from the first stage GT2. Therefore, a pulse is output to OUT when a delay time t _AD of a plurality of stages GT2 has elapsed since the last one shot pulse was input to IN.

By using such a circuit, when an activate command, a read command, and a write command are continuously input at an interval shorter than t _AD , the transfer gate TGC is passed after time t _AD has elapsed from the last command. Since the N-side sense amplifier enable signal SAN and the P-side sense amplifier enable signal SAP1B are deactivated, these signal lines are not unnecessarily charged / discharged, and the power consumption can be reduced. Further, when an activate command, a read command, and a write command are input at such a short time interval, the operating current is large, and therefore the leak current of the sense amplifier at the average current can be ignored.

  As mentioned above, although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

  In the above embodiment, the memory cell is described as a DRAM composed of a transistor and a capacitor. However, the sense amplifier of this embodiment can also be applied to other memories. In particular, it is effective for a large-capacity memory that holds a large amount of data in a sense amplifier and performs a page mode operation in which a read operation or a write operation is performed on the sense amplifier. It may be a RAM, a solid electrolyte memory or the like.

  The semiconductor memory device according to the present embodiment is particularly useful when applied to a portable device DRAM or the like that requires high-speed operation and low power consumption, and is not limited to this, and is widely applied to various memory products in general. Is possible.

1 is a circuit diagram showing a configuration example of a sense amplifier when a folded bit line array is used in a semiconductor memory device according to an embodiment of the present invention. FIG. 1 is a circuit diagram showing a configuration example of a sense amplifier when an open type bit line array is used in a semiconductor memory device according to an embodiment of the present invention. FIG. FIG. 3 is a waveform diagram showing an operation example of the sense amplifier of FIGS. 1 and 2. In the semiconductor memory device by one embodiment of this invention, it is sectional drawing which shows the example of a structure around the memory cell, and shows an example of the leak current path of a bit line. FIG. 5 is a plan view showing a layout configuration example of the DRAM memory array of FIG. 4. FIG. 6 is an explanatory diagram showing the voltage change of the bit line during active standby in the DRAM memory cell of FIG. 4 and shows the influence of the first path in FIG. 5. FIG. 11 is a waveform diagram showing an example of the bit line refresh operation in the semiconductor memory device according to one embodiment of the present invention. FIG. 10 is a waveform diagram showing an example of the second precharge operation in the semiconductor memory device according to the embodiment of the present invention. 1 is a plan view illustrating an example of a chip configuration of a semiconductor memory device according to an embodiment of the present invention, where (a) is a configuration example of the entire chip, and (b) is a configuration example of a memory block in (a). Is shown. FIG. 10 is a plan view showing an example of a detailed arrangement relationship between the sense amplifier row and the sub word driver row in the memory block of FIG. 9. FIG. 10 is a circuit diagram showing a detailed configuration example in the memory array in the memory block of FIG. 9. FIG. 10 is a circuit diagram showing another detailed configuration example in the memory array in the memory block of FIG. 9. FIG. 10 is a circuit diagram illustrating an example of a configuration of a sub word driver row in the memory block of FIG. FIG. 10 is a circuit diagram illustrating an example of a configuration of a cross area in the memory block of FIG. 9. FIG. 10 is a circuit diagram illustrating another configuration example of the cross area in the memory block of FIG. 9. (A)-(d) is a circuit diagram which shows the structural example of the timing generation circuit in the semiconductor memory device by one embodiment of this invention. (A)-(c) is a wave form diagram which shows the operation example of FIG. FIG. 17 illustrates an additional delay circuit in FIG. 16, where (a) is a circuit diagram illustrating a configuration example thereof, and (b) is a waveform diagram illustrating an operation example of (a). 1 is a circuit diagram showing a configuration example of a sense amplifier in a conventional semiconductor memory device studied as a premise of the present invention. FIG. FIG. 20 is an operation waveform diagram illustrating an operation example of FIG. 19. It is a figure which shows the relationship between the electric current at the time of active standby, and the threshold value of a MOS transistor. It is a figure which shows the relationship between sense time and the threshold value of a MOS transistor.

Explanation of symbols

ACC array control circuit AD additional delay circuit ARY memory array AT active region BC bit line contact BIT, BIB sense amplifier internal bit line BL bit line BLEQB, PC precharge signal BLK memory block BLmT, BLmB sense amplifier external bit line CB contact CC, LVTCC cross-couple CHIP memory chip CI capacitive insulating film CNTL control circuit CSD CS line driver CSN N side common source line CSP P side common source line Cs capacitor DLY delay circuit DQC I / O circuit EQD BLEQ signal driver FX, FXB subword driver selection line FXD FX line driver GT logic gate IOP read / write port IOS, IOSB gate signal LEQ local I / O line precharge circuit LI , LIOT, LIOB Local I / O line LP Leakage path M MOS transistor MAA Main amplifier row MC Memory cell MIO, MIOT, MIOB Main I / O line MWLB Main word line N N-type diffusion layer region PCC Precharge circuit PL Plate electrode PW Semiconductor Substrate RACT Activate signal RGC Read / write gate RSAN Read enable signal SA Sense amplifier SAA Sense amplifier array SAN N side sense amplifier enable signal SAP1B P side sense amplifier enable signal SC Storage node contact SEQ CS line precharge circuit SN Storage node SUBA Subamplifier SW Switch SWD sub word driver SWDA sub word driver string TG transfer gate control signal TGC transfer gate TGD transfer gate control signal driver WL word line XDEC row decoder XP cross area YDEC column decoder YS column select line

Claims (19)

A word line,
Multiple bit lines,
A plurality of memory cells including a memory element and a memory cell transistor that connects the memory element to a corresponding bit line in the plurality of bit lines when the word line is active;
A plurality of sense amplifiers for performing amplification and latching of the voltages of the plurality of bit lines in an active state;
A plurality of transfer gates for conducting between the plurality of bit lines and the plurality of sense amplifiers in an active state;
After the plurality of transfer gates and the word lines are activated and the plurality of sense amplifiers are activated, the word lines remain in an activated state and the plurality of transfer gates are deactivated, A semiconductor memory device, wherein the plurality of sense amplifiers are inactivated while the plurality of bit lines and the plurality of sense amplifiers are in a non-conductive state. The semiconductor memory device according to claim 1.
During a read or write operation, the plurality of transfer gates are changed from an inactive state to an active state while the word line remains in an active state, and the plurality of bit lines and the plurality of sense amplifiers are in a conductive state. A semiconductor memory device, wherein a plurality of sense amplifiers are changed from an inactive state to an active state. The semiconductor memory device according to claim 2.
Each of the plurality of sense amplifiers is
A first conductivity type first and second MIS transistor having a source connected to the first common node;
Second conductivity type third and fourth MIS transistors having sources connected to the second common node,
The gates of the first and third MIS transistors and the drains of the second and fourth MIS transistors are connected to any one of the plurality of bit lines,
The gates of the second and fourth MIS transistors and the drains of the first and third MIS transistors are connected to any one of the plurality of bit lines,
Each of the plurality of sense amplifiers is activated when the first common node is driven to a first voltage and the second common node is driven to a second voltage that is lower than the first voltage. A semiconductor memory device. The semiconductor memory device according to claim 3.
And a fifth MIS transistor of the first conductivity type that applies the first voltage to the first common node in an active state,
2. A semiconductor memory device according to claim 1, wherein a threshold voltage of the first and second MIS transistors is lower than a threshold voltage of the fifth MIS transistor. The semiconductor memory device according to claim 4.
The first voltage is 1.0 V or less;
A threshold voltage of the first and second MIS transistors is less than 0.3V;
The threshold voltage of the fifth MIS transistor is 0.3 V or more. The semiconductor memory device according to claim 3.
And a second MIS transistor of the second conductivity type that applies the second voltage to the second common node in an active state,
The semiconductor memory device according to claim 1, wherein a threshold voltage of the third and fourth MIS transistors is lower than a threshold voltage of the sixth MIS transistor. The semiconductor memory device according to claim 6.
The first voltage is 1.0 V or less;
A threshold voltage of the third and fourth MIS transistors is less than 0.3V;
The threshold voltage of the sixth MIS transistor is 0.3 V or more. The semiconductor memory device according to claim 3.
Each of the plurality of transfer gates is configured by a second MIS transistor of the second conductivity type,
The semiconductor memory device, wherein a threshold voltage of the seventh MIS transistor is higher than a threshold voltage of the third and fourth MIS transistors. The semiconductor memory device according to claim 8.
The first voltage is 1.0 V or less;
A threshold voltage of the third and fourth MIS transistors is less than 0.3V;
The threshold voltage of the seventh MIS transistor is 0.5 V or more. A word line,
Multiple bit lines,
Local I / O lines;
A plurality of memory cells including a memory element and a memory cell transistor that connects the memory element to a corresponding bit line in the plurality of bit lines when the word line is active;
A plurality of sense amplifiers for performing amplification and latching of the voltages of the plurality of bit lines in an active state;
A column switch for coupling latch information of one sense amplifier selected from the plurality of sense amplifiers to the local I / O line in an active state;
A plurality of transfer gates for conducting between the plurality of bit lines and the plurality of sense amplifiers in an active state;
A first timing generation circuit including first, second, and third delay circuits that sequentially delay the first activation pulse signal to generate various signals;
The first timing generation circuit includes:
A word line activation signal for activating the word line;
A transfer gate deactivation signal for deactivating the plurality of transfer gates;
A sense amplifier activation signal for activating the plurality of sense amplifiers;
Generating a sense amplifier deactivation signal for deactivating the plurality of sense amplifiers;
The sense amplifier activation signal is generated from the word line activation signal through the first delay circuit,
The transfer gate deactivation signal is generated from the sense amplifier activation signal through the second delay circuit,
The semiconductor memory device, wherein the sense amplifier deactivation signal is generated from the transfer gate deactivation signal through the third delay circuit. The semiconductor memory device according to claim 10.
The second delay circuit extinguishes the sense amplifier activation signal being transmitted when the sense amplifier activation signal is input again while the sense amplifier activation signal is being transmitted through the second delay circuit. A semiconductor memory device comprising means. The semiconductor memory device according to claim 10.
And a second timing generation circuit including fourth, fifth, sixth, seventh and eighth delay circuits for sequentially delaying the second activation pulse signal to generate various signals,
The second timing generation circuit includes a transfer gate activation signal for activating the plurality of transfer gates in addition to the transfer gate deactivation signal, the sense amplifier activation signal, and the sense amplifier deactivation signal. Generating a column switch activation signal for activating the column switch and a column switch deactivation signal for deactivating the column switch;
The sense amplifier activation signal is generated from the transfer gate activation signal through the fourth delay circuit,
The column switch activation signal is generated from the sense amplifier activation signal through the fifth delay circuit,
The column switch deactivation signal is generated from the column switch activation signal through the sixth delay circuit,
The transfer gate deactivation signal is generated from the sense amplifier activation signal through the seventh delay circuit,
The semiconductor memory device, wherein the sense amplifier deactivation signal is generated from the transfer gate deactivation signal via the eighth delay circuit. The semiconductor memory device according to claim 12.
The seventh delay circuit extinguishes the sense amplifier activation signal being transmitted when the sense amplifier activation signal is input again while the sense amplifier activation signal is transmitted through the seventh delay circuit. A semiconductor memory device comprising means. The semiconductor memory device according to claim 10.
And a third timing generation circuit including a ninth delay circuit for generating various signals by delaying the third activation pulse signal,
The third timing generation circuit includes:
A transfer gate activation signal for activating the plurality of transfer gates;
Generating a word line deactivation signal for deactivating the word line;
The semiconductor memory device, wherein the transfer gate activation signal is generated from the word line deactivation signal via the ninth delay circuit. A word line,
Multiple bit lines,
A plurality of memory cells including a memory element and a memory cell transistor that connects the memory element to a corresponding bit line in the plurality of bit lines when the word line is active;
A plurality of sense amplifiers for performing amplification and latching of the voltages of the plurality of bit lines in an active state;
A plurality of transfer gates for conducting between the plurality of bit lines and the plurality of sense amplifiers in an active state;
Refresh means for refreshing the plurality of bit lines in a first state,
In the first state, after the plurality of transfer gates and the word lines are activated, and the plurality of sense amplifiers are activated, the word lines remain in an activated state, and the plurality of transfer gates are activated. A state after the plurality of bit lines and the plurality of sense amplifiers are in a non-conductive state and the plurality of sense amplifiers are inactivated,
The refresh means performs a first operation in which the plurality of transfer gates are transitioned from an inactive state to an active state, and the plurality of sense amplifiers are transitioned from an inactive state to an active state. . The semiconductor memory device according to claim 15.
After the first operation, the refresh means further performs a second operation of transitioning the plurality of transfer gates from an active state to an inactive state and transitioning the plurality of sense amplifiers from an active state to an inactive state. A semiconductor memory device. The semiconductor memory device according to claim 16.
The semiconductor memory device, wherein the first operation and the second operation are performed when the semiconductor memory device receives a command from the outside. The semiconductor memory device according to claim 16.
The refresh means further includes a timer circuit for measuring a time after the word line is activated.
The semiconductor memory device, wherein the first operation and the second operation are performed when a measurement time of the timer circuit reaches a preset time. The semiconductor memory device according to claim 15.
The refresh means further performs a third operation in which, after the first operation, the word line is changed from an active state to an inactive state, and then the plurality of sense amplifiers are changed from an active state to an inactive state. Done
The semiconductor memory device, wherein the first operation and the third operation are performed when a command for deactivating the word line is input.

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