JP2008299928A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the current consumption, the number of elements and the area of a transfer gate provided between a main input-output line MIO and a local input-output line LIO. <P>SOLUTION: A memory cell array obtained by arranging memory mats in a grid form is provided with a sub amplifier 10 which is arranged in a cross area region between memory mats, operates in response to a signal SBAEN and has a transfer gate (thin film NMOS transistor 401 and 402) for directly connecting a sense amplifier 60 and a main amplifier 20 during writing, and a logical circuit which is arranged in the cross area region without the sub amplifier 10 and generates a signal SBAEN to be supplied to the sub amplifier 10 with a signal line wired from a column address decoder and a signal line wired from a row address decoder as an input. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a DRAM (Dynamic Random Access Memory) having a subamplifier.

  In a DRAM, a plurality of sub-amplifiers are provided between a bit line to which a sense amplifier is connected and a main input / output line connected to the main amplifier, thereby enabling high-speed data reading operation ( For example, Patent Document 1 or Patent Document 2).

Japanese Patent Laid-Open No. 2000-1000017 JP 2001-057080 A

  Some of the sub-amplifiers described above are provided with a transfer gate that is in a conductive state only during a write operation because the main input / output line side and the bit line side are directly connected without a sub-amplifier during the write operation. For example, FIG. 4 of Patent Document 1 and transistors M15 and M16).

  7 and 8 show the basic configuration of a subamplifier that is the background of the present invention. FIG. 7 shows an n-channel MOS type (metal oxide semiconductor type) transfer gate for directly connecting the main input / output line side and the bit line side, and FIG. 8 shows a CMOS type.

  In FIG. 7, the sub-amplifier 10A includes five n-channel MOS transistors 11 to 15 (hereinafter may be simply referred to as transistors), two thick films (a gate oxide film is thicker than other transistors). It consists of channel MOS transistors 41 and 42. The main amplifier 20 is connected to a pair of main input / output lines MIOT and MIOB (signal lines that are positive or inverted signals). The drain of the thick n-channel MOS transistor 41 is connected to the main input / output line MIOT, and the drain of the thick n-channel MOS transistor 42 is similarly connected to the main input / output line MIOB. These transistors 41 and 42 constitute a transfer gate for directly connecting the main input / output line side and the bit line side at the time of writing described above. A write flag signal WRTFLG that is at the VPP (positive power supply voltage higher than the positive power supply VDD) level at the time of writing is input to the gates of the transistors 41 and 42.

  The drain of the transistor 11 constituting the sub-amplifier 10A is connected to the main input / output line MIOB, the source is connected to the drain of the transistor 14 and the drain (or source) of the transistor 13, and the gate is connected to the local input / output line LIOT. The drain of the transistor 12 is connected to the main input / output line MIOT, the source is connected to the drain of the transistor 15 and the source (or drain) of the transistor 13, and the gate is connected to the local input / output line LIOB. The sources of the transistors 14 and 15 are connected to the negative power supply VSS and the gate is connected to the sub-amplifier enable signal SBAEN together with the gate of the transistor 13.

  The local input / output lines LIOT and LIOB are a pair of signal lines having positive and inverted levels. Between the local I / O lines LIOT and LIOB, a precharge circuit 30 that precharges the local I / O line pair LIOT / B to the VDD level according to the LIO precharge signal LIOPRE and a local input according to the mat selection signal RBLEQT. An equalizing circuit 40 for equalizing the output line pair LIOT / B using the power supply VPP is connected.

  The drains of n-channel MOS transistors 51 and 52 are connected to local input / output lines LIOT and LIOB. The sources of the n-channel MOS transistors 51 and 52 are connected to a pair of bit lines BLT and BLB which are outputs of the sense amplifier 60, and the gates are both connected to a column address selection line YS.

  In the configuration shown in FIG. 7, the transfer gate (transistors 41 and 42) provided between the main input / output line MIO and the local input / output line LIO is formed of a thick film n-channel MOS transistor and controlled at the VPP voltage level. Like to do. Therefore, there exists a subject that the consumption current by charging / discharging is large. For example, it has been found that the refresh REF current (4Kref) may increase by about 21 mA compared to when it is controlled at the VDD voltage level.

  On the other hand, in the sub-amplifier 10B shown in FIG. 8, the transfer gate composed of the thick film transistors 41 and 42 shown in FIG. 7 includes n-channel MOS transistors 43 and 45, p-channel MOS transistors 44 and 46, and inverters. The circuit 47 is changed to a CMOS type transfer gate. In this case, the write flag signal WRTFLG has a VDD power supply voltage level lower than VPP at the time of writing. In FIG. 8, the same components as those shown in FIG.

  As shown in FIG. 8, when the transfer gate provided between the main input / output line MIO and the local input / output line LIO is a CMOS type transfer gate composed of thin film transistors and controlled at the VDD voltage level, Since the number of elements is larger than that in the configuration of FIG. 7, there is a problem that the area is increased. Compared to the case where the transfer gate is composed of an n-channel MOS, the number of transistors (two transistors in total) is increased per inverter (two transistors) and one IO line (input / output line). . If an attempt is made to bring a control signal from another region, a complementary signal for NMOS / PMOS is required for controlling the transfer gate, resulting in an increase in wiring.

  The present invention has been made in view of the above circumstances, and reduces the current consumption of the transfer gate (TG) provided between the main input / output line MIO and the local input / output line LIO. An object is to provide a semiconductor memory device capable of reducing the area.

  In order to solve the above-mentioned problem, the invention according to claim 1 is arranged at a crossing portion of a gap between the memory mats in a memory cell array configured by arranging a plurality of memory mats composed of a plurality of memory cells in a grid pattern. Is operated in response to an instruction of a control signal, and amplifies the voltage between a pair of local input / output lines connecting the sense amplifier and the main amplifier, and directly connects the sense amplifier and the main amplifier at the time of writing. A sub-amplifier having a transfer gate connected to the signal line, and a signal line routed from a column address decoder and a signal line routed from a row address decoder, arranged at a crossing portion of a gap between memory mats where the sub-amplifier is not disposed. A logic circuit for generating the control signal to be supplied to the sub-amplifier as an input; A thin film n-channel MOS transistor supplied from the row address decoder and turned on or off by an on / off signal having the same voltage level as a column address selection signal It is.

  According to a second aspect of the present invention, there is provided an equalizing circuit for equalizing a bit line which is an output of the sense amplifier based on a level of a mat selection signal which is supplied from the row address decoder and is a signal for selecting the memory mat. Connected to the local input / output line pair, and the logic circuit generates the control signal to be supplied to the sub-amplifier as the mat selection signal as an input by a signal line wired from the row address decoder. This is a semiconductor memory device.

  According to the above configuration, the transfer gate provided in the sub-amplifier that amplifies the voltage between the local input / output line pair connecting the sense amplifier and the main amplifier is a thin film n-channel MOS, and the signal for on / off control is sent to the column address Since the potential is the same as that of the selection line, the charge / discharge current can be reduced as compared with the case where a thick film n-channel MOS is used. In addition, the number of elements can be reduced as compared with the case of using a CMOS type transfer gate.

  Embodiments of the present invention will be described below with reference to the drawings. 1 to 4 are a basic configuration diagram (FIGS. 1 and 3), a sub-amplifier circuit diagram (FIG. 2), and a sub-amplifier control circuit diagram (FIG. 4) in the embodiment of the present invention, and FIG. FIG. 6 is a timing chart of main signals, and FIG. 6 is a simulation waveform at the time of writing. In each figure, the same reference numerals are used for the same components.

  FIG. 1 is a conceptual plan view showing the configuration of the memory cell array 1 of the present embodiment. The memory cell array 1 is configured by arranging memory mats 2, 2,... Each including a plurality of memory cells in a lattice pattern. Around the memory cell array 1, a row address decoder (X-DEC) 3, a column address decoder (Y-DEC) 4, and a main amplifier circuit 5 are provided. In the present embodiment, the area where the sub-amplifier is arranged in the intersection (array area cross area area) of the vertical and horizontal gaps between the memory mats 2 is defined as a cross area area SWC1 (area surrounded by a wavy circle), and the memory A crossing area (SWC2) is an intersection in a range 6 (region indicated by a two-dot chain line) in which no sub-amplifier is arranged in the center of the cell array 1.

  On the memory cell array 1, a signal line that supplies a write flag signal WRTFLG and a mat selection signal RBLEQT that is a signal for selecting the memory mat 2 from the row address decoder (X-DEC) 3 to each cross area area SWC1. Is wired. A column address selection line YS is wired from the column address decoder (Y-DEC) 4 to each memory mat 2. In the cross area SWC1, the main input / output line pair MIO (MIOT / B) is wired from the main amplifier circuit 5, and the local input / output line pair LIO (LIOT / B) to the plurality of memory mats 2 is also wired. ing.

  In each cross area area SWC1 shown in FIG. 1, a circuit block including the sub-amplifier 10 shown in FIG. 2 and its peripheral circuits is arranged. 2, the same reference numerals are used for the same components as those shown in FIG.

  In FIG. 2, except for the main amplifier 20, a plurality of circuits including at least the sub-amplifier 10 are arranged in each cross area region SWC1 in FIG. The sub-amplifier 10 is composed of seven n-channel MOS transistors 11 to 15 and 401 to 402, and amplifies the voltage between the local input / output line pair LIOT / LIOB connecting the sense amplifier 60 and the main amplifier 20. The main amplifier 20 is one of a plurality of amplifiers constituting the main amplifier circuit 5 of FIG. 1, and is connected to a pair of main input / output lines MIOT and MIOB (signal lines that are positive or inverted signals with respect to each other). A drain of a thin film n-channel MOS transistor 401 is connected to the main input / output line MIOT, and a drain of a similar n-channel MOS transistor 402 is connected to the main input / output line MIOB. These transistors 401 and 402 are transfer gates for directly connecting the main input / output line MIOT / B and the local input / output line LIOT / B at the time of writing, that is, the sense amplifier 60 and the main amplifier 20 are directly connected at the time of writing. It becomes a transfer gate to connect to. A write flag signal WRTFLG that is at the VDD level at the time of writing is input to the gates of the transistors 401 and 402. That is, the write flag signal WRTFLG is a signal having the same voltage level as the column address selection signal YS output from the column address decoder (Y-DEC) 4, and controls to turn on or off the thin film n-channel MOS transistors 401 and 402. Signal. The write flag signal WRTFLG is supplied from the row address decoder (X-DEC) 3 in FIG.

  The drain of the transistor 11 constituting the subamplifier 10 is connected to the main input / output line MIOB, the source is connected to the drain of the transistor 14 and the drain (or source) of the transistor 13, and the gate is connected to the local input / output line LIOT. The drain of the transistor 12 is connected to the main input / output line MIOT, the source is connected to the drain of the transistor 15 and the source (or drain) of the transistor 13, and the gate is connected to the local input / output line LIOB. The sources of the transistors 14 and 15 are connected to the negative power supply VSS and the gate is connected to the sub-amplifier enable signal SBAEN together with the gate of the transistor 13. The sub-amplifier enable signal SBAEN is a signal supplied from a control circuit (described later with reference to FIG. 4) provided in the cross area region SWC2 of FIG. 1, and is a signal whose High level becomes the VDD voltage.

  The local input / output lines LIOT and LIOB are a pair of signal lines having positive and inverted levels. Between the local I / O lines LIOT and LIOB, based on the level of the mat selection signal RBLEQT and the precharge circuit 30 that precharges the local I / O line pair LIOT / B to the VDD level according to the LIO precharge signal LIOPRE An equalize circuit 40 for equalizing the local input / output line pair LIOT / B using the power supply VPP is connected.

  The LIO precharge signal LIOPRE is a signal supplied from the control circuit provided in the cross area region SWC2 in FIG. 1, and is a signal whose High level becomes the VDD voltage. The mat selection signal RBLEQT is a signal supplied from the row address decoder (X-DEC) 3 in FIG. 1, and is a signal whose High level becomes the VPP voltage.

  The drains of n-channel MOS transistors 51 and 52 are connected to local input / output lines LIOT and LIOB. The sources of the n-channel MOS transistors 51 and 52 are connected to a pair of bit lines BLT and BLB which are outputs of the sense amplifier 60, and the gates are both connected to a column address selection line YS. The column address selection line YS is a signal supplied from the column address decoder (Y-DEC) 4 in FIG. 1, and is a signal whose High level becomes the VDD voltage. Connected to the sense amplifier 60 are a plurality of memory cells made up of charge storage capacitances and selection MOS transistors, which are configured in the memory mat 2 of FIG.

  Further, in the present embodiment, as shown in FIG. 3, the memory cell array 1 includes areas from the column address decoder (Y-DEC) 4 (or from the main amplifier circuit 5 to the column address decoder (Y-DEC) 4. And wiring for supplying the sub-amplifier enable reference signal SBAEN0 and the LIO precharge reference signal LIOPRE0 to the cross area area (SWC2). The sub-amplifier enable reference signal SBAEN0 and the LIO precharge reference signal LIOPRE0 are generated when the sub-amplifier enable signal SBAEN and the LIO pre-charge signal LIOPRE are generated in the sub-amplifier control circuit (FIG. 4) arranged in the cross area region (SWC2). This is a reference signal. On the memory cell array 1, signal lines for supplying the sub-amplifier enable signal SBAEN and the LIO precharge signal LIOPRE from the cross area area (SWC2) to the cross area area (SWC1) are wired.

  FIG. 4 shows a configuration example of a sub-amplifier control circuit arranged in the cross area area (SWC2). The sub-amplifier control circuit shown in FIG. 4 includes an inverter 71 that receives a mat selection signal RBLEQT (High level is VPP) and two AND circuits 72 and 73 that both receive the output RBLEQB of the inverter 71 as one input. ing. The sub amplifier enable reference signal SBAEN0 is input to the other input of the AND circuit 72, and the output of the AND circuit 72 is supplied to the cross area region (SWC1) as the amplifier enable signal SBAEN (High level is VDD). The LIO precharge reference signal LIOPRE0 is input to the other input of the AND circuit 73, and the output of the AND circuit 73 is supplied to the cross area region (SWC1) as the LIO precharge signal LIOPRE (High level is VDD).

  The sub-amplifier control circuit shown in FIG. 4 outputs the sub-amplifier enable reference signal SBAEN0 and the LIO precharge reference signal LIOPRE0 as the sub-amplifier enable signal SBAEN and the LIO pre-charge signal LIOPRE when the mat selection signal RBLEQT is at the low level. .

  In this embodiment, as shown in FIGS. 1 and 2, a thin-film n-channel MOS is used as a transfer gate (transistors 401 and 402) between the main input / output line MIO and the local input / output line LIO in the array section cross area region (SWC1). A sub-amplifier circuit is formed using transistors. At the time of writing, the write flag signal WRTFLG becomes High, and the data output from the main amplifier 20 (main amplifier circuit 5) to the main input / output line MIO is transferred to the local input / output line via the transfer gate (transistors 401 and 402). Transferred to LIOT / B. At the time of reading, the difference potential between the local input / output line pair LIOT / B is amplified by the sub-amplifier 10 and transferred to the main input / output line pair MIOT / B.

  The signals for controlling the transfer gates (transistors 401 and 402) and the sub-amplifier 10 take logic in other areas other than the cross-area area (SWC1), for example, as shown in FIG. Enter directly in (SWC1). For example, the write flag signal WRTFLG for controlling the transfer gate (transistors 401 and 402) takes the logic of the ROW mat selection signal RBLEQ generated by the row decoder XDEC3 and inputs it to the cross area region SWC1.

  On the other hand, the sub-amplifier enable signal SBAEN and the LIO precharge signal LIOPRE are generated in the cross area area (SWC2) where the sub-amplifier 10 in the center of the memory cell array 1 is not arranged as shown in FIG. The logic circuit shown in FIG. 4 provided in the cross area area (SWC2) takes a logic with the ROW mat selection signal RBLEQ and inputs the result to the cross area area SWC1. According to this configuration, only the selected mat row operates.

  Next, the read operation and the write operation will be described using the timing chart of FIG. 5 and the simulation waveform at the time of write in FIG. In FIG. 6, the upper diagram is a waveform diagram according to the background art (thick film NMOS type) for comparison, and the lower diagram is a waveform diagram according to the present embodiment (thin film NMOS type). First, when the memory mat 2 is activated by the active command (ACT), the mat selection signal RBLEQT (solid line, RBLEQB is a wavy line), which is a bit line equalizing signal, becomes Low level as shown in FIG. As a result, the local input / output line pair LIOT / B of the selected mat column is precharged to the VDD level.

  Thereafter, during a read operation, the column address selection line (column selection line) YS is selected by the read command, and the LIO precharge signal LIOPRE of the selected memory mat 2 becomes the high level, and the precharge off state is entered. At the same time, the sub amplifier enable signal SBAEN is activated to turn on the sub amplifier 10. As a result, the difference potential between the local input / output line pair LIOT / B is amplified and transferred to the main input / output line pair MIOT / B.

  During the write operation, the write flag signal WRTFLG is activated by the write command, and the transfer gate (transistors 401 and 402) of the selected memory mat 2 is turned ON. As a result, the local I / O line pair LIOT / B and the main I / O line pair MIOT / B are connected, and the main I / O line pair MIOT / B is connected to the local I / O line pair LIOT via the transfer gate (transistors 401 and 402). Data is transferred to / B.

  As shown in FIG. 6, the local I / O line LIO potential on the high side drops to about 1V, but there is no inversion delay of the bit line BL (about 40ps), and when the transfer gate (TG) is controlled by thick film VPP. It is equivalent. This is because there is no difference in the configuration of the n-channel MOS between the high-side LIO potential at the VDD level and the VDD-Vt level (threshold voltage). When the column address selection line (column selection line) YS has a VDD amplitude and the LIO potential on the high side is at the VDD level, it becomes VDD−Vt via YS, but when it is VDD−Vt, it is transferred as it is. It is.

  Further, as shown in FIG. 5, after writing or reading, the mat selection signal RBLEQT, which is a bit line equalization signal, is set to a high level by a precharge command (PRE). As a result, the local input / output line pair LIOT / B of the selected mat column is equalized to the VBL level (about 1/2 of VDD).

  According to the present embodiment, the following effects can be obtained. Charge / discharge current is reduced by changing the transfer gate (TG) between the main I / O line MIO and the local I / O line LIO to a thin-film n-channel MOS and changing the control signal from VPP to VDD which has the same potential as the column address selection line YS. It becomes possible to do. Also, by reducing the number of elements in the cross area region (SWC1), the size of the sub-amplifier MOS transistor and the LIO pre-charge MOS transistor can be increased, so that the characteristics can be improved.

  Note that the embodiment of the present invention is not limited to the above, and it is possible to appropriately change the number of transistors included in the circuit constituting the amplifier, or to change the combination of the components of the logic circuit. It is.

Plane conceptual diagram showing a basic configuration of an embodiment of the present invention Block diagram showing the sub-amplifier 10 and its peripheral circuits arranged in the cross area region SWC1 of FIG. Other plane conceptual diagrams showing the basic configuration of the embodiment shown in FIG. Circuit diagram showing sub-amplifier control circuit arranged in cross area region SWC2 of FIG. 1 is a timing chart showing operations at the time of data writing and reading of the embodiment shown in FIG. FIG. 1 is a simulation waveform diagram at the time of data writing of the embodiment shown in FIG. Block diagram showing the basic configuration of a sub-amplifier circuit according to the background art Block diagram showing another basic configuration of the sub-amplifier circuit according to the background art

Explanation of symbols

10 Sub-amplifier
11, 12, 13, 14, 15, 401, 402 n-channel MOS transistor
SWC1 Cross area area (with sub-amplifiers)
SWC2 Cross area area (Sub amplifier control circuit is arranged)

Claims (2)

In a memory cell array configured by arranging a plurality of memory mats composed of a plurality of memory cells in a grid pattern,
It is arranged at the intersection of the gaps between the memory mats, operates according to the instruction of the control signal, amplifies the voltage between the local input / output line pair connecting the sense amplifier and the main amplifier, and at the time of writing A sub-amplifier having a transfer gate that directly connects the sense amplifier and the main amplifier;
The control signal that is arranged at the intersection of the gaps between the memory mats where the sub-amplifier is not arranged, and that is supplied to the sub-amplifier with the signal line wired from the column address decoder and the signal line wired from the row address decoder as inputs And a logic circuit for generating
The transfer gate is a thin film n-channel MOS transistor which is supplied from the row address decoder and is turned on or off by an on / off signal having the same voltage level as a column address selection signal. Storage device. An equalize circuit for equalizing a bit line which is an output of the sense amplifier based on a level of a mat selection signal which is supplied from the row address decoder and is a signal for selecting the memory mat is provided for the local input / output line pair. Connected,
2. The semiconductor memory according to claim 1, wherein the logic circuit generates the control signal to be supplied to the sub-amplifier using the mat selection signal as an input by a signal line wired from the row address decoder. apparatus.

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