JP2017120904A5 - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- JP2017120904A5 JP2017120904A5 JP2016250524A JP2016250524A JP2017120904A5 JP 2017120904 A5 JP2017120904 A5 JP 2017120904A5 JP 2016250524 A JP2016250524 A JP 2016250524A JP 2016250524 A JP2016250524 A JP 2016250524A JP 2017120904 A5 JP2017120904 A5 JP 2017120904A5
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- conductive layer
- layer
- disposed above
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims 11
- 239000000758 substrate Substances 0.000 claims 7
- CJNBYAVZURUTKZ-UHFFFAOYSA-N Hafnium(IV) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims 3
- 229910052721 tungsten Inorganic materials 0.000 claims 3
- 239000010937 tungsten Substances 0.000 claims 3
Claims (3)
前記第１のトランジスタの上方に前記第４の絶縁層が配置され、
前記第４の絶縁層の上方に前記第２のトランジスタが配置され、
前記第４の絶縁層の上方に前記第１の導電層が配置され、
前記第１の導電層の上方に前記第１の絶縁層が配置され、
前記第１の絶縁層の上方に前記第２の絶縁層が配置され、
前記第２の絶縁層の上方に前記第３の絶縁層が配置され、
前記第１の絶縁層と前記第２の絶縁層と前記第３の絶縁層とを貫通する開口部の内部に、前記第２の導電層が配置され、
前記開口部の内部において、前記第２の導電層の上方に前記第３の導電層が配置され、
前記第２の導電層は、前記開口部において前記第１の導電層と電気的に接続され、
前記第２の導電層は、前記第１の導電層の上面と重なる第１の領域と、前記開口部の側面に沿う第２の領域と、前記第２の絶縁層の上面と重なる第３の領域と、を有し、
前記第２の絶縁層は、酸化ハフニウムを有し、
前記第２の導電層は、窒化チタンを有し、
前記第３の導電層は、タングステンを有する、半導体装置。 The first conductive layer, the second conductive layer, the third conductive layer, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the semiconductor A first transistor formed on the substrate; and a second transistor;
The fourth insulating layer is disposed above the first transistor;
The second transistor is disposed above the fourth insulating layer;
The first conductive layer is disposed above the fourth insulating layer;
The first insulating layer is disposed above the first conductive layer;
The second insulating layer is disposed above the first insulating layer;
The third insulating layer is disposed above the second insulating layer;
The second conductive layer is disposed inside an opening that penetrates the first insulating layer, the second insulating layer, and the third insulating layer,
Inside the opening, the third conductive layer is disposed above the second conductive layer,
The second conductive layer is electrically connected to the first conductive layer in the opening,
The second conductive layer includes a first region that overlaps the upper surface of the first conductive layer, a second region that extends along the side surface of the opening, and a third region that overlaps the upper surface of the second insulating layer. An area, and
The second insulating layer comprises hafnium oxide;
The second conductive layer comprises titanium nitride;
The semiconductor device, wherein the third conductive layer includes tungsten.
前記第１のトランジスタの上方に前記第４の絶縁層が配置され、
前記第４の絶縁層の上方に前記第２のトランジスタが配置され、
前記第４の絶縁層の上方に前記第１の導電層が配置され、
前記第１の導電層の上方に前記第１の絶縁層が配置され、
前記第１の絶縁層の上方に前記第２の絶縁層が配置され、
前記第２の絶縁層の上方に前記第３の絶縁層が配置され、
前記第１の絶縁層と前記第２の絶縁層と前記第３の絶縁層とを貫通する開口部の内部に、前記第２の導電層が配置され、
前記開口部の内部において、前記第２の導電層の上方に前記第３の導電層が配置され、
前記第２の導電層は、前記開口部において前記第１の導電層と電気的に接続され、
前記第２の導電層は、前記第１の導電層の上面と重なる第１の領域と、前記開口部の側面に沿う第２の領域と、前記第２の絶縁層の上面と重なる第３の領域と、を有し、
前記第１の領域は、前記半導体基板の裏面と平行であり、
前記第３の領域は、前記半導体基板の裏面と平行であり、
前記第２の絶縁層は、酸化ハフニウムを有し、
前記第２の導電層は、窒化チタンを有し、
前記第３の導電層は、タングステンを有する、半導体装置。 The first conductive layer, the second conductive layer, the third conductive layer, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the semiconductor A first transistor formed on the substrate; and a second transistor;
The fourth insulating layer is disposed above the first transistor;
The second transistor is disposed above the fourth insulating layer;
The first conductive layer is disposed above the fourth insulating layer;
The first insulating layer is disposed above the first conductive layer;
The second insulating layer is disposed above the first insulating layer;
The third insulating layer is disposed above the second insulating layer;
The second conductive layer is disposed inside an opening that penetrates the first insulating layer, the second insulating layer, and the third insulating layer,
Inside the opening, the third conductive layer is disposed above the second conductive layer,
The second conductive layer is electrically connected to the first conductive layer in the opening,
The second conductive layer includes a first region that overlaps the upper surface of the first conductive layer, a second region that extends along the side surface of the opening, and a third region that overlaps the upper surface of the second insulating layer. An area, and
The first region is parallel to a back surface of the semiconductor substrate;
The third region is parallel to the back surface of the semiconductor substrate;
The second insulating layer comprises hafnium oxide;
The second conductive layer comprises titanium nitride;
The semiconductor device, wherein the third conductive layer includes tungsten.
前記第１のトランジスタの上方に前記第４の絶縁層が配置され、
前記第４の絶縁層の上方に前記第２のトランジスタが配置され、
前記第４の絶縁層の上方に前記第１の導電層が配置され、
前記第１の導電層の上方に前記第１の絶縁層が配置され、
前記第１の絶縁層の上方に前記第２の絶縁層が配置され、
前記第２の絶縁層の上方に前記第３の絶縁層が配置され、
前記第１の絶縁層と前記第２の絶縁層と前記第３の絶縁層とを貫通する開口部の内部に、前記第２の導電層が配置され、
前記開口部の内部において、前記第２の導電層の上方に前記第３の導電層が配置され、
前記第２の導電層は、前記開口部において前記第１の導電層と電気的に接続され、
前記第２の導電層は、前記第１の導電層の上面と重なる第１の領域と、前記開口部の側面に沿う第２の領域と、前記第２の絶縁層の上面と重なる第３の領域と、を有し、
前記第１の領域は、前記半導体基板の裏面と概略平行であり、
前記第３の領域は、前記半導体基板の裏面と概略平行であり、
前記第２の絶縁層は、酸化ハフニウムを有し、
前記第２の導電層は、窒化チタンを有し、
前記第３の導電層は、タングステンを有する、半導体装置。 The first conductive layer, the second conductive layer, the third conductive layer, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the semiconductor A first transistor formed on the substrate; and a second transistor;
The fourth insulating layer is disposed above the first transistor;
The second transistor is disposed above the fourth insulating layer;
The first conductive layer is disposed above the fourth insulating layer;
The first insulating layer is disposed above the first conductive layer;
The second insulating layer is disposed above the first insulating layer;
The third insulating layer is disposed above the second insulating layer;
The second conductive layer is disposed inside an opening that penetrates the first insulating layer, the second insulating layer, and the third insulating layer,
Inside the opening, the third conductive layer is disposed above the second conductive layer,
The second conductive layer is electrically connected to the first conductive layer in the opening,
The second conductive layer includes a first region that overlaps the upper surface of the first conductive layer, a second region that extends along the side surface of the opening, and a third region that overlaps the upper surface of the second insulating layer. An area, and
The first region is substantially parallel to a back surface of the semiconductor substrate;
The third region is substantially parallel to the back surface of the semiconductor substrate;
The second insulating layer comprises hafnium oxide;
The second conductive layer comprises titanium nitride;
The semiconductor device, wherein the third conductive layer includes tungsten.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015256898 | 2015-12-28 | ||
| JP2015256898 | 2015-12-28 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021039975A Division JP7133056B2 (en) | 2015-12-28 | 2021-03-12 | semiconductor equipment |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017120904A JP2017120904A (en) | 2017-07-06 |
| JP2017120904A5 true JP2017120904A5 (en) | 2019-11-14 |
| JP6853663B2 JP6853663B2 (en) | 2021-03-31 |
Family
ID=59272234
Family Applications (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016250524A Active JP6853663B2 (en) | 2015-12-28 | 2016-12-26 | Semiconductor device |
| JP2021039975A Active JP7133056B2 (en) | 2015-12-28 | 2021-03-12 | semiconductor equipment |
| JP2022134739A Active JP7399233B2 (en) | 2015-12-28 | 2022-08-26 | semiconductor equipment |
| JP2023205359A Pending JP2024022640A (en) | 2015-12-28 | 2023-12-05 | electrode |
Family Applications After (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021039975A Active JP7133056B2 (en) | 2015-12-28 | 2021-03-12 | semiconductor equipment |
| JP2022134739A Active JP7399233B2 (en) | 2015-12-28 | 2022-08-26 | semiconductor equipment |
| JP2023205359A Pending JP2024022640A (en) | 2015-12-28 | 2023-12-05 | electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (4) | JP6853663B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11626037B2 (en) * | 2017-08-04 | 2023-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and display device |
| CN109494302B (en) | 2017-09-12 | 2024-04-05 | 松下知识产权经营株式会社 | Capacitive element, image sensor, and method for manufacturing capacitive element |
| US11545578B2 (en) | 2018-04-27 | 2023-01-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| WO2019220266A1 (en) * | 2018-05-18 | 2019-11-21 | 株式会社半導体エネルギー研究所 | Semiconductor device, and semiconductor device manufacturing method |
| US10861739B2 (en) * | 2018-06-15 | 2020-12-08 | Tokyo Electron Limited | Method of patterning low-k materials using thermal decomposition materials |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3842852B2 (en) * | 1995-11-27 | 2006-11-08 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| GB2325083B (en) * | 1997-05-09 | 1999-04-14 | United Microelectronics Corp | A dual damascene process |
| JP3078811B1 (en) * | 1998-03-26 | 2000-08-21 | 松下電器産業株式会社 | Method of forming wiring structure |
| US6603204B2 (en) * | 2001-02-28 | 2003-08-05 | International Business Machines Corporation | Low-k interconnect structure comprised of a multilayer of spin-on porous dielectrics |
| US6846899B2 (en) * | 2002-10-01 | 2005-01-25 | Chartered Semiconductor Manufacturing Ltd. | Poly(arylene ether) dielectrics |
| CN100505265C (en) * | 2003-12-26 | 2009-06-24 | 富士通微电子株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| JP2007027291A (en) * | 2005-07-14 | 2007-02-01 | Matsushita Electric Ind Co Ltd | Semiconductor device and its fabrication process |
| DE102010064289B4 (en) * | 2010-12-28 | 2019-06-19 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Size reduction of contact elements and vias in a semiconductor device by incorporation of an additional chamfer material |
| JP6220597B2 (en) | 2012-08-10 | 2017-10-25 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US9018701B2 (en) * | 2012-08-14 | 2015-04-28 | Force Mos Technology Co., Ltd. | Avalanche capability improvement in power semiconductor devices using three masks process |
| JP2014187181A (en) * | 2013-03-22 | 2014-10-02 | Toshiba Corp | Semiconductor device and manufacturing method of the same |
| SG11201604650SA (en) * | 2013-12-26 | 2016-07-28 | Semiconductor Energy Lab | Semiconductor device |
| KR102529174B1 (en) * | 2013-12-27 | 2023-05-08 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
| KR102325158B1 (en) | 2014-01-30 | 2021-11-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device, electronic device, and manufacturing method of semiconductor device |
| JP6545976B2 (en) * | 2014-03-07 | 2019-07-17 | 株式会社半導体エネルギー研究所 | Semiconductor device |
-
2016
- 2016-12-26 JP JP2016250524A patent/JP6853663B2/en active Active
-
2021
- 2021-03-12 JP JP2021039975A patent/JP7133056B2/en active Active
-
2022
- 2022-08-26 JP JP2022134739A patent/JP7399233B2/en active Active
-
2023
- 2023-12-05 JP JP2023205359A patent/JP2024022640A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2016195267A5 (en) | ||
| JP2017005277A5 (en) | ||
| JP2018061001A5 (en) | Transistor | |
| JP2017120904A5 (en) | Semiconductor device | |
| JP2014030012A5 (en) | Semiconductor device | |
| JP2017034249A5 (en) | Semiconductor device | |
| JP2013168644A5 (en) | Semiconductor device | |
| JP2015156477A5 (en) | Semiconductor device | |
| JP2016036021A5 (en) | Method for manufacturing conductor, method for manufacturing semiconductor device | |
| JP2014195063A5 (en) | ||
| JP2014199913A5 (en) | ||
| JP2016201541A5 (en) | Semiconductor device | |
| JP2011054949A5 (en) | Semiconductor device | |
| JP2015005738A5 (en) | Semiconductor device | |
| JP2015179822A5 (en) | Semiconductor device | |
| JP2013214729A5 (en) | ||
| JP2013149961A5 (en) | Semiconductor device | |
| JP2015156515A5 (en) | Method for manufacturing semiconductor device | |
| JP2015109433A5 (en) | ||
| JP2013165132A5 (en) | ||
| JP2017034243A5 (en) | Method for manufacturing memory cell and method for manufacturing semiconductor device | |
| JP2016139800A5 (en) | Semiconductor device | |
| JP2015179810A5 (en) | Semiconductor device | |
| JP2015026831A5 (en) | Semiconductor device | |
| JP2017098545A5 (en) | Semiconductor device |