JP7399233B2 - semiconductor equipment - Google Patents

Description

The present invention relates to, for example, a transistor and a semiconductor device. Alternatively, the present invention relates to, for example, a method for manufacturing a transistor and a semiconductor device. Alternatively, the present invention relates to, for example, a display device, a light emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. Alternatively, the present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light emitting device, a storage device, or an electronic device. Alternatively, the present invention relates to a method for driving a display device, a liquid crystal display device, a light emitting device, a storage device, or an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to products, methods, or manufacturing methods. Alternatively, one aspect of the invention provides a process, machine, manufacture, or composition.
of matter).

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Display devices, light emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic equipment may include semiconductor devices.

In recent years, the development of transistors using oxide semiconductors (typically In--Ga--Zn oxides) has become active, and they are also used in integrated circuits and the like. Oxide semiconductors have a long history, with 19
In 1988, the use of crystalline In-Ga-Zn oxide for semiconductor devices was disclosed (see Patent Document 1). Furthermore, in 1995, a transistor using an oxide semiconductor was invented, and its electrical characteristics have been disclosed (see Patent Document 2).

Furthermore, a semiconductor device that combines a transistor using silicon (Si) for a semiconductor layer and a transistor using an oxide semiconductor for a semiconductor layer is attracting attention (see Patent Document 3).

Japanese Patent Publication No. 63-239117 Special table Hei 11-505377 JP2011-119674

One of the objects is to provide a semiconductor device having a transistor having stable electrical characteristics. Another object of the present invention is to provide a semiconductor device having a transistor with small leakage current when non-conducting. Another object of the present invention is to provide a semiconductor device having a transistor having normally-off electrical characteristics. Another object of the present invention is to provide a semiconductor device having a highly reliable transistor.

Alternatively, one of the objects is to provide a module having the semiconductor device. Alternatively, one object of the present invention is to provide an electronic device having the semiconductor device or the module. Alternatively, one of the challenges is to provide a new semiconductor device. Alternatively, one of the challenges is to provide a new module. Alternatively, one of the challenges is to provide a new electronic device.

Note that the description of these issues does not preclude the existence of other issues. Note that one embodiment of the present invention does not need to solve all of these problems. Note that issues other than these will naturally become clear from the description, drawings, claims, etc., and it is possible to extract issues other than these from the description, drawings, claims, etc. It is.

(1)
One embodiment of the present invention includes a metal containing nitrogen, a first conductor, a second conductor, an insulator,
The insulator is provided with an opening that penetrates the insulator and reaches the second conductor, and a side surface of the opening and a bottom surface of the opening have a region in contact with the metal. and the first
The conductor has a region in contact with the side surface of the opening and the bottom surface of the opening through the metal, and the electrical resistivity of the metal in contact with the bottom surface of the opening is such that the electrical resistivity of the metal in contact with the bottom surface of the opening is The electrode is characterized by having an electrical resistivity lower than that of the metal.

(2)
One aspect of the present invention is the electrode according to (1), wherein the metal contains tantalum and oxygen.

(3)
One aspect of the present invention is characterized in that the first conductor includes copper or tungsten (1
) or (2).

(4)
One aspect of the present invention is the electrode according to any one of (1) to (3), wherein the insulator contains aluminum and oxygen.

(5)
One embodiment of the present invention includes an electrode, a first transistor, and a second transistor, the first transistor has a gate electrode, the second transistor has a drain electrode, and the gate electrode is A semiconductor device characterized in that it is electrically connected to a drain electrode via an electrode, and the electrode is the electrode described in any one of (1) to (4).

(6)
One aspect of the present invention is a module including the electrode according to any one of (1) to (4), the semiconductor device according to (5), and a printed circuit board.

(7)
One aspect of the present invention is characterized by having the electrode according to any one of (1) to (4), the semiconductor device according to (5), the module according to (6), and a speaker or an operation key. It is an electronic device that uses

(8)
One aspect of the present invention provides a plurality of electrodes according to any one of (1) to (4), or (5).
) is a semiconductor wafer having a plurality of semiconductor devices as described in ) and having a dicing area.

(9)
In one embodiment of the present invention, a first insulator is formed over a first conductor, a second insulator is formed over the first insulator, and a third insulator is formed over the second insulator. A hard mask is formed on the third insulator, and a part of the first insulator, the second insulator, and the third insulator are etched using the hard mask as an etching mask. By doing so, an opening is formed that passes through the first insulator, the second insulator, and the third insulator and reaches the top surface of the first conductor, and nitrogen is formed so as to cover the side and bottom surfaces of the opening. A metal film is formed, plasma treatment is performed, a second conductor is formed on the metal containing nitrogen so as to fill the opening, and a polishing process is performed on the hard mask, the metal containing nitrogen, and the second conductor. Then, the hard mask is removed, and the heights of the top surfaces of the nitrogen-containing metal, the second conductor, and the third insulator are made approximately the same, and the electrical resistivity of the nitrogen-containing metal in contact with the bottom of the opening is equal to that of the opening. This is a method for producing an electrode characterized in that the electrical resistivity is lower than that of the nitrogen-containing metal that is in contact with the side surface of the electrode.

(10)
One aspect of the present invention is characterized in that the gas used for plasma processing contains argon (9
) is the method for producing the electrode described in

(11)
One embodiment of the present invention is a method for manufacturing a semiconductor device, wherein the semiconductor device has an electrode, a first transistor, and a second transistor, the first transistor has a gate electrode, and a second transistor has a gate electrode. The transistor has a drain electrode, the gate electrode is electrically connected to the drain electrode via the electrode, and the electrode is formed using the electrode manufacturing method described in either (9) or (10). This is a semiconductor device characterized by being manufactured.

(12)
One aspect of the present invention is a method for manufacturing a module, the module comprising (9) or (10)
), a semiconductor device manufactured using the method for manufacturing a semiconductor device according to (11), and a printed circuit board. This is a method for manufacturing a module.

(13)
One embodiment of the present invention is a method for manufacturing an electronic device, the electronic device comprising: a capacitive element manufactured using the method for manufacturing an electrode according to any one of (9) or (10); A semiconductor device manufactured using the semiconductor device manufacturing method described in (12), a module manufactured using the module manufacturing method described in (12), and an electronic device characterized by having a speaker or an operation key. This is the manufacturing method.

A semiconductor device including a transistor having stable electrical characteristics can be provided. Alternatively, a semiconductor device including a transistor with small leakage current when non-conductive can be provided. Alternatively, a semiconductor device including a transistor having normally-off electrical characteristics can be provided. Alternatively, a semiconductor device including a highly reliable transistor can be provided.

Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided. Alternatively, a new semiconductor device can be provided. Alternatively, new modules can be provided. Alternatively, new electronic equipment can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. In addition, effects other than these can be found in the specification,
This will naturally become clear from the drawings, claims, etc., and it is possible to extract effects other than these from the description, drawings, claims, etc.

1A and 1B are a cross-sectional view and a top view illustrating a structure of a semiconductor device according to one embodiment of the present invention. 1A and 1B are a cross-sectional view and a top view illustrating a structure of a semiconductor device according to one embodiment of the present invention. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a top view illustrating a structure of a transistor according to one embodiment of the present invention. FIGS. 2A and 2B are a cross-sectional view and a top view illustrating a structure of a transistor according to one embodiment of the present invention. FIG. 3 is a diagram illustrating the range of the atomic ratio of an oxide semiconductor according to the present invention. A diagram illustrating a crystal of InMZnO ₄ . A band diagram in a stacked structure of an oxide semiconductor. FIG. 1 is a cross-sectional view illustrating a structure of a capacitor according to one embodiment of the present invention. FIG. 1 is a cross-sectional view illustrating a structure of a transistor according to one embodiment of the present invention. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. FIGS. 2A and 2B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. FIGS. 2A and 2B are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. Figures illustrating structural analysis of CAAC-OS and single-crystal oxide semiconductors by XRD, and diagrams showing selected area electron diffraction patterns of CAAC-OS. A cross-sectional TEM image, a planar TEM image, and its image analysis image of CAAC-OS. A diagram showing an electron diffraction pattern of nc-OS and a cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 3 is a diagram showing changes in crystal parts of In--Ga--Zn oxide due to electron irradiation. 1 is a circuit diagram showing a semiconductor device according to one embodiment of the present invention. 1 is a circuit diagram showing a storage device according to one embodiment of the present invention. 1 is a circuit diagram showing a storage device according to one embodiment of the present invention. 1A and 1B are a circuit diagram and a timing chart for explaining one embodiment of the present invention. Graphs and circuit diagrams for explaining one embodiment of the present invention. 1A and 1B are a circuit diagram and a timing chart for explaining one embodiment of the present invention. 1A and 1B are a circuit diagram and a timing chart for explaining one embodiment of the present invention. 1 is a block diagram, a circuit diagram, and a waveform diagram for explaining one embodiment of the present invention. 1A and 1B are a circuit diagram and a timing chart for explaining one embodiment of the present invention. FIG. 1 is a circuit diagram for explaining one embodiment of the present invention. FIG. 1 is a circuit diagram for explaining one embodiment of the present invention. FIG. 1 is a circuit diagram for explaining one embodiment of the present invention. FIG. 1 is a circuit diagram for explaining one embodiment of the present invention. FIG. 1 is a circuit diagram for explaining one embodiment of the present invention. FIG. 1 is a block diagram showing a semiconductor device according to one embodiment of the present invention. 1 is a circuit diagram showing a semiconductor device according to one embodiment of the present invention. FIG. 1 is a top view showing a semiconductor device according to one embodiment of the present invention. FIG. 1 is a block diagram showing a semiconductor device according to one embodiment of the present invention. 1 is a cross-sectional view showing a semiconductor device according to one embodiment of the present invention. 1 is a cross-sectional view showing a semiconductor device according to one embodiment of the present invention. FIG. 1 is a perspective view showing an electronic device according to one embodiment of the present invention. FIG. 3 is a diagram showing the amount of film reduction of tantalum nitride according to an example. FIG. 3 is a diagram showing sheet resistance measurement results according to an example. The figure which shows the XPS analysis result based on an Example. The figure which shows the XPS analysis result based on an Example. FIG. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. A flowchart and a perspective schematic diagram illustrating an example of a manufacturing process of an electronic component.

Embodiments of the present invention will be described in detail using the drawings. However, those skilled in the art will easily understand that the present invention is not limited to the following description, and that its form and details can be changed in various ways. Further, the present invention is not to be interpreted as being limited to the contents described in the embodiments shown below. In addition, when explaining the configuration of the invention using the drawings, the same reference numerals are used in different drawings. Note that when referring to similar items, the same hatch pattern may be used, and no particular reference numeral may be attached.

The structures shown in the embodiments below can be applied, combined, or replaced with other structures shown in the embodiments as appropriate to form one embodiment of the present invention.

Note that in the drawings, sizes, thicknesses of films (layers), or regions may be exaggerated for clarity.

Note that in this specification, the notation "film" and the notation "layer" can be interchanged.

Also, voltage is a certain potential and a reference potential (for example, ground potential (GND) or source potential)
It often refers to the potential difference between Therefore, it is possible to refer to voltage as potential. Generally, potential (voltage) is relative and determined by the relative magnitude from a reference potential. Therefore, even if it is described as "ground potential", the potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Alternatively, a potential somewhere in the middle of the circuit may be the "ground potential." In that case, a positive potential and a negative potential are defined based on that potential.

Note that the ordinal numbers added as first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by replacing "first" with "second" or "third" as appropriate. Further, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

Note that even when a material is described as a "semiconductor," it may have the characteristics of an "insulator" if its conductivity is sufficiently low, for example. Furthermore, the boundary between "semiconductor" and "insulator" is ambiguous, and it may not be possible to strictly distinguish between them. Therefore, the "semiconductor" described in this specification can sometimes be translated as "insulator." Similarly, the "insulator" described herein can sometimes be translated as "semiconductor."

Furthermore, even when a material is described as a "semiconductor", it may have characteristics as a "conductor" if its conductivity is sufficiently high, for example. Furthermore, the boundary between "semiconductor" and "conductor" is ambiguous, and it may not be possible to strictly distinguish between them. Therefore, the "semiconductor" described in this specification can sometimes be translated as a "conductor." Similarly, the "conductor" described herein can sometimes be translated as "semiconductor."

Note that the term "impurity of a semiconductor" refers to, for example, something other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic % is an impurity. The inclusion of impurities may cause, for example, formation of DOS (Density of States) in the semiconductor, reduction in carrier mobility, or reduction in crystallinity. When the semiconductor is an oxide semiconductor, examples of impurities that change the properties of the semiconductor include Group 1 elements and Group 2 elements.
Group elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components, and in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron,
These include phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, oxygen vacancies may be formed due to the incorporation of impurities such as hydrogen, for example. Further, when the semiconductor is a silicon layer, impurities that change the characteristics of the semiconductor include, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, and the like.

Note that the channel length is, for example, the region where the semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the region where the channel is formed, in a top view of the transistor. The distance between the source (source region or source electrode) and drain (drain region or drain electrode) in Note that in one transistor, the channel length does not necessarily take the same value in all regions. That is, the channel length of one transistor may not be determined to one value. Therefore, in this specification, the channel length refers to any one value, maximum value,
Take the minimum or average value.

For example, in a top view of a transistor, the channel width refers to the region where the semiconductor (or the part of the semiconductor where current flows when the transistor is on) and the gate electrode overlap, or the region where a channel is formed. Refers to the length of the channel region in the vertical direction with respect to the channel length direction. Note that in one transistor, the channel width does not necessarily take the same value in all regions. That is, the channel width of one transistor may not be determined to one value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter referred to as effective channel width) and the channel width shown in the top view of the transistor (hereinafter referred to as apparent channel width) ) may be different. for example,
In a transistor having a three-dimensional structure, the effective channel width may be larger than the apparent channel width shown in a top view of the transistor, and the effect thereof may not be negligible. For example, in a transistor having a fine and three-dimensional structure, a large proportion of the channel region is formed on the side surface of the semiconductor in some cases. In that case, the effective channel width where the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from design values, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

Therefore, in this specification, the apparent channel width is defined as "enclosed channel width (SCW: Su
rrounded Channel Width). Furthermore, in this specification, when simply described as channel width, it may refer to an enclosed channel width or an apparent channel width. Alternatively, in this specification, when simply described as channel width, it may refer to effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, etc. are determined by obtaining a cross-sectional TEM image, etc.
The value can be determined, such as by analyzing the image.

Note that when calculating the field effect mobility of a transistor, the current value per channel width, etc., the calculation may be performed using the enclosed channel width. In that case, the value may be different from the value calculated using the effective channel width.

Note that in this specification and the like, silicon oxynitride has a composition that contains more oxygen than nitrogen, preferably 55 to 65 at% of oxygen and 1 to 65 at% of nitrogen.
It refers to a substance containing silicon in a concentration range of 25 atom % to 35 atom %, and hydrogen in a concentration range of 0.1 atom % to 10 atom %. Furthermore, silicon nitride oxide has a composition that contains more nitrogen than oxygen, and preferably contains 55% nitrogen.
atomic% or more and 65 atomic% or less, oxygen 1 atomic% or more and 20 atomic% or less, silicon 25 atomic%
Hydrogen is contained in a concentration range of 0.1 atomic % or more and 10 atomic % or less.

In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, cases where the angle is between -5° and 5° are also included. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Moreover, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case where the angle is 85° or more and 95° or less is also included. Moreover, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

Furthermore, in this specification, when a crystal is trigonal or rhombohedral, it is expressed as a hexagonal system.

(Embodiment 1)
In this embodiment, a method for manufacturing a semiconductor device according to one embodiment of the present invention will be described with reference to drawings.

<Plug manufacturing method 1>
The structure of a plug and its manufacturing method will be described below as part of the structure of a semiconductor device according to one embodiment of the present invention with reference to cross-sectional views and top views shown in FIGS. 1, 5, and 6. Figure 1 (
A), FIG. 5(A), FIG. 5(C), FIG. 6(A) and FIG. 6(C) are
), FIG. 5(D), FIG. 6(B), and FIG. 6(D) show cross-sectional views corresponding to the dashed line X1-X2 in the top views.

1A and 1B are completed diagrams of the plug, and FIGS. 5 and 6 show the conductor 12 (hereinafter sometimes referred to as a conductive film or wiring), the insulator 13a, and the insulator 14a. and a metal 20a containing nitrogen embedded in an opening 17 formed in an insulator 15a and a conductor 2
The process of connecting 1a and 1a is explained. Here, the opening 17 functions as a via hole or the like, and functions as a plug in which the metal 20a containing nitrogen and the conductor 21a are embedded in the opening 17. Further, at the bottom of the opening 17, the metal 20a containing nitrogen and the conductor 12
The nitrogen-containing metal 20a in the region in contact with has a region with low resistance. Figure 1 (A
) The region where the resistance of the metal 20a containing nitrogen is reduced is indicated by a dotted line.

First, a conductor 12 is formed on a substrate. The conductor 12 may have a single layer structure or a laminated structure. Note that the substrate is not illustrated in FIG. 1(A), FIG. 6, and FIG. Further, another conductor, an insulator, a semiconductor, or the like may be provided between the substrate and the conductor 12.

The conductor 12 may be formed using a method similar to that for forming the nitrogen-containing metal 20 and the conductor 21, which will be described later.

Next, an insulator 13 is formed on the conductor 12 . The insulator 13 may have a single layer structure or a laminated structure. The insulator 13 is formed by sputtering, chemical vapor deposition (CV), etc.
D: Chemical Vapor Deposition) method, molecular beam epitaxy (
MBE (Molecular Beam Epitaxy) method, pulsed laser deposition (PL)
D: Pulsed Laser Deposition) method or atomic layer deposition (ALD)
:Atomic Layer Deposition) method.

Note that the CVD method is plasma CVD (PECVD: Plasma E
Thermal CVD (TCVD) method that uses heat
D) method, photo CVD method that uses light, etc. Furthermore, depending on the raw material gas used, metal CVD (MCVD) method, organometallic CVD (
MOCVD (Metal Organic CVD) method.

Next, an insulator 14 is formed on the insulator 13. The insulator 14 may have a single layer structure or a laminated structure. The insulator 14 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

It is preferable to use a material for the insulator 14 that is less permeable to hydrogen and water than the insulator 13. Examples of the insulator 14 include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide,
Hafnium oxynitride or the like can be used. By using these as the insulator 14, it can function as an insulating film that blocks the diffusion of hydrogen and water.

Next, an insulator 15 is formed on the insulator 14. The insulator 15 may have a single layer structure or a laminated structure. Alternatively, a structure may be adopted in which the insulator 15 is omitted. Insulator 15
The film formation can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a material for the hard mask 16 is formed on the insulator 15 . Here, hard mask 16
As the material, a conductor such as a metal material or an insulator may be used. Further, the material of the hard mask 16 may be formed as a single layer or as a laminated layer of an insulator and a conductor. Note that in this specification and the like, the term "hard mask" refers to a mask made using a material other than resist (metal material or insulating material). The material of the hard mask 16 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a hard mask 1 is formed using a resist mask formed using a lithography method or the like.
6 is etched to form a hard mask 16 having an opening 17a (FIG. 5(A)
See (B). ). Here, FIG. 5(A) is a cross-sectional view corresponding to the dashed line X1-X2 shown in FIG. 5(B). Similarly, a cross-sectional view and a top view are shown below, corresponding to the dashed dotted line X1-X2.

Note that in the lithography method, the resist is first exposed to light through a mask. Next, a resist mask is formed by removing or leaving the exposed area using a developer. Next, a conductor, semiconductor, insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask may be formed by exposing a resist to light using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when using an electron beam or an ion beam, a mask is not required. In addition, to remove the resist mask, perform dry etching processing such as ashing, perform wet etching processing, perform wet etching processing in addition to dry etching processing, or perform dry etching processing in addition to wet etching processing. be able to.

Although the opening 17a has a circular upper surface, it is not limited to this. For example, the upper surface may have an elliptical shape or a polygonal shape such as a triangle or a quadrangle. Moreover, when setting it as a polygonal shape, it is good also as a shape with rounded corners.

Next, the insulator 15, the insulator 14, and the insulator 13 are etched using the hard mask 16 as an etching mask until the upper surface of the conductor 12 is exposed.
5a, an insulator 14a, and an insulator 13a are formed. Here, the etching film thickness of the hard mask 16 becomes thinner and becomes a hard mask 16a. Note that it is preferable to use dry etching for etching.

As a dry etching device, a capacitively coupled plasma (CCP:
A Capacitively Coupled Plasma) etching apparatus can be used. A capacitively coupled plasma etching apparatus having parallel plate type electrodes may have a configuration in which a high frequency power source is applied to one electrode of the parallel plate type electrodes. Alternatively, a configuration may be adopted in which a plurality of different high frequency power sources are applied to one electrode of a parallel plate type electrode. Alternatively, a configuration may be adopted in which a high frequency power source having the same frequency is applied to each of the parallel plate type electrodes. Alternatively, a configuration may be adopted in which high frequency power sources having different frequencies are applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source is, for example, an inductively coupled plasma (ICP).
A plasma etching device or the like can be used.

By-products may be formed on the sides of the opening 17. By-products are insulator 13, insulator 1
4. Components contained in the insulator 15 or the hard mask 16, or the insulator 13 and the insulator 1
4 or the components contained in the etching gas of the insulator 15. By-products are
It can be removed by performing plasma treatment using a gas containing O ₂ gas.

Furthermore, oxides of the conductor 12 may be generated at the bottom portion of the opening 17 where the conductor 12 is exposed. This oxide can be removed by cleaning with pure water or a chemical solution (see FIGS. 5C and 5D).

Next, a metal 20 containing nitrogen is formed in the opening 17 . As the nitrogen-containing metal 20, it is preferable to use a conductor that is less permeable to hydrogen than the conductor 21. Metals with nitrogen 2
It is preferable to use tantalum nitride or titanium nitride, especially tantalum nitride. By providing such a metal 20 containing nitrogen, diffusion of impurities such as hydrogen and water into the conductor 21 can be suppressed. Further, it is possible to obtain effects such as preventing diffusion of metal components contained in the conductor 21, preventing oxidation of the conductor 21, and improving adhesion of the conductor 21 to the opening 17. Furthermore, when forming the metal 20 containing nitrogen in a laminated manner, titanium, tantalum, titanium nitride, tantalum nitride, or the like may be used, for example. In addition, when forming a film of tantalum nitride as a metal containing nitrogen, RTA (Rapid
Heat treatment may be performed using a thermal annealing device.

The metal 20 containing nitrogen can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the metal 20 containing nitrogen is
It is preferable that the film be formed with good coverage so as to cover the inner wall and bottom surface of the film. For example, it is preferable to use a collimated sputtering method, an MCVD method, an ALD method, or the like.

The collimated sputtering method can perform directional film formation by installing a collimator between the target and the substrate. That is, sputtered particles having a component perpendicular to the substrate pass through the collimator and reach the substrate. This makes it easier for the sputtered particles to reach the bottom surface of the opening 17 having a high aspect ratio, so that a sufficient film can be formed on the bottom surface of the opening 17 as well.

Furthermore, by forming the metal 20 containing nitrogen into a film using the ALD method, the metal 20 containing nitrogen can be formed into a film with good coverage, and pinholes etc. are not formed in the metal 20 containing nitrogen. can be suppressed. By forming the metal 20 containing nitrogen in this manner, it is possible to further suppress impurities such as hydrogen and water from passing through the metal 20 containing nitrogen and diffusing into the conductor 21. For example, when forming a film of tantalum nitride as the nitrogen-containing metal 20 using the ALD method, pentakis(dimethylamino)tantalum (structural formula: Ta[N
(CH ₃ ) ₂ ] ₅ ) can be used as a precursor.

If the ALD method or the like is used to form a film of the metal 20 containing nitrogen, the metal 20 containing nitrogen may be formed with high electrical resistivity. If the electrical resistivity of the metal 20 containing nitrogen becomes high, a problem may occur in the electrical connection with the conductor 12.

Here, a method for reducing the resistance of a metal containing nitrogen, which is one embodiment of the present invention, will be described.
By irradiating the metal 20 containing nitrogen with plasma containing a rare gas, the electrical resistivity of the metal 20 containing nitrogen can be lowered. Specifically, by irradiating plasma using, for example, argon gas, the surface of the metal 20 containing nitrogen is irradiated with positive ions of argon in the plasma. Since positive ions of argon are accelerated by the electric field in the plasma, for example, if the direction of the electric field is perpendicular to a plane parallel to the back surface of the substrate, the positive ions of argon are irradiated in the direction of the electric field. Therefore, since the surface of the metal 20 having nitrogen formed on the side surface of the opening 17 faces approximately parallel to the direction of the electric field, the amount of positive ion irradiation of argon is reduced. It is difficult to reduce the resistance of the metal 20. On the other hand, the region facing substantially parallel to the back surface of the substrate faces perpendicular to the direction of the electric field and is therefore irradiated with more positive argon ions, so that the region facing substantially parallel to the back surface of the substrate has a lower resistance. Therefore, electrical connection with the exposed portion of the conductor 12 at the bottom of the opening 17 is favorable, which is preferable. The direction of ion irradiation is indicated by an arrow in FIG. 6(A). Further, a region where the resistance of the nitrogen-containing metal 20 is reduced by ion irradiation is indicated by a dotted line (see FIGS. 6A and 6B).

As a device for performing plasma processing, a dry etching device, a PECVD device, a high-density plasma device, a sputtering device, etc. can be used. In particular, when a sputtering device is used, it is preferable that the sputtering device has a reverse sputtering function.

In film formation by sputtering, the electric field is usually set so that the positive ions in the plasma move toward the target, but in reverse sputtering, the positive ions in the plasma
This refers to processing by switching the electric field so that it goes in the direction of the substrate rather than the target.

Next, an example using tantalum nitride will be described regarding the mechanism by which the resistance of a metal containing nitrogen is reduced by ion irradiation. Tantalum nitride includes not only Ta and N bonds but also Ta and O bonds. Tantalum nitride, which has a large proportion of Ta and N bonds, has a low resistivity, but as the proportion of Ta and O bonds increases, the resistivity increases. Therefore, the ratio of Ta and N bonds in tantalum nitride can be increased by cutting the bonds between Ta and O and reducing the bonds between Ta and O by physical damage caused by ion irradiation. As a result, it is thought that the resistance of tantalum nitride can be lowered.

Alternatively, if tantalum nitride is formed using ALD, etc., the area near the surface of tantalum nitride will be
The proportion of Ta and O bonds may be larger than that of Ta and N bonds. It is thought that it is possible to lower the resistance of tantalum nitride by removing the high-resistance portion with a large proportion of Ta and O bonds through physical damage caused by ion irradiation. The high-resistance portion with a large proportion of Ta and O bonds is located at a distance of 3 nm or less from the surface, or 5 nm or less from the surface.

Next, a conductor 21 is formed on the metal 20 containing nitrogen so as to fill the opening 17. (See FIGS. 6(C) and (D).).

Examples of the conductor 21 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or in a stacked layer. Conductor 21
The film formation can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, a plating method, or the like. Here, since the conductor 21 is formed so as to fill the opening 17, it is preferable to use a CVD method (particularly an MCVD method) or a plating method.

Next, the conductor 21, the metal 20 containing nitrogen, the hard mask 16a, and the insulator 15a are polished to form the metal 20a containing nitrogen and the conductor 21a embedded in the opening 17 (see FIG. ) and (B).). Polishing treatments include mechanical polishing, chemical polishing, and chemical mechanical polishing.
CMP) etc. may be performed.

Here, the opening 17 functions as a via hole, a contact hole, or the like. A metal 20a containing nitrogen and a conductor 21a are embedded in the opening 17 and function as a plug.

Here, in the semiconductor device described in this embodiment, an oxide semiconductor is provided over a semiconductor substrate, and the stacked insulator and the insulator are provided between the semiconductor substrate and the oxide semiconductor. A conductor is provided which functions as a plug and is embedded in the formed opening. In the semiconductor device described in this embodiment, a transistor is formed using an oxide semiconductor, and an element layer including the transistor is formed over an element layer including a semiconductor substrate. A transistor may be formed in an element layer including a semiconductor substrate. Further, an element layer including a capacitor or the like may be provided as appropriate. For example, an element layer containing a capacitor or the like may be formed on an element layer containing an oxide semiconductor, or between an element layer containing a semiconductor substrate and an element layer containing an oxide semiconductor. good.
Here, since the insulator 14a has a function of blocking the diffusion of hydrogen and water, impurities such as hydrogen and water diffuse from the insulator 13a through the insulator 14a into the element layer including the oxide semiconductor. can be prevented from happening. Furthermore, the metal 20 containing nitrogen has a function of blocking the diffusion of hydrogen and water, and the metal 20 containing nitrogen has the function of blocking the diffusion of hydrogen and water.
It is designed to block the As a result, the conductor 2 is placed in the opening 17 of the insulator 14a.
It is possible to prevent impurities such as hydrogen and water from diffusing into the element layer including the oxide semiconductor through 1.

In this way, the insulator 14a and the nitrogen-containing metal 20a are connected between the semiconductor substrate and the oxide semiconductor.
As a result, impurities such as hydrogen or water contained in the element layer including the semiconductor substrate are diffused into the upper layer through the plug (conductor 21) and via hole (opening 17) formed in the insulator 14a. You can keep things in check. Particularly when using a silicon substrate as a semiconductor substrate, hydrogen is used to terminate dangling bonds in the silicon substrate, so the amount of hydrogen contained in the element layer containing the semiconductor substrate is large, and even the element layer containing the oxide semiconductor. Although there is a risk that hydrogen will diffuse, the structure shown in this embodiment can prevent hydrogen from diffusing into the element layer including an oxide semiconductor.

It is preferable that the oxide semiconductor has reduced impurities such as hydrogen or water, has a low carrier density, and is highly pure or substantially pure. By forming a transistor using such an oxide semiconductor, the electrical characteristics of the transistor can be stabilized. Further, by using an oxide semiconductor that is highly pure or substantially pure, leakage current when the transistor is non-conductive can be reduced. Further, by using an oxide semiconductor that is highly pure or substantially pure, the reliability of the transistor can be improved.

<Plug manufacturing method 2>
Below, regarding plugs with different configurations from those in FIGS. 1(A) and (B), FIGS. 1(C) and (D)
This will be explained using a cross-sectional view and a top view. Figure 1 (C) and (D) are
2 shows a cross-sectional view and a top view corresponding to FIG.

FIGS. 1(C) and 1(D) are completed views of the plug, including a metal 20a containing nitrogen embedded in openings 17 formed in insulators 13a, 14a, and 15a, and a conductor 22a.
and the conductor 21a. Here, the opening 17 functions as a via hole or the like, and functions as a plug in which the metal 20a containing nitrogen, the conductor 21a, and the conductor 22a are embedded in the opening 17. The plug shown in FIGS. 1(A) and (B) is
The difference is that a conductor 22a is disposed between a metal 20a containing nitrogen and a conductor 21a. Further, on the bottom surface of the opening 17, the nitrogen-containing metal 20a in the region where the nitrogen-containing metal 20a and the conductor 12 are in contact has a region where the resistance is reduced. In FIG. 1C, a region where the resistance of the nitrogen-containing metal 20a is reduced is indicated by a dotted line.

The method for manufacturing this plug shown in FIGS. 1(C) and (D) is the same as plug manufacturing method 1 until the metal 20 containing nitrogen is deposited and plasma treatment is performed (FIG. 6(A) ) and (B).). Plasma treatment method and nitrogen-containing metal 20a by plasma treatment
Regarding the effect of lowering the resistance, the above-mentioned plug manufacturing method 1 is taken into consideration.

Furthermore, after performing reverse sputtering as the plasma treatment, for example, the conductor that will become the conductor 22a may be formed by sputtering. This method can be carried out continuously in the same sputtering apparatus, and is therefore expected to improve productivity.

As the conductor that becomes the conductor 22a, it is preferable to use, for example, tantalum nitride or titanium nitride, particularly tantalum nitride. Further, the conductor that becomes the conductor 22a can also be a laminated film. For example, a laminated film of tantalum nitride and tantalum can be used. By forming a laminated film of tantalum nitride and tantalum, when copper is used as the conductor 21a, the adhesion between copper and tantalum is improved, which is preferable.

Regarding the subsequent manufacturing steps and effects, the above-mentioned plug manufacturing method 1 will be referred to. With this, the plug shown in FIGS. 1(C) and 1(D) can be manufactured.

<Wiring and plug manufacturing method 1>
The cross-sectional views and top views illustrated in FIGS. 2A and 2B and FIGS. 7 to 11 will be described below with respect to the structure and manufacturing method of wiring and plugs as part of the structure of a semiconductor device according to one embodiment of the present invention. This will be explained using figures. 2A and 2B and FIGS. 7 to 11 show a cross-sectional view and a top view corresponding to the dashed line X1-X2.

2A and 2B are completed diagrams of the wiring and the plug, and FIGS. 7 to 11 show the conductor 12 (hereinafter sometimes referred to as a conductive film or wiring), the insulator 13a, and the insulator 13a. The process of connecting the conductor 21a to the metal 20a containing nitrogen embedded in the opening 17f formed in the insulator 14b and the insulator 15c will be described. Here, the shape of the opening 17f is different between the upper part and the lower part, and the lower part of the opening 17f (hereinafter referred to as opening 17fa) functions as a via hole or contact hole, and the upper part of opening 17f (hereinafter referred to as opening 17fb). ) functions as a groove in which a wiring pattern or the like is embedded. Therefore, the portion of the metal 20a containing nitrogen and the portion of the conductor 21a embedded in the opening 17fa functions as a plug, and the portion of the metal 20a containing nitrogen and the portion of the conductor 21a embedded in the opening 17fb functions as a wiring or the like. Further, on the bottom surface of the opening 17fa, the nitrogen-containing metal 20a in the region where the nitrogen-containing metal 20a and the conductor 12 are in contact has a region where the resistance is reduced. In FIG. 2A, a region where the resistance of the nitrogen-containing metal 20a is reduced is indicated by a dotted line.

First, a conductor 12 is formed on a substrate. The conductor 12 may have a single layer structure or a laminated structure. Note that the substrate is not illustrated in FIGS. 2A and 2B and FIGS. 7 to 11. Further, another conductor, an insulator, a semiconductor, or the like may be provided between the substrate and the conductor 12.

The conductor 12 may be formed using the same method as that for the nitrogen-containing metal 20, the conductor 21, and the like.

Next, an insulator 13 is formed on the conductor 12 . The insulator 13 may have a single layer structure or a laminated structure. The insulator 13 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, an insulator 14 is formed on the insulator 13. The insulator 14 may have a single layer structure or a laminated structure. The insulator 14 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

It is preferable to use a material for the insulator 14 that is less permeable to hydrogen and water than the insulator 13. Examples of the insulator 14 include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide,
Hafnium oxynitride or the like can be used. By using these as the insulator 14, it can function as an insulating film that blocks the diffusion of hydrogen and water.

Next, an insulator 15 is formed on the insulator 14. The insulator 15 may have a single layer structure or a laminated structure. The insulator 15 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a material for the hard mask 16 is formed on the insulator 15 . Here, hard mask 16
As the material, a conductor such as a metal material or an insulator may be used. Further, the material of the hard mask 16 may be formed as a single layer or as a laminated layer of an insulator and a conductor. Note that in this specification and the like, the term "hard mask" refers to a mask made using a material other than resist (metal material or insulating material). The material of the hard mask 16 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, a hard mask 1 is formed using a resist mask formed using a lithography method or the like.
6 is etched to form a hard mask 16 having an opening 17a (FIG. 7(A)
See (B). ). Here, FIG. 7(A) is a cross-sectional view corresponding to the dashed line X1-X2 shown in FIG. 7(B). Similarly, a cross-sectional view and a top view are shown below, corresponding to the dashed dotted line X1-X2.

Here, the opening 17a corresponds to an opening 17fb to be formed in a later step, that is, a groove in which a wiring pattern is to be embedded. Therefore, the top surface shape of the opening 17a corresponds to the wiring pattern.

Next, a resist mask 1 having an opening 17b is placed on the insulator 15 and the hard mask 16.
8a (see FIGS. 7(C) and 7(D)). Here, the resist mask 18a is preferably formed to cover the hard mask 16. Note that simply forming a resist also includes forming an organic coating film or the like under the resist.

Here, the opening 17b corresponds to an opening 17fa, that is, a via hole or a contact hole, which will be formed in a later step. Therefore, the top surface shape of the opening 17b corresponds to a via hole or a contact hole. Furthermore, it is preferable that the opening 17b corresponding to the via hole or the contact hole be formed in the opening 17a corresponding to the groove in which the wiring pattern is embedded. In this case, the maximum width of the opening 17b is equal to or less than the minimum width of the opening 17a. For example, the width of the opening 17b in the X1-X2 direction shown in FIGS.
A) The width in the X1-X2 direction of the opening 17a shown in (B) is smaller than or equal to the width. By doing so, the via hole or contact hole can be formed with a margin relative to the groove of the wiring pattern.

Although the opening 17b has a circular upper surface, it is not limited to this. For example, the upper surface may have an elliptical shape or a polygonal shape such as a triangle or a quadrangle. Moreover, when setting it as a polygonal shape, it is good also as a shape with rounded corners.

Next, using the resist mask 18a, the insulator 15 is etched to form an insulator 15a having an opening 17c (see FIGS. 8A and 8B). Here, etching is performed in the opening 17c until the upper surface of the insulator 14 is exposed. Note that dry etching is preferably used for the etching.

Next, the insulator 14 is etched using the resist mask 18a to form an insulator 14a having an opening 17d (see FIGS. 8C and 8D). Here, etching is performed in the opening 17d until the upper surface of the insulator 13 is exposed. Note that it is preferable to use dry etching for the etching. As the dry etching device, one similar to that described above can be used.

Further, when forming the opening 17d, it is not necessarily necessary to stop the etching at the upper surface of the insulator 13. For example, the opening 17d may be formed, and then a portion of the insulator 13 may be etched to form an insulator having a recess formed at a position overlapping the opening 17d.

Next, the resist mask 18a is removed (see FIGS. 9A and 9B). resist mask 1
If an organic coating film is formed under the resist mask 8a, it is preferable to remove it together with the resist mask 18a. The resist mask 18a can be removed by performing a dry etching process such as ashing, by performing a wet etching process, by performing a wet etching process in addition to a dry etching process, or by performing a dry etching process in addition to a wet etching process. can.

Further, after removing the resist mask 18a, by-products may be formed to surround the upper edge of the opening 17c. The by-product is formed containing a component contained in the insulator 14, the insulator 15, or the resist mask 18a, or a component contained in the etching gas for the insulator 14 or the insulator 15. The by-product can be removed when forming the opening 17e in the next step.

Next, using the hard mask 16, the insulator 13, the insulator 14a, and the insulator 15a are etched to form the insulator 13a, the insulator 14b, and the insulator 15b in which the opening 17e is formed (FIG. 9(C) ) (See D). Here, etching is performed until the upper surface of the conductor 12 is exposed in the opening 17e. Further, at this time, the edges of the openings 17a of the hard mask 16 may also be etched to form the hard mask 16a. In the hard mask 16a, the edge of the opening 17a has a tapered shape, and the upper part of the edge of the opening 17a has a rounded shape.
Note that it is preferable to use dry etching for the etching. As the dry etching device, one similar to that described above can be used.

Here, the opening 17e is located at the lower part and is formed using the insulator 14a as a mask.
ea and an opening 17eb located above and formed using the hard mask 16 as a mask. The opening 17ea will function as a via hole or contact hole in a later process, and the opening 17eb will function as a groove in which a wiring pattern or the like will be buried in a later process.

It is preferable that the edge of the opening 17eb (which can also be called an inner wall of the opening 17eb) of the insulator 15b has a tapered shape. Note that, as shown in FIG. 9(D), the tapered portion of the insulator 15b may be formed so as to be visible from the top surface.

It is preferable that the edge of the opening 17ea (also referred to as the inner wall of the opening 17ea) of the insulator 13a and the insulator 14b has a tapered shape. Moreover, the opening 17ea of the insulator 14b
Preferably, the upper part of the edge is rounded. By forming the opening 17ea in such a shape, the metal 20 containing nitrogen, which has a high blocking performance against hydrogen, can be formed with good coverage in a later step. Note that, as shown in FIG. 9(D), the tapered portion of the insulator 13a may be formed so as to be visible from the top surface.

In order to etch the opening 17ea into such a shape, in the dry etching, it is preferable not to make the etching rate of the insulator 13 excessively larger than the etching rate of the insulator 14a. For example, the etching rate of the insulator 13 may be 8 times or less, preferably 6 times or less, and more preferably 4 times or less than the etching rate of the insulator 14a.

By performing the dry etching under such conditions, a tapered shape can be formed at the edge of the opening 17ea. Furthermore, even if by-products are formed, the by-products can be removed to form a shape in which the upper part of the edge of the opening 17ea of the insulator 14b has a rounded shape.

However, the shape of the opening 17e is not necessarily limited to the above shape. For example, the inner walls of the opening 17ea and the opening 17eb may be formed substantially vertically.
Further, the opening 17eb may be formed in the insulator 15b and the insulator 14b, or the opening 17eb may be formed in the insulator 15b, the insulator 14b, and the insulator 13a.

Next, a film of metal 20 containing nitrogen is formed in the opening 17e. Here, metal 2 with nitrogen
It is preferable that the film 0 be formed with good coverage so as to cover the inner wall and bottom surface of the opening 17e. In particular, it is preferable that the metal 20 containing nitrogen is in contact with the insulator 14b at the edge of the opening 17e, and it is more preferable that the metal 20 containing nitrogen closes the opening formed in the insulator 14b. As described above, by tapering the edge of the opening 17ea of the insulator 14b and rounding the upper part of the edge of the opening 17ea of the insulator 14b, the coverage of the nitrogen-containing metal 20 is further improved. be able to.

As the nitrogen-containing metal 20, it is preferable to use a conductor that is less permeable to hydrogen than the conductor 21. As the nitrogen-containing metal 20, it is preferable to use tantalum nitride or titanium nitride, particularly tantalum nitride. By providing such a metal 20 containing nitrogen, diffusion of impurities such as hydrogen and water into the conductor 21 can be suppressed. Further, it is possible to obtain effects such as preventing diffusion of metal components contained in the conductor 21, preventing oxidation of the conductor 21, and improving adhesion of the conductor 21 to the opening 17e. Furthermore, when forming the metal 20 containing nitrogen in a laminated manner, titanium, tantalum, titanium nitride, tantalum nitride, or the like may be used, for example. In addition, when forming a film of tantalum nitride as a metal containing nitrogen,
After film formation, heat treatment using an RTA apparatus may be performed.

The metal 20 containing nitrogen can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Here, the metal film containing nitrogen is preferably formed by a method that provides good coverage, such as collimated sputtering, MCVD, or ALD.

Here, the collimated sputtering method can perform directional film formation by installing a collimator between the target and the substrate. That is, sputtered particles having a component perpendicular to the substrate pass through the collimator and reach the substrate. This makes it easier for the sputtered particles to reach the bottom surface of the opening 17ea, which has a high aspect ratio, so that a sufficient film can be formed on the bottom surface of the opening 17ea. Further, by tapering the inner walls of the openings 17ea and 17eb as described above, it is possible to form a film sufficiently on the inner walls of the openings 17ea and 17eb.

Furthermore, by forming the metal 20 containing nitrogen into a film using the ALD method, the metal 20 containing nitrogen can be formed into a film with good coverage, and pinholes etc. are not formed in the metal 20 containing nitrogen. can be suppressed. By forming the metal 20 containing nitrogen in this manner, it is possible to further suppress impurities such as hydrogen and water from passing through the metal 20 containing nitrogen and diffusing into the conductor 21. For example, when forming a film of tantalum nitride as the nitrogen-containing metal 20 using the ALD method, pentakis(dimethylamino)tantalum (structural formula: Ta[N
(CH ₃ ) ₂ ] ₅ ) can be used as a precursor.

If the ALD method or the like is used to form a film of the metal 20 containing nitrogen, the metal 20 containing nitrogen may be formed with high electrical resistivity. If the electrical resistivity of the metal 20 containing nitrogen becomes high, a problem may occur in the electrical connection with the conductor 12.

Here, a method for reducing the resistance of a metal containing nitrogen, which is one embodiment of the present invention, will be described.
By irradiating the metal 20 containing nitrogen with plasma containing a rare gas, the electrical resistivity of the metal 20 containing nitrogen can be lowered. Specifically, by irradiating plasma using, for example, argon gas, the surface of the metal 20 containing nitrogen is irradiated with positive ions of argon in the plasma. Since positive ions of argon are accelerated by the electric field in the plasma, for example, if the direction of the electric field is perpendicular to a surface substantially parallel to the back surface of the substrate, the positive ions of argon are irradiated in the direction of the electric field. Therefore, since the surface of the metal 20 having nitrogen formed on the side surface of the opening 17e faces approximately parallel to the electric field direction, the amount of positive ion irradiation of argon is reduced, so that the surface of the metal 20 having nitrogen formed on the side surface of the opening 17e is It is difficult to reduce the resistance of the metal 20. On the other hand, the region facing substantially parallel to the back surface of the substrate faces perpendicular to the direction of the electric field and is therefore irradiated with more positive argon ions, so that the region facing substantially parallel to the back surface of the substrate has a lower resistance. Therefore, opening 1
This is preferable because it provides good electrical connection with the exposed portion of the conductor 12 on the bottom surface of 7e. Note that among the regions where the insulator 14b and the nitrogen-containing metal 20 are in contact, the resistance of the nitrogen-containing metal 20 in a region substantially parallel to the back surface of the substrate is also reduced. In FIG. 10(A), the direction of ion irradiation is indicated by an arrow. Furthermore, a region where the resistance of the nitrogen-containing metal 20 is reduced by ion irradiation is indicated by a dotted line. (See FIGS. 10(A) and (B).)

As a device for performing plasma processing, a dry etching device, a PECVD device, a high-density plasma device, a sputtering device, etc. can be used. In particular, when a sputtering device is used, it is preferable that the sputtering device has a reverse sputtering function.

In film formation by sputtering, the electric field is usually set so that the positive ions in the plasma move toward the target, but in reverse sputtering, the positive ions in the plasma
This refers to processing by switching the electric field so that it goes in the direction of the substrate rather than the target.

Next, an example using tantalum nitride will be described regarding the mechanism by which the resistance of a metal containing nitrogen is reduced by ion irradiation. Tantalum nitride includes not only Ta and N bonds but also Ta and O bonds. Tantalum nitride, which has a large proportion of Ta and N bonds, has a low resistivity, but as the proportion of Ta and O bonds increases, the resistivity increases. Therefore, the ratio of Ta and N bonds in tantalum nitride can be increased by cutting the bonds between Ta and O and reducing the bonds between Ta and O by physical damage caused by ion irradiation. As a result, it is thought that the resistance of tantalum nitride can be lowered.

Alternatively, if tantalum nitride is formed using ALD, etc., the area near the surface of tantalum nitride will be
The proportion of Ta and O bonds may be larger than that of Ta and N bonds. It is thought that it is possible to lower the resistance of tantalum nitride by removing the high-resistance portion with a large proportion of Ta and O bonds through physical damage caused by ion irradiation. The high-resistance portion with a large proportion of Ta and O bonds is located at a distance of 3 nm or less from the surface, or 5 nm or less from the surface.

Next, a conductor 21 is formed on the metal 20 containing nitrogen so as to fill the opening 17e. (
See FIGS. 11(A) and (B). ).

Examples of the conductor 21 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, A conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or in a stacked layer. Conductor 21
The film formation of the conductor 21 is performed by sputtering method, CVD method, MBE method, PLD method, A
This can be done using an LD method, a plating method, or the like. Here, since the conductor 21 is formed so as to fill the opening 17e, it is preferable to use a CVD method (particularly an MCVD method) or a plating method.

Next, the conductor 21, the metal 20 containing nitrogen, the hard mask 16a, and the insulator 15b are polished, and the metal 20a containing nitrogen and the conductor 21a are embedded in the opening 17f.
(See FIGS. 11(C) and 11(D).) As the polishing treatment, mechanical polishing, chemical polishing, CMP, etc. may be performed. For example, by performing a CMP process, the insulator 15b, the conductor 2
1 and the upper part of the metal 20 containing nitrogen and the hard mask 16a can be removed to form an insulator 15c with a flat upper surface, a conductor 21a, and a metal 20a containing nitrogen.

Here, the opening 17f can be seen to be composed of an opening 17fa located at the bottom and functioning as a via hole or a contact hole, and an opening 17fb located at the top and functioning as a groove in which a wiring pattern or the like is buried. . Opening 17fa is formed in insulator 13a and insulator 14b, and opening 17fb is formed in insulator 15c. The portion of the nitrogen-containing metal 20a and the conductor 21a that is embedded in the opening 17fa functions as a plug, and the portion of the nitrogen-containing metal 20a and the conductor 21a that is embedded in the opening 17fb functions as a wiring or the like.

It is preferable that the metal 20a containing nitrogen is in contact with the insulator 14b at the edge of the opening 17fa. It is more preferable that the nitrogen-containing metal 20a is in contact with the rounded upper part of the opening 17fa of the insulator 14b, the tapered part of the edge of the opening 17fa, and the nitrogen-containing metal 20a is in contact with the upper surface of the insulator 14b. It is even more preferable that Furthermore, metal 2 with nitrogen
0a is preferably in contact with the inner wall of the opening 17fa of the insulator 13a and the inner wall of the opening 17fb of the insulator 15c.

Further, as shown in this embodiment, after forming the opening 17e consisting of the opening 17ea which functions as a via hole or contact hole, and the opening 17eb which functions as a groove in which a wiring pattern or the like is buried, the metal 20 containing nitrogen is formed. By forming the film, a portion of the nitrogen-containing metal 20a that functions as a wiring and a portion that functions as a plug are formed integrally. As a result, the nitrogen-containing metal 20a is continuously formed near the boundary between the opening 17ea and the opening 17eb, for example, so that the blocking function against hydrogen and water can be further improved. In addition, when forming interconnects and plugs using the single damascene method, conductive film formation and polishing treatment such as CMP treatment are required for plug formation and wiring formation, respectively. In the method shown in the embodiment, the formation of a conductive film for forming wiring and plugs and polishing treatment such as CMP treatment can be completed in one time, so that the number of steps can be shortened.

Here, in the semiconductor device described in this embodiment, an oxide semiconductor is provided over a semiconductor substrate, and the stacked insulator and the insulator are provided between the semiconductor substrate and the oxide semiconductor. A conductor, which functions as a wiring and a plug, is embedded in the formed opening. In the semiconductor device described in this embodiment, a transistor is formed using an oxide semiconductor, and an element layer including the transistor is formed over an element layer including a semiconductor substrate.
A transistor may be formed in an element layer including a semiconductor substrate. Further, an element layer including a capacitor or the like may be provided as appropriate. For example, an element layer containing a capacitor or the like may be formed on an element layer containing an oxide semiconductor, or between an element layer containing a semiconductor substrate and an element layer containing an oxide semiconductor. good.

In a semiconductor device having such a configuration, as shown in FIGS. 11C and 11D, the insulator 14b
It is preferable that the nitrogen-containing metal 20a be in contact with the edge of the opening 17fa formed in the opening 17fa. In other words, the opening 17fa formed in the insulator 14b is connected to the nitrogen-containing metal 20a.
It is preferable that the shape is closed with.

Here, since the insulator 14b has a function of blocking the diffusion of hydrogen and water, impurities such as hydrogen and water diffuse from the insulator 13a through the insulator 14b into the element layer including the oxide semiconductor. can be prevented from happening. Furthermore, the metal 20 containing nitrogen has a function of blocking the diffusion of hydrogen and water, and the metal 20 containing nitrogen has a function of blocking the diffusion of hydrogen and water.
It is designed to block the This can prevent impurities such as hydrogen and water from diffusing into the element layer including the oxide semiconductor through the conductor 21 in the opening 17f of the insulator 14b.

In this way, the insulator 14b and the nitrogen-containing metal 20a are connected between the semiconductor substrate and the oxide semiconductor.
By dividing the insulator 14b, impurities such as hydrogen or water contained in the element layer including the semiconductor substrate are diffused into the upper layer through the plug (conductor 21) and via hole (opening 17fa) formed in the insulator 14b. You can keep things in check. Particularly when using a silicon substrate as a semiconductor substrate, hydrogen is used to terminate dangling bonds in the silicon substrate, so the amount of hydrogen contained in the element layer containing the semiconductor substrate is large, and even the element layer containing the oxide semiconductor. Although there is a risk that hydrogen will diffuse, the structure shown in this embodiment can prevent hydrogen from diffusing into the element layer including an oxide semiconductor.

As will be described in detail later, it is preferable that the oxide semiconductor has reduced impurities such as hydrogen or water, has a low carrier density, and is highly pure or substantially pure. By forming a transistor using such an oxide semiconductor, the electrical characteristics of the transistor can be stabilized. Further, by using an oxide semiconductor that is highly pure or substantially pure, leakage current when the transistor is non-conductive can be reduced. Further, by using an oxide semiconductor that is highly pure or substantially pure, the reliability of the transistor can be improved.

<Wiring and plug manufacturing method 2>
Below, regarding plugs with different configurations from those in FIGS. 2(A) and (B), FIGS. 2(C) and (D)
This will be explained using a cross-sectional view and a top view. FIGS. 2(C) and (D) are shown on the dashed line
2 shows a cross-sectional view and a top view corresponding to FIG.

FIG. 2(C) is a completed diagram of the wiring and the plug, showing the insulator 13a, the insulator 14b, and the insulator 1.
The metal 20a containing nitrogen embedded in the opening 17f formed in the opening 5c, the conductor 22a, and the conductor 21a are connected to each other. Here, the shape of the opening 17f is different between the upper part and the lower part, and the lower part of the opening 17f (hereinafter referred to as opening 17fa) functions as a via hole or contact hole, and the upper part of opening 17f (hereinafter referred to as opening 17fb). ) functions as a groove in which a wiring pattern or the like is embedded. Therefore, the portions of the nitrogen-containing metal 20a, the conductor 22a, and the conductor 21a that are embedded in the opening 17fa function as plugs, and the nitrogen-containing metal 20a, the conductor 22a, and the portions of the conductor 21a that are embedded in the opening 17fb function as wiring. It functions as such. The wiring and plug shown in FIGS. 2(A) and 2(B) are as follows:
The difference is that a conductor 22a is disposed between a metal 20a containing nitrogen and a conductor 21a. Further, on the bottom surface of the opening 17fa, the nitrogen-containing metal 20a in the region where the nitrogen-containing metal 20a and the conductor 12 are in contact has a region where the resistance is reduced. In FIG. 2C, a region where the resistance of the nitrogen-containing metal 20a is reduced is indicated by a dotted line.

The method for manufacturing the wiring and plug shown in FIGS. 2(C) and (D) is as follows:
The process from forming a film of 0 to performing plasma treatment is the same as the wiring and plug manufacturing method 1 (Figure 1
See 0(A) and (B). ). Regarding the method of plasma treatment and the effect of lowering the resistance of the nitrogen-containing metal 20a by plasma treatment, the above-mentioned wiring and plug manufacturing method 1 will be referred to.

Furthermore, after performing reverse sputtering as the plasma treatment, for example, the conductor that will become the conductor 22a may be formed by sputtering. This method can be carried out continuously in the same sputtering apparatus, and is therefore expected to improve productivity.

As the conductor that becomes the conductor 22a, it is preferable to use, for example, tantalum nitride or titanium nitride, particularly tantalum nitride. Further, the conductor that becomes the conductor 22a can also be a laminated film. For example, a laminated film of tantalum nitride and tantalum can be used. By forming a laminated film of tantalum nitride and tantalum, when copper is used as the conductor 21a, the adhesion between copper and tantalum is improved, which is preferable.

Regarding the subsequent manufacturing steps and effects, the above-mentioned wiring and plug manufacturing method 1 will be referred to.
With this, the wiring and plug shown in FIGS. 2(C) and 2(D) can be manufactured.

Note that the shapes of the wiring and the plug shown in this embodiment are not limited to the shapes shown in FIG. 2. Wires and plugs whose shapes differ from those shown in FIG. 2 are shown below.

The shape of the wiring and the plug shown in FIG. 3A differs from the shape shown in FIG. 2C in that the shape of the opening 17g is different from the shape of the opening 17f. It can be seen that the opening 17g is composed of an opening 17ga located at the bottom and functioning as a via hole or a contact hole, and an opening 17gb located at the top and functioning as a groove in which a wiring pattern or the like is buried. opening 1
7ga is formed under the insulator 13a and the insulator 14b, and the opening 17gb is formed under the insulator 15.
c and on top of the insulator 14b. Therefore, in the configuration shown in FIG. 3A, the portions of the nitrogen-containing metal 20a and the conductor 21a that function as wiring, etc. are the insulator 14b.
It is installed so that it is embedded in the upper part of the. Here, the inner wall of the opening provided in the insulator 14b is formed in a step-like manner, with the inner wall of the opening 17ga and the inner wall of the opening 17gb.

The shape of the wiring and plug shown in FIG. 3(B) differs from the shape shown in FIG. 2(C) in that the shape of the opening 17h is different from the shape of the opening 17f. The opening 17h can be seen to be composed of an opening 17ha located at the bottom and functioning as a via hole or a contact hole, and an opening 17hb located at the top and functioning as a groove in which a wiring pattern or the like is buried. opening 1
7ha is formed at the bottom of the insulator 13a, and the opening 17hb is formed at the top of the insulator 15c, the insulator 14b, and the insulator 13a. Therefore, in the configuration shown in FIG. 3B, the portions of the nitrogen-containing metal 20a and the conductor 21a that function as wiring, etc. are provided so as to be embedded in the upper part of the insulator 13a. Here, the inner wall of the opening provided in the insulator 13a is
The inner wall of the opening 17ha and the inner wall of the opening 17hb are formed in a stepped shape.

The shape of the wiring and the plug shown in FIG. 3(C) differs from the shape shown in FIG. 2(C) in that the shape of the opening 17i is different from the shape of the opening 17f. The opening 17i can be considered to be composed of an opening 17ia located at the bottom and functioning as a via hole or a contact hole, and an opening 17ib located at the top and functioning as a groove in which a wiring pattern or the like is buried. opening 1
7ia is formed in the insulator 13a, and an opening 17ib is formed in the insulator 15c and the insulator 14b. Therefore, in the configuration shown in FIG. 3C, portions of the nitrogen-containing metal 20a and the conductor 21a that function as wiring or the like are embedded in the insulator 14b. Here, the inner wall provided in the opening of the insulator 14b is formed into a gently tapered shape.

The shape of the wiring and the plug shown in FIG. 4A differs from the shape shown in FIG. 2C in that the shape of the opening 17j is different from the shape of the opening 17f. It can be seen that the opening 17j is composed of an opening 17ja located at the lower part and functioning as a via hole or a contact hole, and an opening 17jb located at the upper part functioning as a groove in which a wiring pattern or the like is buried. opening 1
7ja is formed in the insulator 13a and the insulator 14b, and the opening 17jb is formed in the insulator 15c. Therefore, in the configuration shown in FIG. 4A, portions of the nitrogen-containing metal 20a and the conductor 21a that function as wiring or the like are embedded in the insulator 15c. Here, the inner wall of the opening 17ja provided in the insulator 13a and the insulator 14b is connected to the conductor 1.
2 is provided substantially perpendicularly to. Furthermore, the inner wall of the opening 17jb provided in the insulator 15c is provided approximately perpendicularly to the insulator 14b. In addition, when the inner wall of the opening is provided substantially vertically in this way, in order to form the metal 20a containing nitrogen with a sufficient thickness on the inner wall of the opening, ALD is used.
It is preferable to form the metal 20a containing nitrogen using a method or the like.

The shapes of the wiring and plug shown in FIGS. 4(B) and 4(C) differ from the shape shown in FIG. 4(A) in that the shape of the opening 17k is different from the opening 17j. It can be seen that the opening 17k is composed of an opening 17ka located at the lower part and functioning as a via hole or a contact hole, and an opening 17kb located at the upper part and functioning as a groove in which a wiring pattern or the like is buried.
In the shapes of the wiring and plug shown in FIGS. 4(B) and 4(C), the maximum width of the opening 17ka is
This approximately matches the minimum width of kb. For example, X1- of the opening 17ka shown in FIGS.
The width in the X2 direction substantially matches the width of the opening 17 kb in the X1-X2 direction. By doing so, the area occupied by the wiring can be reduced. When forming the opening 17k, for example, the width in the X1-X2 direction of the opening 17a of the hard mask 16 shown in FIGS. 7(A) and (B) and the resist mask 18a shown in FIGS. 7(C) and (D) are determined. The widths of the openings 17b in the X1-X2 direction may be set to be approximately the same.

<Structure of transistor including oxide semiconductor film>
FIGS. 12A, 12B, and 12C show an example of a structure of a transistor 60a formed in an element layer containing an oxide semiconductor. FIG. 12A is a top view of the transistor 60a, and FIG.
(B) is a cross-sectional view corresponding to the channel length direction A1-A2 of the transistor 60a, and FIG.
2(C) is a cross-sectional view corresponding to the channel width direction A3-A4 of the transistor 60a. Note that the channel length direction of a transistor refers to the direction between the source (source region or source electrode) and the drain (drain region or drain electrode) in a plane parallel to the substrate.
The channel width direction means the direction in which carriers move, and the channel width direction means the direction perpendicular to the channel length direction in a plane parallel to the substrate.

Note that in some cross-sectional views such as FIG. 12(B) and FIG. 12(C), the ends of patterned conductors, semiconductors, or insulators are shown at right angles, but this embodiment The semiconductor device shown in is not limited to this, but may have a shape with rounded ends.

The transistor 60a includes a conductor 62a, a conductor 62b, an insulator 65, an insulator 63, an insulator 64, an insulator 66a, a semiconductor 66b, a conductor 68a, and a conductor 68b.
It has an insulator 66c, an insulator 72, and a conductor 74. Here, the conductor 62a and the conductor 62b function as a back gate of the transistor 60a, and the insulator 65, the insulator 63, and the insulator 64 function as a gate insulating film for the back gate of the transistor 60a. Further, the conductor 68a and the conductor 68b function as the source or drain of the transistor 60a. Further, the insulator 72 functions as a gate insulating film of the transistor 60a, and the conductor 74 functions as a gate of the transistor 60a.

Although the details will be described later, when the insulator 66a and the insulator 66c are used alone, the insulator 66a and the insulator 66c may be a conductor,
Materials that can function as semiconductors or insulators may be used. However, when stacking with the semiconductor 66b to form a transistor, electrons flow through the semiconductor 66b, near the interface between the semiconductor 66b and the insulator 66a, and near the interface between the semiconductor 66b and the insulator 66c; It has a region that does not function as a channel of the transistor. Therefore, in this specification and the like, the insulator 66a and the insulator 66c are not referred to as a conductor or a semiconductor, but are referred to as an insulator or an oxide insulator.

Note that in this embodiment and the like, the description of an insulator can also be translated as an insulating film or an insulating layer. Moreover, the description of a conductor can also be paraphrased as a conductive film or a conductive layer. Moreover, the description "semiconductor" can also be paraphrased as a semiconductor film or a semiconductor layer.

At the bottom of the transistor 60a, an insulator 67 having an opening is provided above the insulator 61, a conductor 62a is provided in the opening, and a conductor 62 is provided above the conductor 62a.
b is provided. At least a portion of the conductor 62a and the conductor 62b is an insulator 66.
a, a semiconductor 66b, and an insulator 66c. Here, the conductor 62a and the conductor 62b that function as the back gate of the transistor 60a can be manufactured in parallel with the conductor 21a and the conductor 21b that function as the above-described wiring and plug. Therefore, the insulator 61 corresponds to the insulator 14b, the insulator 67 corresponds to the insulator 15c, the conductor 62a corresponds to the nitrogen-containing metal 20a, and the conductor 62b corresponds to the conductor 21a.

An insulator 65 is provided on and in contact with the conductor 62a and the conductor 62b so as to cover the upper surfaces of the conductor 62a and the conductor 62b. An insulator 63 is provided on the insulator 65, and an insulator 64 is provided on the insulator 63.

Here, one end of the conductor 62a and the conductor 62b in the channel length direction overlaps with a part of the conductor 68a, and the other end of the conductor 62a and the conductor 62b in the channel length direction overlaps with a part of the conductor 68b. is preferred. By providing the conductor 62a and the conductor 62b in this manner, the region between the conductor 68a and the conductor 68b of the semiconductor 66b, that is, the channel formation region of the semiconductor 66b, can be sufficiently covered with the conductor 62a and the conductor 62b. I can do it. Thereby, the conductor 62a and the conductor 62b can more effectively control the threshold voltage of the transistor 60a.

An insulator 66a is provided on the insulator 64, and a semiconductor 66b is provided in contact with at least a portion of the upper surface of the insulator 66a. Note that in FIGS. 12(B) and (C), the insulator 66a
Although the insulator 66a and the semiconductor 66b are formed such that the end portions of the semiconductor 66b and the semiconductor 66b substantially coincide with each other, the structure of the semiconductor device shown in this embodiment is not limited to this.

A conductor 68a and a conductor 68b are formed in contact with at least a portion of the upper surface of the semiconductor 66b. The conductor 68a and the conductor 68b are formed apart from each other, and preferably are formed facing each other with the conductor 74 in between, as shown in FIG. 12(B).

An insulator 66c is provided in contact with at least a portion of the upper surface of the semiconductor 66b. Insulator 66c
is formed so as to cover the upper surface of the conductor 68a and the upper surface of the conductor 68b, and
It is preferable that a portion of the upper surface of the semiconductor 66b be in contact between the conductor 8a and the conductor 68b.

An insulator 72 is provided on the insulator 66c. The insulator 72 includes the conductor 68a and the conductor 68.
It is preferable to contact a part of the upper surface of the insulator 66c between the portions b.

A conductor 74 is provided on the insulator 72 . It is preferable that the conductor 74 contacts a part of the upper surface of the insulator 72 between the conductor 68a and the conductor 68b.

Further, an insulator 79 is provided to cover the conductor 74 . However, the insulator 79 does not necessarily need to be provided.

The insulator 66c is provided so as to cover the insulator 66a, the semiconductor 66b, the conductor 68a, and the conductor 68b, and to be in contact with the upper surface of the insulator 64.

However, the transistor 60a is not limited to the configuration shown in FIGS. 12A, 12B, and 12C. For example, the side surfaces of the insulator 66c, the insulator 72, and the conductor 74 in the A1-A2 direction may be aligned. Further, for example, the insulator 72 is the insulator 66
a, the semiconductor 66b, the conductor 68a, and the conductor 68b may be covered, and the structure may be provided so as to be in contact with the upper surface of the insulator 64.

Note that the conductor 74 includes the insulator 72, the insulator 66c, the insulator 64, the insulator 63, and the insulator 65.
It may also be configured to be connected to the conductor 62b through an opening formed in, for example.

An insulator 77 is provided on the insulator 66c and the insulator 79. Furthermore, the insulator 7
An insulator 78 is provided on top of 7 .

Next, a modification of the transistor 60a will be described using FIGS. 13(A), (B), and (C). Note that FIG. 13(A) is a top view of the transistor 60b, and FIGS. 13(B) and (C) are a cross-sectional view of the transistor 60b in the channel length direction and the same as FIGS. 12(B) and (C). 60b is a cross-sectional view in the channel width direction.

The transistor 60b shown in FIGS. 13A, 13B, and 13C includes an insulator 64, a conductor 6
An insulator 77 is provided on the conductor 8a and the conductor 68b, and the insulator 77 and the conductor 68a
12(A), (B), and (C) in that the insulator 66c, the insulator 72, and the conductor 74 are provided so as to be embedded in the opening formed in the conductor 68b.
This is different from the transistor 60a shown in FIG. Note that for other configurations of the transistor 60b shown in FIGS. 13(A), (B), and (C), the configuration of the transistor 60a shown in FIGS. 12(A), (B), and (C) can be referred to. can.

Further, the transistor 60b may have a configuration in which an insulator 76 is provided on an insulator 77 and an insulator 78 is provided on the insulator 76. At this time, an insulator that can be used for the insulator 77 may be used as the insulator 76. Further, although the transistor 60b is configured without the insulator 79, the present invention is not limited to this, and the insulator 79 may be provided.

However, the transistor 60b is not limited to the configuration shown in FIGS. 13A, 13B, and 13C. For example, the sides of the insulator 66c, the insulator 72, and the conductor 74 are the semiconductor 66c, the insulator 72, and the conductor 74.
It may have a tapered shape that is inclined at an angle of 30° or more and less than 90° with respect to the upper surface of 6b.

<Oxide semiconductor>
The oxide semiconductor used for the semiconductor 66b will be described below.

Preferably, the oxide contains at least indium or zinc. In particular, it is preferable to include indium and zinc. Moreover, in addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

Here, consider the case where the oxide contains indium, element M, and zinc. In addition, element M
may be aluminum, gallium, yttrium or tin. Other elements that can be used as the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above-mentioned elements may be combined.

First, a preferable range of the atomic ratio of indium, element M, and zinc contained in the oxide according to the present invention will be described with reference to FIGS. 14(A), 14(B), and 14(C). Note that, in FIG. 14, the atomic ratio of oxygen is not described. In addition, the terms of the atomic ratio of indium, element M, and zinc in the oxide are expressed as [In], [M], and [Zn].
shall be.

In FIGS. 14(A), 14(B), and 14(C), the broken lines indicate [In]:[M]
:[Zn]=(1+α):(1-α):A line with an atomic ratio of 1 (-1≦α≦1), [
A line with an atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):2, [I
n]:[M]:[Zn]=(1+α):(1-α):A line with an atomic ratio of 3, [In
]:[M]:[Zn]=(1+α):(1-α):A line with an atomic ratio of 4, and [
The line represents the atomic ratio of In]:[M]:[Zn]=(1+α):(1−α):5.

In addition, the dashed-dotted line is the line where the atomic ratio (β≧0) is [In]:[M]:[Zn]=1:1:β, [In]:[M]:[Zn]=1: 2: Line with the atomic ratio of β, [In]
:[M]:[Zn]=1:3:A line with an atomic ratio of β, [In]:[M]:[Zn]
A line with an atomic ratio of =1:4:β, a line with an atomic ratio of [In]:[M]:[Zn]=2:1:β, and a line with an atomic ratio of [In]:[M]:[Zn] ] = represents a line with an atomic ratio of 5:1:β.

Further, the two-dot chain line represents a line where the atomic ratio (-1≦γ≦1) is [In]:[M]:[Zn]=(1+γ):2:(1−γ). In addition, as shown in FIG. 14, [In]:[M]:[Z
An oxide having an atomic ratio of n]=0:2:1 or a value close thereto tends to have a spinel-type crystal structure.

14(A) and 14(B) show indium, which the oxide of one embodiment of the present invention has,
An example of a preferable range of the atomic ratio of element M and zinc is shown.

As an example, FIG. 15 shows InMZnO where [In]:[M]:[Zn]=1:1:1.
₄ is shown. Moreover, FIG. 15 shows InMZn when observed from a direction parallel to the b-axis.
This is the crystal structure of _O4 . Note that the layer containing M, Zn, and oxygen shown in FIG. 15 (hereinafter referred to as (M, Z
The metal element in layer n) represents the element M or zinc. In this case, it is assumed that the proportions of element M and zinc are equal. Element M and zinc can be substituted, and the arrangement is irregular.

InMZnO ₄ has a layered crystal structure (also referred to as a layered structure), as shown in FIG.
The number of layers containing indium and oxygen (hereinafter referred to as In layer) is 1, and the number of layers (M, Zn) containing element M, zinc, and oxygen is 2.

Furthermore, indium and element M can be substituted for each other. Therefore, the element M of the (M, Zn) layer can be replaced with indium, and it can also be expressed as an (In, M, Zn) layer. In that case, a layered structure is adopted in which there is one In layer and two (In, M, Zn) layers.

An oxide having an atomic ratio of [In]:[M]:[Zn]=1:1:2 has a layered structure in which there is one In layer and three (M, Zn) layers. In other words, [Z
n] increases, the ratio of the (M, Zn) layer to the In layer increases when the oxide crystallizes.

However, in the oxide, if the In layer is 1 and the (M, Zn) layer is a non-integer number, then I
There are cases in which there are multiple types of layered structures in which the number of n layers is 1 and the number of (M, Zn) layers is an integer number. For example, when [In]:[M]:[Zn]=1:1:1.5, the In layer is 1 and (M
, Zn) layers and a layered structure in which there are three (M, Zn) layers coexist in some cases.

For example, when forming an oxide into a film using a sputtering apparatus, a film having an atomic ratio different from that of the target is formed. In particular, depending on the substrate temperature during film formation, the target [Zn
] The [Zn] of the film may be smaller than that.

Furthermore, multiple phases may coexist in the oxide (two-phase coexistence, three-phase coexistence, etc.). for example,
At an atomic ratio that is close to the atomic ratio of [In]:[M]:[Zn]=0:2:1, two phases of a spinel crystal structure and a layered crystal structure tend to coexist. Also, [In]: [M]:
At an atomic ratio that is close to the atomic ratio of [Zn]=1:0:0, two phases of a bixbite crystal structure and a layered crystal structure tend to coexist. When multiple phases coexist in an oxide, grain boundaries (also referred to as grain boundaries) may be formed between different crystal structures.

Furthermore, by increasing the indium content, the carrier mobility (electron mobility) of the oxide can be increased. This is because in an oxide containing indium, element M, and zinc, the s orbitals of the heavy metal mainly contribute to carrier conduction, and by increasing the indium content, the area where the s orbitals overlap becomes larger. This is because an oxide with a high indium content has higher carrier mobility than an oxide with a low indium content.

On the other hand, when the content of indium and zinc in the oxide becomes low, carrier mobility becomes low. Therefore, at the atomic ratio showing [In]:[M]:[Zn]=0:1:0 and the atomic ratio that is the neighboring value (for example, region C shown in FIG. 14(C)), the insulating property becomes higher.

Therefore, the oxide of one embodiment of the present invention preferably has an atomic ratio shown in region A in FIG. 14(A), which tends to have a layered structure with high carrier mobility and few grain boundaries.

Moreover, the region B shown in FIG.
1 and its neighboring values are shown. Neighboring values include, for example, the atomic ratio [In]:[M]
:[Zn]=5:3:4 is included. The oxide having the atomic ratio shown in region B is an excellent oxide with particularly high crystallinity and high carrier mobility.

Note that the conditions under which the oxide forms a layered structure are not uniquely determined by the atomic ratio. There are differences in the difficulty of forming a layered structure depending on the atomic ratio. On the other hand, even if the atomic ratio is the same, it may or may not form a layered structure depending on the formation conditions. Therefore, the illustrated regions are regions in which the oxide exhibits an atomic ratio having a layered structure, and are regions A to C.
The boundaries are not strict.

Next, a case where the above oxide is used in a transistor will be described.

Note that by using the above oxide in a transistor, carrier scattering at grain boundaries and the like can be reduced, so a transistor with high field-effect mobility can be realized. Further, a highly reliable transistor can be realized.

Further, it is preferable to use an oxide with low carrier density for the transistor. for example,
The oxide has a carrier density of less than 8×10 ¹¹ /cm ³ , preferably 1×10 ¹¹ /cm ³
It is less than 1×10 ¹⁰ /cm ³ , more preferably less than 1×10 −9 /cm 3 , and may be 1×10 ⁻⁹ /cm ³ or more.

Note that since highly pure or substantially pure oxides have fewer carrier generation sources, the carrier density can be lowered. Further, since highly pure or substantially pure oxides have a low defect level density, the trap level density may also be low.

In addition, the charges trapped in the trap levels of the oxide take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor whose channel region is formed in an oxide with a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide. Further, in order to reduce the impurity concentration in the oxide, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

Here, the influence of each impurity in the oxide will be explained.

When an oxide contains silicon or carbon, which is one of the Group 14 elements, a defect level is formed in the oxide. For this reason, the concentration of silicon and carbon in the oxide and the concentration of silicon and carbon near the interface with the oxide (secondary ion mass spectrometry (SIMS)
ry Ion Mass Spectrometry), 2×1
0 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁷ atoms/cm ³ or less.

In addition, when an oxide contains an alkali metal or an alkaline earth metal, a defect level is formed,
May generate carriers. Therefore, transistors using oxides containing alkali metals or alkaline earth metals tend to have normally-on characteristics. For this reason, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the oxide. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide obtained by SIMS is
The concentration should be 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

Further, when nitrogen is contained in the oxide, electrons as carriers are generated, the carrier density increases, and the oxide is likely to become n-type. As a result, a transistor using an oxide containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide is
Less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, even more preferably 5×10 ¹⁷
Atoms/ ^cm3 or less.

Furthermore, hydrogen contained in the oxide reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the oxide be reduced as much as possible. Specifically, in oxides, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably 1×10 ¹⁹ atoms/cm ³
less than 5 x 10 atoms/cm3, more preferably less than ^{1 x 10} atoms/ ^cm3 , more preferably less than 1 x 10 atoms/cm3
Less than ¹⁸ atoms/ ^cm3 .

By using an oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be provided.

Next, a case where the oxide has a two-layer structure or a three-layer structure will be described. oxide S1,
The layered structure of oxide S2 and oxide S3, and the band diagram of the insulator in contact with the layered structure, and the layered structure of oxide S2 and oxide S3, and the band diagram of the insulator in contact with the layered structure. 16 will be used for explanation.

FIG. 16(A) shows insulator I1, oxide S1, oxide S2, oxide S3, and insulator I2.
FIG. 2 is an example of a band diagram in the film thickness direction of a laminated structure having . In addition, FIG. 16(B) shows the insulator I
1 is an example of a band diagram in the film thickness direction of a stacked structure including oxide S2, oxide S3, and insulator I2. Note that the band diagram shows the energy level (Ec) at the lower end of the conduction band of the insulator I1, oxide S1, oxide S2, oxide S3, and insulator I2 for easy understanding.

Oxide S1 and oxide S3 have an energy level at the bottom of the conduction band closer to the vacuum level than oxide S2, and typically, the energy level at the bottom of the conduction band of oxide S2 and oxide S1, Oxide S
The difference from the energy level of the lower end of the conduction band of No. 3 is 0.15 eV or more, or 0.5 eV or more,
And it is preferably 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of oxide S1 and oxide S3 and the electron affinity of oxide S2 is 0.15 eV or more, or 0.
．． It is preferably 5 eV or more and 2 eV or less, or 1 eV or less.

As shown in FIG. 16(A) and FIG. 16(B), oxide S1, oxide S2, oxide S3
, the energy level at the bottom of the conduction band changes gently. In other words, it can also be said to be continuously changing or continuously joining. In order to have such a band diagram, it is preferable to lower the defect level density of the mixed layer formed at the interface between oxide S1 and oxide S2 or at the interface between oxide S2 and oxide S3.

Specifically, the oxide S1 and the oxide S2, and the oxide S2 and the oxide S3 have a common element other than oxygen (as a main component), thereby forming a mixed layer with a low defect level density. be able to. For example, when the oxide S2 is an In--Ga--Zn oxide, it is preferable to use an In--Ga--Zn oxide, a Ga--Zn oxide, a gallium oxide, or the like as the oxide S1 and the oxide S3.

At this time, the main path of carriers is the oxide S2. Since the density of defect levels at the interface between oxide S1 and oxide S2 and the interface between oxide S2 and oxide S3 can be lowered, the influence of interfacial scattering on carrier conduction is small, and a high on-current can be achieved. can get.

When electrons are captured in the trap level, the captured electrons behave like fixed charges, so the threshold voltage of the transistor shifts in the positive direction. By providing the oxide S1 and the oxide S3, the trap level can be moved away from the oxide S2. With this configuration, it is possible to prevent the threshold voltage of the transistor from shifting in the positive direction.

For the oxide S1 and the oxide S3, materials whose conductivity is sufficiently lower than that of the oxide S2 are used.
At this time, the oxide S2, the interface between the oxide S2 and the oxide S1, and the interface between the oxide S2 and the oxide S
The interface with 3 mainly functions as a channel region. For example, as the oxide S1 and the oxide S3, oxides having the atomic ratio shown in the region C in FIG. 14C where the insulation property is high may be used. Note that region C shown in FIG. 14(C) indicates an atomic ratio that is [In]:[M]:[Zn]=0:1:0 or a value in the vicinity thereof.

In particular, when using an oxide having the atomic ratio shown in region A for the oxide S2, the oxide S1 and the oxide S3 have an oxide in which [M]/[In] is 1 or more, preferably 2 or more. It is preferable to use In addition, as the oxide S3, it is possible to obtain sufficiently high insulation properties [M]/
It is preferable to use an oxide in which ([Zn]+[In]) is 1 or more.

Note that the insulator 66a, semiconductor 66b, and insulator 66c are formed by sputtering, CVD, or MB.
The film can be formed using the E method, PLD method, ALD method, or the like.

Further, it is preferable that the insulator 66a, the semiconductor 66b, and the insulator 66c undergo a substrate heat treatment during film formation, or undergo a heat treatment after film formation. By performing such heat treatment, water or hydrogen contained in the insulator 66a, semiconductor 66b, insulator 66c, etc. can be further reduced. Further, excess oxygen can be supplied to the insulator 106a and the semiconductor 106b in some cases. The heat treatment is performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher4.
The temperature may be 50°C or lower, more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, heat treatment is performed in an inert gas atmosphere, and then 1% or more of oxidizing gas is added at 10 ppm or more to compensate for the desorbed oxygen.
The heat treatment may be performed in an atmosphere containing 10% or more. For the heat treatment, an RTA device using lamp heating can also be used. Heat treatment using an RTA apparatus takes a shorter time than using a furnace, and is therefore effective for increasing productivity.

Note that when tantalum nitride is used for the conductor 62a serving as the back gate of the transistor, the nitrogen-containing metal 20a constituting the plug and wiring shown in FIG. The temperature may be set to above 400°C or below. By performing the heat treatment in such a temperature range, release of hydrogen from the tantalum nitride film can be suppressed.

Further, a low resistance region may be formed in a region in contact with the conductor 68a or the conductor 68b, such as the semiconductor 66b or the insulator 66c. The low resistance region is mainly caused by oxygen being extracted by the conductor 68a or 68b that the semiconductor 66b is in contact with, or by the conductive material contained in the conductor 68a or 68b combining with elements in the semiconductor 66b. It is formed.
Formation of such a low resistance region makes it possible to reduce the contact resistance between the conductor 68a or 68b and the semiconductor 66b, thereby increasing the on-state current of the transistor 60a.

Further, the semiconductor 66b has a conductor 68a and a conductor 6 between the conductor 68a and the conductor 68b.
It may have a region thinner than the region overlapping with 8b. This is formed by removing a portion of the upper surface of the semiconductor 66b when forming the conductor 68a and the conductor 68b. On the upper surface of the semiconductor 66b, a low resistance region similar to the above-described low resistance region may be formed when a conductor that becomes the conductor 68a and the conductor 68b is formed. in this way,
By removing the region located between the conductor 68a and the conductor 68b on the upper surface of the semiconductor 66b, it is possible to prevent a channel from being formed in a region with low resistance on the upper surface of the semiconductor 66b.

Note that the three-layer structure of the insulator 66a, semiconductor 66b, and insulator 66c described above is an example.
For example, a two-layer structure may be used in which either the insulator 66a or the insulator 66c is not provided. Alternatively, a single layer structure may be used in which neither the insulator 66a nor the insulator 66c is provided. Alternatively, an n-layer structure (n is an integer of 4 or more) having any of the insulators, semiconductors, or conductors exemplified as the insulator 66a, semiconductor 66b, or insulator 66c may be used.

<Insulators, conductors>
Each component other than the semiconductor of the transistor 60a will be described in detail below.

As the insulator 59 and the insulator 61, an insulator having a function of blocking hydrogen or water is used. Hydrogen and water in the insulator provided near the insulator 66a, semiconductor 66b, and insulator 66c are one of the factors that generate carriers in the insulator 66a, semiconductor 66b, and insulator 66c, which also function as oxide semiconductors. Become. This may reduce the reliability of transistor 60a. In particular, when silicon or the like is used for the semiconductor substrate 91, hydrogen is used to terminate dangling bonds in the semiconductor substrate, so there is a risk that the hydrogen will diffuse to a transistor including an oxide semiconductor. On the other hand, by providing the insulator 59 and the insulator 61 that have the function of blocking hydrogen or water, diffusion of hydrogen or water from the lower layer of the transistor including an oxide semiconductor is suppressed, and the transistor including the oxide semiconductor reliability can be improved. It is preferable that the insulator 59 and the insulator 61 are less permeable to hydrogen or water than the insulator 65 or the insulator 64.

Further, it is preferable that the insulator 59 and the insulator 61 also have a function of blocking oxygen.
Insulator 59 and insulator 61 block oxygen diffusing from insulator 64, so that
Oxygen can be effectively supplied from the insulator 64 to the insulator 66a, semiconductor 66b, and insulator 66c.

As the insulator 59 and the insulator 61, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, or the like can be used. Preferably, the insulator 59 is A
The film is formed using the LD method, and the insulator 61 is formed using the sputtering method. These are insulators 59
When used as the insulator 61, it can function as an insulating film that blocks the diffusion of oxygen, hydrogen, or water. Further, as the insulator 59 and the insulator 61, for example, silicon nitride, silicon nitride oxide, or the like can be used. By using these as the insulator 59 and the insulator 61, they can function as an insulating film that blocks the diffusion of hydrogen and water. Note that the insulator 59 and the insulator 61 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Examples of the insulator 67 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium,
An insulator containing zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a stack. Note that the insulator 67 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

It is preferable that the conductor 62a and the conductor 62b at least partially overlap the semiconductor 66b in a region sandwiched between the conductor 68a and the conductor 68b. Conductor 62a and conductor 6
2b functions as a back gate of transistor 60a. By providing such conductors 62a and 62b, the threshold voltage of transistor 60a can be controlled. By controlling the threshold voltage, the gate (
When the voltage applied to the conductor 74) is low, for example, when the applied voltage is 0V or less, it is possible to prevent the transistor 60a from becoming conductive. In other words, the transistor 60a
It becomes easier to shift the electrical characteristics of the switch to the normally-off direction.

Further, the conductor 62a and the conductor 62b functioning as back gates may be connected to wiring or terminals to which a predetermined potential is supplied. For example, the conductor 62a and the conductor 6
2b may be connected to a wiring to which a constant potential is supplied. The fixed potential can be a high power supply potential or a low power supply potential such as ground potential.

The conductor 62a may be a conductor that can be used for the nitrogen-containing metal, and the conductor 62b may be a conductor that can be used for the conductor 21.

The insulator 65 is provided to cover the conductor 62a and the conductor 62b. The insulator 65 is
An insulator similar to the insulator 64 or insulator 72 described later can be used.

The insulator 63 is provided to cover the insulator 65. Preferably, the insulator 63 has a function of blocking oxygen. By providing such an insulator 63, it is possible to prevent the conductor 62a and the conductor 62b from extracting oxygen from the insulator 64. This results in
Oxygen can be effectively supplied from the insulator 64 to the insulator 66a, semiconductor 66b, and insulator 66c. In addition, by increasing the coverage of the insulator 63, oxygen extracted from the insulator 64 can be further reduced, and from the insulator 64 to the insulator 66a, the semiconductor 66b, and the insulator 66c.
can supply oxygen more effectively.

As the insulator 63, an oxide or nitride containing boron, aluminum, silicon, scandium, titanium, gallium, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium, or thallium is used. Preferably, hafnium oxide or aluminum oxide is used. Note that the insulator 63 is formed by sputtering, CV
This can be carried out using the D method, MBE method, PLD method, ALD method, or the like.

Note that in the insulator 65, the insulator 63, and the insulator 64, it is preferable that the insulator 63 has an electron trapping region. When the insulator 65 and the insulator 64 have the function of suppressing electron emission, the electrons captured by the insulator 63 behave like negative fixed charges. Therefore, the insulator 63 has a function as a floating gate.

It is preferable that the insulator 64 contains a small amount of water or hydrogen in the film. For example, the insulator 64 may include, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The body may be used in a single layer or in a stack. For example, the insulator 64 may include aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or Tantalum may be used. Preferably, silicon oxide or silicon oxynitride is used. Note that the insulator 64 is formed by sputtering, CV
This can be carried out using the D method, MBE method, PLD method, ALD method, or the like.

Further, it is preferable that the insulator 64 is an insulator containing excess oxygen. Such an insulator 6
4, oxygen can be supplied from the insulator 64 to the insulator 66a, the semiconductor 66b, and the insulator 66c. The oxygen can reduce oxygen vacancies that become defects in the insulator 66a, semiconductor 66b, and insulator 66c, which are oxide semiconductors. Thereby, the insulator 66a, the semiconductor 66b, and the insulator 66c can be made of oxide semiconductors with low defect level density and stable characteristics.

Note that in this specification and the like, excess oxygen refers to, for example, oxygen contained in an amount exceeding the stoichiometric composition. Alternatively, excess oxygen refers to, for example, oxygen released from a film or layer containing excess oxygen by heating. Excess oxygen can move inside the membrane or layer, for example. There are cases in which excess oxygen moves between atoms in a film or layer, and there are cases in which the excess oxygen moves in a round-trip manner while replacing oxygen constituting the film or layer.

The insulator 64 containing excess oxygen was found to have a temperature of 100°C in temperature programmed desorption gas spectroscopy analysis (TDS analysis).
The amount of oxygen molecules desorbed is 1.0×10 ¹⁴ molecules/cm 2 or ^more and 1.0×10 ¹⁶ molecules within the surface temperature range of 100° C. or higher and 500° C. or higher or 100° C. or higher and 500° C. or higher.
es/cm ² or less, more preferably 1.0×10 ¹⁵ molecules/cm ² or more and 5.0×10 ¹⁵ molecules/cm ² or less.

A method for measuring the amount of released molecules using TDS analysis will be described below, taking the amount of released oxygen as an example.

The total amount of gas released when a measurement sample is subjected to TDS analysis is proportional to the integral value of the ionic strength of the released gas. The total amount of gas released can then be calculated by comparison with a standard sample.

For example, from the TDS analysis results of a silicon substrate containing hydrogen at a predetermined density, which is a standard sample, and the TDS analysis results of a measurement sample, the amount of released oxygen molecules (N _O2 ) of the measurement sample can be calculated using the formula shown below. I can do it. Here, it is assumed that all of the gas detected at a mass-to-charge ratio of 32 obtained by TDS analysis is derived from oxygen molecules. Although the mass-to-charge ratio of CH ₃ OH is 32, it is not considered here as it is unlikely to exist. In addition, oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18, which are isotopes of oxygen atoms, are not considered because their abundance in nature is extremely small.

Here, it is assumed that N _O2 =N _H2 /S _H2 ×S _O2 ×α.

N _H2 is a value obtained by converting the hydrogen molecules desorbed from the standard sample into density. S _H2 is an integral value of ion intensity when a standard sample is analyzed by TDS. Here, the reference value of the standard sample is N
Let _H2 /S _H2 . S _O2 is an integral value of ion intensity when a measurement sample is analyzed by TDS. α is a coefficient that affects ion intensity in TDS analysis. For details of the above formula, refer to Japanese Patent Application Laid-Open No. 6-275697. The amount of oxygen released is measured using a temperature programmed desorption analyzer EMD-WA1000S/W manufactured by Denshi Kagaku Co., Ltd., using a silicon substrate containing a certain amount of hydrogen atoms as a standard sample.

Furthermore, in TDS analysis, some oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Note that since the above α includes the ionization rate of oxygen molecules, the amount of released oxygen atoms can also be estimated by evaluating the amount of released oxygen molecules.

Note that N _O2 is the amount of released oxygen molecules. The amount released in terms of oxygen atoms is twice the amount released of oxygen molecules.

Alternatively, an insulator that releases oxygen through heat treatment may contain peroxide radicals.
Specifically, the spin density due to peroxide radicals is 5×10 ¹⁷ spins/cm ³
This means the above. Note that insulators containing peroxide radicals can be analyzed using electron spin resonance method (ES).
(R: Electron Spin Resonance), there may be an asymmetrical signal near a g value of 2.01.

Further, the insulator 64 or the insulator 63 may have a function of preventing diffusion of impurities from the lower layer.

Further, as described above, it is preferable that the upper surface or lower surface of the semiconductor 66b has high flatness. Therefore, the top surface of the insulator 64 may be flattened by CMP or the like to improve its flatness.

Conductor 68a and conductor 68b each function as either a source electrode or a drain electrode of transistor 60a.

Examples of the conductor 68a and the conductor 68b include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium,
A conductor containing one or more of tin, tantalum, and tungsten may be used in a single layer or in a stacked layer. For example, when the conductor 68a and the conductor 68b have a laminated structure, tungsten may be laminated on tantalum nitride. In addition, the conductor 68a and the conductor 6
8b may be an alloy or a compound, for example, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen. A conductor or the like may also be used. Note that the conductor 68a and the conductor 68b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

The insulator 72 functions as a gate insulating film of the transistor 60a. The insulator 72 may be an insulator containing excess oxygen, similar to the insulator 64. By providing such an insulator 72, oxygen can be supplied from the insulator 72 to the insulator 66a, the semiconductor 66b, and the insulator 106.

Examples of the insulator 72 and the insulator 77 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator may be used in a single layer or in a laminated manner. For example, as the insulator 72 and the insulator 77,
Aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide may be used. Note that the insulator 72 and the insulator 77 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Furthermore, the insulator 77 is preferably an insulator containing excess oxygen. Such an insulator 7
By providing 7, oxygen can be supplied from the insulator 77 to the insulator 66a, the semiconductor 66b, and the insulator 66c. The oxygen can reduce oxygen vacancies that become defects in the insulator 66a, semiconductor 66b, and insulator 66c, which are oxide semiconductors. Thereby, the insulator 66a, the semiconductor 66b, and the insulator 66c can be made of oxide semiconductors with low defect level density and stable characteristics.

The insulator 77 containing excess oxygen was found to have a temperature of 100°C in temperature programmed desorption gas spectroscopy analysis (TDS analysis).
The amount of oxygen molecules desorbed is 1.0×10 ¹⁴ molecules/cm 2 or ^more and 1.0×10 ¹⁶ molecules within the surface temperature range of 100° C. or higher and 500° C. or higher or 100° C. or higher and 500° C. or higher.
es/cm ² or less, more preferably 1.0×10 ¹⁵ molecules/cm ² or more and 5.0×10 ¹⁵ molecules/cm ² or less.

Further, it is preferable that the insulator 77 contains few impurities such as hydrogen, water, and nitrogen oxides (NO _x , such as nitrogen monoxide and nitrogen dioxide). By using such an insulator 77, impurities such as hydrogen, water, and nitrogen oxides are suppressed from diffusing from the insulator 77 to the insulator 66a, the semiconductor 66b, and the insulator 66c, and the semiconductor 66b is reduced to a defect level. An oxide semiconductor having low density and stable characteristics can be obtained.

Here, the insulator 77 has a surface temperature of 200°C or more and 560°C or less as determined by TDS analysis.
The amount of H ₂ O molecules released is 3.80×10 ¹⁵ molecules/cm ² or less, more preferably 2.40×10 ¹⁵ molecules/cm ² or less. Furthermore, TDS analysis of the insulator 77 shows that the amount of H ₂ O molecules desorbed is 7.0 in the surface temperature range of 0° C. to 400° C.
More preferably, it is 00×10 ¹⁴ molecules/cm ² or less. In addition, the amount of NO ₂ molecules released from the insulator 77 was 1.80×10 ¹³ molecules in TDS analysis.
It is preferable that it be s/cm ² or less.

Conductor 74 functions as a gate electrode of transistor 60a or 60b. Conductor 74
Examples include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum. A conductor containing one or more types of tungsten and tungsten may be used in a single layer or in a laminated manner. For example, when the conductor 74 has a laminated structure, it may have a structure in which tungsten is laminated on tantalum nitride. Further, the conductor 74 may be an alloy or a compound, for example, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium. A conductor containing nitrogen may also be used. Note that the conductor 74
The film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Preferably, it may have a two-layer structure in which a conductor is formed using a sputtering method on tantalum nitride film formed by, for example, an ALD method. Since the tantalum nitride film is formed using the ALD method in the region in contact with the gate insulating film, it is preferable because there is less damage to the insulator 72 that functions as the gate insulating film. Furthermore, after removing the high resistivity region near the surface of the tantalum nitride film formed by the ALD method by performing reverse sputtering, a film of tantalum nitride, tungsten, etc. can be formed using the sputtering method to form a multilayer structure. . This structure is preferable because it reduces damage to the insulator 72 caused by sputtering. Removal of the high resistance region by reverse sputtering and film formation by sputtering can be performed using the same apparatus.

Here, as shown in FIG. 12(C), the conductor 62a, the conductor 62b, and the conductor 74
The electric field generated from the conductor can electrically surround the semiconductor 66b.
This is called a channel (s-channel) structure. ). Therefore, the entire semiconductor 66b (
Channels are formed on the top, bottom and side surfaces. In the s-channel structure, a large current can flow between the source and drain of the transistor, and the current when conducting (on current) can be increased.

Note that when the transistor has an S-channel structure, a channel is also formed on the side surface of the semiconductor 66b. Therefore, the thicker the semiconductor 66b, the larger the channel region.
That is, the thicker the semiconductor 66b is, the higher the on-state current of the transistor can be. Further, as the semiconductor 66b becomes thicker, the ratio of regions with high carrier controllability increases, so that the subthreshold swing value can be reduced. For example, 10 nm or more, preferably 2
The semiconductor 66b may have a region with a thickness of 0 nm or more, more preferably 30 nm or more. However, since the productivity of the semiconductor device may decrease, the semiconductor 66b may have a region with a thickness of 150 nm or less, for example.

Since a high on-current can be obtained, the s-channel structure can be said to be a structure suitable for miniaturized transistors. Since a transistor can be miniaturized, a semiconductor device including the transistor can have a high degree of integration and high density. For example, the transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less,
The transistor preferably has a region with a channel width of 40 nm or less, further preferably 30 nm or less, and even more preferably 20 nm or less.

Preferably, the insulator 79 is an insulator that can be used for the insulator 63. For example, the insulator 79 may be made of gallium oxide or aluminum oxide formed using an ALD method. By providing such an insulator 79 covering the conductor 74, it is possible to prevent the conductor 74 from taking away excess oxygen supplied to the insulator 77 and oxidizing the conductor 74.

The thickness of the insulator 78 can be, for example, 5 nm or more, or 20 nm or more. Furthermore, it is preferable that at least a portion of the insulator 78 be formed in contact with the upper surface of the insulator 77.

The insulator 78 may be, for example, an insulator containing carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. It may be used in layers or in a laminated manner. The insulator 78 preferably has the effect of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals, and the like. As such an insulator, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that instead of the nitride insulating film, an oxide insulating film having an effect of blocking oxygen, hydrogen, water, etc. may be provided. Examples of the oxide insulating film include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride. Further, as the insulator 78, an oxide that can be used as the above-mentioned insulator 66a or insulator 66c can also be used. Note that the insulator 78 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, the insulator 78 is preferably formed using a sputtering method, more preferably using a sputtering method in an atmosphere containing oxygen. By forming the insulator 78 by sputtering, oxygen is added near the surface of the insulator 77 (after the insulator 78 is formed, the interface between the insulator 77 and the insulator 78) at the same time as the film is formed. For example, aluminum oxide may be formed using a sputtering method. Furthermore, it is preferable to form an aluminum oxide film thereon using an ALD method. By using the ALD method, the formation of pinholes and the like can be suppressed, so that the effect of blocking oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. of the insulator 78 can be further improved.

It is preferable to perform heat treatment when forming the insulator 78, or after forming the film.
By performing the heat treatment, oxygen added to the insulator 77 can be diffused and supplied to the insulator 66a, the semiconductor 66b, and the insulator 66c. Further, the oxygen may be supplied from the insulator 77 to the insulator 66a, the semiconductor 66b, and the insulator 66c via the insulator 72 or the insulator 64. The heat treatment is performed at a temperature of 250°C or higher and 650°C or lower, preferably 350°C or higher and 450°C or higher.
It can be done at temperatures below ℃. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. The heat treatment may be performed under reduced pressure. For the heat treatment, an RTA device using lamp heating can also be used.

Note that when tantalum nitride is used for the conductor 62a serving as the back gate of the transistor, the nitrogen-containing metal 20a constituting the plug and wiring shown in FIGS. The temperature may be set to 370°C or higher and 400°C or lower.
By performing heat treatment in such a temperature range, release of hydrogen from tantalum nitride can be suppressed.

The insulator 78 is an insulator that is less permeable to oxygen than the insulator 77, and preferably has a function of blocking oxygen. By providing such an insulator 78, when oxygen is supplied from the insulator 77 to the insulator 66a, the semiconductor 66b, and the insulator 66c, the oxygen is prevented from being released to the outside above the insulator 78. be able to.

Note that aluminum oxide is preferable for application to the insulator 78 because it has a high blocking effect that prevents both impurities such as hydrogen and moisture, and oxygen from passing through the film.

<Configuration of capacitive element>
FIG. 17A shows an example of the configuration of the capacitive element 80a. The capacitive element 80a includes a conductor 82,
It has an insulator 83 and a conductor 84. As shown in FIG. 17(A), a conductor 82 is provided on an insulator 81, an insulator 83 is provided to cover the conductor 82, and an insulator 83 is provided on the insulator 81.
A conductor 84 is provided to cover the conductor 84, and an insulator 85 is provided on the conductor 84.

Here, the insulator 83 is provided so as to be in contact with the side surface of the conductor 82, and the conductor 84 is provided so as to be in contact with the side surface of the conductor 82.
It is preferable that it be provided so as to be in contact with the side surface of the convex portion No. 3. Thereby, not only the top surface of the conductor 82 but also the side surface of the conductor 82 can function as a capacitive element, so that the capacitance value can be increased.

Examples of the conductor 82 and the conductor 84 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, A conductor containing one or more of silver, indium, tin, tantalum, and tungsten may be used in a single layer or in a stacked layer. For example, it may be an alloy or a compound, and conductors include aluminum, copper and titanium, copper and manganese, indium, tin and oxygen, titanium and nitrogen. etc. may also be used. Note that the conductor 82 and the conductor 84 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Examples of the insulator 83 include aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulator containing one or more selected from hafnium oxide, tantalum oxide, etc. can be used. For example, silicon oxynitride may be stacked on aluminum oxide. Also,
Hafnium silicate (HfSi _x O _y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSix _{O y} N _z (x>0, y>0, z>0)), nitrogen-doped It is preferred to use high-k materials such as hafnium aluminate (HfAl _x O _y N _z (x>0, y>0, z>0)), hafnium oxide, or yttrium oxide. Further, when a high-k material is used as the insulator 83, the capacitance value may be increased by performing heat treatment. By using such a high-k material, the insulator 83
Even if the thickness is increased, a sufficient capacitance value of the capacitive element 80a can be ensured. By making the insulator 83 thicker, leakage current generated between the conductor 82 and the conductor 84 can be suppressed. Note that the insulator 83 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method,
This can be done using an ALD method or the like.

As the insulator 81 and the insulator 85, an insulator that can be used as the insulator 77 may be used. Further, the insulator 85 is made of organic silane gas (for example, TEOS (Tetra-E
The film may also be formed using thyl-Ortho-Silicate).

Next, a modification of the capacitive element 80a will be described using FIGS. 17(B) and 17(C).

The capacitive element 80b shown in FIG. 17(B) differs from the capacitive element 80a shown in FIG. 17(A) in that the conductor 84 is formed to overlap the upper surface of the conductor 82. In addition, Fig. 17 (
In B), the side edge of the conductor 84 and the side edge of the conductor 82 are provided so as to overlap, but the capacitive element 80b is not limited to this.

The capacitive element 80c shown in FIG. 17(C) is provided with an insulator 86 having an opening above the insulator 81, and the conductor 82 is provided in the opening. ) is different from the capacitive element 80a shown in FIG. Here, the opening of the insulator 86 and the upper surface of the insulator 81 can be regarded as a groove, and the conductor 82 is preferably provided along the groove. Also, Figure 17
As shown in (C), the upper surface of the insulator 86 and the upper surface of the conductor 82 may be formed to substantially coincide with each other.

An insulator 83 is provided on the conductor 82 , and a conductor 84 is provided on the insulator 83 . Here, the conductor 84 has a region facing the conductor 82 via the insulator 83 in the groove portion. Moreover, it is preferable that the insulator 83 is provided so as to cover the upper surface of the conductor 82 .
Providing the insulator 83 in this manner can prevent leakage current from flowing between the conductor 82 and the conductor 84. Further, the side edge of the insulator 83 and the side edge of the conductor 84 may be provided so as to approximately coincide with each other. In this way, it is preferable that the capacitive element 80c has a concave shape, a cylinder shape, or the like. Note that in the capacitive element 80c, the top surface shape of the conductor 82, the insulator 83, and the conductor 84 may be a polygonal shape other than a quadrangle, or may be a circular shape including an ellipse.

<Structure of transistor formed on semiconductor substrate>
FIGS. 18A and 18B show an example of a structure of a transistor 90a included in an element layer including a semiconductor substrate. FIG. 18(A) shows the channel length direction B1- of the transistor 90a.
18B is a sectional view corresponding to B2, and FIG. 18B is a cross-sectional view corresponding to B2 in the channel width direction B3 of the transistor 90a
- It is a sectional view corresponding to B4.

A plurality of convex portions are formed on the semiconductor substrate 91, and an element isolation region 97 is formed in a groove portion (sometimes referred to as a trench) between the plurality of convex portions. An insulator 94 is formed on the semiconductor substrate 91 and the element isolation region 97, and a conductor 96 is formed on the insulator 94. An insulator 95 is formed in contact with the side surfaces of the insulator 94 and the conductor 96. An insulator 99 is provided on the semiconductor substrate 91, the element isolation region 97, the insulator 95, and the conductor 96, and an insulator 98 is further provided on the insulator 99.

Further, as shown in FIG. 18(A), in the convex portion of the semiconductor substrate 91, at least the insulator 9
A low-resistance region 93a and a low-resistance region 93b are formed so as to partially overlap with the low-resistance region 93b, and a low-resistance region 92a and a low-resistance region 92b are formed outside the low-resistance region 93a and the low-resistance region 93b. Note that it is preferable that the resistance of the low resistance region 92a and the low resistance region 92b is lower than that of the low resistance region 93a and the low resistance region 93b.

Here, the conductor 96 functions as a gate of the transistor 90a, the insulator 94 functions as a gate insulating film of the transistor 90a, the low resistance region 92a functions as one of the source or drain of the transistor 90a, and the low resistance region 92b serves as the other source or drain of transistor 90a. Further, the insulator 95 functions as a sidewall insulating film of the transistor 90a. Further, the low resistance region 93a and the low resistance region 93b function as an LDD (Lightly Doped Drain) region of the transistor 90a. Furthermore, in the convex portion of the semiconductor substrate 91, the conductor 96 overlaps with the low resistance region 93a.
A region located between low resistance region 93b and low resistance region 93b functions as a channel formation region of transistor 90a.

In the transistor 90a, as shown in FIG. 18B, the sides and top of the convex portion in the channel formation region and the conductor 96 overlap with the insulator 94 in between, so that the side portions of the channel formation region The carrier flows in a wide range including the upper part. Therefore, the amount of carriers that move in the transistor 90a can be increased while keeping the area occupied by the transistor 90a on the substrate small. As a result, in the transistor 90a, the on-state current increases and the field effect mobility increases. In particular, if the length of the protrusion in the channel width direction (channel width) in the channel forming region is W, and the height of the protrusion in the channel forming region is T, then the ratio of the height T of the protrusion to the channel width W (T When the aspect ratio corresponding to /W) is high, the range in which carriers flow becomes wider, so that the on-current of the transistor 90a can be increased, and the field effect mobility can also be increased. For example, in the case of a transistor 90a using a bulk semiconductor substrate 91, the aspect ratio is preferably 0.5 or more, and more preferably 1 or more.

The transistor 90a shown in FIGS. 18A and 18B is manufactured using a trench isolation method (STI method: Shal
An example is shown in which elements are isolated using low trench isolation).
The semiconductor device shown in this embodiment is not limited to this.

As the semiconductor substrate 91, for example, a single semiconductor substrate such as silicon or germanium, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, etc.
A semiconductor substrate made of gallium oxide or the like may be used. Preferably, a single crystal silicon substrate is used as the semiconductor substrate 91. Furthermore, as the semiconductor substrate 91, a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate, may be used.

As the semiconductor substrate 91, for example, a semiconductor substrate having an impurity imparting p-type conductivity is used. However, as the semiconductor substrate 91, a semiconductor substrate having an impurity imparting n-type conductivity may be used. Alternatively, the semiconductor substrate 91 may be of i-type.

Furthermore, the low resistance region 92a and the low resistance region 92b provided in the semiconductor substrate 91 contain an element that imparts n-type conductivity such as phosphorus or arsenic, or an element that imparts p-type conductivity such as boron or aluminum. It is preferable to include. Similarly, it is preferable that the low resistance region 93a and the low resistance region 93b also contain an element imparting n-type conductivity such as phosphorus or arsenic, or an element imparting p-type conductivity such as boron or aluminum. . However, the low resistance region 93a
Since it is preferable that the low resistance region 93b functions as an LDD, the low resistance region 93a
The concentration of the element imparting conductivity contained in the low resistance region 93b is preferably lower than the concentration of the element imparting conductivity contained in the low resistance region 92a and the low resistance region 92b.
Note that the low resistance region 92a and the low resistance region 92b may be formed using silicide or the like.

The insulators 94 and 95 are, for example, aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, An insulator containing one or more selected from neodymium oxide, hafnium oxide, tantalum oxide, etc. can be used. In addition, hafnium silicate (HfSi _x O _y (x>0, y>0)),
Nitrogen-doped hafnium silicate (HfSi _x O _y N _z (x>0, y>0, z>0
)), nitrogen-doped hafnium aluminate (HfAl _x O _y N _z (x>0, y>0
, z>0)), hafnium oxide, or yttrium oxide. Note that the insulator 94 and the insulator 95 can be formed by sputtering, CVD, or MB.
This can be carried out using the E method, PLD method, ALD method, or the like.

As the conductor 96, it is preferable to use a metal selected from tantalum, tungsten, titanium, molybdenum, chromium, niobium, etc., or an alloy material or a compound material containing these metals as a main component. Furthermore, polycrystalline silicon doped with impurities such as phosphorus can be used. Further, the conductor 96 may be formed with a laminated structure of a metal film containing nitrogen and the above metal film. As the metal containing nitrogen, tungsten nitride, molybdenum nitride, and titanium nitride can be used. By providing a metal film containing nitrogen, the adhesion of the metal film can be improved and peeling can be prevented. Note that the conductor 96 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

As the insulator 98 and the insulator 99, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. The insulator may be used in a single layer or in a laminated manner. Note that the insulator 98 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Further, as the insulator 98, silicon carbonitride (silicon carbonitride) is used as the insulator 98.
e), silicon oxycarbide, etc. can be used. In addition, USG (Undoped Silicate Glass), BPSG (
Boron Phosphorus Silicate Glass), BSG (Bor
osilicate Glass) etc. can be used. USG, BPSG, etc. may be formed using an atmospheric pressure CVD method. Also, for example, HSQ (hydrogen silsesquioxane)
etc. may be formed using a coating method.

However, it may be preferable for the insulator 99 to contain hydrogen. For example, silicon nitride containing hydrogen may be used as the insulator 99. The presence of hydrogen in the insulator 99 may reduce defects in the semiconductor substrate 91 and improve the characteristics of the transistor 90a. For example, when a material containing silicon is used as the semiconductor substrate 91, defects such as dangling bonds of silicon can be terminated with hydrogen.

Next, a modification of the transistor 90a will be described using FIGS. 18C and 18D. Note that, like FIGS. 18A and 18B, FIGS. 18C and 18D are a cross-sectional view of the transistor 90a in the channel length direction and a cross-sectional view of the transistor 90a in the channel width direction.

The transistor 90b shown in FIGS. 18C and 18D differs from the transistor 90a shown in FIGS. 18A and 18B in that a convex portion is not formed in the semiconductor substrate 91. In addition, Figure 18
For other structures of the transistor 90b shown in FIGS. 18(C) and 18(D), the structure of the transistor 90a shown in FIGS. 18(A) and 18(B) can be referred to.

Note that although insulator 94 is provided in contact with the lower surface of conductor 96 in transistor 90a and transistor 90b, the semiconductor device shown in this embodiment is not limited to this. For example, the insulator 94 may be provided in contact with the lower and side surfaces of the conductor 96.

<Example of configuration of semiconductor device>
An element layer containing an oxide semiconductor (hereinafter referred to as an element layer 30) is provided on an element layer containing a semiconductor substrate (hereinafter referred to as an element layer 50), and an element including a capacitive element is provided on the element layer 30. layer (hereinafter,
It is called an element layer 40. ) is shown in FIG. 19. FIG. 19 is a cross-sectional view of the transistor 60a and the transistor 90a corresponding to the channel length direction C1-C2. Note that although the channel length directions of the transistor 60a and the transistor 90a are parallel in FIG. 19, the channel length directions are not limited to this, and can be set as appropriate.

The element layer 50 is provided with a transistor 90a shown in FIG. Regarding the low resistance region 93a, the low resistance region 93b, the low resistance region 92a, and the low resistance region 92b, the above description can be referred to.

The element layer 50 includes a conductor 51a and a conductor 52a, a conductor 51b and a conductor 52b,
A portion of the conductor 51c and the conductor 52c that functions as a plug is provided. The conductors 51a and 52a are formed in openings of the insulators 98 and 99, with their lower surfaces in contact with the low resistance region 92a. The conductor 51b and the conductor 52b are formed in the opening of the insulator 98, with their lower surfaces in contact with the conductor 96. Conductor 51c and conductor 5
2c is formed in the openings of the insulators 98 and 99, with its lower surface in contact with the low resistance region 92b.

Here, the conductors 51a to 51c may have a structure similar to that of the nitrogen-containing metal 20a shown in FIGS. 2(A) and 2(B). Further, the conductors 52a to 52c are shown in FIG.
The structure may be similar to that of the conductor 21a shown in A) and (B). However, the present invention is not limited to this, and the plug and the wiring may be formed separately, for example, using a single damascene method or the like.

As shown in FIG. 19, conductors 51a to 51c and conductors 52a to 52c
Preferably, and have a laminated structure. As the conductors 51a to 51c, for example, titanium, tantalum, titanium nitride, tantalum nitride, or the like may be used in a single layer or a laminated layer. By using a nitrogen-containing metal such as tantalum nitride or titanium nitride, especially tantalum nitride, for the conductors 51a to 51c, impurities such as hydrogen and water contained in the element layer 50 etc. are absorbed into the conductors 51a to 51c. This can prevent the particles from diffusing into the layers and moving to the upper layer. This applies not only to the conductors 51a to 51c but also to other conductors functioning as plugs and wiring. Therefore, the conductors 111a to 111c and the conductors 121a to 121c, which are located below the element layer 30, have a layered structure in which metals containing nitrogen such as tantalum nitride or titanium nitride, especially nitrided By using tantalum, impurities such as hydrogen and water can be prevented from diffusing into the upper element layer 30. With such a configuration, the oxide semiconductor included in the element layer 30 can be a highly pure or substantially high-purity intrinsic oxide semiconductor.

An insulator 102a and an insulator 102b are provided on the insulator 98. The conductor 51a, the conductor 52a, and the conductor 51 are inserted into the openings formed in the insulator 102a and the insulator 102b.
b, the conductor 52b, the conductor 51c, and the portions of the conductor 52c that function as wiring, etc., are provided so as to be embedded. For example, if a metal that easily diffuses, such as copper, is used for the conductors 52a to 52c, an insulator that is difficult for copper to pass through, such as silicon nitride or silicon nitride carbide, may cause impurities such as copper to diffuse into the transistor 90a. This can be prevented. Further, it is preferable to use an insulator having a lower hydrogen concentration than the insulator 98 or the like as the insulator 102a. Further, it is preferable that the dielectric constant of the insulator 102b is lower than that of the insulator 102a. Note that in FIG. 19, the insulator 102a and the insulator 102b are provided in a laminated manner;
The material is not limited to this, and may be a single layer insulator.

An insulator 104 is provided on the insulator 102b, an insulator 106 is provided on the insulator 104, and an insulator 108 is provided on the insulator 106. Insulator 102a, insulator 102b
, an insulator that can be used for the insulator 98 may be used as the insulator 104, the insulator 106, and the insulator 108. Further, any one of the insulator 102a, the insulator 102b, the insulator 104, the insulator 106, and the insulator 108 is preferably an insulator that has a function of blocking impurities such as hydrogen and oxygen. Insulators that have the function of blocking impurities such as hydrogen and oxygen include, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum. , insulators containing neodymium, hafnium or tantalum,
It may be used in a single layer or in a laminated manner. For example, silicon nitride or the like may be used.

Furthermore, when using a metal that easily diffuses, such as copper, for the conductors 52a to 52c, the insulator 1
By using an insulator such as silicon nitride or silicon nitride carbide that is difficult for copper to pass through as 04, it is possible to prevent impurities such as copper from diffusing into the oxide semiconductor film included in the element layer 30.

The insulator 104 and the insulator 106 include a conductor 111a, a conductor 112a, and a conductor 1.
11b and the conductor 112b, and the conductor 111c and the conductor 112c are provided with portions that function as plugs. Further, the insulator 108 includes a conductor 111a and a conductor 1
12a, conductor 111b and conductor 112b, conductor 111c and conductor 112c,
A portion that functions as wiring is provided. The conductor 111a and the conductor 112a are
They are formed in openings of insulators 104, 106, and 108, with their lower surfaces in contact with conductor 52a. The conductor 111b and the conductor 112b are formed in the openings of the insulator 104, the insulator 106, and the insulator 108, with their lower surfaces in contact with the conductor 52b. The conductor 111c and the conductor 112c are formed in the openings of the insulator 104, the insulator 106, and the insulator 108, with their lower surfaces in contact with the conductor 52c.

Here, the conductors 111a to 111c may have a structure similar to that of the nitrogen-containing metal 20a shown in FIGS. 2(A) and 2(B). Further, the conductors 112a to 112c may have the same structure as the conductor 21a shown in FIGS. 2(A) and 2(B). However, the present invention is not limited to this, and the plug and the wiring may be formed separately, for example, using a single damascene method or the like.

An insulator 110 is provided on top of the insulator 108. For the insulator 110, an insulator that can be used for the insulator 106 may be used.

The element layer 30 on the insulator 110 is provided with the transistor 60a shown in FIG. 63, insulator 64, insulator 66a, semiconductor 66b, insulator 66c, conductor 68a, conductor 68b, insulator 72, conductor 74, insulator 79, insulator 77, and insulator 78 as described above. can be taken into account.

The insulator 61, the insulator 59, the insulator 58, and the insulator 110 include a conductor 121a and a conductor 122a, a conductor 121b and a conductor 122b, a conductor 121c and a conductor 12.
2c, is provided with a portion that functions as a plug. Further, the insulator 67 includes a conductor 1
21a and the conductor 122a, the conductor 121b and the conductor 122b, and the conductor 121c and the conductor 122c. The conductor 121a and the conductor 122a are formed in the openings of the insulator 67, the insulator 61, the insulator 59, the insulator 58, and the insulator 110, with their lower surfaces in contact with the conductor 112a. The conductor 121b and the conductor 122b are formed in the openings of the insulator 67, the insulator 61, the insulator 59, the insulator 58, and the insulator 110, with their lower surfaces in contact with the conductor 112b. The conductor 121c and the conductor 122c are formed in the openings of the insulator 67, the insulator 61, the insulator 59, the insulator 58, and the insulator 110, with their lower surfaces in contact with the conductor 112c.

Here, the conductors 121a to 121c may have a structure similar to that of the nitrogen-containing metal 20a shown in FIGS. 2A and 2B. Further, the conductors 122a to 122c may have the same structure as the conductor 21a shown in FIGS. 2(A) and 2(B).

Further, the conductor 62a and the conductor 62b are formed in the same layer as the conductor 121a and the conductor 122a, the conductor 121b and the conductor 122b, and the conductor 121c and the conductor 122c.

As shown in FIG. 19, the semiconductor substrate 91 and the semiconductor 66b are separated by the insulator 61, the insulator 59, the insulator 58, and the conductors 121a to 121c. Since the conductors 121a to 121c have a function of blocking hydrogen and water diffusion, the element layer 5
Impurities such as hydrogen or water contained in the insulators 61, 59, and 5
Diffusion into the semiconductor 66b via the conductors 122a to 122c functioning as via holes and plugs formed in the semiconductor 66b can be prevented.

Here, FIG. 20 shows a sectional view corresponding to the C3-C4 section near the scribe line 138. As shown in FIG. 20, in the vicinity of the region overlapping with the scribe line 138, the insulator 6
7. Openings are formed in the insulator 65, the insulator 63, the insulator 64, and the insulator 77, and the insulator 6
7. It is preferable that an insulator 78 is formed to cover the side surfaces of the insulator 65, the insulator 63, the insulator 64, and the insulator 77, and that the insulator 78 and the insulator 61 are in contact with each other at the opening.

By having such a shape, the insulator 78 and the insulator 61 are connected to the insulator 67 and the insulator 65.
, the insulator 63, the insulator 64, and the insulator 77 can be covered up to the side surfaces. Since the insulator 78 and the insulator 61 have a function of blocking hydrogen and water, even if the semiconductor device shown in this embodiment is scribed, the insulator 67, the insulator 65, the insulator 63, and the insulator Hydrogen or water can be prevented from entering from the side surfaces of the transistor 64 and the insulator 77 and diffusing into the transistor 60a.

Furthermore, as described above, excess oxygen can be supplied to the insulator 77 as the insulator 78 is formed. At this time, by covering the side surface of the insulator 77 with the insulator 78, oxygen is prevented from diffusing outside the insulator 78, and the insulator 77 is filled with oxygen.
Oxygen can be supplied to a, the semiconductor 66b, and the insulator 66c. The oxygen can reduce oxygen vacancies that cause defects in the insulator 66a, semiconductor 66b, and insulator 66c.
Thereby, the semiconductor 66b can be an oxide semiconductor with stable characteristics and low defect level density.

An insulator 88 is provided on top of the insulator 78 . Although the same insulator as the insulator 78 can be used for the insulator 88, it is preferable to form the film by ALD method. Insulator 8 on top of insulator 88
9 is provided. As the insulator 89, an insulator that can be used for the insulator 59 may be used.
Insulator 81 is provided on insulator 89 . For the insulator 81, an insulator that can be used for the insulator 77 may be used.

The insulator 81, the insulator 89, the insulator 88, the insulator 78, the insulator 77, the insulator 66c, the insulator 64, the insulator 63, and the insulator 65 include a conductor 31a and a conductor 32a that function as plugs. , a conductor 31b and a conductor 32b, a conductor 31c and a conductor 32c, a conductor 31d and a conductor 32d, and a conductor 31e and a conductor 32e. The conductor 31a and the conductor 32a have their lower surfaces in contact with the conductor 122a, and the insulator 81 and the insulator 8
9, are formed in the openings of insulator 88, insulator 78, insulator 77, insulator 66c, insulator 64, insulator 63, and insulator 65. The conductor 31b and the conductor 32b are insulator 81, insulator 89, insulator 88, insulator 78, insulator 7, with their lower surfaces in contact with conductor 68a.
7 and in the opening of the insulator 66c. The conductor 31c and the conductor 32c are formed in the openings of the insulator 81, the insulator 89, the insulator 88, the insulator 78, the insulator 77, and the insulator 66c, with their lower surfaces in contact with the conductor 68b. . Conductor 31d and conductor 3
2d is an opening in insulator 81, insulator 89, insulator 88, insulator 78, insulator 77, insulator 66c, insulator 64, insulator 63, and insulator 65, with the lower surface in contact with conductor 122b. is formed within. The conductor 31e and the conductor 32e have lower surfaces in contact with the conductor 122c, and include an insulator 81, an insulator 89, an insulator 88, an insulator 78, an insulator 77, an insulator 66c, an insulator 64, an insulator 63, and is formed in the opening of the insulator 65.

Here, as the conductors 31a to 31e, conductors that can be used for the nitrogen-containing metal 20a shown in FIGS. 2(A) and 2(B) may be used. Conductor 31a to conductor 31e
By having such a structure, each of the openings described above can be closed with the conductors 31a to 31e. Since the conductors 31a to 31e have a function of blocking the diffusion of hydrogen and water, they prevent impurities such as hydrogen or water from diffusing into the transistor 60a via the conductors 32a to 32e. be able to. Further, as the conductors 32a to 32e, any conductor that can be used for the conductor 21a shown in FIGS. 2(A) and 2(B) may be used.

On the insulator 81, a conductor 33a, a conductor 33b, a conductor 82, and a conductor 33e are formed. Here, the conductor 82 is one of the electrodes of the capacitive element 80a of the element layer 40. The conductor 33a is in contact with the exposed top surfaces of the conductor 31a and the conductor 32a, the conductor 33b is in contact with the exposed top surfaces of the conductor 31b and the conductor 32b, and the conductor 82 is in contact with the conductor 31c, the conductor 32c, and the conductor 32b. The conductor 33 is in contact with the exposed upper surface of the conductor 31d and the conductor 32d.
e is in contact with the exposed upper surfaces of the conductor 31e and the conductor 32e.

Here, a conductor that can be used for the conductor 82 may be used as the conductor 33a, the conductor 33b, and the conductor 33e.

Note that although the wiring and plug connected to the conductor 74 and the conductor 62b are not illustrated in the cross-sectional view shown in FIG. 19, they can be provided separately.

The element layer 40 is provided with a capacitive element 80a shown in FIG.
, the conductor 82, the insulator 83, the conductor 84, and the insulator 85, the above description can be referred to.

The element layer 40 includes a conductor 41a and a conductor 42a, which function as plugs, and a conductor 41b.
and conductor 42b, conductor 41c and conductor 42c, conductor 41d and conductor 42
d is provided. The conductor 41a and the conductor 42a are formed in the openings of the insulators 83 and 85, with their lower surfaces in contact with the conductor 33a. The conductor 41b and the conductor 42b are formed in the openings of the insulator 83 and the insulator 85, with their lower surfaces in contact with the conductor 33b. The conductor 41c and the conductor 42c have their lower surfaces in contact with the conductor 84, and the insulator 8
It is formed in the opening of 5. The conductor 41d and the conductor 42d have the conductor 33 on the lower surface.
It is formed in the opening of the insulator 83 and the insulator 85 in contact with e.

Here, as the conductors 41a to 41d, conductors that can be used for the nitrogen-containing metal 20a shown in FIGS. 2(A) and 2(B) may be used. Further, as the conductors 42a to 42d, any conductor that can be used for the conductor 21a shown in FIGS. 2(A) and 2(B) may be used.

The conductors 43a to 43d functioning as wiring are formed on the insulator 85. The conductor 43a is in contact with the exposed upper surfaces of the conductor 41a and the conductor 42a, and the conductor 43b is in contact with the exposed upper surfaces of the conductor 41a and the conductor 42a.
is in contact with the exposed upper surfaces of the conductor 41b and the conductor 42b, and the conductor 43c is in contact with the exposed upper surface of the conductor 41b and the conductor 42b.
and the exposed upper surface of the conductor 42c, the conductor 43d is in contact with the conductor 41d and the conductor 4
It is in contact with the exposed upper surface of 2d.

Here, the conductors 43a to 43d are the conductor 33a, the conductor 33b, and the conductor 3.
Any conductor that can be used for 3e may be used. Further, the conductors 43a to 43d
are formed on the element layer 30, so there may be no need to perform high-temperature heat treatment after forming the conductors 43a to 43d. Therefore, as the conductors 43a to 43d,
For example, wiring resistance can be lowered by using a metal material such as aluminum or copper that has low heat resistance but low resistance.

An insulator 134 is formed on the insulator 85, covering the conductors 43a to 43d. For the insulator 134, an insulator that can be used for the insulator 85 may be used.

The insulator 134 is provided with a conductor 131 and a conductor 132 that function as a plug. The conductor 131 and the conductor 132 have lower surfaces in contact with the conductor 42a, and the insulator 134
It is formed in the opening of.

Here, as the conductor 131, a conductor that can be used for the nitrogen-containing metal 20a shown in FIGS. 2(A) and 2(B) may be used. Further, the conductor 132 is shown in FIGS.
Any conductor that can be used for the conductor 21a shown in FIG.

A conductor 133 functioning as a wiring is formed on an insulator 134. Conductor 133
is in contact with the exposed upper surfaces of the conductor 131 and the conductor 132. Here, the conductor 133
In this case, any conductor that can be used as the conductor 33a, the conductor 33b, and the conductor 33e may be used.

An insulator 136 is formed on the insulator 134 so as to have an opening above the conductor 133. For the insulator 136, an insulator that can be used for the insulator 134 may be used. Also,
As the insulator 136, an organic insulating film such as polyimide may be used.

Further, FIG. 23 shows a semiconductor device having a configuration different from that in FIG. 19. FIG. 23 is a cross-sectional view of the transistor 60a and the transistor 90a corresponding to the channel length direction C1-C2. Note that although the channel length directions of the transistor 60a and the transistor 90a are parallel in FIG. 23, the channel length directions are not limited to this and can be set as appropriate.

The insulator 77 is arranged to cover the transistor 60a, similar to the semiconductor device shown in FIG. 19. A structure different from that of the semiconductor device shown in FIG. 19 will be explained below.

The insulator 77, the insulator 66c, the insulator 64, the insulator 63, and the insulator 65 include a conductor 31a and a conductor 32a, a conductor 31b and a conductor 32b, and a conductor 31c and a conductor 32c that function as plugs. , a conductor 31d, a conductor 32d, a conductor 31e, and a conductor 32e. The conductor 31a and the conductor 32a have the conductor 122 on the lower surface.
They are formed in openings of insulator 77, insulator 66c, insulator 64, insulator 63, and insulator 65 in contact with a. The conductor 31b and the conductor 32b are formed in the openings of the insulator 77 and the insulator 66c, with their lower surfaces in contact with the conductor 68a. The conductor 31c and the conductor 32c are formed in the openings of the insulator 77 and the insulator 66c, with their lower surfaces in contact with the conductor 68b. The conductor 31d and the conductor 32d are formed in the openings of the insulator 77, the insulator 66c, the insulator 64, the insulator 63, and the insulator 65, with their lower surfaces in contact with the conductor 122b. The conductor 31e and the conductor 32e are formed in the openings of the insulator 77, the insulator 66c, the insulator 64, the insulator 63, and the insulator 65, with their lower surfaces in contact with the conductor 122c.

Conductor 31a and conductor 32a, conductor 31b and conductor 32 functioning as a plug
b, conductor 31c and conductor 32c, conductor 31d and conductor 32d, conductor 31e
The conductor 32e is covered with an insulator 55a, an insulator 55b, an insulator 55c, an insulator 55d, and an insulator 55e so as to cover the upper surface of each of the conductors 32e. Insulator 55a, insulator 55
b, as the insulator 55c, the insulator 55d, and the insulator 55e, the same insulator as the insulator 78 can be used, but it is preferable to form the film by ALD method.

As the insulators 55a, 55b, 55c, 55d, and 55e, for example, metal oxides such as aluminum oxide, hafnium oxide, tantalum oxide, or metal nitrides such as tantalum nitride may be used. is preferred. In particular, aluminum oxide has a high blocking effect that prevents the membrane from permeating both oxygen and impurities such as hydrogen and moisture that cause fluctuations in the electrical characteristics of the transistor. Therefore, aluminum oxide is free from impurities such as hydrogen and moisture during and after the transistor manufacturing process.
It is possible to prevent the mixture from entering 0a.

On the insulator 55a, on the insulator 55b, on the insulator 55c, on the insulator 55d, on the insulator 55e, and on the insulator 77, an insulator 78, an insulator 88, an insulator 89, and an insulator 81 are arranged in order. They are arranged in layers. By forming the insulator 78, oxygen can be supplied to the insulator 77. This oxygen becomes excess oxygen, passes through the insulator 77 and the insulator 66c, and diffuses into the semiconductor 66b, so that defects in the semiconductor 66b can be repaired.

Further, in the insulator 78, the insulator 88, the insulator 89, and the insulator 81, conductors 31a to 31e and conductors 32a to 32e are embedded. Note that the conductor 3
The conductors 1a to 31e and the conductors 32a to 32e function as plugs or wirings that are electrically connected to the capacitive element 80a, the transistor 60a, or the transistor 90a. The conductors 31a to 31e may be conductors that can be used for the nitrogen-containing metal 20a shown in FIGS. 2(A) and 2(B). Further, as the conductors 32a to 32e, any conductor that can be used for the conductor 21a shown in FIGS. 2(A) and 2(B) may be used.

The insulator 81, the insulator 89, the insulator 88, the insulator 78, and the insulator 55c are provided with a conductor 41c, a conductor 42c, a conductor 41d, and a conductor 42d that function as plugs. The conductor 41c and the conductor 42c are formed in the openings of the insulator 81, the insulator 89, the insulator 88, the insulator 78, and the insulator 55c, with their lower surfaces in contact with the conductor 32c. The conductor 41d and the conductor 42d have their lower surfaces in contact with the conductor 32d, and the insulator 81
, insulator 89, insulator 88, insulator 78, and insulator 55d. Further, the conductor 87 includes the conductor 41c, the conductor 41d, the conductor 42c, and the conductor 42.
It is arranged so as to be in contact with the upper surface of d. Further, conductors 82a and 82b are arranged in contact with the upper surface of the conductor 87. The conductor 87, the conductor 82a, and the conductor 82b function as one electrode of the capacitive element 80a.

An insulator 83 is provided on the insulator 81, the conductor 87, the conductor 82a, and the conductor 82b. The insulator 83 has a function as a dielectric of the capacitive element 80a. The insulator 83 can have a three-layer structure of an insulator 83a, an insulator 83b, and an insulator 83c. For example, the insulator 83a, the insulator 83b, and the insulator 83c are formed using the ALD method.
3a may be silicon oxide, the insulator 83b may be aluminum oxide, and the insulator 83c may be silicon oxide.

The insulator 83, the insulator 81, the insulator 89, the insulator 88, the insulator 78, and the insulator 55a include a conductor 41a and a conductor 42a, a conductor 41b and a conductor 42b, and a conductor 41e that function as plugs. and a conductor 42e. The conductor 41a and the conductor 42a are formed in the openings of the insulator 83, the insulator 81, the insulator 89, the insulator 88, the insulator 78, and the insulator 55a, with their lower surfaces in contact with the conductor 32a. There is. The conductor 41b and the conductor 42b have their lower surfaces in contact with the conductor 32b, and the insulator 83, the insulator 81, and the insulator 89
, are formed in the openings of the insulator 88, the insulator 78, and the insulator 55b. Conductor 4
1e and conductor 42e are formed in openings of insulator 83, insulator 81, insulator 89, insulator 88, insulator 78, and insulator 55e, with the lower surfaces in contact with conductor 32e.

A conductor 43a is provided on the insulator 83 and has a region in contact with the upper surface of the conductor 42a. Further, on the insulator 83, a conductor 43b has a region in contact with the upper surface of the conductor 42b.
is provided. There is. Further, on the insulator 83, a conductor 43c is provided which has a region in contact with the upper surface of the conductor 42e. Furthermore, a conductor 84 is provided on the insulator 83 . Note that the conductor 84 has the function of the other electrode of the capacitive element 80a.

An insulator 134 is provided on the insulator 83, the conductor 43a, the conductor 43b, the conductor 43c, and the conductor 84. The insulator 134 includes a conductor 131 that functions as a plug.
and 132 are provided. The conductors 131 and 132 are formed in the opening of the insulator 134, with their lower surfaces in contact with the conductor 43a.

Here, as the conductor 131, a conductor that can be used for the nitrogen-containing metal 20a shown in FIGS. 2A and 2B may be used. In addition, the conductor 132 is shown in FIGS.
Any conductor that can be used for the conductor 21a shown in FIG.

A conductor 133 functioning as a wiring is formed on an insulator 134. Conductor 133
is in contact with the exposed upper surfaces of the conductor 131 and the conductor 132. Here, the conductor 133
In this case, any conductor that can be used as the conductor 33a, the conductor 33b, and the conductor 33e may be used.

An insulator 136 is formed on the insulator 134 so as to have an opening above the conductor 133. For the insulator 136, an insulator that can be used for the insulator 134 may be used. Also,
As the insulator 136, an organic insulating film such as polyimide may be used.

<Method for manufacturing a transistor including an oxide semiconductor film>

Next, a method for manufacturing a transistor 60a having an oxide semiconductor film on a conductor 62a and a conductor 62b functioning as a back gate of the transistor 60a shown in FIG. 12 will be described using cross-sectional views shown in FIGS. 21 and 22. explain. FIG. 21(A), FIG. 21(C),
21(E), FIG. 22(A), FIG. 22(C), and FIG. 22(E) are cross-sectional views corresponding to the channel length direction A1-A2 of the transistor 60a, and FIG. 21(B), FIG. D), Figure 2
1(F), FIG. 22(B), FIG. 22(D), and FIG. 22(F) are cross-sectional views corresponding to the channel width direction A3-A4 of the transistor 60a.

First, the insulator 65 is formed on the insulator 67, the conductor 62a, and the conductor 62b. As the insulator 65, the above-mentioned insulator may be used. The insulator 65 is formed by a sputtering method,
This can be carried out using a CVD method, an MBE method, a PLD method, an ALD method, or the like. for example,
As the insulator 65, a film of silicon oxide, silicon oxynitride, or the like may be formed using the PECVD method.

Next, an insulator 63 is formed on the insulator 65. As the insulator 63, the above-mentioned insulator may be used. The insulator 63 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as the insulator 63, a film of hafnium oxide, aluminum oxide, or the like may be formed using an ALD method.

Next, an insulator 64 is formed on the insulator 63 (see FIGS. 21A and 21B). Insulator 64
As such, the above-mentioned insulator may be used. The film of the insulator 64 is formed by sputtering method or CVD.
This can be carried out using a method such as a method, an MBE method, a PLD method, an ALD method, or the like. For example, as the insulator 64, a film of silicon oxide, silicon oxynitride, or the like may be formed using a PECVD method. In addition, the film formation of the insulator 65, the insulator 63, and the insulator 64 is not exposed to the atmosphere.
It may be performed continuously using the LD method.

Next, it is preferable to perform heat treatment. By performing heat treatment, the insulator 65 and the insulator 63
And water or hydrogen in the insulator 64 can be further reduced. In addition, the insulator 6
4 may be allowed to have excess oxygen. Heat treatment is 250℃ or higher and 650℃
Hereinafter, preferably the temperature is 350°C or higher and 450°C or lower. Furthermore, when using tantalum nitride for the conductor 62a, which is the back gate of the transistor, the heat treatment temperature is set to 350°C.
The temperature may be higher than or equal to 410°C, preferably higher than or equal to 370°C and lower than or equal to 400°C. By performing heat treatment in such a temperature range, release of hydrogen from tantalum nitride can be suppressed. The heat treatment is carried out in an inert gas atmosphere or with an oxidizing gas of 10 ppm or more, 1% or more, or 1
It is carried out in an atmosphere containing 0% or more. The heat treatment may be performed under reduced pressure. Or, heat treatment is
After heat treatment in an inert gas atmosphere, add 10pp of oxidizing gas to compensate for the desorbed oxygen.
The heat treatment may be performed in an atmosphere containing m or more, 1% or more, or 10% or more. Heat treatment can remove impurities such as hydrogen and water. For the heat treatment, an RTA device using lamp heating can also be used. Heat treatment using an RTA apparatus takes a shorter time than using a furnace, and is therefore effective for increasing productivity.

Next, an insulator 69a that will become the insulator 66a is formed. As the insulator 69a, an insulator or a semiconductor that can be used as the above-mentioned insulator 66a may be used. Insulator 69a
The film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, it is preferable to form the insulator 69a while heating the substrate. The temperature for heating the substrate may be, for example, the same as in the heat treatment described later.

Next, a semiconductor that will become the semiconductor 66b is formed. As the semiconductor 66b, a semiconductor that can be used as the semiconductor 66b described above may be used. The film formation of the semiconductor 66b is as follows:
This can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Further, it is preferable that the semiconductor 66b be formed while heating the substrate. The temperature for heating the substrate may be, for example, the same as in the heat treatment described later. Note that by sequentially performing the film formation of the insulator 69a and the film formation of the semiconductor to become the semiconductor 66b without exposing it to the atmosphere, it is possible to reduce the incorporation of impurities into the film and the interface.

Next, it is preferable to heat the insulator 69a and the semiconductor 69b. By performing the heat treatment, the hydrogen concentration in the insulator 66a and the semiconductor 66b may be reduced. Further, oxygen vacancies in the insulator 66a and the semiconductor 66b can be reduced in some cases. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 350°C or higher and 450°C or lower. Furthermore, when tantalum nitride is used for the conductor 62a, which is the back gate of the transistor, the heat treatment temperature is set at 350° C. or higher and 410° C. or lower, preferably 370° C. or higher and 40° C. or higher.
The temperature may be 0°C or lower. By performing heat treatment in such a temperature range, release of hydrogen from tantalum nitride can be suppressed. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to compensate for the desorbed oxygen after the heat treatment is performed in an inert gas atmosphere. The heat treatment can improve the crystallinity of the insulator 66a and the semiconductor 66b, and can remove impurities such as hydrogen and water. For the heat treatment, an RTA device using lamp heating can also be used. Heat treatment using an RTA apparatus takes a shorter time than using a furnace, and is therefore effective for increasing productivity. Insulator 66a and semiconductor 66
When CAAC-OS, which will be described later as b, is used, heat treatment increases the peak intensity and decreases the full width at half maximum. That is, the heat treatment increases the crystallinity of CAAC-OS.

Through the heat treatment, oxygen can be supplied from the insulator 64 to the insulator 69a and the semiconductor 69b. By performing heat treatment on the insulator 64, oxygen can be extremely easily supplied to the insulator that will become the insulator 66a and the semiconductor that will become the semiconductor 66b.

Here, the insulator 63 functions as a barrier film that blocks oxygen. By providing the insulator 63 under the insulator 64, oxygen diffused into the insulator 64 can be prevented from diffusing into layers below the insulator 64.

By supplying oxygen to the insulator that will become the insulator 66a and the semiconductor that will become the semiconductor 66b and reducing oxygen vacancies, high-purity intrinsic or substantially high-purity intrinsic oxidation with low defect level density can be achieved. It can be a physical semiconductor.

Next, the conductor 68 that becomes the conductor 68a and the conductor 68b is formed (FIG. 21C) (D
)reference. ). The conductor 68 may be any conductor that can be used as the conductor 68a and the conductor 68b described above. The conductor 68 can be formed by sputtering, CVD, or MBE.
This can be carried out using a method such as a method, a PLD method, an ALD method, or the like. For example, tantalum nitride may be formed as the conductor 68 by sputtering, and tungsten may be further formed thereon.

Next, a resist or the like is formed on the conductor 68, and the insulator 69a,
The semiconductor 69b and the conductor 68 are processed into island shapes to form the island-shaped conductor 68, semiconductor 66b, and insulator 66a.

Next, heat treatment may be performed. By performing the heat treatment, water or hydrogen in the insulator 64, the insulator 63, the insulator 65, the insulator 66a, and the semiconductor 66b can be further reduced. The heat treatment is 250°C or more and 650°C or less, preferably 350°C or more and 450°C
You can do it below. Furthermore, when tantalum nitride is used for the conductor 62a, which is the back gate of the transistor, the heat treatment temperature is set at 350°C or more and 410°C or less, preferably 370°C.
The temperature may be set to above 400°C or below. By performing heat treatment in such a temperature range, release of hydrogen from tantalum nitride can be suppressed. The heat treatment may be performed in an inert gas atmosphere. Alternatively, the process may be performed in an atmosphere containing an oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen after the heat treatment is performed in an inert gas atmosphere. For the heat treatment, an RTA device using lamp heating can also be used. Heat treatment using an RTA apparatus takes a shorter time than using a furnace, and is therefore effective for increasing productivity.

By the heat treatment performed so far, impurities such as water and hydrogen that affect the oxide semiconductor can be reduced before the oxide semiconductor is formed. Furthermore, as described above, the insulator 61
By blocking the via hole formed in the insulator 61 with a conductor 121a or the like, it is possible to suppress impurities such as hydrogen contained in a layer below the insulator 61 from diffusing into a layer above the insulator 61. Further, by setting the temperature of the process performed after the oxide semiconductor film is formed to be lower than the temperature at which hydrogen is released from the conductor 121a or the like, the influence of impurity diffusion can be reduced.

By forming the insulator 66a and the semiconductor 66b and performing heat treatment while the surface of the insulator 64 is exposed, the insulator 66a and the semiconductor 66b are formed while suppressing water and hydrogen from being supplied to the insulator 66a and the semiconductor 66b. 64, water or hydrogen in the insulators 63 and 65 can be further reduced.

Further, when forming the insulator 66a and the semiconductor 66b described above, if an etching gas containing impurities such as hydrogen and carbon is used, impurities such as hydrogen and carbon may be incorporated into the insulator 66a and the semiconductor 66b. be. By further performing heat treatment after forming the insulator 66a and the semiconductor 66b in this manner, impurities such as hydrogen and carbon taken in during etching can be removed.

Next, a resist or the like is formed on the island-shaped conductor 68 and processed using the resist or the like.
A conductor 68a and a conductor 68b are formed (see FIGS. 21E and 21F).

Further, a low resistance region may be formed in a region of the semiconductor 66b that is in contact with the conductor 68a or the conductor 68b. Further, the semiconductor 66b may have a region between the conductor 68a and the conductor 68b that is thinner than the region overlapping the conductor 68a or the conductor 68b. This is formed by removing a portion of the upper surface of the semiconductor 66b when forming the conductor 68a and the conductor 68b.

Next, an insulator 69c, which becomes an insulator 66c, is formed on the insulator 64, the insulator 66a, the semiconductor 66b, the conductor 68a, and the conductor 68b. The insulator 69c is the insulator 6 described above.
An insulator or a semiconductor that can be used as 6c or the like may be used. Insulator 66
The film c can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The surface of the semiconductor 66b, etc. may be etched before forming the insulator that will become the insulator 66c. For example, etching can be performed using plasma containing a rare gas. Thereafter, by continuously forming an insulator to become the insulator 66c without being exposed to the atmosphere, it is possible to reduce the incorporation of impurities into the interface between the semiconductor 66b and the insulator 66c. Impurities present at the interface between films may be more easily diffused than impurities within the film. Therefore, by reducing the amount of impurities mixed in, stable electrical characteristics can be imparted to the transistor.

Next, an insulator 72a that will become the insulator 72 is formed on the insulator 69c. As the insulator 72a, an insulator that can be used as the above-mentioned insulator 72 may be used. Insulator 72a
The film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as the insulator 69c, a film of silicon oxynitride or the like may be formed using a PECVD method. Note that by sequentially performing the film formation of the insulator 69c and the film formation of the insulator 72a without exposing the film to the atmosphere, it is possible to reduce contamination of impurities into the film and at the interface.

Next, a conductor that will become the conductor 74 is formed on the insulator 72 . As the conductor that becomes the conductor 74, a conductor that can be used as the conductor 74 described above may be used. Conductor 74
The conductor film can be formed by sputtering method, CVD method, MBE method, PLD method, ALD method.
This can be done using methods such as law.
For example, a film of titanium nitride may be formed as a conductor to become the conductor 74 using an ALD method, and a film of tantalum nitride may be formed thereon after reverse sputtering using a sputtering method.

Next, a resist or the like is formed on the conductor that will become the conductor 74, and processed using the resist or the like to form the conductor 74 (see FIGS. 22A and 22B).

Next, an insulator that will become the insulator 79 is formed on the insulator 72a. As the insulator 79, an insulator that can be used as the insulator 79 described above may be used. Insulator 7
The insulator film 9 can be formed by sputtering method, CVD method, MBE method, PLD method, AL
This can be done using the D method or the like. For example, as the insulator that becomes the insulator 79, gallium oxide, aluminum oxide, or the like may be formed using an ALD method.

Next, a resist or the like is formed on the insulator that will become the insulator 79, and processed using the resist or the like to form the insulator 79 (see FIGS. 22C and 22D).

Next, the insulator 7 is placed on the insulator 64, the insulator 79, the conductor 68a, the conductor 68b, etc.
7 is formed into a film. As the insulator 77, the above-mentioned insulator may be used. As mentioned above, the insulator 77 preferably contains few impurities such as hydrogen, water, and nitrogen oxides. The insulator 77 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, as the insulator 77, a film of silicon oxynitride or the like may be formed using a PECVD method.

Next, it is preferable to improve the flatness of the upper surface of the insulator 77 using a CMP method or the like.

Here, as shown in FIG. 20, the scribe line 138 is
It is preferable to form openings in the insulator 67, insulator 65, insulator 63, insulator 64, and insulator 77 in the vicinity of the area overlapping with the insulator 67, insulator 65, insulator 63, insulator 64, and insulator 77.

Next, an insulator 78 is formed on the insulator 77. The above-mentioned insulator may be used as the insulator 78 (see FIGS. 22(E) and 22(F)). The insulator 78 is formed by sputtering method, CVD
This can be carried out using a method such as a method, an MBE method, a PLD method, an ALD method, or the like. Note that in the vicinity of the scribe line 138 shown in FIG. 17, an insulator 78 is formed to cover the side surfaces of the insulator 67, insulator 65, insulator 63, insulator 64, and insulator 77 in the opening, and Insulator 78 and insulator 61 are in contact with each other.

The insulator 78 is preferably formed by using plasma, more preferably by sputtering, and even more preferably by sputtering in an atmosphere containing oxygen.

The sputtering method uses DC (Direct C), which uses a DC power source as a sputtering power source.
Further, a pulsed DC sputtering method in which a bias is applied in a pulsed manner, and an RF (Radio Frequency) sputtering method in which a high frequency power source is used as a sputtering power source may be used. Further, a magnetron sputtering method in which a magnet mechanism is provided inside a chamber, a bias sputtering method in which a voltage is also applied to the substrate during film formation, a reactive sputtering method performed in a reactive gas atmosphere, etc. may be used. Alternatively, the above-mentioned PESP or VDSP may be used. Note that the oxygen gas flow rate and film-forming power for sputtering may be appropriately determined depending on the amount of oxygen added and the like.

Here, as the insulator 78, it is preferable to provide an oxide insulating film such as aluminum oxide that has a blocking effect against oxygen, hydrogen, water, and the like. For example, aluminum oxide may be formed as the insulator 78 using a sputtering method. Furthermore, it is preferable to form an aluminum oxide film thereon using an ALD method. By using aluminum oxide formed into a film using the ALD method, the formation of pinholes can be prevented, so that the blocking performance of the insulator 61 against hydrogen and water can be further improved.

By forming the insulator 78 by sputtering, oxygen is added to the vicinity of the surface of the insulator 77 (after the insulator 78 is formed, the interface between the insulator 77 and the insulator 78) at the same time as the film is formed. Here, oxygen is added to the insulator 77 as, for example, oxygen radicals, but the state in which oxygen is added is not limited to this. Oxygen may be added to the insulator 77 in the form of oxygen atoms, oxygen ions, or the like. Note that with the addition of oxygen, the insulator 77 may contain more oxygen than the stoichiometric composition, and the oxygen at this time can also be referred to as excess oxygen.

Note that it is preferable to heat the substrate when forming the insulator 78. Substrate heating is 250
It may be carried out at a temperature of 350°C or higher and 450°C or lower, preferably 350°C or higher and 450°C or lower. Further, when tantalum nitride is used for the conductor 62a, which is the back gate of the transistor, the heat treatment temperature may be set to 350° C. or higher and 410° C. or lower, preferably 370° C. or higher and 400° C. or lower.
By performing heat treatment in such a temperature range, release of hydrogen from tantalum nitride can be suppressed.

Next, it is preferable to perform heat treatment. By performing the heat treatment, oxygen added to the insulator 64 or the insulator 77 can be diffused and supplied to the insulator 66a, the semiconductor 66b, the insulator 66ca, and the insulator 66cb. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 350°C or higher and 450°C or lower. The heat treatment is performed in an inert gas atmosphere or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. The heat treatment may be performed under reduced pressure. For the heat treatment, an RTA device using lamp heating can also be used.

Further, the temperature of the heat treatment is preferably lower than that of the heat treatment after the semiconductor 66b is formed. The temperature difference from the heat treatment after forming the semiconductor 66b film is 20°C or more and 150°C or less, preferably 40°C.
Above 100°C. This makes it possible to suppress excessive release of excess oxygen (oxygen) from the insulator 64 and the like. Note that the heat treatment after forming the insulator 78 may be performed if equivalent heat treatment can be performed during the formation of each layer (for example, when equivalent heating is performed during the formation of the insulator 78). There are cases where it is not necessary.

By the heat treatment, the oxygen added to the insulator 64 and the insulator 77 is diffused into the insulator 64 or the insulator 72. The insulator 78 is an insulator that is less permeable to oxygen than the insulator 77, and functions as a barrier film that blocks oxygen. Since such an insulator 78 is formed on the insulator 77, oxygen that diffuses in the insulator 77 does not diffuse above the insulator 77, but mainly diffuses in the lateral or downward direction through the insulator 77. I will do it. Note that when heating the insulator 78 while heating the substrate, oxygen can be diffused into the insulator 64 and the insulator 77 at the same time as being added.

Oxygen diffused through the insulator 64 or the insulator 77 is supplied to the insulator 66a, the insulator 66ca, the insulator 66cb, and the semiconductor 66b. At this time, by providing the insulator 63 having the function of blocking oxygen under the insulator 64, it is possible to prevent the oxygen diffused into the insulator 64 from diffusing into layers below the insulator 64. . Furthermore, in the vicinity of the scribe line 138 shown in FIG. It can be filled with oxygen, and oxygen can be supplied from the insulator 77 to the insulator 66a, the semiconductor 66b, and the insulator 66c.

Furthermore, during the heat treatment, impurities such as hydrogen and water that diffuse from the lower layer are blocked by the insulator 61 and the conductor 121a provided in the via hole of the insulator 61, and are diffused from the top and side surfaces of the insulator 77. Impurities such as hydrogen and water can be blocked by the insulator 78. As a result, the insulator 7 is wrapped with the insulator 61 and the insulator 78.
7. The amount of impurities such as hydrogen and water can be reduced in the insulator 66a, the insulator 66c, the semiconductor 66b, and the like. In addition, impurities such as hydrogen in the insulator 77, etc.
It may combine with oxygen to form water, which may prevent oxygen from diffusing. Therefore, by reducing the amount of impurities such as hydrogen and water in the insulator 77, the supply of oxygen can be promoted.

In this way, it is possible to suppress the diffusion of impurities such as water and hydrogen and effectively supply oxygen to the insulator 66a, the insulator 66c, and the semiconductor 66b, especially the region where the channel is formed in the semiconductor 66b. can. By supplying oxygen to the insulator 66a, the insulator 66ca, the insulator 66cb, and the semiconductor 66b and reducing oxygen vacancies, high-purity intrinsic or substantially high-purity intrinsic oxidation with low defect level density is achieved. It can be a physical semiconductor.

Note that the heat treatment after the insulator 78 is formed may be performed at any time after the insulator 78 is formed. For example, it may be performed after the insulator 119 is formed.

In this way, the transistor 60a can be formed.

In this manner, by using the method for manufacturing a semiconductor device described in this embodiment, a semiconductor device including a transistor with stable electrical characteristics can be provided. Furthermore, by using the method for manufacturing a semiconductor device described in this embodiment, a semiconductor device including a transistor with low leakage current when non-conducting can be provided. Furthermore, by using the method for manufacturing a semiconductor device described in this embodiment, a semiconductor device including a transistor with normally-off electrical characteristics can be provided. Further, by using the method for manufacturing a semiconductor device described in this embodiment, a semiconductor device including a highly reliable transistor can be provided.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes and examples described in this specification.

(Embodiment 2)
In this embodiment, details of the oxide semiconductor included in the semiconductor device of one embodiment of the present invention will be described below.

<Structure of oxide semiconductor>
The structure of an oxide semiconductor will be described below.

Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single crystal oxide semiconductor, CAAC-OS (c-axis-aligned
crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide semiconductor)
uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l
ike oxide semiconductor) and amorphous oxide semiconductor.

From another perspective, oxide semiconductors are divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. As the crystalline oxide semiconductor, single crystal oxide semiconductor, CAAC-
These include OS, polycrystalline oxide semiconductor, and nc-OS.

Amorphous structures are generally isotropic and do not have a heterogeneous structure, are metastable and have an unfixed arrangement of atoms, have flexible bond angles, and have short-range order but not long-range order. It is said that it does not have

In other words, a stable oxide semiconductor is transformed into a completely amorphous semiconductor.
) cannot be called an oxide semiconductor. Further, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. On the other hand, a-li
Although the ke OS is not isotropic, it is an unstable structure having voids (also called voids).
In terms of instability, a-like OS is close to an amorphous oxide semiconductor in terms of physical properties.

<CAAC-OS>
First, we will explain CAAC-OS.

CAAC-OS is a type of oxide semiconductor having a plurality of c-axis oriented crystal parts (also referred to as pellets).

A case where CAAC-OS is analyzed by X-ray diffraction (XRD) will be described. For example, when a CAAC-OS having an InGaZnO ₄ crystal classified into space group R-3m is analyzed by an out-of-plane method, the diffraction angle (2θ) is as shown in FIG. 24(A). A peak appears near 31°. This peak is attributed to the (009) plane of the InGaZnO ₄ crystal. Therefore, in CAAC-OS, the crystal has c-axis orientation, and the c-axis is the plane on which the CAAC-OS film is formed (formed surface). (Also referred to as a surface.) or in a direction substantially perpendicular to the top surface. In addition, 2θ is 31°
In addition to nearby peaks, a peak may also appear near 2θ of 36°. The peak near 2θ of 36° is due to the crystal structure classified into space group Fd-3m. Therefore, CAAC
-OS preferably does not show this peak.

On the other hand, an in-pla
When structural analysis is performed using the ne method, a peak appears near 2θ of 56°. This peak is I
It is assigned to the (110) plane of nGaZnO ₄ crystal. Even if the analysis (φ scan) is performed while fixing 2θ to around 56° and rotating the sample around the normal vector of the sample surface as the axis (φ axis), a clear No peak appears. On the other hand, single crystal InGaZ
When φ scanning is performed for nO ₄ with 2θ fixed at around 56°, six peaks attributed to crystal planes equivalent to the (110) plane are observed as shown in FIG. 24(C). Therefore, X
Structural analysis using RD confirms that the a-axis and b-axis orientations of CAAC-OS are irregular.

Next, the CAAC-OS analyzed by electron diffraction will be explained. For example, InGaZ
When an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS having an nO ₄ crystal in parallel to the surface on which the CAAC-OS is formed, a diffraction pattern (selected area electron diffraction) as shown in FIG. 24(D) is obtained. ) may appear. This diffraction pattern includes In
A spot due to the (009) plane of the GaZnO ₄ crystal is included. Therefore, electron diffraction also reveals that the pellets contained in the CAAC-OS have c-axis orientation, with the c-axis oriented in a direction substantially perpendicular to the surface on which it is formed or the upper surface. On the other hand, Figure 24(E) shows the diffraction pattern when an electron beam with a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface.
Shown below. From FIG. 24(E), a ring-shaped diffraction pattern is confirmed. Therefore, even by electron diffraction using an electron beam with a probe diameter of 300 nm, it can be seen that the a-axis and b-axis of the pellet contained in CAAC-OS have no orientation. Note that the first ring in FIG. 24(E) is considered to be caused by the (010) plane and (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 24(E) is considered to be due to the (110) plane or the like.

In addition, a transmission electron microscope (TEM)
When a composite analytical image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of CAAC-OS is observed using a microscope, a plurality of pellets can be confirmed. On the other hand, even in a high-resolution TEM image, boundaries between pellets, that is, grain boundaries (also referred to as grain boundaries) may not be clearly visible in some cases. Therefore, CAAC
-OS can be said to be less prone to decrease in electron mobility due to grain boundaries.

Figure 25(A) shows a high-resolution T cross-section of the CAAC-OS observed from a direction approximately parallel to the sample surface.
An EM image is shown. Spherical aberration correction (Spherical Ab
error corrector) function was used. A high-resolution TEM image using a spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image is
For example, it can be observed using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

From FIG. 25(A), a pellet, which is a region in which metal atoms are arranged in a layered manner, can be confirmed. It can be seen that the size of a single pellet is 1 nm or more, or 3 nm or more. Therefore, the pellets can also be referred to as nanocrystals (nc). In addition, the CAAC-OS is a CANC (C-Axis Aligned nano
It can also be called an oxide semiconductor with ocrystals. The pellets are CAAC
-Reflects the unevenness of the formation surface or top surface of the OS, and is parallel to the formation surface or top surface of the CAAC-OS.

In addition, FIGS. 25(B) and 25(C) show CAAC observed from a direction approximately perpendicular to the sample surface.
- Shows a Cs-corrected high-resolution TEM image of the plane of the OS. FIG. 25(D) and FIG. 25(E) are
These are images obtained by image processing of FIG. 25(B) and FIG. 25(C), respectively. The image processing method will be described below. First, Figure 25(B) is transformed into a fast Fourier transform (FFT).
An FFT image is obtained by performing Fourier Transform) processing. Next, mask processing is performed to leave a range between 2.8 nm ⁻¹ and 5.0 nm ⁻¹ in the acquired FFT image with the origin as a reference. Next, the masked FFT image is subjected to inverse fast Fourier transform (IFFT:
Inverse Fast Fourier Transform) processing to obtain an image processed. The image obtained in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 25(D), broken lines indicate locations where the lattice arrangement is disordered. The area surrounded by the broken line is
It is one pellet. The portions indicated by broken lines are the connecting portions between the pellets. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. Note that the shape of the pellet is not limited to a regular hexagonal shape, but is often a non-regular hexagonal shape.

In FIG. 25(E), dotted lines indicate locations where the orientation of the lattice array changes between an area where the lattice arrays are aligned and another area where the lattice arrays are aligned, indicating changes in the orientation of the lattice arrays. Indicated by a broken line. Even in the vicinity of the dotted line, clear grain boundaries cannot be confirmed. By connecting surrounding lattice points around a lattice point near the dotted line, a distorted hexagon, pentagon, and/or heptagon can be formed. That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the a-b plane direction,
This is thought to be because distortion can be tolerated due to changes in the bond distance between atoms due to substitution of metal elements.

As shown above, CAAC-OS has c-axis orientation and a plurality of pellets (nanocrystals) connected in the a-b plane direction, resulting in a distorted crystal structure. Therefore, CA
AC-OS is configured using CAA crystal (c-axis-aligned a-b-pl)
It can also be referred to as an oxide semiconductor having an ane-anchored crystal.

CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors can be degraded by impurities or defects, so CAAC-OS
It can also be said to be an oxide semiconductor with few oxygen vacancies (such as oxygen vacancies).

Note that impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, elements such as silicon, which have a stronger bond with oxygen than the metal elements that make up the oxide semiconductor, deprive the oxide semiconductor of oxygen, disrupting the atomic arrangement of the oxide semiconductor and reducing its crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and causes a decrease in crystallinity.

<nc-OS>
Next, the nc-OS will be explained.

A case where the nc-OS is analyzed by XRD will be explained. For example, when an nc-OS is subjected to structural analysis using an out-of-plane method, no peak indicating orientation appears. That is, the crystal of nc-OS has no orientation.

In addition, for example, an nc-OS having InGaZnO ₄ crystals is made into a thin piece with a thickness of 34 nm.
When an electron beam with a probe diameter of 50 nm is incident on the region parallel to the surface to be formed, the area shown in FIG.
A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) is observed. Further, a diffraction pattern (nanobeam electron diffraction pattern) when an electron beam with a probe diameter of 1 nm is incident on the same sample is shown in FIG. 26(B). From FIG. 26(B), a plurality of spots are observed within the ring-shaped area. Therefore, in the nc-OS, orderliness is not confirmed when an electron beam with a probe diameter of 50 nm is incident, but orderliness is confirmed when an electron beam with a probe diameter of 1 nm is incident.

Furthermore, when an electron beam with a probe diameter of 1 nm is incident on a region with a thickness of less than 10 nm,
As shown in FIG. 26(C), an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal pattern may be observed. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal, in a thickness range of less than 10 nm. Note that since the crystals are oriented in various directions, there are regions where regular electron diffraction patterns are not observed.

FIG. 26(D) shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. In the high-resolution TEM image of the nc-OS, there are areas where crystal parts can be confirmed, such as areas indicated by auxiliary lines, and areas where no crystal parts can be clearly confirmed. The crystal part included in the nc-OS has a size of 1 nm or more and 10 nm or less, and particularly often has a size of 1 nm or more and 3 nm or less. Note that the size of the crystal part is 1
An oxide semiconductor with a diameter greater than 0 nm and less than or equal to 100 nm is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor).
crystalline oxide semiconductor). In nc-OS, for example, grain boundaries may not be clearly visible in a high-resolution TEM image. Note that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, hereinafter, the crystal part of the nc-OS may be referred to as a pellet.

As described above, the nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, in nc-OS, no regularity is observed in the crystal orientation between different pellets. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductor.

In addition, since the crystal orientation among pellets (nanocrystals) does not have regularity, nc-OS is
It can also be called an oxide semiconductor having RANC (Random Aligned nanocrystals) or an oxide semiconductor having NANC (Non-Aligned nanocrystals).

The nc-OS is an oxide semiconductor with higher regularity than an amorphous oxide semiconductor. Therefore,
The nc-OS has a lower defect level density than an a-like OS or an amorphous oxide semiconductor. However, in nc-OS, there is no regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher defect level density than the CAAC-OS.

<a-like OS>
The a-like OS is an oxide semiconductor having a structure between that of an nc-OS and an amorphous oxide semiconductor.

FIG. 27 shows a high-resolution cross-sectional TEM image of a-like OS. Here, FIG. 27(A) is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. Figure 27 (B
) is a high-resolution cross-sectional TEM image of a-like OS after irradiation with electrons (e ⁻ ) of 4.3×10 ⁸ e ⁻ /nm ² . From FIG. 27(A) and FIG. 27(B), a-like OS
It can be seen that striped bright regions extending in the vertical direction are observed from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. Note that the bright region is presumed to be a hole or a low density region.

Because of this problem, a-like OS has an unstable structure. Below, a-like
To show that the OS has an unstable structure compared to CAAC-OS and nc-OS, the structure change due to electron irradiation is shown.

A-like OS, nc-OS, and CAAC-OS are prepared as samples. Both samples are In--Ga--Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is obtained. High-resolution cross-sectional TEM images show that each sample has crystalline parts.

Note that the unit cell of InGaZnO ₄ crystal has three In-O layers and Ga-Zn-
It is known to have a structure in which a total of nine layers, including six O layers, are layered in the c-axis direction. The spacing between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, parts where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less are referred to as InGaZn
It was regarded as a crystal part of _O4 . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 28 is an example in which the average size of crystalline parts (22 to 30 places) of each sample was investigated. Note that the length of the lattice fringes mentioned above is the size of the crystal part. From Figure 28, a-like
It can be seen that the crystal part of the OS becomes larger in accordance with the cumulative amount of electron irradiation related to acquisition of a TEM image. From FIG. 28, the crystal part (also called initial nucleus), which was about 1.2 nm in size at the initial stage of TEM observation, has a cumulative electron (e ^- ) irradiation dose of 4.2×10 ⁸ e ^-
/nm ² , it can be seen that the size has grown to about 1.9 nm. On the other hand, nc
-OS and CAAC-OS have a cumulative electron irradiation dose of 4.2×10 ⁸ from the start of electron irradiation.
It can be seen that there is no change in the size of the crystal part in the range up to e ⁻ /nm ² . From FIG. 28, the size of the crystal part of nc-OS and CAAC-OS is
It can be seen that they are approximately 1.3 nm and 1.8 nm, respectively. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an accelerating voltage of 300 kV, a current density of 6.7×10 ⁵ e ⁻ /(nm ² ·s), and a diameter of the irradiation area of 230 nm.

As described above, in the a-like OS, growth of crystal parts may be observed due to electron irradiation. On the other hand, in nc-OS and CAAC-OS, almost no growth of crystal parts due to electron irradiation is observed. That is, compared to nc-OS and CAAC-OS, a-like OS has
It can be seen that the structure is unstable.

Furthermore, because of the structure, a-like OS has a lower density structure than nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal with the same composition. Also, the density of nc-OS and CAAC
The density of -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor whose density is less than 78% of that of a single crystal.

For example, in an oxide semiconductor satisfying an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO ₄ having a rhombohedral crystal structure is 6.357 g/cm ³ . Therefore, for example, in an oxide semiconductor that satisfies the [atomic ratio] of In:Ga:Zn=1:1:1, the density of a-like OS is 5.0 g/cm ³ or more and less than 5.9 g/cm ³ . Further, for example, in an oxide semiconductor satisfying an atomic ratio of In:Ga:Zn=1:1:1,
The density of nc-OS and CAAC-OS is 5.9 g/cm ³ or more and 6.3 g/cm ³
less than

Note that when single crystals with the same composition do not exist, by combining single crystals with different compositions at an arbitrary ratio, it is possible to estimate the density corresponding to a single crystal with a desired composition. The density corresponding to a single crystal with a desired composition is determined by the ratio of combining single crystals with different compositions.
It can be estimated using a weighted average. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

As described above, oxide semiconductors have various structures, each having various properties. Note that the oxide semiconductor is, for example, an amorphous oxide semiconductor, a-like OS, nc-OS,
It may be a laminated film having two or more types of CAAC-OS.

<Carrier density of oxide semiconductor>
Next, carrier density of an oxide semiconductor will be explained below.

Factors that affect carrier density in oxide semiconductors include oxygen vacancies (
Vo) or impurities in an oxide semiconductor.

When the number of oxygen vacancies in an oxide semiconductor increases, the density of defect levels increases when hydrogen is bonded to the oxygen vacancies (this state is also referred to as VoH). Alternatively, when the amount of impurities in the oxide semiconductor increases, the density of defect levels increases due to the impurities. Therefore, by controlling the defect level density in the oxide semiconductor, the carrier density in the oxide semiconductor can be controlled.

Here, a transistor using an oxide semiconductor in a channel region will be considered.

When the purpose is to suppress a negative shift in the threshold voltage of a transistor or reduce the off-state current of a transistor, it is preferable to lower the carrier density of the oxide semiconductor. In order to lower the carrier density of the oxide semiconductor, the impurity concentration in the oxide semiconductor may be lowered to lower the defect level density. In this specification and the like, low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic. The carrier density of a high-purity intrinsic oxide semiconductor is less than 8×10 ¹⁵ cm ⁻³ , preferably 1×10 ¹¹
cm ⁻³ , more preferably less than 1×10 ¹⁰ cm ⁻³ and 1×10 ⁻⁹ cm ⁻
It may be ³ or more.

On the other hand, when the purpose is to improve the on-current of a transistor or the field effect mobility of a transistor, it is preferable to increase the carrier density of the oxide semiconductor. In order to increase the carrier density of the oxide semiconductor, the impurity concentration of the oxide semiconductor may be slightly increased or the defect level density of the oxide semiconductor may be slightly increased. Alternatively, the band gap of the oxide semiconductor may be made smaller. For example, Id-Vg of a transistor
An oxide semiconductor with a slightly high impurity concentration or a slightly high defect level density can be considered to be substantially intrinsic within a range where a characteristic on/off ratio can be achieved. In addition, an oxide semiconductor that has a large electron affinity, a correspondingly small band gap, and an increased density of thermally excited electrons (carriers) can be substantially considered to be intrinsic. Note that when an oxide semiconductor with higher electron affinity is used, the threshold voltage of the transistor becomes lower.

The above-mentioned oxide semiconductor with increased carrier density is slightly n-type. Therefore, an oxide semiconductor with increased carrier density may be referred to as "Slightly-n".

The carrier density of a substantially intrinsic oxide semiconductor is 1×10 ⁵ cm ⁻³ or more and 1×10 ¹⁸ c
m ⁻³ or less, more preferably 1×10 ⁷ cm ⁻³ or more and 1×10 ¹⁷ cm ⁻³ or less, and even more preferably 1×10 ⁹ cm ⁻³ or more and 5×10 ¹⁶ cm ⁻³ or less, and 1×10 ¹⁰
cm ⁻³ or more and 1×10 ¹⁶ cm ⁻³ or less, more preferably 1×10 ¹¹ cm ⁻³ or more and 1
More preferably, it is not more than ×10 ¹⁵ cm ⁻³ .

As described above, this embodiment mode can be implemented by appropriately combining at least a portion thereof with other embodiment modes and examples described in this specification.

(Embodiment 3)
In this embodiment, an example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described.

<Circuit>
An example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described below.

<CMOS inverter>
The circuit diagram shown in FIG. 29A shows a so-called CMO in which a p-channel transistor 2200 and an n-channel transistor 2100 are connected in series and their respective gates are connected.
The configuration of the S inverter is shown. Here, in the circuit shown in FIG. 29(A), the transistor 2
The transistor 200 can be formed using the transistor 60a shown in FIG. 12 or the transistor 60b shown in FIG. 13, and the transistor 2100 can be formed using the transistor 90a or the transistor 90b shown in FIG.

In the semiconductor device shown in FIG. 29A, the area occupied by the element can be reduced by manufacturing a p-channel transistor using a semiconductor substrate and manufacturing an n-channel transistor above it. That is, the degree of integration of the semiconductor device can be increased. Furthermore, compared to the case where an n-channel transistor and a p-channel transistor are manufactured using the same semiconductor substrate, the process can be simplified, so productivity of the semiconductor device can be increased. Furthermore, the yield of semiconductor devices can be increased. Further, p-channel transistors can sometimes omit complicated processes such as LDD (Lightly Doped Drain) regions, shallow trench structures, and strain designs. Therefore, productivity and yield can be increased in some cases compared to the case where an n-channel transistor is manufactured using a semiconductor substrate.

<CMOS analog switch>
Further, the circuit diagram shown in FIG. 29B shows a structure in which the sources and drains of the transistor 2100 and the transistor 2200 are connected. With such a configuration, it can function as a so-called CMOS analog switch. Here, FIG. 29(B)
In the circuit shown in FIG. 1, the transistor 2200 can be formed using the transistor 60a shown in FIG. 12 or the transistor 60b shown in FIG. 13, and the transistor 2100 can be formed using the transistor 90a or the transistor 90b shown in FIG. .

<Storage device 1>
FIG. 30 shows an example of a semiconductor device (storage device) using a transistor according to one embodiment of the present invention, which can retain memory contents even in a situation where power is not supplied, and has no limit to the number of times of writing.
Shown below.

The semiconductor device illustrated in FIG. 30A includes a transistor 3200 using a first semiconductor, a transistor 3300 using a second semiconductor, and a capacitor 3400. Note that as the transistor 3300, a transistor similar to the above-described transistor 2100 can be used. Here, the circuit shown in FIG. It can be formed using a semiconductor device shown in No. 19 or the like.

The transistor 3300 is preferably a transistor with low off-state current. transistor 33
For example, a transistor using an oxide semiconductor can be used as the transistor 00. Since the off-state current of the transistor 3300 is small, memory contents can be retained at a specific node of the semiconductor device for a long period of time. In other words, a refresh operation is not required or the frequency of refresh operations can be extremely reduced, resulting in a semiconductor device with low power consumption.

In FIG. 30A, a first wiring 3001 is electrically connected to the source of the transistor 3200, and a second wiring 3002 is electrically connected to the drain of the transistor 3200. Further, the third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300, and the fourth wiring 3004 is electrically connected to the gate of the transistor 3300. and the gate of transistor 3200 and the source of transistor 3300,
The other side of the drain is electrically connected to one of the electrodes of the capacitor 3400 and connected to the fifth wiring 30.
05 is electrically connected to the other electrode of the capacitive element 3400.

The semiconductor device shown in FIG. 30A has a characteristic that the potential of the gate of the transistor 3200 can be held, so that information can be written, held, and read as described below.

Describe writing and retaining information. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the node FG electrically connected to the gate of the transistor 3200 and one of the electrodes of the capacitor 3400. That is, a predetermined charge is applied to the gate of the transistor 3200 (writing). Here, charges that provide two different potential levels (hereinafter referred to as low level charges and high level charges) are used.
Either of these shall be given. Thereafter, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is rendered non-conductive, thereby rendering the transistor 3300 non-conductive, thereby retaining charge at the node FG (retention).

Since the off-state current of transistor 3300 is small, the charge on node FG is held for a long period of time.

Next, reading information will be explained. When an appropriate potential (read potential) is applied to the fifth interconnect 3005 while a predetermined potential (constant potential) is applied to the first interconnect 3001, the second interconnect 3002 receives the charge held at the node FG. Takes a potential depending on the amount. This means that if the transistor 3200 is an n-channel type, the apparent threshold voltage V _{th_H} when a high level charge is applied to the gate of the transistor 3200 is different from the apparent threshold voltage V th_H when a low level charge is applied to the gate of the transistor 3200. This is because the threshold voltage V _{th_L} is lower than the apparent threshold voltage V th_L in the case where the threshold voltage V th_L exists. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary to bring the transistor 3200 into a "conductive state". Therefore, by setting the potential of the fifth wiring 3005 to the potential V ₀ between V _{th_H} and V _{th_L} , the charge applied to the node FG can be determined. For example, in writing, node FG
When a high level charge is applied to , the potential of the fifth wiring 3005 becomes V ₀ (>
V _{th_H} ), the transistor 3200 becomes “conductive”. On the other hand, node FG
When a low level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V ₀ (<V
_{th_L} ), the transistor 3200 remains “non-conducting”. Therefore, by determining the potential of the second wiring 3002, the information held in the node FG can be read.

Note that when memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. For example, in a memory cell from which information is not read, a potential that causes the transistor 3200 to be in a "non-conducting state" regardless of the charge applied to the node FG, that is, a potential lower than V _{th_H} is applied to the fifth wiring 3005. Therefore, a configuration may be adopted in which only the information of a desired memory cell can be read. Alternatively, by applying to the fifth wiring 3005 a potential that makes the transistor 3200 conductive regardless of the charge applied to the node FG, that is, a potential higher than V _{th_L} , only the information of the desired memory cell can be transmitted. The configuration may be such that it can be read.

Note that although the example in which two types of charges are held in the node FG has been described above, the semiconductor device according to the present invention is not limited to this. For example, the node FG of the semiconductor device may have a configuration in which three or more types of charges can be held at the node. With such a configuration, the semiconductor device can be multivalued and its storage capacity can be increased.

<Storage device 2>
The semiconductor device shown in FIG. 30B differs from the semiconductor device shown in FIG. 30A in that it does not include the transistor 3200. In this case as well, information can be written and held by operations similar to those of the semiconductor device shown in FIG. 30(A). Here, the circuit shown in FIG. 30(B) is
The transistor 3300 can be formed using the transistor 60a shown in FIG. 12 or the transistor 60b shown in FIG. 13, and the capacitor 3400 can be formed using the capacitor 80a shown in FIG.
It can be formed using, for example. Further, a sense amplifier or the like may be provided in the lower layer of the semiconductor device shown in FIG. 30(B), and in that case, the transistor 90a shown in FIG.
Alternatively, it can be formed using the transistor 90b.

Reading information in the semiconductor device shown in FIG. 30(B) will be described. When the transistor 3300 becomes conductive, the third wiring 3003 and the capacitor 3400 in a floating state
are electrically connected, and charges are redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 takes different values depending on the potential of one of the electrodes of the capacitor 3400 (or the charge accumulated in the capacitor 3400).

For example, the potential of one electrode of the capacitive element 3400 is V, the capacitance of the capacitive element 3400 is C, and the third
Assuming that the capacitance component of the wiring 3003 is CB, and the potential of the third wiring 3003 before the charge is redistributed is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB×
VB0+CV)/(CB+C). Therefore, assuming that the potential of one electrode of the capacitive element 3400 has two states, V1 and V0 (V1>V0), as the state of the memory cell,
Potential of the third wiring 3003 when holding the potential V1 (=(CB×VB0+CV1)
/(CB+C)) is the potential of the third wiring 3003 when the potential V0 is held (=(C
It can be seen that it is higher than B×VB0+CV0)/(CB+C)).

Information can then be read by comparing the potential of the third wiring 3003 with a predetermined potential.

In this case, a transistor to which the first semiconductor is applied is used in a drive circuit for driving a memory cell, and a transistor to which the second semiconductor is applied as the transistor 3300 is stacked and arranged on the drive circuit. do it.

The semiconductor device described above can retain memory content for a long period of time by using a transistor that uses an oxide semiconductor and has a small off-state current. In other words, a refresh operation is not required or the frequency of the refresh operation can be made extremely low, so that a semiconductor device with low power consumption can be realized. Further, even when no power is supplied (however, the potential is preferably fixed), it is possible to retain memory contents for a long period of time.

Furthermore, since the semiconductor device does not require a high voltage to write information, element deterioration is less likely to occur. For example, unlike conventional nonvolatile memories, electrons are not injected into the floating gate or extracted from the floating gate, so problems such as deterioration of the insulator do not occur. That is, the semiconductor device according to one embodiment of the present invention has no limit to the number of times that it can be rewritten, which is a problem with conventional nonvolatile memories, and has dramatically improved reliability. Furthermore, since information is written depending on whether the transistor is on or off, high-speed operation is possible.

<Storage device 3>
A modification of the semiconductor device (memory device) shown in FIG. 30A will be described using the circuit diagram shown in FIG.

The semiconductor device illustrated in FIG. 31 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600. Here, as the transistor 4100, a transistor similar to the above-described transistor 3200 can be used, and the transistor 420
For transistors 0 to 4400, transistors similar to the above-described transistor 3300 can be used. Note that although illustration of the semiconductor devices shown in FIG. 31 is omitted in FIG. 31, a plurality of semiconductor devices are provided in a matrix. The semiconductor device shown in FIG. 31 includes a wiring 4001, a wiring 4003, and a wiring 400.
Writing and reading of data voltages can be controlled according to signals or potentials applied to the terminals 5 to 4009. Here, in the circuit shown in FIG. 31, the transistor 4100 can be formed using the transistor 90a or the transistor 90b shown in FIG. The capacitor 4500 and the capacitor 4600 can be formed using the capacitor 80a shown in FIG. 17.

One of the source and drain of the transistor 4100 is connected to the wiring 4003. The other of the source and drain of the transistor 4100 is connected to the wiring 4001. Note that although the conductivity type of the transistor 4100 is shown as a p-channel type in FIG. 33, it may be an n-channel type.

The semiconductor device shown in FIG. 31 has two data holding sections. For example, the first data holding portion holds charges between one of the source or drain of transistor 4400 connected to node FG1, one electrode of capacitor 4600, and one of the source or drain of transistor 4200. Further, the second data holding section is connected between the gate of the transistor 4100 connected to the node FG2, the other of the source or drain of the transistor 4200, one of the source or drain of the transistor 4300, and one electrode of the capacitor 4500. Holds charge.

The other of the source and drain of the transistor 4300 is connected to the wiring 4003. The other of the source and drain of the transistor 4400 is connected to the wiring 4001. A gate of transistor 4400 is connected to wiring 4005. The gate of transistor 4200 is connected to wiring 4006. A gate of the transistor 4300 is connected to a wiring 4007. The other electrode of capacitor 4600 is connected to wiring 4008. Capacitive element 45
The other electrode of 00 is connected to wiring 4009.

The transistors 4200 to 4400 function as switches that control data voltage writing and charge retention. Note that the transistors 4200 to 4400 are preferably transistors in which a low current (off-state current) flows between a source and a drain in a non-conductive state. The transistor with low off-state current is preferably a transistor including an oxide semiconductor in a channel formation region (OS transistor). OS transistors have advantages such as low off-state current and the ability to be fabricated in layers with silicon-containing transistors. Note that although the conductivity types of the transistors 4200 to 14 are shown as n-channel type in FIG. 33, they may be p-channel type.

It is preferable that the transistor 4200, the transistor 4300, and the transistor 4400 be provided in separate layers even if the transistor is formed using an oxide semiconductor. That is, Figure 3
As shown in FIG. 31, the semiconductor device shown in FIG.
021 and a second layer 4022 having transistors 4200 and 4300.
and a third layer 4023 including a transistor 4400.
By stacking layers including transistors, the circuit area can be reduced, and the semiconductor device can be made smaller.

Next, an operation of writing information to the semiconductor device shown in FIG. 31 will be described.

First, a data voltage write operation (hereinafter referred to as
This is called write operation 1. ) will be explained. Note that in the following, the data voltage written to the data holding portion connected to the node FG1 is assumed to be _VD1 , and the threshold voltage of the transistor 4100 is assumed to be Vth.

In write operation 1, after setting the wiring 4003 to V _D1 and setting the wiring 4001 to the ground potential,
Become electrically floating. Also, the wirings 4005 and 4006 are set to high level. Also wiring 4
007 to 4009 are set to low level. Then, the node FG2 which is in an electrically floating state
The potential of the transistor 4100 increases, and current flows through the transistor 4100. When the current flows, the wiring 40
The potential of 01 increases. Further, the transistor 4400 and the transistor 4200 are turned on. Therefore, as the potential of the wiring 4001 rises, the potentials of the nodes FG1 and FG2 rise. When the potential of the node FG2 increases and the voltage (Vgs) between the gate and source of the transistor 4100 reaches the threshold voltage Vth of the transistor 4100, the voltage of the transistor 410 increases.
The current flowing through 0 becomes smaller. Therefore, the potentials of the wiring 4001 and nodes FG1 and FG2 stop rising and become constant at "V _D1 - Vth", which is lower than V _D1 by Vth.

In other words, V _D1 applied to the wiring 4003 is reduced by the current flowing through the transistor 4100.
The voltage is applied to the wiring 4001, and the potentials of nodes FG1 and FG2 rise. When the potential of the node FG2 becomes "V _D1 - Vth" due to the increase in potential, the Vgs of the transistor 4100 becomes Vth, and the current stops.

Next, the operation of writing a data voltage to the data holding section connected to the node FG2 (hereinafter referred to as write operation 2) will be described. Note that the description will be made assuming that the data voltage written to the data holding section connected to the node FG2 is _VD2 .

In write operation 2, after setting the wiring 4001 to V _D2 and setting the wiring 4003 to the ground potential,
Become electrically floating. Also, the wiring 4007 is set to high level. Also, wiring 4005, 4
Set 006, 4008, and 4009 to low level. The transistor 4300 is turned on and the wiring 4003 is set to a low level. Therefore, the potential of node FG2 also drops to a low level, and current flows through transistor 4100. As the current flows, the potential of the wiring 4003 increases. Further, the transistor 4300 becomes conductive. Therefore, as the potential of the wiring 4003 increases, the potential of the node FG2 increases. When the potential of node FG2 rises and Vgs of transistor 4100 reaches Vth of transistor 4100, transistor 4
The current flowing through 100 becomes smaller. Therefore, the potentials of the wiring 4003 and FG2 stop rising and become constant at "V _D2 - Vth", which is lower than V _D2 by Vth.

In other words, V _D2 applied to the wiring 4001 is reduced by the current flowing through the transistor 4100.
It is applied to wiring 4003, and the potential of node FG2 rises. When the potential of the node FG2 becomes "V _D2 - Vth" due to the increase in potential, Vgs of the transistor 4100 becomes Vth, and the current stops. At this time, the potential of the node FG1 is
400 are in a non-conductive state, and "V _D1 -Vth" written in write operation 1 is held.

In the semiconductor device shown in FIG. 33, after data voltages are written into a plurality of data holding parts, the wiring 4009 is set to a high level to raise the potentials of nodes FG1 and FG2. Then, each transistor is made non-conductive to eliminate the movement of charge and hold the written data voltage.

By the above-described operation of writing data voltages to nodes FG1 and FG2, data voltages can be held in a plurality of data holding sections. Note that the written potential is “V _D
1 -Vth" and "V _D2 -Vth" have been described as examples, but these are data voltages corresponding to multi-value data. Therefore, when holding 4-bit data in each data holding section, 16 values of "V _D1 -Vth" and "V _D2 -Vth" can be taken.

Next, the operation of reading information from the semiconductor device shown in FIG. 31 will be described.

First, a data voltage reading operation (hereinafter referred to as
This is called read operation 1. ) will be explained.

In read operation 1, the wiring 4003 is precharged and then placed in an electrically floating state.
discharge. Wires 4005 to 4008 are set to low level. Further, the wiring 4009 is set to a low level, and the potential of the node FG2, which is in an electrically floating state, is set to "V _D2 -Vth". As the potential of node FG2 decreases, current flows through transistor 4100. As the current flows, the potential of the electrically floating wiring 4003 decreases. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When the Vgs of the transistor 4100 becomes the Vth of the transistor 4100, the current flowing through the transistor 4100 becomes small. In other words, the potential of the wiring 4003 is equal to the potential of the node FG2 "V _D2 - Vth"
, it becomes "V _D2 " which is a value larger by Vth. The potential of this wiring 4003 is the node F
It corresponds to the data voltage of the data holding unit connected to G2. The data voltage of the read analog value undergoes A/D conversion to obtain data in the data holding section connected to the node FG2.

That is, by placing the precharged wiring 4003 in a floating state and switching the potential of the wiring 4009 from a high level to a low level, a current flows through the transistor 4100. As the current flows, the potential of the wiring 4003, which was in a floating state, decreases to “V _D2 ”. In the transistor 4100, the Vgs between "V _D2 - Vth" of the node FG2 becomes Vth, so the current stops. Then, on the wiring 4003, “V _D2” written in write operation 2
" is read out.

After acquiring the data in the data holding section connected to node FG2, transistor 4300 is turned on to discharge "V _D2 -Vth" of node FG2.

Next, the charge held in node FG1 is distributed to node FG2, and the data voltage of the data holding section connected to node FG1 is transferred to the data holding section connected to node FG2. Here, the wirings 4001 and 4003 are set to low level. The wiring 4006 is set to high level. Further, the wiring 4005 and wirings 4007 to 4009 are set to low level. transistor 4200
becomes conductive, so that the charge on node FG1 is distributed between node FG2 and node FG2.

Here, the potential after the charge distribution decreases from the written potential "V _D1 -Vth". Therefore, it is preferable that the capacitance value of the capacitor 4600 is larger than that of the capacitor 4500. Alternatively, it is preferable that the potential "V _D1 - Vth" written to the node FG1 be higher than the potential "V _D2 - Vth" representing the same data. In this way, by changing the ratio of capacitance values and increasing the potential to be written in advance, it is possible to suppress a decrease in potential after charge distribution. Fluctuations in potential due to charge distribution will be described later.

Next, an operation of reading a data voltage to the data holding section connected to the node FG1 (hereinafter referred to as read operation 2) will be described.

In read operation 2, the wiring 4003 is precharged and then placed in an electrically floating state.
discharge. Wires 4005 to 4008 are set to low level. Moreover, the wiring 4009 is
Set to high level during precharge and then set to low level. By setting the wiring 4009 to a low level, the electrically floating node FG2 is brought to the potential "V _D1 -Vth". As the potential of node FG2 decreases, current flows through transistor 4100. As the current flows, the potential of the electrically floating wiring 4003 decreases. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. V of transistor 4100
When gs reaches Vth of the transistor 4100, the current flowing through the transistor 4100 becomes small. That is, the potential of the wiring 4003 becomes "V D1 ", which is a value greater than the potential "V _D1 - Vth _" of the node FG2 by Vth. The potential of this wiring 4003 is the node FG
This corresponds to the data voltage of the data holding unit connected to 1. The data voltage of the read analog value undergoes A/D conversion to obtain data in the data holding section connected to the node FG1.
The above is the operation of reading the data voltage to the data holding section connected to the node FG1.

That is, by placing the precharged wiring 4003 in a floating state and switching the potential of the wiring 4009 from a high level to a low level, a current flows through the transistor 4100. As the current flows, the potential of the wiring 4003, which was in a floating state, decreases to "V _D1 ". In the transistor 4100, the Vgs between “V _D1 −Vth” of the node FG2 becomes Vth, so the current stops. Then, on the wiring 4003, “V _D1” written in write operation 1
" is read out.

By the above-described operation of reading data voltages from nodes FG1 and FG2, data voltages can be read from a plurality of data holding sections. For example, by holding 4 bits (16 values) of data in each node FG1 and node FG2, a total of 8 bits (256 values) is generated.
data can be retained. In addition, in FIG. 31, the first layer 4021 to the third layer 4021
However, by forming additional layers, the storage capacity can be increased without increasing the area of the semiconductor device.

Note that the read potential can be read as a voltage that is larger than the written data voltage by Vth. Therefore, "V _D1 -Vth" and "V _D2 -
A configuration may be adopted in which reading is performed by canceling out Vth of "Vth". As a result, the storage capacity per memory cell can be improved, and the read data can be made closer to correct data, making it possible to provide excellent data reliability.

<Storage device 4>
The semiconductor device shown in FIG. 30C differs from the semiconductor device shown in FIG. 30A in that it includes a transistor 3500 and a sixth wiring 3006. In this case as well, information can be written and held by operations similar to those of the semiconductor device shown in FIG. 30(A). Further, as the transistor 3500, a transistor similar to the above-described transistor 3200 may be used.
Here, the transistor 3200 and the transistor 3500 are configured with the above element layer 50,
By forming the transistor 3300 with the above element layer 30 and forming the capacitor 3400 with the above element layer 40, the circuit shown in FIG. 30A can be formed using the semiconductor device shown in FIG. 19. Here, in the circuit shown in FIG. 30C, the transistor 3200 and the transistor 3500 can be formed using the transistor 90a or the transistor 90b shown in FIG. 18, and the transistor 3300 can be formed using the transistor 60a shown in FIG. The capacitor 3400 can be formed using the transistor 60b shown in FIG. 17, and the capacitor 3400 can be formed using the capacitor 80a shown in FIG.

The sixth wiring 3006 is electrically connected to the gate of the transistor 3500, one of the source and drain of the transistor 3500 is electrically connected to the drain of the transistor 3200, and the other of the source and drain of the transistor 3500 is electrically connected to the third It is electrically connected to wiring 3003.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes and examples described in this specification.

(Embodiment 4)
In this embodiment, an example of a circuit configuration to which the OS transistor described in the above embodiment can be applied will be described with reference to FIGS. 32 to 35.

FIG. 32(A) shows a circuit diagram of the inverter. Inverter 800 outputs from an output terminal OUT a signal obtained by inverting the logic of a signal applied to input terminal IN. Inverter 800 has multiple OS transistors. The signal _SBG is a signal that can switch the electrical characteristics of the OS transistor.

FIG. 32(B) shows an example of the inverter 800. Inverter 800 includes an OS transistor 810 and an OS transistor 820. Since the inverter 800 can be manufactured using an n-channel transistor, it can be manufactured using CMOS (Complementary MMOS).
Compared to the case where an inverter (CMOS inverter) is manufactured using CMOS inverter (CMOS inverter), it can be manufactured at a lower cost.

Note that the inverter 800 having an OS transistor is a CM composed of Si transistors.
It can also be placed on the OS. Since the inverter 800 can be placed overlapping the CMOS circuit, an increase in circuit area due to the addition of the inverter 800 can be suppressed.

The OS transistors 810 and 820 have a first gate that functions as a front gate, a second gate that functions as a back gate, and a first gate that functions as either a source or a drain.
It has a terminal and a second terminal functioning as the other of a source or a drain.

A first gate of OS transistor 810 is connected to a second terminal. OS transistor 81
The second gate of 0 is connected to the wiring that supplies the signal _SBG . A first terminal of OS transistor 810 is connected to a wiring that provides voltage VDD. A second terminal of OS transistor 810 is connected to output terminal OUT.

A first gate of OS transistor 820 is connected to input terminal IN. The second gate of OS transistor 820 is connected to input terminal IN. A first terminal of OS transistor 820 is connected to output terminal OUT. A second terminal of the OS transistor 820 is connected to a wiring that provides voltage VSS.

FIG. 32(C) is a timing chart for explaining the operation of inverter 800.
The timing chart in FIG. 32C shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the signal waveform of the signal _SBG , and the threshold voltage of the OS transistor 810 (FET 810).

By applying the signal _SBG to the second gate of the OS transistor 810, the OS transistor 8
10 threshold voltages can be controlled.

The signal S _BG has a voltage V _{BG_A} for shifting the threshold voltage negatively, and a voltage V _{BG_B} for shifting the threshold voltage positively. By applying the voltage V _{BG_A} to the second gate, the OS transistor 810 can be negatively shifted to the threshold voltage V _{TH_A} . Further, by applying the voltage V _{BG_B} to the second gate, the OS transistor 810 can be positively shifted to the threshold voltage V _{TH_B} .

In order to visualize the above description, FIG. 33A shows a Vg-Id curve, which is one of the electrical characteristics of a transistor.

The electrical characteristics of the OS transistor 810 described above can be shifted to the curve represented by the broken line 840 in FIG. 33(A) by increasing the voltage of the second gate to the voltage _{VBG_A} . Further, the electrical characteristics of the OS transistor 810 described above can be shifted to the curve represented by the solid line 841 in FIG. 33(A) by reducing the voltage of the second gate to a voltage _{VBG_B} . As shown in FIG. 33A, the OS transistor 810 can shift the threshold voltage positively or negatively by switching the signal S _BG to the voltage V _{BG_A} or the voltage V _{BG_B} .

By positively shifting the threshold voltage to the threshold voltage V _{TH_B} , the OS transistor 810 can be placed in a state where current does not easily flow. FIG. 33(B) shows this state visualized. As shown in FIG. 33(B), the current I _B flowing through the OS transistor 810 can be made extremely small. Therefore, when the signal applied to the input terminal IN is at a high level and the OS transistor 820 is in an on state (ON), the voltage at the output terminal OUT can be lowered steeply.

As shown in FIG. 33(B), the current flowing through the OS transistor 810 can be made difficult to flow, so the signal waveform 831 of the output terminal in the timing chart shown in FIG. 32(C) can be changed abruptly. I can do it. Wiring that provides voltage VDD and voltage VSS
Since it is possible to reduce the through current that flows between the wire and the wiring that provides the power, operation can be performed with low power consumption.

Further, by negatively shifting the threshold voltage to the threshold voltage V _{TH_A} , the OS transistor 810 can be placed in a state where current easily flows. FIG. 33(C) shows this state visualized. As shown in FIG. 33(C), the current _IA flowing at this time can be made larger than at least the current _IB . Therefore, when the signal applied to the input terminal IN is at a low level and the OS transistor 820 is in an off state (OFF), the voltage at the output terminal OUT can be sharply increased.

As shown in FIG. 33(C), the current flowing through the OS transistor 810 can be made easy to flow, so the signal waveform 832 of the output terminal in the timing chart shown in FIG. 32(C) can be changed sharply. I can do it.

Note that the threshold voltage of the OS transistor 810 is preferably controlled by the signal _SBG before the state of the OS transistor 820 is switched, that is, before time T1 or T2. For example, as illustrated in FIG. 32C, the threshold voltage of the OS transistor 810 may be switched from the threshold voltage V _{TH_A} to the threshold voltage V _{TH_B} before time T1 when the signal applied to the input terminal IN switches to high level. is preferred. Furthermore, as shown in FIG. 32C, the threshold voltage of the OS transistor 810 is switched from the threshold voltage V _{TH_B} to the threshold voltage V _{TH_A} before time T2 when the signal applied to the input terminal IN switches to low level. is preferred.

Note that in the timing chart of FIG. 32(C), the signal S
Although the configuration for switching _BG is shown, another configuration may be used. For example, the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. 34(A).

34(A) includes an OS transistor 850 in addition to the circuit configuration shown in FIG. 32(B). A first terminal of OS transistor 850 is connected to a second gate of OS transistor 810. Further, the second terminal of the OS transistor 850 is connected to a wiring that provides voltage V _{BG_B} (or voltage V _{BG_A} ). A first gate of OS transistor 850 is connected to a wiring that provides signal _SF . The second gate of the OS transistor 850 is connected to the voltage V _{BG_
B} (or voltage V _{BG_A} ).

The operation in FIG. 34(A) will be explained using the timing chart in FIG. 34(B).

The voltage for controlling the threshold voltage of the OS transistor 810 is configured to be applied to the second gate of the OS transistor 810 before time T3 when the signal applied to the input terminal IN switches to high level. The signal _SF is set to high level to turn on the OS transistor 850, and the voltage _{VBG_B} for controlling the threshold voltage is applied to the node _NBG .

After the node _NBG reaches the voltage _{VBG_B} , the OS transistor 850 is turned off. Since the off-state current of the OS transistor 850 is extremely small, by keeping the OS transistor 850 in the off state, the node _NBG can be brought into a state very close to a floating state, and the voltage _{VBG_B} that was once held at the node _NBG can be held. . Therefore, the number of times the voltage V _{BG_B} is applied to the second gate of the OS transistor 850 is reduced, and the power consumption required for rewriting the voltage V _{BG_B} can be reduced.

Note that in the circuit configurations of FIGS. 32(B) and 34(A), a configuration is shown in which the voltage applied to the second gate of the OS transistor 810 is applied by external control, but another configuration may be used. For example, a configuration may be adopted in which a voltage for controlling the threshold voltage is generated based on a signal applied to the input terminal IN and applied to the second gate of the OS transistor 810. An example of a circuit configuration that can realize this configuration is shown in FIG. 35(A).

In FIG. 35A, a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810 in the circuit configuration shown in FIG. 32B. An input terminal of CMOS inverter 860 is connected to input terminal IN. The output terminal of CMOS inverter 860 is connected to the second gate of OS transistor 810.

The operation in FIG. 35(A) will be explained using the timing chart in FIG. 35(B). In the timing chart of FIG. 35(B), the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the OS transistor 810 (
The figure shows changes in the threshold voltage of FET 810).

The output waveform IN_B, which is a signal obtained by inverting the logic of the signal applied to the input terminal IN, can be a signal that controls the threshold voltage of the OS transistor 810. Therefore, FIG. 32(A)
As described in (C), the threshold voltage of the OS transistor 810 can be controlled. For example, at time T4 in FIG. 35(B), the signal applied to the input terminal IN is at a high level and the OS transistor 820 is turned on. At this time, the output waveform IN_B becomes low level. Therefore, the OS transistor 810 can be put in a state where current does not easily flow, and the voltage at the output terminal OUT can be lowered steeply.

Further, at time T5 in FIG. 35(B), the signal applied to the input terminal IN is at a low level and the OS transistor 820 is turned off. At this time, the output waveform IN_B becomes high level. Therefore, the OS transistor 810 can be in a state where current easily flows,
The voltage at the output terminal OUT can be increased sharply.

As described above, in the configuration of this embodiment, the back gate voltage of the inverter having the OS transistor is switched according to the logic of the signal at the input terminal IN. With this configuration, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor with a signal applied to the input terminal IN, the voltage at the output terminal OUT can be changed sharply. Further, the through current between the wirings that supply the power supply voltage can be reduced. Therefore, it is possible to reduce power consumption.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes and examples described in this specification.

(Embodiment 5)
In this embodiment, an example of a semiconductor device having a plurality of circuits including the OS transistor described in the above embodiment will be described with reference to FIGS. 36 to 42.

FIG. 36A is a block diagram of the semiconductor device 900. The semiconductor device 900 includes a power supply circuit 901 , a circuit 902 , a voltage generation circuit 903 , a circuit 904 , a voltage generation circuit 905 , and a circuit 906 .

A power supply circuit 901 is a circuit that generates a reference voltage _VORG . The voltage V _ORG may be a plurality of voltages instead of a single voltage. Voltage V _ORG can be generated based on voltage V ₀ applied from outside of semiconductor device 900. The semiconductor device 900 can generate the voltage _VORG based on a single externally applied power supply voltage. Therefore, the semiconductor device 900 can operate without applying multiple external power supply voltages.

Circuits 902, 904, and 906 are circuits that operate with different power supply voltages. For example, the power supply voltage of the circuit 902 is a voltage applied based on the voltage V _ORG and the voltage V _SS (V _ORG > V _SS ). Further, for example, the power supply voltage of the circuit 904 is the voltage V _POG and the voltage V _SS (V _P
This is the voltage applied based on _OG > V _ORG ). Further, for example, the power supply voltage of the circuit 906 is a voltage applied based on the voltage V _ORG and the voltage V _NEG (V _ORG > V _SS > V _NEG ). Note that if the voltage _VSS is equal to the ground potential (GND), the power supply circuit 90
1. The types of voltages generated can be reduced.

Voltage generation circuit 903 is a circuit that generates voltage V _POG . Voltage generation circuit 903 can generate voltage V _POG based on voltage V _ORG supplied from power supply circuit 901 . Therefore,
A semiconductor device 900 having a circuit 904 can operate based on a single externally applied power supply voltage.

Voltage generation circuit 905 is a circuit that generates voltage V _NEG . The voltage generation circuit 905 can generate the voltage V _NEG based on the voltage V _ORG applied from the power supply circuit 901 . Therefore,
A semiconductor device 900 including a circuit 906 can operate based on a single externally applied power supply voltage.

FIG. 36(B) is an example of a circuit 904 that operates with voltage V _POG , and FIG. 36(C) is an example of a waveform of a signal for operating the circuit 904.

In FIG. 36B, a transistor 911 is shown. The signal applied to the gate of the transistor 911 is generated based on the voltage V _POG and the voltage V _SS , for example. The signal has a voltage V POG when the transistor 911 is turned on, and a voltage V _POG when the transistor 911 is turned off.
It will be _SS . Voltage V _POG is greater than voltage V _ORG , as illustrated in FIG. 36(C). Therefore, in the transistor 911, conduction can be established between the source (S) and the drain (D) more reliably. As a result, the circuit 904 can be a circuit with reduced malfunctions.

FIG. 36(D) is an example of a circuit 906 that operates with voltage V _NEG , and FIG. 36(E) is an example of a waveform of a signal for operating the circuit 906.

FIG. 36D shows a transistor 912 having a back gate. The signal applied to the gate of the transistor 912 is generated based on the voltage V _ORG and the voltage V _SS , for example. The signal is generated based on the voltage V _ORG when the transistor 911 is turned on, and based on the voltage V _SS when the transistor 911 is turned off. Further, a signal applied to the back gate of transistor 912 is generated based on voltage V _NEG . Voltage V _NEG is smaller than voltage V _SS (GND), as illustrated in FIG. 36(E). Therefore, the threshold voltage of the transistor 912 can be controlled to shift positively. Therefore, the transistor 91
2 can be brought into a non-conductive state more reliably, and the current flowing between the source (S) and the drain (D) can be reduced. As a result, the circuit 906 can be a circuit in which malfunctions are reduced and power consumption is reduced.

Note that the voltage V _NEG may be directly applied to the back gate of the transistor 912. Alternatively, a configuration may be employed in which a signal to be applied to the gate of the transistor 912 is generated based on the voltage V _ORG and the voltage V _NEG , and the signal is applied to the back gate of the transistor 912.

Further, FIGS. 37A and 37B show modifications of FIGS. 36D and 36E.

In the circuit diagram shown in FIG. 37A, a transistor 922 whose conduction state can be controlled by a control circuit 921 is shown between the voltage generation circuit 905 and the circuit 906. The transistor 922 is an n-channel OS transistor. The control signal _SBG output by the control circuit 921 is a signal that controls the conduction state of the transistor 922. Further, transistors 912A and 912B included in the circuit 906 are the same OS transistors as the transistor 922.

The timing chart in FIG. 37B shows changes in the potential of the control signal _SBG , and the states of the back gate potentials of the transistors 912A and 912B are shown by changes in the potential of the node _NBG . When the control signal _SBG is at a high level, the transistor 922 becomes conductive, and the node N
_BG becomes voltage V _NEG . After that, when the control signal S _BG is at low level, the node N _BG
becomes electrically floating. Since the transistor 922 is an OS transistor, its off-state current is small. Therefore, even if the node _NBG is electrically floating, the once applied voltage _VNEG can be maintained.

Further, FIG. 38(A) shows an example of a circuit configuration applicable to the voltage generation circuit 903 described above. The voltage generation circuit 903 shown in FIG. 38(A) includes diodes D1 to D5 and a capacitor C1.
This is a 5-stage charge pump including C5 to C5 and an inverter INV. Clock signal CLK is applied to capacitors C1 to C5 directly or via inverter INV. If the power supply voltage of the inverter INV is the voltage applied based on the voltage V _ORG and the voltage V _SS , then by applying the clock signal CLK, the voltage V _POG is boosted to a positive voltage five times the voltage V _ORG . Obtainable. Note that the forward voltage of the diodes D1 to D5 is 0V. In addition, by changing the number of charge pump stages, the desired voltage V _POG
can be obtained.

Further, FIG. 38(B) shows an example of a circuit configuration applicable to the voltage generation circuit 905 described above. The voltage generation circuit 905 shown in FIG. 38(B) includes diodes D1 to D5 and a capacitor C1.
It is a four-stage charge pump including C5 to C5 and an inverter INV. Clock signal CLK is applied to capacitors C1 to C5 directly or via inverter INV. Assuming that the power supply voltage of the inverter INV is a voltage applied based on the voltage V _ORG and the voltage V _SS , by applying the clock signal CLK, the power supply voltage of the inverter INV is set to the ground, that is, the voltage V _SS
A voltage V _NEG that is stepped down to a negative voltage four times the voltage V ORG can be obtained from the voltage V _ORG . In addition,
The forward voltages of the diodes D1 to D5 are set to 0V. Further, by changing the number of charge pump stages, a desired voltage V _NEG can be obtained.

Note that the circuit configuration of the voltage generation circuit 903 described above is not limited to the configuration of the circuit diagram shown in FIG. 38(A). Modifications of the voltage generation circuit 903 are shown in FIGS. 39A to 39C and FIGS. 40A and 40B.

A voltage generation circuit 903A shown in FIG. 39A includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1. Clock signal CLK is applied to the gates of transistors M1 to M10 directly or via inverter INV1. By applying the clock signal CLK, it is possible to obtain a voltage V _POG that is boosted to a positive voltage four times the voltage V _ORG . Note that a desired voltage V _POG can be obtained by changing the number of stages. In the voltage generation circuit 903A shown in FIG. 39(A), the off-state current can be reduced by using the transistors M1 to M10 as OS transistors, and the off-state current can be reduced by using the transistors M1 to M10 as OS transistors.
14 can be suppressed from leaking. Therefore, it is possible to efficiently convert the voltage V _ORG to the voltage V _P
It is possible to increase the pressure to _OG .

Further, voltage generation circuit 903B shown in FIG. 39(B) includes transistors M11 to M14, capacitors C15 and C16, and inverter INV2. Clock signal CLK is applied to the gates of transistors M11 to M14 directly or via inverter INV2. By applying the clock signal CLK, it is possible to obtain a voltage V _POG that is boosted to a positive voltage twice the voltage V _ORG . The voltage generation circuit 903B shown in FIG. 39(B) is
By using the transistors M11 to M14 as OS transistors, the off-state current can be reduced.
Leakage of charges held in capacitors C15 and C16 can be suppressed. Therefore, it is possible to efficiently boost the voltage V _ORG to the voltage V _POG .

Further, the voltage generation circuit 903C shown in FIG. 39(C) includes an inductor I11, a transistor M1
5, a diode D6, and a capacitor C17. The conduction state of transistor M15 is controlled by control signal EN. Using the control signal EN, it is possible to obtain a voltage V _POG that is a boosted voltage V _ORG . Since the voltage generation circuit 903C shown in FIG. 39C uses the inductor I11 to boost the voltage, it is possible to boost the voltage with high conversion efficiency.

Further, the voltage generation circuit 903D shown in FIG. 40(A) is different from the voltage generation circuit 903D shown in FIG. 38(A).
This corresponds to a configuration in which the diodes D1 to D5 of No. 3 are replaced with diode-connected transistors M16 to M20. The voltage generation circuit 903D shown in FIG. 40(A) includes a transistor M1
By using OS transistors 6 to M20, the off-state current can be reduced, and leakage of charges held in the capacitors C1 to C5 can be suppressed. Therefore, the voltage V _ORG can be efficiently converted to the voltage V
It is possible to increase the voltage to _POG .

Further, the voltage generation circuit 903E shown in FIG. 40(B) is different from the voltage generation circuit 903E shown in FIG. 40(A).
This corresponds to a configuration in which the 3D transistors M16 to M20 are replaced with transistors M21 to M25 having back gates. Since the voltage generation circuit 903E shown in FIG. 40B can apply the same voltage to the back gate as the gate, the amount of current flowing through the transistor can be increased. Therefore, it is possible to efficiently boost the voltage V _ORG to the voltage V _POG .

Note that the modification of the voltage generation circuit 903 is also applicable to the voltage generation circuit 905 shown in FIG. 38(B). The configuration of the circuit diagram in this case is shown in FIGS. 41(A) to (C) and FIGS. 42(A) and (B).
Shown below. The voltage generation circuit 905A shown in FIG. 41A can obtain the voltage V _NEG , which is reduced from the voltage V _SS to a negative voltage three times the voltage V _ORG , by applying the clock signal CLK. Further, the voltage generation circuit 905A shown in FIG. 41(B) generates a voltage VN which is stepped down from the voltage _VSS to a negative voltage twice the voltage _VORG by applying the clock signal CLK _.
You can get _EG .

Voltage generation circuits 905A to 905 shown in FIGS. 41(A) to (C), FIGS. 42(A), and (B)
In E, in the voltage generation circuits 903A to 903E shown in FIGS. 39(A) to (C) and FIGS. 40(A) and (B), the voltage applied to each wiring is changed or the arrangement of elements is changed. corresponds to Voltage generating circuits 905A to 905E shown in FIGS. 41(A) to (C) and FIGS. 42(A) and 42(B) efficiently generate voltage V
It is possible to step down the voltage from _SS to voltage V _NEG .

As described above, with the configuration of this embodiment, the voltage necessary for the circuit included in the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the types of power supply voltages applied from the outside.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes and examples described in this specification.

(Embodiment 6)
In this embodiment, an example of a CPU including a transistor according to one embodiment of the present invention and a semiconductor device such as the above-described memory device will be described.

<CPU configuration>

A semiconductor device 400 shown in FIG. 43 includes a CPU core 401, a power management unit 421, and a peripheral circuit 422. Power management unit 421 includes a power controller 402 and a power switch 403. The peripheral circuit 422 includes a cache 404 having a cache memory, and a bus interface (BUS I/F) 405.
, and a debug interface (Debug I/F) 406. CPU core 4
01 is a data bus 423, a control device 407, a PC (program counter) 408, a pipeline register 409, a pipeline register 410, an ALU (Arithmetic
logic unit) 411, and a register file 412. CPU core 4
01 and the peripheral circuits 422 such as the cache 404 are exchanged using the data bus 42.
3.

The semiconductor device (cell) can be applied to many logic circuits including the power controller 402 and the control device 407. In particular, it can be applied to all logic circuits that can be constructed using standard cells. As a result, a compact semiconductor device 400 can be provided. Further, it is possible to provide a semiconductor device 400 that can reduce power consumption. Further, it is possible to provide a semiconductor device 400 that can improve operating speed. Further, it is possible to provide a semiconductor device 400 that can reduce fluctuations in power supply voltage.

A p-channel Si transistor and a transistor whose channel formation region includes the oxide semiconductor (preferably an oxide containing In, Ga, and Zn) described in the previous embodiment are used in a semiconductor device (cell), By applying the semiconductor device (cell) to the semiconductor device 400, a small-sized semiconductor device 400 can be provided. In addition, a semiconductor device 4 that can reduce power consumption
00 can be provided. Further, it is possible to provide a semiconductor device 400 that can improve operating speed. In particular, manufacturing costs can be kept low by using only p-channel type Si transistors.

A control device 407 controls the operations of a PC 408, a pipeline register 409, a pipeline register 410, an ALU 411, a register file 412, a cache 404, a bus interface 405, a debug interface 406, and a power controller 402. It has the ability to decode and execute instructions included in programs such as applications.

The ALU 411 has a function of performing various arithmetic operations such as arithmetic operations and logical operations.

The cache 404 has a function of temporarily storing frequently used data. P
C408 is a register that has the function of storing the address of the next instruction to be executed. Although not shown in FIG. 43, the cache 404 is provided with a cache controller that controls the operation of the cache memory.

Pipeline register 409 is a register that has a function of temporarily storing instruction data.

The register file 412 has a plurality of registers including general-purpose registers, and stores data read from the main memory or data obtained as a result of arithmetic processing by the ALU 411.
etc. can be memorized.

The pipeline register 410 stores data used for arithmetic processing by the ALU 411 or
This register has the function of temporarily storing data obtained as a result of the arithmetic processing of the LU 411.

The bus interface 405 functions as a data path between the semiconductor device 400 and various devices outside the semiconductor device 400. Debug interface 4
06 has a function as a signal path for inputting a command for controlling debugging to the semiconductor device 400.

The power switch 403 has a function of controlling the supply of power supply voltage to various circuits other than the power controller 402 included in the semiconductor device 400. The various circuits described above each belong to several power domains, and whether or not a power supply voltage is supplied to the various circuits belonging to the same power domain is controlled by the power switch 403. Further, the power controller 402 has a function of controlling the operation of the power switch 403.

The semiconductor device 400 having the above configuration can perform power gating.
The flow of power gating operation will be explained using an example.

First, the CPU core 401 sets the timing for stopping the supply of power supply voltage in the register of the power controller 402. Next, from the CPU core 401 to the power controller 4
A command to start power gating is sent to 02. Next, various registers and cache 404 included in semiconductor device 400 start saving data. Next, the supply of power supply voltage to various circuits other than the power controller 402 included in the semiconductor device 400 is stopped by the power switch 403. The interrupt signal is then sent to the power controller 402.
, the supply of power supply voltage to various circuits included in the semiconductor device 400 is started. Note that the power controller 402 may be provided with a counter, and the counter may be used to determine the timing at which supply of the power supply voltage is started, without depending on the input of the interrupt signal. The various registers and cache 404 then begin returning data. Execution of instructions in controller 407 then resumes.

Such power gating can be performed on the entire processor or on one or more logic circuits that make up the processor. Furthermore, the power supply can be stopped even for a short period of time. Therefore, power consumption can be reduced spatially or temporally with fine granularity.

When performing power gating, it is preferable that the information held by the CPU core 401 and peripheral circuits 422 can be saved in a short period of time. By doing so, the power can be turned on and off in a short period of time, which increases the power saving effect.

In order to save the information held by the CPU core 401 and the peripheral circuit 422 in a short period of time, it is preferable that the flip-flop circuit can save data within the circuit (referred to as a flip-flop circuit capable of backup). Further, it is preferable that the SRAM cell can save data within the cell (referred to as a backup-capable SRAM cell). A flip-flop circuit or an SRAM cell that can be backed up preferably includes a transistor whose channel formation region includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn). As a result, the transistor has a low off-state current, making it possible to create backup-capable flip-flop circuits and SR
AM cells can retain information without power supply for long periods of time. In addition, the high switching speed of transistors enables backup-capable flip-flop circuits and SR
AM cells may allow short-term data evacuation and restoration.

An example of a flip-flop circuit that can be backed up will be explained using FIG. 44.

A semiconductor device 500 shown in FIG. 44 is an example of a flip-flop circuit that can be backed up. The semiconductor device 500 includes a first memory circuit 501, a second memory circuit 502, a third memory circuit 503, and a read circuit 504. The semiconductor device 500 has a potential V1
The potential difference between the potential V2 and the potential V2 is supplied as the power supply voltage. One of the potentials V1 and V2 is at a high level, and the other is at a low level. Hereinafter, an example of the configuration of the semiconductor device 500 will be described, taking as an example a case where the potential V1 is at a low level and the potential V2 is at a high level.

The first memory circuit 501 has a function of holding data when a signal D including data is input during a period when a power supply voltage is supplied to the semiconductor device 500. Then, during a period when the power supply voltage is supplied to the semiconductor device 500, the first memory circuit 501 outputs a signal Q including the held data. On the other hand, the first memory circuit 501 cannot hold data during a period when the power supply voltage is not supplied to the semiconductor device 500. That is, the first memory circuit 501 can be called a volatile memory circuit.

The second memory circuit 502 has a function of reading and storing (or saving) data held in the first memory circuit 501. The third storage circuit 503 has a function of reading and storing (or saving) data held in the second storage circuit 502. The read circuit 504 has a function of reading data held in the second memory circuit 502 or the third memory circuit 503 and storing it in the first memory circuit 501 (or returning it).

In particular, the third memory circuit 503 has a function of reading and storing (or saving) data held in the second memory circuit 502 even during a period when the power supply voltage is not supplied to the semiconductor device 500. .

As shown in FIG. 44, the second memory circuit 502 includes a transistor 512 and a capacitor 519. The third memory circuit 503 includes a transistor 513, a transistor 515, and a capacitor 520. The readout circuit 504 includes a transistor 510 and a transistor 51.
8, a transistor 509, and a transistor 517.

The transistor 512 has a function of charging and discharging the capacitor 519 with charge according to the data held in the first storage circuit 501. The transistor 512 is connected to the first memory circuit 5
It is desirable that the capacitive element 519 can be charged and discharged with charges corresponding to the data held in 01 at high speed. Specifically, the transistor 512 desirably includes crystalline silicon (preferably polycrystalline silicon, more preferably single crystal silicon) in a channel formation region.

A conductive state or a non-conductive state of the transistor 513 is selected according to the charge held in the capacitor 519. The transistor 515 has a function of charging and discharging the capacitor 520 with charge according to the potential of the wiring 544 when the transistor 513 is conductive. It is desirable that the transistor 515 has extremely low off-state current. Specifically, the transistor 515 desirably includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region.

To specifically explain the connection relationship between each element, one of the source and drain of the transistor 512 is connected to the first memory circuit 501. The other of the source and drain of the transistor 512 is connected to one electrode of the capacitor 519, the gate of the transistor 513, and the gate of the transistor 518. The other electrode of capacitive element 519 is connected to wiring 542. One of the source and drain of the transistor 513 is connected to a wiring 544. The other of the source and drain of transistor 513 is connected to one of the source and drain of transistor 515. The other of the source and drain of the transistor 515 is connected to one electrode of the capacitor 520 and the gate of the transistor 510. The other electrode of capacitive element 520 is connected to wiring 543. transistor 51
One of the source and drain of 0 is connected to the wiring 541. The other of the source and drain of transistor 510 is connected to one of the source and drain of transistor 518. The other of the source and drain of transistor 518 is connected to one of the source and drain of transistor 509. The other of the source and drain of the transistor 509 is connected to one of the source and drain of the transistor 517 and the first memory circuit 501. The other of the source and drain of the transistor 517 is connected to the wiring 540. Further, in FIG. 44, the gate of the transistor 509 is connected to the transistor 509.
Although the gate of transistor 509 is connected to the gate of transistor 517, the gate of transistor 509 does not necessarily have to be connected to the gate of transistor 517.

The transistor exemplified in the previous embodiment can be used as the transistor 515. Since the off-state current of the transistor 515 is small, the semiconductor device 500 can retain information for a long period of time without power supply. Since the transistor 515 has good switching characteristics, the semiconductor device 500 can perform high-speed backup and recovery.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes and examples described in this specification.
(Embodiment 7)
In this embodiment, an example of an imaging device using a transistor or the like according to one embodiment of the present invention will be described.

<Imaging device>
An imaging device according to one embodiment of the present invention will be described below.

FIG. 45(A) is a plan view illustrating an example of an imaging device 200 according to one embodiment of the present invention. The imaging device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290. The pixel section 210 has a plurality of pixels 211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more).
The peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, and the peripheral circuit 290 each have a function of being connected to the plurality of pixels 211 and supplying signals for driving the plurality of pixels 211. Note that in this specification and the like, the peripheral circuit 260, the peripheral circuit 270, the peripheral circuit 280, the peripheral circuit 290, etc. may all be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 can be said to be part of the peripheral circuit.

Further, it is preferable that the imaging device 200 includes a light source 291. The light source 291 emits detection light P
1 can be emitted.

Further, the peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. Further, the peripheral circuit may be formed on the substrate on which the pixel portion 210 is formed. Further, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that the peripheral circuits include a peripheral circuit 260, a peripheral circuit 270, a peripheral circuit 280, and a peripheral circuit 290.
One or more of these may be omitted.

Further, as shown in FIG. 45(B), in the pixel unit 210 included in the imaging device 200, the pixels 211 may be arranged at an angle. By arranging the pixels 211 at an angle, the pixel spacing (pitch) in the row and column directions can be shortened. Thereby, the quality of imaging in the imaging device 200 can be further improved.

<Pixel configuration example 1>
A color image display is realized by configuring one pixel 211 of the imaging device 200 with a plurality of subpixels 212, and combining each subpixel 212 with a filter (color filter) that transmits light in a specific wavelength range. You can obtain information for

FIG. 46(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in FIG. 46(A) includes a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") provided with a color filter that transmits light in the red (R) wavelength range, and a sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") that transmits light in the red (R) wavelength range. Subpixel 212 (hereinafter also referred to as "subpixel 212G") provided with a color filter that transmits light in the area
and a subpixel 212 (hereinafter also referred to as "subpixel 212B") provided with a color filter that transmits light in the blue (B) wavelength range. The subpixel 212 can function as a photosensor.

The subpixels 212 (subpixel 212R, subpixel 212G, and subpixel 212B) are connected to the wiring 23
1. Electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. Further, the subpixel 212R, the subpixel 212G, and the subpixel 212B each have an independent wiring 25
Connected to 3. In addition, in this specification and the like, for example, the wiring 248, the wiring 249, and the wiring 250 connected to the n-th pixel 211 are referred to as the wiring 248[n] and the wiring 249, respectively.
[n], and wiring 250[n]. Further, for example, the wiring 253 connected to the m-th column pixel 211 is written as wiring 253[m]. Note that in FIG. 48A, the wiring 253 connected to the subpixel 212R of the m-th column pixel 211 is connected to the wiring 253[m]R, the wiring 253 connected to the subpixel 212G is connected to the wiring 253[m]G, and The wiring 253 connected to the subpixel 212B is indicated as a wiring 253[m]B. The sub-pixel 212 is electrically connected to peripheral circuits via the wiring.

Further, the imaging device 200 has a configuration in which sub-pixels 212 of adjacent pixels 211 that are provided with color filters that transmit light in the same wavelength range are electrically connected to each other via a switch.
In FIG. 46(B), sub-pixels 212 of a pixel 211 arranged in n rows (n is an integer from 1 to p and below) and m columns (m is an integer from 1 to q and below) and sub-pixels 212 adjacent to the pixel 211 are shown. A connection example of sub-pixels 212 included in a pixel 211 arranged in row n+1 and column m is shown. In FIG. 46B, a subpixel 212R arranged in row n and column m and a subpixel 212R arranged in row n+1 and column m are connected via a switch 201. Further, sub-pixels 212G arranged in n rows and m columns and n+
Sub-pixels 212G arranged in the 1st row and the mth column are connected via the switch 202. Also,
The subpixel 212B arranged in the nth row and m column and the subpixel 212B arranged in the n+1th row and m column are connected via the switch 203.

Note that the color filter used for the subpixel 212 is not limited to red (R), green (G), and blue (B), but transmits cyan (C), yellow (Y), and magenta (M) light, respectively. Color filters may also be used. Sub-pixel 2 that detects light in three different wavelength ranges in one pixel 211
By providing 12, a full color image can be obtained.

Alternatively, in addition to the subpixel 212 provided with a color filter that transmits red (R), green (G), and blue (B) light, a color filter that transmits yellow (Y) light is provided. A pixel 211 having a sub-pixel 212 may also be used. Or cyan (C) and yellow (Y), respectively.
) and a subpixel 212 provided with a color filter that transmits magenta (M) light, as well as a subpixel 212 provided with a color filter that transmits blue (B) light.
1 may be used. Subpixel 21 that detects light in four different wavelength ranges in one pixel 211
2, the color reproducibility of the acquired image can be further improved.

For example, in FIG. 46A, a subpixel 212 that detects light in the red wavelength range, a subpixel 212 that detects light in the green wavelength range, and a subpixel 212 that detects light in the blue wavelength range The pixel number ratio (or light-receiving area ratio) does not need to be 1:1:1. For example, a Bayer arrangement may be used in which the pixel number ratio (light-receiving area ratio) is red:green:blue=1:2:1. Alternatively, the pixel number ratio (light-receiving area ratio) may be set to red:green:blue=1:6:1.

Note that the number of sub-pixels 212 provided in the pixel 211 may be one, but preferably two or more. For example, by providing two or more sub-pixels 212 that detect light in the same wavelength range, redundancy can be increased and the reliability of the imaging device 200 can be increased.

Also, IR (Infrared) absorbs or reflects visible light and transmits infrared light.
By using a filter, it is possible to realize an imaging device 200 that detects infrared light.

Further, by using an ND (Neutral Density) filter (neutral density filter), it is possible to prevent output saturation that occurs when a large amount of light enters the photoelectric conversion element (light receiving element). By using a combination of ND filters with different light attenuation amounts, the dynamic range of the imaging device can be increased.

Further, in addition to the above-described filter, a lens may be provided in the pixel 211. Here, an example of the arrangement of the pixel 211, the filter 254, and the lens 255 will be described using the cross-sectional view of FIG. By providing the lens 255, the photoelectric conversion element provided in the subpixel 212 can efficiently receive incident light. Specifically, as shown in FIG. 47A, a lens 255, a filter 254 (filter 254R, filter 254G, and filter 2
54B) and the pixel circuit 230, etc., the light 256 can be made to enter the photoelectric conversion element 220.

However, as shown in the area surrounded by the dashed line, a portion of the light 256 indicated by the arrow may be blocked by a portion of the wiring 257. Therefore, as shown in FIG. 47(B), a lens 255 and a filter 254 are arranged on the photoelectric conversion element 220 side,
A structure that allows the light 256 to be efficiently received is preferable. By allowing the light 256 to enter the photoelectric conversion element 220 from the photoelectric conversion element 220 side, it is possible to provide the imaging device 200 with high detection sensitivity.

As the photoelectric conversion element 220 shown in FIG. 47, a photoelectric conversion element in which a pn type junction or a pin type junction is formed may be used.

Further, the photoelectric conversion element 220 may be formed using a substance that has a function of absorbing radiation and generating electric charges. Examples of substances that have the function of absorbing radiation and generating electric charges include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium-zinc alloys.

For example, if selenium is used in the photoelectric conversion element 220, in addition to visible light, ultraviolet light, and infrared light,
Photoelectric conversion element 22 that has a light absorption coefficient over a wide wavelength range such as X-rays and gamma rays
0 can be achieved.

Here, one pixel 211 included in the imaging device 200 may include a sub-pixel 212 having a first filter in addition to the sub-pixel 212 shown in FIG. 46.

<Pixel configuration example 2>
An example in which a pixel is configured using a transistor using silicon and a transistor using an oxide semiconductor will be described below. As each transistor, a transistor similar to that shown in the above embodiment mode can be used.

FIG. 48 is a cross-sectional view of elements constituting the imaging device. The imaging device shown in FIG. 48 includes a transistor 351 using silicon provided on a silicon substrate 300, a transistor 352 using an oxide semiconductor, and a transistor 353 stacked over the transistor 351.
, and a photodiode 360 provided on the silicon substrate 300. Each transistor and photodiode 360 has electrical connections with various plugs 370 and wiring 371. Further, an anode 361 of the photodiode 360 is electrically connected to a plug 370 via a low resistance region 363.

The imaging device also includes a layer 310 provided on the silicon substrate 300 and having a transistor 351 and a photodiode 360, and a layer 310 provided in contact with the layer 310 and having wiring 371.
20, a layer 330 provided in contact with the layer 320 and having a transistor 352 and a transistor 353, and a layer 3 provided in contact with the layer 330 and having a wiring 372 and a wiring 373.
It is equipped with 40.

Note that in the example of the cross-sectional view in FIG. 48, the silicon substrate 300 has a light-receiving surface of the photodiode 360 on a surface opposite to the surface on which the transistor 351 is formed. With this configuration, an optical path can be secured without being affected by various transistors, wiring, and the like. Therefore, pixels with a high aperture ratio can be formed. In addition, the photodiode 360
The light-receiving surface of the transistor 351 can also be made the same as the surface on which the transistor 351 is formed.

Note that when a pixel is configured using only a transistor using an oxide semiconductor, the layer 31
0 may be a layer including a transistor using an oxide semiconductor. Alternatively, the layer 310 may be omitted, and the pixel may be formed only with a transistor using an oxide semiconductor.

Note that the silicon substrate 300 may be an SOI substrate. Further, instead of the silicon substrate 300, a substrate containing germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor can also be used.

Here, an insulator 380 is provided between the layer 310 including the transistor 351 and the photodiode 360 and the layer 330 including the transistor 352 and the transistor 353. However, the position of the insulator 380 is not limited. Further, an insulator 379 is provided below the insulator 380, and an insulator 381 is provided above the insulator 380. Here, insulator 3
79 corresponds to the insulator 110 shown in FIG. 19, the insulator 380 corresponds to the insulator 61 shown in FIG. 19, and the insulator 381 corresponds to the insulator 67 shown in FIG.

Conductors 390a to 390e are inserted into the openings provided in the insulators 379 to 380.
is provided. The conductor 390a, the conductor 390b, and the conductor 390e correspond to the conductor 121a and the conductor 122a shown in FIG. 19, and function as a plug and wiring. Further, the conductor 390c corresponds to the conductor 62a and the conductor 62b illustrated in FIG. 19, and functions as a back gate of the transistor 353. In addition, the conductor 390d
corresponds to the conductor 62a and the conductor 62b shown in FIG.
functions as a back gate.

Hydrogen in the insulator provided near the channel formation region of the transistor 351 has the effect of terminating silicon dangling bonds and improving the reliability of the transistor 351. On the other hand, hydrogen in an insulator provided near the transistors 352, 353, and the like is one of the factors that generate carriers in the oxide semiconductor. Therefore, transistor 3
52, the transistor 353, etc. may become a factor that deteriorates the reliability of the transistor 353 and the like. Therefore, when a transistor using an oxide semiconductor is stacked over a transistor using a silicon-based semiconductor, it is preferable to provide the insulator 380 having a function of blocking hydrogen between them. By confining hydrogen in a layer below the insulator 380, the reliability of the transistor 351 can be improved. Furthermore, diffusion of hydrogen from a layer below the insulator 380 to a layer above the insulator 380 can be suppressed, so the reliability of the transistors 352, 353, and the like can be improved. Furthermore, by forming the conductor 390a, the conductor 390b, and the conductor 390e, it is possible to suppress hydrogen from diffusing into the upper layer through the via hole formed in the insulator 380.
In addition, reliability of the transistor 353 and the like can be improved.

Further, in the cross-sectional view of FIG. 48, a photodiode 360 provided in the layer 310 and a photodiode 360 provided in the layer 330
They can be formed so as to overlap with the transistors provided in the first and second transistors. In this way, the degree of pixel integration can be increased. That is, the resolution of the imaging device can be increased.

Further, part or all of the imaging device may be curved. By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, optical design of lenses and the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for aberration correction can be reduced, it is possible to reduce the size and weight of electronic equipment using the imaging device. Furthermore, the quality of captured images can be improved.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes and examples described in this specification.

(Embodiment 8)
In this embodiment, an electronic device using a transistor or the like according to one embodiment of the present invention will be described.

<Electronic equipment>
A semiconductor device according to one embodiment of the present invention can be used in a display device, a personal computer, and an image playback device including a recording medium (typically a DVD: Digital Versatile Disc).
It can be used in devices (equipped with a display capable of reproducing recording media such as, for example, and displaying images). In addition, examples of electronic devices that can use the semiconductor device according to one embodiment of the present invention include mobile phones, game machines including portable ones, mobile data terminals, electronic book terminals, cameras such as video cameras and digital still cameras, and goggles. Examples include type displays (head-mounted displays), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copying machines, facsimile machines, printers, multifunction printers, automated teller machines (ATMs), and vending machines. It will be done. Specific examples of these electronic devices are shown in FIG.

FIG. 49A shows a portable game machine, which includes a housing 1901, a housing 1902, a display portion 1903,
It includes a display portion 1904, a microphone 1905, a speaker 1906, an operation key 1907, a stylus 1908, and the like. Note that although the portable game machine shown in FIG. 49(A) has two display sections 1903 and 1904, the number of display sections that the portable game machine has is not limited to this.

FIG. 49B shows a mobile data terminal, which includes a first housing 1911, a second housing 1912, a first display portion 1913, a second display portion 1914, a connection portion 1915, operation keys 1916, and the like. 1st
The display section 1913 is provided in the first casing 1911, and the second display section 1914 is provided in the second casing 1.
912. The first housing 1911 and the second housing 1912 are connected to the connecting portion 1
915 , and the angle between the first housing 1911 and the second housing 1912 can be changed by the connecting portion 1915 . The video on the first display section 1913 is displayed on the connection section 191
A configuration may also be adopted in which the switching is performed according to the angle between the first housing 1911 and the second housing 1912 in No. 5. Further, at least one of the first display section 1913 and the second display section 1914 may be a display device that has an additional function as a position input device. Note that the function as a position input device can be added by providing a touch panel to the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, also called a photosensor, in the pixel portion of the display device.

FIG. 49(C) shows a notebook personal computer, which includes a housing 1921 and a display section 1922.
, a keyboard 1923, a pointing device 1924, and the like.

FIG. 49(D) shows an electric refrigerator-freezer, which includes a housing 1931, a refrigerator door 1932, a freezer door 1933, and the like.

FIG. 49(E) shows a video camera including a first housing 1941, a second housing 1942, and a display section 19.
43, an operation key 1944, a lens 1945, a connecting portion 1946, and the like. Operation key 194
4 and the lens 1945 are provided in the first casing 1941, and the display section 1943 is provided in the second casing 1942. The first housing 1941 and the second housing 1942 are connected by a connecting portion 1946, and the angle between the first housing 1941 and the second housing 1942 is
Connection portion 1946 allows for changes. The video on the display section 1943 is transferred to the connection section 194.
A configuration may also be adopted in which switching is performed according to the angle between the first casing 1941 and the second casing 1942 in No. 6.

FIG. 49(F) shows a car, with a car body 1951, wheels 1952, a dashboard 1953,
It has a light 1954 etc.

Note that in this embodiment, one aspect of the present invention has been described. However, one embodiment of the present invention is not limited to these. That is, since various aspects of the invention are described in this embodiment and the like, one aspect of the present invention is not limited to a specific aspect. For example, as one embodiment of the present invention, an example is shown in which a channel formation region, a source/drain region, and the like of a transistor include an oxide semiconductor; however, one embodiment of the present invention is not limited thereto. In some cases,
Alternatively, depending on the situation, various transistors, channel formation regions of transistors, source/drain regions of transistors, or the like in one embodiment of the present invention may include various semiconductors. In some cases or depending on the circumstances, various transistors, channel formation regions of transistors, source/drain regions of transistors, or the like in one embodiment of the present invention may be made of, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium. It may contain at least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor. Alternatively, for example, in some cases or depending on the circumstances, various transistors, channel formation regions of the transistors, source/drain regions of the transistors, etc. of one embodiment of the present invention may not include an oxide semiconductor. good.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes and examples described in this specification.
(Embodiment 9)
In this embodiment, a semiconductor wafer, a chip, and an electronic component according to one embodiment of the present invention will be described.

<Semiconductor wafers, chips>
FIG. 54(A) shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a "semiconductor wafer") can be used. A plurality of circuit areas 712 are provided on the substrate 711. Circuit area 712
can be provided with a semiconductor device according to one embodiment of the present invention, a CPU, an RF tag, an image sensor, or the like.

Each of the plurality of circuit regions 712 is surrounded by an isolation region 713. A separation line (also referred to as a “dicing line”) 714 is set at a position overlapping the separation region 713. Separation line 7
By cutting the substrate 711 along the line 14, the chip 715 including the circuit area 712 is separated from the substrate 7.
It can be extracted from 11. An enlarged view of the chip 715 is shown in FIG. 54(B).

Further, a conductive layer or a semiconductor layer may be provided in the isolation region 713. By providing a conductive layer or a semiconductor layer in the isolation region 713, ESD that may occur during the dicing process can be alleviated and a decrease in yield in the dicing process can be prevented. Further, the dicing process is generally performed while flowing pure water in which carbon dioxide gas and the like are dissolved to lower the resistivity to the cutting part for purposes such as cooling the substrate, removing chips, and preventing static electricity. By providing a conductive layer or a semiconductor layer in the separation region 713, the amount of pure water used can be reduced. Therefore, the production cost of semiconductor devices can be reduced. Furthermore, productivity of semiconductor devices can be improved.

The semiconductor layer provided in the isolation region 713 has a band gap of 2.5 eV or more and 4.2 eV.
Hereinafter, it is preferable to use a material having a voltage of 2.7 eV or more and 3.5 eV or less. When such a material is used, accumulated charges can be discharged slowly, so rapid movement of charges due to ESD can be suppressed, and electrostatic damage can be made less likely to occur.

<Electronic parts>
An example in which the chip 715 is applied to an electronic component will be described using FIG. 55. Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic components have multiple standards and names depending on the direction in which the terminal is taken out and the shape of the terminal.

The electronic component is completed by combining the semiconductor device shown in the above embodiment mode and parts other than the semiconductor device in an assembly process (post-process).

The post-process will be explained using the flowchart shown in FIG. 55(A). After the element substrate having the semiconductor device shown in the above embodiment mode is completed in the pre-process, the back surface (
A "back surface grinding step" is performed to grind the surface (on which no semiconductor device or the like is formed) (step S721). By making the element substrate thinner by grinding, it is possible to reduce warping of the element substrate and downsize the electronic component.

Next, a "dicing process" is performed to separate the element substrate into multiple chips (chips 715).
Step S722). Then, a "die bonding process" is performed in which the separated chips are individually picked up and bonded onto a lead frame (step S723). For bonding the chip and the lead frame in the die bonding process, an appropriate method is selected depending on the product, such as bonding with resin or bonding with tape. Note that the chip may be bonded onto the interposer substrate instead of the lead frame.

Next, a "wire bonding process" is performed to electrically connect the leads of the lead frame and the electrodes on the chip using thin metal wires (step S724). Silver wire or gold wire can be used as the thin metal wire. Further, as the wire bonding, ball bonding or wedge bonding can be used.

The wire-bonded chip is subjected to a "sealing process (molding process)" in which it is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, which protects the circuitry built into the chip and the wires that connect the chip and leads from external mechanical forces, and also protects the electronic components from moisture and dust. deterioration (deterioration in reliability) can be reduced.

Next, a "lead plating process" is performed to plate the leads of the lead frame (step S726). The plating treatment prevents the leads from rusting, making it possible to more reliably solder them later when mounting them on a printed circuit board. Next, a "forming step" is performed in which the lead is cut and molded (step S727).

Next, a "marking step" is performed in which a printing process (marking) is performed on the surface of the package (step S728). Then, the electronic component is completed (step S729) through an "inspection process" (step S729) to check whether the external shape is good or not and whether or not there are malfunctions.

Furthermore, a schematic perspective view of the completed electronic component is shown in FIG. 55(B). FIG. 55B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. The electronic component 750 shown in FIG. 55(B) shows a lead 755 and a semiconductor device 753. As the semiconductor device 753, the semiconductor device described in the above embodiment mode or the like can be used.

The electronic component 750 shown in FIG. 55(B) is mounted, for example, on a printed circuit board 752. A plurality of such electronic components 750 are combined and electrically connected to each other on a printed circuit board 752, thereby completing a board (mounted board 754) on which electronic components are mounted. The completed mounting board 754 is used for electronic devices and the like.

This embodiment mode can be implemented by appropriately combining at least a part of it with other embodiment modes and examples described in this specification.

In this example, the effects of the plasma treatment according to the present invention were confirmed. As the metal containing nitrogen, a tantalum nitride film using the ALD method was used. The tantalum nitride film was subjected to plasma treatment, and fluctuations in sheet resistance were measured, and XPS (Xray Photoelectron Sp
electroscopy) analysis was performed.

For the sample, a tantalum nitride film was formed with a thickness of 30 nm on a glass substrate using the ALD method. Pentakis(dimethylamino)tantalum was used as a precursor.

Next, the film thickness and sheet resistance of the tantalum nitride were measured. The film thickness was measured using an ellipsometry method, and the sheet resistance value was measured using a sheet resistance measuring device. Next, plasma treatment was performed. In this example, the plasma treatment was reverse sputtering using argon gas using a sputtering apparatus having a reverse sputtering function.

The conditions for reverse sputtering were changed depending on the sample. That is, sample 1 has an input power of 50 W and processing time of 30 seconds, sample 2 has an input power of 50 W and processing time of 60 seconds, and sample 3 has an input power of 100 W.
For sample 4, the input power was 100 W and the treatment time was 60 seconds. For sample 5, the input power was 150 W and the treatment time was 60 seconds. For the sample 6, the power input was 200 W and the treatment time was 60 seconds. Sample 7 was not subjected to reverse sputtering treatment as a comparative sample.

Next, the film thicknesses and sheet resistance values of Samples 1 to 6 after the reverse sputtering treatment were measured. In addition, XPS analysis was performed on the film surfaces of Samples 2, 4, 5, 6, and 7. In addition, sample 7 is
XPS analysis in the depth direction of the film was also conducted.

FIG. 50 shows a graph of the amount of film reduction of the tantalum nitride film depending on the input power and processing time of reverse sputtering. When the input power is increased, the amount of film reduction of tantalum nitride increases, and when the input power is 20
At 0 W and a treatment time of 60 seconds, the amount of film reduction was about 4.3 nm.

FIG. 51 shows a graph of variations in sheet resistance of tantalum nitride films depending on reverse sputtering conditions. When the input power of reverse sputtering was 50 W, the amount of variation in the sheet resistance value was small even when the processing time was 60 seconds. Input power 100W, processing time 60 seconds, input power 150W, processing time 6
When the input power is 200 W and the processing time is 60 seconds, the sheet resistance value fluctuates greatly, and when the input power is 200 W and the processing time is 60 seconds, the fluctuation is the largest.
It was found that compared to KΩ/□, after the reverse sputtering process, the resistance was significantly reduced to about 12KΩ/□.

FIG. 52 shows the XPS analysis results for the membrane surfaces of Samples 2, 4, 5, 6, and 7. Figure 5
The notation in 2 is 50W for sample 2, 100W for sample 4, 150W for sample 5, and 200W for sample 6.
W, sample 7 corresponds to after film formation. The horizontal axis represents binding energy.
y), and the vertical axis represents signal intensity (Intensity) corresponding to binding energy.

According to FIG. 52, when reverse sputtering was performed, the spectral intensity with high binding energy decreased, and the spectral intensity with low binding energy became strong, and this tendency was greater when the input power was increased. In other words, it was found that when reverse sputtering is performed, the film composition changes from tantalum oxide to tantalum oxynitride and from tantalum oxynitride to tantalum nitride from the side with higher low binding energy to the side with lower binding energy.

FIG. 53 shows the XPS analysis results of sample 7 in the depth direction. Figure 53 shows tantalum (Ta), nitrogen (N), oxygen (O), and silicon (Si) in the depth direction from the film surface of sample 7 to the glass.
profile. According to FIG. 53, about 2 nm from the outermost surface of the tantalum nitride film
At a depth of 3 nm, the proportion of oxygen (O) is large, close to 60 atomic %, and the proportion of nitrogen (N) is as low as 20 atomic % or less, which is close to tantalum oxide. Further, deeper than about 2 nm to 3 nm from the film surface, the ratio of oxygen (O) and nitrogen (N) is reversed from that near the surface, and the ratio of oxygen is 4 atomic % to 6 atomic %, and nitrogen (N) is Approximately 40a
tomic%.

From the above results, by reverse sputtering to a depth of approximately 2 to 3 nm from the outermost surface of the film, the film with a high proportion of oxygen (O) and high electrical resistance was removed, and tantalum nitride with low electrical resistance was replaced. can be formed. This result agrees with the result that a low sheet resistance value was obtained under reverse sputtering conditions of 200 W and 60 seconds.

12 Conductor 13 Insulator 13a Insulator 14 Insulator 14a Insulator 14b Insulator 15 Insulator 15a Insulator 15b Insulator 15c Insulator 16 Hard mask 16a Hard mask 17 Opening 17a Opening 17b Opening 17c Opening 17d Opening 17e Opening 17ea Opening 17eb Opening 17f Opening 17fa Opening 17fb Opening 17g Opening 17ga Opening 17gb Opening 17h Opening 17ha Opening 17hb Opening 17i Opening 17ia Opening 17ib Opening 17j Opening 17ja Opening 17jb Opening 17k Opening 17ka Opening 17kb Opening 18a Resist mask 20 Metal 20a Metal 21 Conductor 21a Conductive Body 21b Conductor 22a Conductor 30 Element layer 31a Conductor 31b Conductor 31c Conductor 31d Conductor 31e Conductor 32a Conductor 32b Conductor 32c Conductor 32d Conductor 32e Conductor 33a Conductor 33b Conductor 33e Conductor 40 Element layer 41a Conductor 41b Conductor 41c Conductor 41d Conductor 41e Conductor 42a Conductor 42b Conductor 42c Conductor 42d Conductor 42e Conductor 43a Conductor 43b Conductor 43c Conductor 43d Conductor 50 Element layer 51a Conductor 51b Conductor 51c Conductor 52a Conductor 52b Conductor 52c Conductor 55a Insulator 55b Insulator 55c Insulator 55d Insulator 55e Insulator 58 Insulator 59 Insulator 60 Processing time 60a Transistor 60b Transistor 61 Insulator 62a Conductor 62b Conductor 63 Insulator 64 Insulator 65 Insulator 66a Insulator 66b Semiconductor 66c Insulator 66ca Insulator 66cb Insulator 67 Insulator 68 Conductor 68a Conductor 68b Conductor 69a Insulator 69b Semiconductor 69c Insulator 72 Insulator 72a Insulation Body 74 Conductor 76 Insulator 77 Insulator 78 Insulator 79 Insulator 80a Capacitor 80b Capacitor 80c Capacitor 81 Insulator 82 Conductor 82a Conductor 82b Conductor 83 Insulator 83a Insulator 83b Insulator 83c Insulator 84 Conductor 85 Insulator 86 Insulator 87 Conductor 88 Insulator 89 Insulator 90a Transistor 90b Transistor 91 Semiconductor substrate 92a Low resistance region 92b Low resistance region 93a Low resistance region 93b Low resistance region 94 Insulator 95 Insulator 96 Conductor 97 Element isolation region 98 Insulator 99 Insulator 102a Insulator 102b Insulator 104 Insulator 106 Insulator 106a Insulator 106b Semiconductor 108 Insulator 110 Insulator 111a Conductor 111b Conductor 111c Conductor 112a Conductor 112b Conductor 112c Conductor 119 Insulator 121a Conductor 121b Conductor 121c Conductor 122a Conductor 122b Conductor 122c Conductor 131 Conductor 132 Conductor 133 Conductor 134 Insulator 136 Insulator 138 Scribe line 200 Imaging device 201 Switch 202 Switch 203 Switch 210 Pixel Section 211 Pixel 212 Subpixel 212B Subpixel 212G Subpixel 212R Subpixel 220 Photoelectric conversion element 230 Pixel circuit 231 Wiring 247 Wiring 248 Wiring 249 Wiring 250 Wiring 250K Sheet resistance value 253 Wiring 254 Filter 254B Filter 254G Filter 254R Filter 255 Lens 256 light 257 Wiring 260 Peripheral circuit 270 Peripheral circuit 280 Peripheral circuit 290 Peripheral circuit 291 Light source 300 Silicon substrate 310 Layer 320 Layer 330 Layer 340 Layer 351 Transistor 352 Transistor 353 Transistor 360 Photodiode 361 Anode 363 Low resistance region 370 Plug 371 Wiring 372 Wiring 373 Wiring 379 Insulator 380 Insulator 381 Insulator 390a Conductor 390b Conductor 390c Conductor 390d Conductor 390e Conductor 400 Semiconductor device 401 CPU core 402 Power controller 403 Power switch 404 Cache 405 Bus interface 406 Debug interface 407 Control device 408 PC
409 Pipeline register 410 Pipeline register 411 ALU
412 Register file 421 Power management unit 422 Peripheral circuit 423 Data bus 500 Semiconductor device 501 Memory circuit 502 Memory circuit 503 Memory circuit 504 Circuit 509 Transistor 510 Transistor 512 Transistor 513 Transistor 515 Transistor 517 Transistor 518 Transistor 519 Capacitor 520 Capacitor 540 Wiring 541 Wiring 542 Wiring 543 Wiring 544 Wiring 711 Board 712 Circuit area 713 Separation area 714 Separation line 715 Chip 750 Electronic component 752 Printed circuit board 753 Semiconductor device 754 Mounting board 755 Lead 800 Inverter 810 OS transistor 820 OS transistor 831 Signal waveform 832 Signal waveform 840 Broken line 841 Solid line 850 OS transistor 860 CMOS inverter 900 Semiconductor device 901 Power supply circuit 902 Circuit 903 Voltage generation circuit 903A Voltage generation circuit 903B Voltage generation circuit 903C Voltage generation circuit 903D Voltage generation circuit 903E Voltage generation circuit 904 Circuit 905 Voltage generation circuit 905A Voltage generation circuit 905E Voltage generation circuit 906 Circuit 911 Transistor 912 Transistor 912A Transistor 912B Transistor 921 Control circuit 922 Transistor 1901 Housing 1902 Housing 1903 Display section 1904 Display section 1905 Microphone 1906 Speaker 1907 Operation key 1908 Stylus 1911 Housing 1912 Housing 1913 Display section 1914 Display portion 1915 connection part 1916 Operation key 1921 indicator 1922 display part 1923 keyboard 1924 Pointing device 1931 housing 1932 refrigerator door for refrigerator room 1941 housing 1941 housing 1942 display part 1 Vehicle body 1952 Wheels 1953 Dashboard 1954 Lights 2100 Transistor 2200 Transistor 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 Wiring 3006 Wiring 3200 Transistor 3300 Transistor 3400 Capacitor 3500 Transistor 4001 Wiring 4003 Wiring 4005 Wiring 4006 Wiring 4007 Wiring 4008 Wiring 4009 Wiring 4021 Layer 4022 Layer 4023 Layer 4100 Transistor 4200 Transistor 4300 Transistor 4400 Transistor 4500 Capacitor 4600 Capacitor

Claims (2)

a first transistor, a second transistor, a capacitor, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. , has
the second transistor is placed above the first transistor,
The first conductive layer, the second conductive layer, and the third conductive layer are a first conductive layer that electrically connects the layer having the first transistor and the layer having the second transistor. Functions as a connecting member,
The fourth conductive layer and the fifth conductive layer are semiconductors that function as a second connecting member that electrically connects the source or drain of the second transistor and one electrode of the capacitor. A device,
a first insulating layer is disposed above the first conductive layer,
a second insulating layer is arranged above the first insulating layer,
a third insulating layer is arranged above the second insulating layer,
The second conductive layer is arranged inside a first opening that penetrates the first insulating layer, the second insulating layer, and the third insulating layer,
The third conductive layer is arranged above the second conductive layer inside the first opening,
the second conductive layer is electrically connected to the first conductive layer in the first opening,
The second conductive layer has a first region overlapping with the top surface of the first conductive layer, a second region along the side surface of the first insulating layer, and a second region along the side surface of the second insulating layer. a third region; and a fourth region along a side surface of the third insulating layer;
A fourth insulating layer is arranged between the source or drain of the second transistor and one electrode of the capacitor,
The fourth conductive layer and the fifth conductive layer are arranged inside a second opening penetrating the fourth insulating layer,
The first insulating layer, the second insulating layer, and the third insulating layer are provided at a different layer from the gate insulating layer of the second transistor,
The upper part of the first connection member functions as a wiring having an extending region in a plan view,
The second connection member has a circular shape in plan view,
In the semiconductor device, the area of the second connection member is smaller than the area of the first connection member in plan view. a first transistor, a second transistor, a capacitor, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. , has
the second transistor is placed above the first transistor,
The first conductive layer, the second conductive layer, and the third conductive layer are a first conductive layer that electrically connects the layer having the first transistor and the layer having the second transistor. Functions as a connecting member,
The fourth conductive layer and the fifth conductive layer are semiconductors that function as a second connecting member that electrically connects the source or drain of the second transistor and one electrode of the capacitor. A device,
a first insulating layer is disposed above the first conductive layer,
a second insulating layer is arranged above the first insulating layer,
a third insulating layer is arranged above the second insulating layer,
The second conductive layer is arranged inside a first opening that penetrates the first insulating layer, the second insulating layer, and the third insulating layer,
The third conductive layer is arranged above the second conductive layer inside the first opening,
the second conductive layer is electrically connected to the first conductive layer in the first opening,
The second conductive layer has a first region overlapping with the top surface of the first conductive layer, a second region along the side surface of the first insulating layer, and a second region along the side surface of the second insulating layer. a third region; and a fourth region along a side surface of the third insulating layer;
The second insulating layer includes hafnium oxide,
The second conductive layer includes titanium nitride,
the third conductive layer includes tungsten;
A fourth insulating layer is arranged between the source or drain of the second transistor and one electrode of the capacitor,
The fourth conductive layer and the fifth conductive layer are arranged inside a second opening penetrating the fourth insulating layer,
The first insulating layer, the second insulating layer, and the third insulating layer are provided at a different layer from the gate insulating layer of the second transistor,
The upper part of the first connection member functions as a wiring having an extending region in a plan view,
The second connection member has a circular shape in plan view,
In the semiconductor device, the area of the second connection member is smaller than the area of the first connection member in plan view.

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