JP2017108080A - Method of manufacturing nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a nitride semiconductor device that, even when a heat treatment temperature is higher than a pit generation temperature or a decomposition temperature of a protective film provided on a GaN layer, prevents a pit from being generated on the protective film and prevents the protective film from being decomposed.SOLUTION: The method of manufacturing a nitride semiconductor device includes steps of: forming a first protective film on an impurity-doped gallium nitride layer; forming a second protective film higher in heat resistance than the first protective film on the first protective film; and heat treating the gallium nitride layer.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for manufacturing a nitride semiconductor device.

Conventionally, a cap layer made of aluminum nitride (hereinafter referred to as AlN) is provided on a gallium nitride (hereinafter referred to as GaN) -based compound semiconductor doped with a p-type impurity and subjected to heat treatment (for example, see Patent Document 1). Conventionally, MgN-doped AlN is provided on a GaN-based compound semiconductor layer doped with magnesium (Mg) to form a cap layer during heat treatment (see, for example, Patent Document 2).
[Prior art documents]
[Patent Literature]
[Patent Document 1] JP-A-5-183189 [Patent Document 2] JP-A-8-186322

  In the activation heat treatment after ion implantation, heating at a temperature about 2/3 of the melting point of the material constituting the semiconductor layer is empirically required. Specifically, when a nitride semiconductor such as GaN is used as the semiconductor material, the heating temperature is expected to be about 1500 ° C. to 1700 ° C. However, when heat-treating the GaN layer in such a high temperature region, pits are generated in AlN used as the cap layer. In addition, nitrogen escapes from AlN and decomposes. As a result, there is a problem that nitrogen is released from the underlying GaN layer due to generation or decomposition of AlN pits.

  Therefore, conventionally, a GaN layer doped with a p-type impurity has been heat-treated at about 1,300 ° C. However, at about 1300 ° C., the p-type impurity cannot be activated sufficiently. If the activation is not sufficient, crystal defects remain in the GaN layer. Since crystal defects cause an effect of compensating n-type carriers for p-type impurities, it is difficult to obtain a sufficient p-type carrier concentration.

  Even at a heat treatment temperature higher than the pit generation temperature or decomposition temperature of the protective film provided on the GaN layer, generation of pits in the protective film or decomposition of the protective film is prevented.

  The method for manufacturing a nitride semiconductor device according to the first aspect of the present invention may include a step of forming a first protective film, a step of forming a second protective film, and a step of heat treatment. The first protective film may be formed on the gallium nitride layer doped with impurities. The second protective film may be formed on the first protective film. The second protective film may have higher heat resistance than the first protective film. In the heat treatment step, the gallium nitride layer may be heat treated.

  The first protective film may be a nitride film containing aluminum nitride.

  The second protective film may be any one of a refractory metal, a carbon film, and a boron nitride film.

  The refractory metal may be any of tungsten, tantalum and molybdenum.

  The carbon film may be any of a graphite film, a DLC film, and a nanodiamond film.

  The method for manufacturing a nitride semiconductor device may further include a step of selectively removing the second protective film with respect to the first protective film after the step of heat-treating the gallium nitride layer.

  The method for manufacturing a nitride semiconductor device may further include a step of selectively removing the first protective film from the gallium nitride layer after the step of selectively removing the second protective film.

  The impurity-doped gallium nitride layer may have a region doped with p-type impurities for the gallium nitride layer.

  The thickness of the second protective film on the region doped with the p-type impurity may be larger than the thickness of the second protective film on the other region on the gallium nitride layer not doped with the p-type impurity.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

2 is a schematic diagram showing a cross section of a vertical MOSFET 100. FIG. 5 is a flowchart showing a method 200 for manufacturing the vertical MOSFET 100. FIG. FIG. 4 is a diagram showing a step (S10) of forming an n ⁻ -type GaN layer 20. It is a figure which shows the step (S20) which forms an impurity region. It is a figure which shows the step (S30) which forms the 1st protective film 60. FIG. It is a figure which shows the step (S40) which forms the 2nd protective film 62. It is a figure which shows the step (S50) which heat-processes the GaN layer. It is a figure which shows the step (S60) which removes the 2nd protective film 62 selectively with respect to the 1st protective film 60. FIG. It is a figure which shows the step (S70) which removes the 1st protective film 60 selectively with respect to the GaN layer 40. FIG. It is a figure which shows the step (S80) of forming the gate insulating film 54 grade | etc.,. It is a figure which shows the modification (S42) of the step in which the 2nd protective film 62 is formed. It is a figure which shows the step (S34) which forms the 1st protective film 60 in the main surface 42 and the other main surface 44. It is a figure which shows the step (S44) which forms the 2nd protective film 62 in the main surface 42 side and the other main surface 44 side.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a schematic diagram showing a cross section of the vertical MOSFET 100. The nitride semiconductor device of this example is a planar gate type vertical MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 100. The vertical MOSFET 100 includes a GaN layer 40, a gate insulating film 54, a gate electrode 50, a source electrode 56, and a drain electrode 58.

The GaN layer 40 of this example includes an n ⁺ -type GaN substrate 10 and an n ⁻ -type GaN layer 20 that is epitaxially formed on the n ⁺ -type GaN substrate 10. The upper surface of the n ⁻ -type GaN layer 20 is a main surface 42 of the GaN layer 40, and the lower surface of the n ⁺ -type GaN substrate 10 is another main surface 44 of the GaN layer 40. In this example, “upper” and “upper” indicate directions from the other main surface 44 toward the main surface 42. On the other hand, “lower” and “lower” refer to directions opposite to “upper” and “upper”.

In the present specification, n or p means that electrons or holes are majority carriers, respectively. In addition, regarding + or − written on the right shoulder of n or p, + means that the carrier concentration is higher than that in which it is not described, and − means that the carrier concentration is lower than that in which it is not described. To do. When simply described as n-type, the n-type is a concept including an n ⁺ type and an n ⁻ type. Similarly, when simply described as a p-type, the p-type is a concept including a p ⁺ type and a p ⁻ type.

The GaN layer 40 has a p-type well region 30, an n ⁺ -type source region 32, and a p ⁺ -type contact region 34 on the main surface 42 side. The n ⁺ type source region 32 and the p ⁺ type contact region 34 are provided in the p type well region 30 so that a part thereof is exposed to the main surface 42. A region on the main surface 42 side of the p-type well region 30 different from the n ⁺ -type source region 32 and the p ⁺ -type contact region 34 becomes a channel formation region 36. A schematic shape of the channel forming region 36 is indicated by a dotted line.

On the main surface 42 of the GaN layer 40, a source electrode 56 is provided in direct contact with the n ⁺ type source region 32 and the p ⁺ type contact region 34. A drain electrode 58 is provided in direct contact with the other main surface 44 of the GaN layer 40. A ground potential may be applied to the source electrode 56, and a power supply voltage (V _DD ) may be applied to the drain electrode 58.

A gate insulating film 54 is provided in direct contact with the main surface 42 of the GaN layer 40. A gate electrode 50 is provided on and in contact with the gate insulating film 54. In this example, when a positive voltage is applied to the gate electrode 50, a charge inversion layer is formed in the channel formation region 36 immediately below the gate electrode 50. Thereby, an electron current flows in the order of the source electrode 56, the n ⁺ -type source region 32, the channel formation region 36, the n ⁻ -type GaN layer 20, the n ⁺ -type GaN substrate 10 and the drain electrode 58.

  First Embodiment FIG. 2 is a flowchart showing a method 200 for manufacturing a vertical MOSFET 100. In this embodiment, each step is executed in the order from S10 to S80. The present embodiment is characterized in that the GaN layer 40 is heat-treated after the second protective film 62 is formed on the first protective film 60. As will be described later, the second protective film 62 may be any one of a carbon film, a boron nitride (BN) film, and a refractory metal. An example using a carbon film is described as a first embodiment, an example using a boron nitride film is described as a second embodiment, and an example using a refractory metal is described as a third embodiment.

FIG. 3A is a diagram showing a step (S10) of forming the n ⁻ -type GaN layer 20. The n ⁻ -type GaN layer 20 of this example is formed by metal organic vapor phase epitaxy (MOCVD) while doping n-type impurities. The n-type impurity may be one or more elements of oxygen (O) and silicon (Si). Instead of the MOCVD method, a halide vapor phase growth method (HVPE method) or a molecular beam epitaxy method (MBE method) may be used. Furthermore, instead of the n ⁺ -type GaN substrate 10, an n ⁺ -type silicon carbide (SiC) substrate or a zirconium boride (ZrB ₂ ) substrate may be used.

The n type impurity concentration of the n ⁺ type GaN substrate 10 may be 1E + 17 cm ⁻³ or more and 1E + 20 cm ⁻³ or less. The n type impurity concentration of the n ⁻ type GaN layer 20 may be about 1E + 16 cm ⁻³ . Assuming a 1200V breakdown voltage, the thickness of the n ⁺ -type GaN substrate 10 may be 100 μm or more and 500 μm or less, and the thickness of the n ⁻ -type GaN layer 20 may be 10 μm. In this specification, E means a power of 10, for example, 1E + 16 means 1 × 10 ¹⁶ . For example, E-6 means ^10-6 .

FIG. 3B is a diagram showing a step (S20) of forming an impurity region. Next, the main surface 42 of the GaN layer 40 is selectively doped with p-type impurities for the GaN layer 40. Thereby, the p-type well region 30 and the p ⁺ -type contact region 34 are formed. Thereafter, an n-type impurity for the GaN layer 40 is doped into a region where the n ⁺ -type source region 32 is formed. The p-type impurity may be one or more elements of magnesium (Mg) and beryllium (Be).

The p-type impurity concentration of the p-type well region 30 may be 1E + 17 cm ⁻³ . The p type impurity concentration of the p ⁺ type contact region 34 may be 4E + 19 cm ⁻³ . The n ⁺ type source region 32 may have an n type impurity concentration of 1E + 20 cm ⁻³ . Impurity doping can be performed by a known ion doping method.

FIG. 3C is a diagram showing a step of forming the first protective film 60 (S30). The first protective film 60 is formed on the GaN layer 40 doped with n-type and p-type impurities. The first protective film 60 may be an Al _x In _y Ga _1-xy N (0 <x ≦ 1, 0 ≦ y ≦ 1) film. In one example, the first protective film 60 may be a nitride film containing AlN. In a most preferred example, the first protective film 60 is an AlN film.

  From the viewpoint of heat resistance, the first protective film 60 is preferably an AlN, GaN film, and InN film in this order. That is, the AlN film is most preferable from the viewpoint of heat resistance. Furthermore, the first protective film 60 needs to be selectively etched with respect to the underlying GaN layer 40, and an AlN film is most preferable in terms of selective etching with respect to the underlying layer. The temperature at which nitrogen decomposes in the AlN film is considered to be about 1,400 ° C. to 1,500 ° C.

  In the present embodiment, the heat resistance of the film means melting or thermal softening that is an entire change of the film, or decomposition or sublimation that is a partial change of the film. A film having high heat resistance means a film in which melting, thermal softening, decomposition, or sublimation of the film does not occur in a predetermined temperature range. For example, AlN can be said to have high heat resistance in the temperature range of 800 ° C. to 1,200 ° C., but AlN cannot be said to have high heat resistance in the temperature range of 1,400 ° C. to 1,500 ° C.

Note that the Al _x In _y Ga _1-xy N (0 <x ≦ 1, 0 ≦ y ≦ 1) film has good adhesion to the GaN layer 40. Therefore, the Al _x In _y Ga _1-xy N film does not peel from the GaN layer 40 in the subsequent heat treatment step (S50). Note that it is also possible to use silicon nitride (Si ₃ N ₄ ) or silicon oxide (SiO ₂ ) as the first protective film 60. However, Si atoms diffuse into the GaN layer 40 in the subsequent heat treatment step (S50) and function as n-type impurities for the GaN layer 40. Therefore, if the influence on the underlying GaN layer 40 is taken into consideration, the Al _x In _y Ga _1-xy N film is more preferable than Si ₃ N ₄ or SiO ₂ .

The AlN film as the first protective film 60 is trimethyl aluminum (TMA; Al (CH ₃ ) ₃ ) gas, ammonia (NH ₃ ) gas, and at least one of hydrogen (H ₂ ) gas and nitrogen (N ₂ ). It can be formed by MOCVD using a mixed gas containing. When forming the AlN film, the GaN layer 40 may be heated. The heating temperature is preferably lower than that in the subsequent heat treatment step (S50). In this embodiment, the temperature of the said heating may be 500 degreeC or more and 1200 degrees C or less. Note that when forming the AlN film, the atmospheric pressure in the film formation chamber may be set to 5 kPa or more and 100 kPa or less. The film thickness of the AlN film may be 2 nm or more and 100 nm or less. As an example, it may be 4 nm.

  The AlN film as the first protective film 60 may be formed by a sputtering method. In this case, the film thickness of AlN may be 100 nm or more and 1000 nm or less. As an example, it may be 500 nm. The AlN film may be formed by a PLD (Pulsed Laser Deposition) method. In this case, the film thickness of AlN may be 10 nm or more and 100 nm or less. As an example, it may be 80 nm. The upper limit value of the AlN film thickness may be determined in consideration of ease of removal in a later stage.

  The denser the first protective film 60, the higher the surface protective effect of the GaN layer 40. That is, the denser the film, the higher the effect of preventing nitrogen from decomposing from the main surface 42. The first protective film 60 is epitaxially formed when formed by MOCVD, HVPE, MBE, or PLD. On the other hand, the first protective film 60 becomes a polycrystalline film when formed by sputtering. Since the epitaxial film is denser than the polycrystalline film, the first protective film 60 is preferably formed by the MOCVD method, the HVPE method, the MBE method, or the PLD method.

  FIG. 3D is a diagram showing a step of forming the second protective film 62 (S40). The second protective film 62 is formed on the first protective film 60. The second protective film 62 has higher heat resistance than the first protective film 60. Therefore, pit generation in the first protective film 60 or decomposition of the first protective film 60 can be prevented even at a heat treatment temperature higher than the pit generation temperature or decomposition temperature of the first protective film 60.

  The second protective film 62 in the present embodiment is a carbon film. The carbon film may be any one of a graphite film, a DLC (Diamond-like Carbon) film, a nanodiamond film, and a resist carbonized film. Since the raw material of the carbon film is inexpensive, it is effective for suppressing the manufacturing cost of the vertical MOSFET 100. In addition, the carbon film can be easily removed by oxygen ashing or heating in an oxygen atmosphere. In addition, the removal method can selectively remove the first protective film 60.

  The DLC film can be formed by sputtering or ion plating using graphite as a target. The DLC film formed by the sputtering method may have a thickness of 10 nm to 100 nm. As an example, it may be 50 nm. Further, a DLC film or a nanodiamond film can be formed by a plasma CVD method using a hydrocarbon gas as a source gas. The DLC film formed by the plasma CVD method may have a thickness of 10 nm to 100 nm. As an example, it may be 50 nm.

  Note that both the AlN film as the first protective film 60 and the carbon film as the second protective film 62 may be formed by sputtering. In this case, the film can be formed by changing the target in the same chamber without transferring the GaN layer 40 between the chambers. Therefore, film formation becomes easy. Note that the film production method affects the crystallinity. When both the AlN film as the first protective film 60 and the carbon film as the second protective film 62 are formed by sputtering, the AlN film is polycrystalline and the carbon film is an amorphous film. In this case, in the subsequent steps S60 and S70, the etching rate is higher than in the case where at least one of the two is a single crystalline film, so that the protective film can be easily removed.

  Instead of the DLC film or the nanodiamond film, a resist carbonized film may be used. A resist carbonized film can be formed by heating and carbonizing a resist film used for photolithography. Further, a graphite film may be used in place of the DLC film, nanodiamond film or resist carbonized film. The graphite film can be formed by reducing graphite oxide with light. Moreover, it can form by apply | coating the graphite containing solution disperse | distributed to the solvent, and removing a solvent after that.

FIG. 3E is a diagram showing a step of heat-treating the GaN layer 40 (S50). The GaN layer 40 is heat treated in a heat treatment furnace 70. The heat treatment furnace 70 may be a high frequency induction heating furnace. During the heat treatment, the inside of the heat treatment furnace 70 may be an inert gas atmosphere. In this embodiment, an argon (Ar) or nitrogen (N ₂ ) atmosphere may be used. The heat treatment temperature is 800 ° C or higher, preferably 1,200 ° C or higher, most preferably 1,500 ° C or higher. In particular, p-type impurities in the GaN layer 40 can be sufficiently activated by heat treatment at 1,500 ° C. or higher. By the heat treatment, the p-type well region 30, the n ⁺ -type source region 32 and the p ⁺ -type contact region 34 are completed.

  FIG. 3F is a diagram illustrating a step of selectively removing the second protective film 62 with respect to the first protective film 60 (S60). In the present embodiment, since the second protective film 62 is a carbon film, the second protective film 62 is removed by ashing using oxygen plasma. At this time, the first protective film 60 is not removed. Therefore, the influence on the GaN layer 40 due to the etching process for removing the second protective film 62 can be suppressed.

  FIG. 3G is a diagram showing a step (S70) of selectively removing the first protective film 60 from the GaN layer 40. The AlN film, which is the first protective film 60, is selectively removed from the underlying GaN layer 40 by wet etching using a potassium hydroxide aqueous solution (KOHaq). Therefore, even if the first protective film 60 is provided, it is possible to suppress the influence on the GaN layer 40 that is the base when the protective film is removed.

FIG. 3H is a diagram showing a step (S80) of forming the gate insulating film 54 and the like. In this embodiment, as the gate insulating film 54, a SiO ₂ film formed by PECVD (Plasma Enhanced CVD) is deposited to a thickness of about 100 nm. In this stage, since the high-temperature heat treatment at about 1500 ° C. performed in the heat treatment stage (S50) is not performed, there is no problem of mixing n-type impurities even if the SiO ₂ film is used. Instead of the SiO ₂ film, a SiN _x film, a SiON film, an Al ₂ O ₃ film, a MgO film, a GaO _x film, or a GdO _x film may be used. The gate insulating film 54 may be a stack of the above insulating films.

Polysilicon is deposited on the SiO ₂ film by LPCVD (Low Pressure CVD). Next, the polysilicon is doped with one or more of phosphorus (P) and arsenic (As), which are n-type impurities to the polysilicon. Thereby, n-type polysilicon is obtained. The n-type polysilicon may be formed by introducing n-type impurities into the polysilicon growth atmosphere. After the n-type polysilicon is formed, the n-type impurity is activated by heat treatment at about 900 ° C. In place of n-type polysilicon, a metal film of gold (Au), platinum (Pt) and nickel (Ni) or an alloy film thereof may be used.

Next, the n-type polysilicon and the SiO ₂ film are patterned by photolithography and etching. Thereby, the gate electrode 50 and the gate insulating film 54 are formed. Further, after the etching, the n ⁺ type source region 32 and the p ⁺ type contact region 34 are partially exposed.

Next, the source electrode 56 is formed in a region where the n ⁺ type source region 32 and the p ⁺ type contact region 34 are partially exposed. The source electrode 56 may be formed of a conductor that is in ohmic contact with the n ⁺ -type source region 32 and the p ⁺ -type contact region 34 or a low-resistance conductor that is close to the ohmic contact. The source electrode 56 of this example is a laminated metal film in which Al is laminated on titanium (Ti). The source electrode 56 can be formed by forming a film by sputtering and then patterning by photolithography and etching. Further, the source electrode 56 may be formed by a lift-off method and a selective growth method.

  Next, the drain electrode 58 is formed under the other main surface 44 of the GaN layer 40. Similarly to the source electrode 56, the drain electrode 58 may be a laminated metal film in which Ti and Al are sequentially laminated. Thereafter, an oxide film for element isolation is appropriately formed on the main surface 42 side of the GaN layer 40. Thereby, the vertical MOSFET 100 is completed.

Second Embodiment In this embodiment, a boron nitride (BN) film is used as the second protective film 62. This is different from the first embodiment. Note that S10 to S30, S50, S70, and S80 are the same as those in the first embodiment. Therefore, only S40 and S60, which are different from the first embodiment, will be described.

In S40 of this embodiment, a BN film as the second protective film 62 may be formed on the first protective film 60 by a pulse laser deposition method. Specifically, the target is irradiated with a KrF excimer laser at an energy density of 2 [J / cm ² ] using BN polycrystal as a target. The inside of the chamber in which the pulse laser deposition method is performed may be an ammonia (NH ₃ ) atmosphere at 900 ° C. and 5E-5 [Torr]. The BN film may be 10 [nm] or more and 1,000 [nm] or less. Note that the BN film may be formed by a CVD method or a sputtering method instead of the pulse laser deposition method.

  When BN is used, both the AlN film as the first protective film 60 and the BN film as the second protective film 62 can be made crystalline. Thereby, the main surface 42 of the GaN layer 40 can be covered with a dense protective film. Therefore, the surface protection effect of the main surface 42 of the GaN layer 40 can be enhanced as compared with the first embodiment. In addition, by using crystalline BN, the surface protection effect of the first protective film 60 can be enhanced as compared with the first embodiment.

  In S60 of this embodiment, BN may be etched using a gas mainly containing oxygen gas as a plasma etching gas. Thereby, the BN film as the second protective film 62 and the AlN film as the first protective film 60 can be selectively removed.

(Third Embodiment) In this embodiment, a refractory metal is used as the second protective film 62. This is different from the first embodiment. Note that S10 to S30, S50, S70, and S80 are the same as those in the first embodiment. Therefore, only S40 and S60, which are different from the first embodiment, will be described. The refractory metal may be any of tungsten (W), tantalum (Ta), and molybdenum (Mo). In this embodiment, an example of W will be described.

  In S40 of this embodiment, a W film as the second protective film 62 may be formed on the first protective film 60 by sputtering. Specifically, a W target may be placed in a chamber, and the inside of the chamber may be 1 [Pa] argon (Ar) atmosphere. By providing a potential difference between the W target and the GaN layer 40, ionized Ar strikes the W target. As a result, the hit W atoms are formed on the first protective film 60. The W film may be 10 [nm] or more and 500 [nm] or less. The sputtering power supply that provides the potential difference may have a power of 300 [W].

Compared with the first embodiment and the second embodiment, the refractory metal generally has a thermal expansion coefficient close to that of the AlN film used for the first protective film 60. Therefore, since it becomes difficult to peel off from the AlN film, the surface protection effect during the heat treatment (S50) can be improved. In particular, the thermal expansion coefficient of W is close to that of AlN used for the first protective film 60 as compared with Mo and Ta. As an example of the thermal expansion coefficient (unit: E-6 ° C. ⁻¹ ), W is 4.5, Mo is 5.3, and Ta is 6.3. On the other hand, AlN is 4.6 as an example of a thermal expansion coefficient (a unit is E-6 degreeC <^-1> ). Therefore, the combination of using the W film as the second protective film 62 and using the AlN film as the first protective film 60 has the highest surface protective effect.

In S60 of the present embodiment, the refractory metal may be wet etched using a mixed solution of hydrofluoric acid (HF) and nitric acid (HNO ₃ ). Alternatively, dry etching may be performed using fluorine gas or chlorine gas instead of wet etching. Thereby, the refractory metal film as the second protective film 62 and the AlN film as the first protective film 60 can be selectively removed.

  As a modification, two layers of the second protective film 62 made of different materials may be stacked. In one example, a BN film may be formed on the carbon film, and vice versa (that is, a carbon film may be formed on the BN film). Further, a refractory metal film may be formed on the BN film, or vice versa. Furthermore, a carbon film may be formed on the refractory metal, or vice versa.

  (Fourth Embodiment) FIG. 4 is a view showing a modification (S42) at the stage of forming the second protective film 62. In FIG. In the present embodiment, the thickness of the second protective film 62 is changed according to the position on the main surface 42. That is, the thickness 64-2 on the region doped with the p-type impurity may be larger than the thickness 62-1 on the other region not doped with the p-type impurity. Specifically, after forming the second protective film 62 once, an additional second protective film may be formed to form the second protective film 62 that changes depending on the region. . Thus, by making the thickness of the second protective film 62 on the p-type well region 30 thicker than that of other regions, it is possible to more reliably prevent nitrogen escape from the p-type well region 30. .

  Fifth Embodiment FIG. 5A is a diagram showing a step (S34) of forming a first protective film 60 on the main surface 42 and the other main surface 44. FIG. FIG. 5B is a diagram showing a step (S44) of forming the second protective film 62 on the main surface 42 side and the other main surface 44 side. In the present embodiment, in addition to the main surface 42, the first protective film 60 and the second protective film 62 are stacked under the other main surface 44. Thereby, nitrogen escape from the other main surface 44 can be prevented during the heat treatment (S50).

  Note that the heat treatment stage in which the first protective film 60 and the second protective film 62 are stacked is not limited to the purpose of activating the p-type impurity region. The heat treatment method may be applied to PDA (Postdeposition Annealing) after forming an insulating film, or metal sintering.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the operation flow in the claims, the description, and the drawings is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

10 ·· n ⁺ type GaN substrate, 20 ·· n ⁻ type GaN layer, 30 ·· p type well region, 32 ·· n ⁺ type source region, 34 ·· p ⁺ type contact region, 36 ·· channel formation region , 40 .. GaN layer, 42 .. main surface, 44 .. other main surface, 50 .. gate electrode, 54 .. gate insulating film, 56 .. source electrode, 58 .. drain electrode, 60. 1, protective film 62, second protective film 64, thickness 70, heat treatment furnace 100, vertical MOSFET 200, manufacturing method

Claims (9)

A method for manufacturing a nitride semiconductor device, comprising:
Forming a first protective film on the impurity-doped gallium nitride layer;
Forming a second protective film having a higher heat resistance than the first protective film on the first protective film;
And a step of heat-treating the gallium nitride layer. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the first protective film is a nitride film containing aluminum nitride. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the second protective film is any one of a carbon film, a boron nitride film, and a refractory metal. The method for manufacturing a nitride semiconductor device according to claim 3, wherein the refractory metal is any one of tungsten, tantalum, and molybdenum. The method for manufacturing a nitride semiconductor device according to claim 3, wherein the carbon film is any one of a graphite film, a DLC film, and a nanodiamond film. 6. The nitriding according to claim 1, further comprising the step of selectively removing the second protective film with respect to the first protective film after the step of heat-treating the gallium nitride layer. For manufacturing a semiconductor device. The nitride semiconductor device according to claim 6, further comprising a step of selectively removing the first protective film from the gallium nitride layer after the step of selectively removing the second protective film. Production method. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the gallium nitride layer doped with an impurity has a region doped with a p-type impurity with respect to the gallium nitride layer. The thickness of the second protective film on the region doped with the p-type impurity is larger than the thickness of the second protective film on the other region on the gallium nitride layer not doped with the p-type impurity. The method for manufacturing a nitride semiconductor device according to claim 8, which is larger.

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