JP2017098402A - Through electrode substrate and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a through electrode substrate having improved electrical characteristics, and ensuring high yield even when a through hole having a hole diameter of more than about 60 μm is included, and to provide a method of manufacturing the same.SOLUTION: A method of manufacturing a through electrode includes to form a through hole in a substrate, to form a seed layer on the first surface of the substrate, to immerse the substrate into a first plating liquid, and to grow a first plating layer from the first surface until the through hole is closed, by first plating for supplying a current to the seed layer, to immerse the substrate into a second plating liquid, and to grow a second plating layer on the first plating layer until the space surrounded by a plane including the first face and the first plating layer is filled, by second plating for supplying a current to the first plating layer, before polishing the first surface until the first surface of the substrate is exposed.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a through electrode substrate and a manufacturing method thereof.

  In recent years, three-dimensional mounting technology in which semiconductor chips are stacked vertically has become indispensable for higher integration and higher functionality of LSI systems. In this technique, it is necessary to efficiently connect the upper and lower semiconductor chips. In view of this, a through electrode technique in which a through hole is provided in a semiconductor chip, a conductive material is filled in the through hole, and both surfaces of the semiconductor chip are electrically connected is attracting attention.

  In particular, as a technique for forming a through electrode by plating treatment, a technique of filling a conductive material by a so-called bottom-up method in which a cover plating is formed in the vicinity of one opening edge of the through hole and the conductive material is grown in the thickness direction of the substrate. Is known (Patent Documents 1 and 2).

JP 2013-106015 A JP 2014-187297 A

  In particular, in the case of filling plating to a through hole having a hole diameter of about 50 μm or more, a depression is generated on the surface of the filled conductor, and the depression remains on the surface even after polishing by CMP. In the subsequent wiring formation process, an insulating film enters the recess, resulting in a patterning failure and a cause of electrical conduction failure.

  In view of the above circumstances, an object of the present invention is to provide a through electrode substrate having a high yield and improved electrical characteristics even when a through hole having a hole diameter of about 60 μm or more is included, and a method for manufacturing the same. To do.

  The method for manufacturing a through electrode substrate according to an embodiment of the present invention includes forming a through hole in a substrate, forming a seed layer on a first surface of the substrate, immersing the substrate in a first plating solution, and A first plating process for supplying a current to the layer, the first plating layer is grown from the first surface side until the through-hole is closed, the substrate is immersed in a second plating solution, and the first plating layer A second plating layer is grown on the first plating layer until the space surrounded by the plane including the first surface and the first plating layer is filled by the second plating process for supplying a current to the first plating layer. And polishing the first surface side until the first surface of the substrate is exposed.

  By such a manufacturing method, even if the hole diameter of the through hole is larger than about 60 μm, it is possible to avoid the formation of a depression on the surface of the through electrode filled in the through hole. As a result, the occurrence of electrical continuity failure can be suppressed. Therefore, the manufacturing yield can be improved and a highly reliable through electrode substrate can be provided.

  The second plating solution may have a lower sulfuric acid concentration than the first plating solution.

  By such a manufacturing method, even if the hole diameter of the through hole is larger than about 60 μm, it is possible to avoid the formation of a depression on the surface of the through electrode filled in the through hole. As a result, the occurrence of electrical continuity failure can be suppressed. Therefore, the manufacturing yield can be improved and a highly reliable through electrode substrate can be provided.

  After the through hole is closed, the first surface may be shielded from the second plating solution in order to prevent the growth of the second conductive layer on the first surface side.

  With such a manufacturing method, the growth of the second conductive layer on the surface of the through electrode substrate can be minimized. Thereby, the polishing amount of the conductive layer to be removed by the CMP process can be minimized. Accordingly, the processing time is shortened, and the through electrode substrate can be manufactured at a low cost.

  The through hole may be capable of including a circle having a diameter of 60 μm in a planar shape.

  By such a manufacturing method, it is possible to avoid the formation of a depression on the surface of the through electrode filled in the through hole in the through hole having various shapes or sizes. As a result, the occurrence of electrical continuity failure can be suppressed. Therefore, the manufacturing yield can be improved and a highly reliable through electrode substrate can be provided.

  The substrate may be a glass substrate.

  By such a manufacturing method, even if the glass substrate requires a hole diameter of about 60 μm or more, it is possible to avoid the formation of a depression on the surface of the through electrode filled in the through hole. As a result, the occurrence of electrical continuity failure can be suppressed. Therefore, the manufacturing yield can be improved and a highly reliable through electrode substrate can be provided.

  A through electrode substrate according to an embodiment of the present invention fills a substrate having a through hole, a first conductive layer that fills a part of the through hole, and has a recess on one opening edge side of the through hole, and the recess. A second conductive layer.

  By having such a configuration, the surface of the through electrode filled in the through hole becomes flat. Thereby, an increase in contact resistance between the through electrode and the wiring can be avoided. Therefore, it is possible to provide a through electrode substrate having excellent electrical characteristics and high reliability.

  The through hole may be capable of including a circle having a diameter of 60 μm in a planar shape.

  By having such a configuration, the surface of the through electrode filled in the through hole becomes flat in the through holes of various shapes or sizes. Thereby, an increase in contact resistance between the through electrode and the wiring can be avoided. Therefore, it is possible to provide a through electrode substrate having excellent electrical characteristics and high reliability.

  The substrate may be a glass substrate.

  By having such a configuration, the surface of the through electrode filled in the through hole becomes flat even if the glass substrate requires a hole diameter of about 60 μm or more. Thereby, an increase in contact resistance between the through electrode and the wiring can be avoided. Therefore, it is possible to provide a through electrode substrate having excellent electrical characteristics and high reliability.

  A through electrode substrate having a high yield and improved electrical characteristics and a method for manufacturing the same can be provided.

It is a top view showing an outline of a penetration electrode substrate concerning one embodiment of the present invention. It is an AA 'sectional view of a penetration electrode substrate concerning one embodiment of the present invention. It is sectional drawing, the top view, and bottom view before the wiring layer formation of the penetration electrode substrate concerning one embodiment of the present invention. It is sectional drawing for demonstrating the manufacturing method of the penetration electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the penetration electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the penetration electrode substrate which concerns on one Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the penetration electrode substrate which concerns on one Embodiment of this invention. In the penetration electrode substrate concerning one embodiment of the present invention, it is a figure showing some examples of plane shape of a penetration electrode which can be manufactured. It is a figure showing a semiconductor device concerning one embodiment of the present invention. It is a figure showing a semiconductor device concerning one embodiment of the present invention. It is a figure showing a semiconductor device concerning one embodiment of the present invention.

  Hereinafter, a configuration of a through electrode substrate and a manufacturing method thereof according to an embodiment of the present invention will be described in detail with reference to the drawings. In addition, embodiment shown below is an example of embodiment of this invention, This invention is limited to these embodiment, and is not interpreted. Note that in the drawings referred to in this embodiment, the same portions or portions having similar functions are denoted by the same reference symbols or similar symbols, and repeated description thereof may be omitted. In addition, the dimensional ratio in the drawing may be different from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.

<First Embodiment>
The configuration and manufacturing method of the through electrode substrate 100 according to the present embodiment will be described in detail with reference to the drawings.

[Configuration of through electrode substrate]
The configuration of the through electrode substrate 100 according to the present embodiment will be described in detail with reference to FIGS. 1 to 3. FIG. 1 is a plan view showing an outline of a through electrode substrate 100 according to the present embodiment. FIG. 2 is a cross-sectional view taken along the line AA ′ of the through electrode substrate 100 according to the present embodiment. FIG. 3 is a cross-sectional view, a top view, and a bottom view of the through electrode substrate 100 according to the present embodiment before forming a wiring layer.

  The through electrode substrate according to this embodiment includes a substrate 102, a through electrode 110, and a wiring layer 130. The through electrode 110 includes a first conductive layer 110a and a second conductive layer 110b.

  The substrate 102 has a first surface 104 and a second surface 106 opposite to the first surface 104. Furthermore, it has a through hole 108 that is disposed inside the substrate 102 and connects the first surface 104 and the second surface 106.

  Although there is no restriction | limiting in particular as a hole diameter of the through-hole 108, 60 micrometers or more may be sufficient. The planar shape of the through hole 108 is not limited to a circle, and may be various shapes as will be described later.

  Although the through hole 108 of the through electrode substrate 100 according to the present embodiment has a shape obtained by hollowing out a cylinder, the shape is not limited to such a shape as will be described later. That is, the shape of the opening edge of the through hole 108 is not limited to a circle. Moreover, it is not restricted to columnar shape, The cross-sectional shape cut | disconnected in the substrate surface direction may differ according to the depth direction.

  As the substrate 102, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, or the like can be used. As the semiconductor substrate, for example, a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate, or the like can be used. As the conductive substrate, for example, an aluminum substrate, a stainless steel substrate, or the like can be used. Moreover, these may be laminated.

  The thickness of the substrate 102 is not particularly limited, but for example, it is preferable to use the substrate 102 having a thickness of 100 μm to 800 μm. More preferably, the thickness is 200 μm or more and 500 μm or less. As the thickness of the substrate 102 decreases, the deflection of the substrate 102 increases. As a result, handling in the manufacturing process becomes difficult, and the substrate 102 is warped by internal stress such as a thin film formed on the substrate 102. Further, when the thickness of the substrate 102 is increased, the formation time of the through hole 108 is increased. As a result, the manufacturing process becomes longer and the manufacturing cost increases.

  The first conductive layer 110 a fills a part of the through hole 108 and has a recess on one opening edge side of the through hole 108. Further, the first conductive layer 110 a closes the through hole 108. In this embodiment, as shown in FIGS. 2 and 3, the substrate 102 has a recess on the opening edge side of the through hole 108 on the first surface 104 side. Further, the first conductive layer 110 a closes the through hole 108 in the vicinity of the opening edge of the through hole 108 on the first surface 104 side of the substrate 102. FIG. 3B is a plan view of the through electrode substrate 100 before the wiring layer 130 is formed, as viewed from the first surface 104 side. In plan view, the second conductive layer 110 b is disposed inside the through hole 108, surrounds the periphery, and is in contact with the edge of the through hole 108 and is filled with the first conductive layer 110 a.

  The second conductive layer 110b fills at least the concave portion of the first conductive layer 110a. In the present embodiment, the first conductive layer 110a that closes the through hole 108 is also filled with the through hole 108 on the second surface 106 side. FIG. 3C is a plan view of the through electrode substrate 100 before the wiring layer 130 is formed, as viewed from the second surface 106 side. The second conductive layer 110b is disposed inside the through hole 108 in plan view.

  As the first conductive layer 110a and the second conductive layer 110b, for example, copper (Cu), gold (Au), silver (Ag), platinum (Pt), rhodium (Rh), tin (Sn), aluminum It can be selected from metals such as (Al), nickel (Ni), chromium (Cr), or alloys using these metals. The first conductive layer 110a and the second conductive layer 110b may be made of the same material or different materials. When both are the same materials, the crystal grain size of both may be different.

  The wiring layer 130 is disposed on the first surface 104 and the second surface 106 of the substrate 102, and the wiring layers 130 on both surfaces are electrically connected via the through electrode 110.

  With the above configuration, the surface of the through electrode 110 filled in the through hole 108 becomes flat. Thereby, an increase in contact resistance between the through electrode 110 and the wiring layer 130 can be avoided. Therefore, it is possible to provide the through electrode substrate 100 having excellent electrical characteristics and high reliability.

  In particular, when the substrate 102 is a glass substrate, it is necessary to form the through hole 108 having a larger hole diameter than that of the silicon substrate. Specifically, it is necessary to form the through hole 108 having a hole diameter of about 60 μm. As will be described later, it is difficult to completely fill the through electrode 110 in the through hole 108 having such a relatively large hole diameter.

  According to the present embodiment, by having such a configuration, the surface of the through electrode 100 filled in the through hole 108 becomes flat even if the glass substrate requires a hole diameter of about 60 μm or more. Thereby, an increase in contact resistance between the through electrode 100 and the wiring layer 130 can be avoided. Therefore, it is possible to provide the through electrode substrate 100 having excellent electrical characteristics and high reliability.

[Method of manufacturing through electrode substrate]
The manufacturing method of the through electrode substrate 100 according to the present embodiment will be described in detail with reference to FIGS. 4 to 7 are cross-sectional views for explaining a method of manufacturing the through electrode substrate 100 according to this embodiment.

  First, the substrate 102 is prepared. As the substrate 102, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a resin substrate, or the like can be used. As the semiconductor substrate, for example, a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate, or the like can be used. As the conductive substrate, for example, an aluminum substrate, a stainless steel substrate, or the like can be used. Moreover, these may be laminated.

  The thickness of the substrate 102 is not particularly limited, but for example, it is preferable to use the substrate 102 having a thickness of 100 μm to 800 μm. More preferably, the thickness is 200 μm or more and 500 μm or less. As the thickness of the substrate 102 decreases, the deflection of the substrate 102 increases. As a result, handling in the manufacturing process becomes difficult, and the substrate 102 is warped by internal stress such as a thin film formed on the substrate 102. Further, when the thickness of the substrate 102 is increased, the formation time of the through hole 108 is increased. As a result, the manufacturing process becomes longer and the manufacturing cost increases.

  Next, a through hole 108 is formed in the substrate 102 (FIG. 4A). Although there is no restriction | limiting in particular as a hole diameter of the through-hole 108, 60 micrometers or more may be sufficient. The planar shape of the through hole 108 is not limited to a circle, and may be various shapes as will be described later.

  The through-hole 108 is formed by forming a mask on the first surface 104 or the second surface 106 of the substrate 102, RIE (Reactive Ion Etching), DRIE (Deep RIE: Deep Reactive Ion Etching), etc. It can be formed by using dry etching, sandblasting, laser processing or the like.

  Next, a seed layer 112 is formed on the first surface 104 side of the substrate 102 (FIG. 4B). The seed layer 112 is formed using, for example, a sputtering method. The seed layer 112 is provided in the vicinity of the opening edge of the through hole 108 on the first surface 104 side so as to form a so-called lid plating. Therefore, the seed layer 112 is deposited on the first surface 104 of the substrate 102 and can be formed on the sidewall of the through hole 108. It is preferable not to adhere as much as possible. Therefore, it is preferable to use a long throw sputtering method with high directivity. In the present embodiment, a sputtering method is assumed as a method for forming the seed layer 112, but is not limited thereto, and for example, a vapor deposition method or an electroless plating method may be used.

  As a material for the seed layer 112, a conductive material having good adhesion to the base substrate 102 can be used. For example, it is possible to use titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta), nickel (Ni), chromium (Cr), aluminum (Al), these compounds, or alloys thereof. it can. In particular, when the plating layer deposited on the seed layer 112 includes copper (Cu), the seed layer 112 can use a material that suppresses diffusion of Cu. For example, titanium nitride (TiN), molybdenum nitride ( MoN), tantalum nitride (TaN), or the like may be used. Furthermore, these may be laminated. Here, the thickness of the seed layer 112 is not particularly limited, but can be appropriately selected within a range of, for example, 50 nm or more and 400 nm or less.

  Next, the through electrode 110 is filled into the through hole 108 by electrolytic plating. In the present embodiment, the electrolytic plating process is performed in two stages, a first stage and a second stage.

  First, as a first-stage electrolytic plating process, the substrate 102 is immersed in the first plating solution 114, and the first conductive layer 110a is grown by an electrolytic plating process that supplies current to the seed layer 112 (FIG. 5A). ). In the first-stage electrolytic plating process, the first conductive layer 110a is grown around the seed layer 112 until the through hole 108 is closed (FIG. 5B). That is, the first conductive layer 110a is grown until the cover plating is formed on the first surface 104 side.

  As a material of the first conductive layer 110a, a conductive material having good adhesion to the seed layer 112 and high electrical conductivity can be used. For example, a metal such as copper (Cu), gold (Au), silver (Ag), platinum (Pt), rhodium (Rh), tin (Sn), aluminum (Al), nickel (Ni), chromium (Cr) or the like It can select from the alloy etc. which used these. Furthermore, these may be laminated. In the present embodiment, Cu is used as the first conductive layer 110a.

  In the steps so far, the first conductive layer 110a is likely to be finished into a shape having a recess on the first surface 104 side. In particular, the larger the hole diameter of the through hole 108, the deeper the concave portion. In particular, when the hole diameter is about 60 μm or more, it is easy to finish so that the bottom of the concave portion is located between both planes of the substrate 102 as shown by the broken line in FIG.

  Even when the first conductive layer 110a is further grown by the first-stage plating process, when the first plating solution 114 assuming filling plating is used, the recesses are filled with the first conductive layer 110a due to its embedding characteristics. Becomes difficult.

  When the first surface 104 is exposed by a CMP (chemical vapor mechanical polishing) process or the like in a state in which such a recess remains, the recess of the first conductive layer 110a remains and does not become flat. In a later wiring formation step, for example, if an insulating layer or the like enters the recess, there is a concern that a conduction failure may occur.

  Therefore, in the present embodiment, as the second stage plating process, the substrate 102 is immersed in the second plating solution 116 having a higher embeddability than the first plating solution 114 (FIG. 6A), and the first conductive layer is formed. The second conductive layer 110b is grown so as to fill the concave portion of the first conductive layer 110a that closes the through hole 108 by the second plating process for supplying current to 110a. The concave portion is filled with the second conductive layer 110b by the second stage plating process (FIG. 6B). Further, the second conductive layer is grown, and the through electrode 110 filling the through hole 108 is formed. The material of the second conductive layer 110b may be the same material as the first conductive layer 110a or a different material. In the present embodiment, Cu is used as the second conductive layer 110b, similarly to the first conductive layer 110a.

  Here, the plating solution with high embedding refers to a plating solution having a stronger tendency to suppress plating deposition on the surface of the substrate and promote plating deposition on the recessed portion.

  As examples of the first plating solution 114 and the second plating solution 116 that can be used in the present embodiment, Table 1 summarizes their main components and concentrations.

  The first plating solution 114 and the second plating solution 116 both contain sulfuric acid, copper sulfate, and chlorine. Furthermore, a suppressor and an accelerator may be included as an additive. The essential difference between the first plating solution 114 and the second plating solution 116 is the concentration of sulfuric acid. The higher the sulfuric acid concentration of the plating solution, the higher the uniformity and the lower the embedding property. On the other hand, the lower the sulfuric acid concentration of the plating solution, the lower the uniformity and the higher the embedding property. The plating solution having a higher embeddability than the first plating solution 114 is a plating solution having a lower sulfuric acid concentration than the first plating solution 114. In addition, the second plating solution 116 is a plating solution that suppresses plating deposition on the surface of the substrate 102 and promotes plating deposition in the recessed portion by changing the type of additive and adjusting the concentration.

  Here, after at least a part of the through hole 108 is blocked, the first surface 104 may be shielded from the second plating solution 116 in order to prevent the growth of the second conductive layer 110b on the first surface 104 side. Good (FIG. 7A).

  With such a manufacturing method, the growth of the second conductive layer 110b on the surface of the through electrode substrate 100 can be minimized. Thereby, the polishing amount of the conductive layer to be removed by a subsequent CMP (Chemical Mechanical Polishing) process or the like can be minimized. Accordingly, the processing time is shortened, and the through electrode substrate 100 can be manufactured at a low cost.

  After the above steps, the first surface 104 side of the substrate 102 is polished until the first surface 104 of the substrate 102 is exposed (FIG. 7B). In the present embodiment, the seed layer 112, the first conductive layer 110a, and the second conductive layer 110b attached to the first surface 104 of the substrate 102 are removed by a CMP process or the like.

  At this stage, the exposed surfaces of the through electrodes 110 on the first surface 104 side and the second surface 106 side are finished flat. With respect to the surface of the through electrode 110 on the first surface 104 side, the first conductive layer 110a and the second conductive layer 110b are exposed. With respect to the surface of the through electrode 110 on the second surface 106 side, the second conductive layer 110b is exposed.

  In the above, the manufacturing method of the penetration electrode substrate 100 concerning this embodiment was explained. In the process of forming the conventional through electrode 110, the second stage plating process in this embodiment is not performed. In such a manufacturing process, when the hole diameter of the through hole 108 is about 60 μm or more, the recess near the opening edge is not filled, and the bottom of the recess remains while being located between both surfaces of the substrate. When polished in this state by CMP treatment or the like. Finished with the recess remaining on the surface of the through electrode. That is, the through electrode cannot completely fill the through hole due to the concave portion. If the process proceeds to a subsequent process in this state, there is a concern that, for example, in the process of forming the wiring layer 130, a conduction failure may occur due to an insulating layer entering the recess.

  In the above, the manufacturing method of the penetration electrode substrate 100 concerning this embodiment was explained. According to the method for manufacturing the through electrode substrate 100 according to the present embodiment, even if the glass substrate is required to have a hole diameter of about 60 μm or more, the surface of the through electrode 110 filled in the through hole 108 is prevented from being depressed. can do. As a result, the occurrence of electrical continuity failure can be suppressed. Therefore, the manufacturing yield can be improved and the through electrode substrate 100 with high reliability can be provided.

<Modification>
The configuration of the through electrode substrate 100 according to a modification of the present embodiment will be described with reference to the drawings. FIG. 8 is a diagram showing several examples of the planar shape of the through electrode 110 that can be manufactured in the through electrode substrate 100 according to this modification. According to the present invention, the planar shape of the through hole 108 is not limited to a circle, and the through electrode 110 can be filled in various shapes as exemplified in 108b to 108e. However, these illustrated shapes are merely examples, and are not limited thereto.

  A circle having a diameter of 60 μm is indicated by a dotted line inside each of the illustrated through holes 108a to 108e. That is, the through holes 108a to 108e may include a circle whose planar shape has a diameter of 60 μm.

  By having such a configuration, the surface of the through electrode 110 filled in the through hole becomes flat in the through holes of various shapes or sizes. Thereby, an increase in contact resistance between the through electrode 110 and the wiring layer 130 can be avoided. Therefore, it is possible to provide the through electrode substrate 100 having excellent electrical characteristics and high reliability.

Second Embodiment
In the present embodiment, a semiconductor device manufactured using the through electrode substrate 100 in the first embodiment will be described.

  FIG. 9 is a diagram illustrating the semiconductor device according to the present embodiment. In the semiconductor device 1000, three through electrode substrates 1310, 1320, and 1330 are stacked and connected to an LSI substrate 1400 on which a semiconductor element such as a DRAM is formed, for example. The through electrode substrate 1310 has connection terminals 1511 and 1512 formed by first wiring, second wiring, and the like. These through electrode substrates 1310, 1320, and 1330 may be through electrode substrates formed from substrates of different materials. The connection terminal 1512 is connected to the connection terminal 1500 of the LSI substrate 1400 by the bump 1610. The connection terminal 1511 is connected to the connection terminal 1522 of the through electrode substrate 1320 by the bump 1620. The connection terminals 1521 of the through electrode substrate 1320 and the connection terminals 1532 of the through electrode substrate 1330 are also connected by the bumps 1630. For the bumps 1610, 1620, and 1630, for example, a metal such as indium, copper, or gold is used.

  In addition, when laminating | stacking a through-electrode board | substrate, not only three layers but two layers may be sufficient, and also four or more layers may be sufficient. Further, the connection between the through-electrode substrate and another substrate is not limited to using bumps, and other bonding techniques such as eutectic bonding may be used. Alternatively, polyimide, epoxy resin, or the like may be applied and baked to bond the through electrode substrate and another substrate.

  FIG. 10 is a diagram illustrating another example of the semiconductor device according to the present embodiment. A semiconductor device 1000 illustrated in FIG. 11 includes semiconductor chips (LSI chips) 1410 and 1420 such as a MEMS device, a CPU, a memory, and the like, and a through electrode substrate 1300 that are stacked and connected to the LSI substrate 1400.

  A through electrode substrate 1300 is disposed between the semiconductor chip 1410 and the semiconductor chip 1420 and connected by bumps 1640 and 1650. A semiconductor chip 1410 is placed on the LSI substrate 1400, and the LSI substrate 1400 and the semiconductor chip 1420 are connected by a wire 1700. In this example, the through electrode substrate 1300 is used as an interposer for stacking a plurality of semiconductor chips and three-dimensionally mounting them, and manufacturing a multifunctional semiconductor device by stacking a plurality of semiconductor chips having different functions. can do. For example, by using the semiconductor chip 1410 as a three-axis acceleration sensor and the semiconductor chip 1420 as a two-axis magnetic sensor, a semiconductor device in which a five-axis motion sensor is realized by one module can be manufactured.

  When the semiconductor chip is a sensor formed by a MEMS device, the sensing result may be output as an analog signal. In this case, a low-pass filter, an amplifier, and the like may also be formed on the semiconductor chip or the through electrode substrate 1300.

  FIG. 11 is a diagram illustrating another example of the semiconductor device according to the present embodiment. Although the above two examples (FIGS. 9 and 10) are three-dimensional mounting, this example is an example applied to the combined mounting of two and three dimensions (sometimes referred to as 2.5 dimensions). . In the example shown in FIG. 11, six through electrode substrates 1310, 1320, 1330, 1340, 1350, and 1360 are stacked and connected to the LSI substrate 1400. However, all the through electrode substrates are not only laminated and arranged, but are also arranged side by side in the in-plane direction of the substrate. These through electrode substrates may be through electrode substrates formed from substrates of different materials.

  In the example of FIG. 11, the through electrode substrates 1310 and 1350 are connected to the LSI substrate 1400, the through electrode substrates 1320 and 1340 are connected to the through electrode substrate 1310, and the through electrode substrate 1330 is connected to the through electrode substrate 1320. The through electrode substrate 1360 is connected to the through electrode substrate 1350.

  The semiconductor device 1000 manufactured as described above includes various devices such as portable terminals (mobile phones, smartphones, notebook personal computers, etc.), information processing devices (desktop personal computers, servers, car navigations, etc.), home appliances, and the like. Installed in electrical devices.

  The through electrode substrate 100 and the electronic device having them according to the preferred embodiment of the present invention have been described above. However, these are merely examples, and the technical scope of the present invention is not limited thereto. Indeed, various modifications will be apparent to those skilled in the art without departing from the spirit of the invention as claimed in the claims. Therefore, it should be understood that these changes also belong to the technical scope of the present invention.

Through electrode substrate: 100, 200, 300
Substrate: 102
First side: 104
Second side: 106
Through hole: 108
Through electrode: 110
Seed layer: 112
First plating solution: 114
Second plating solution: 116
Wiring layer: 130
Semiconductor device: 1000
Through electrode substrate: 1300, 1310, 1320, 1330, 1340, 1350, 1360
LSI substrate: 1400
Semiconductor chip: 1410, 1420
Bump: 1640, 1650

Claims (8)

Forming a through hole in the substrate,
Forming a seed layer on the first surface of the substrate;
By immersing the substrate in a first plating solution and supplying a current to the seed layer, a first plating layer is grown around the seed layer until at least part of the through hole is blocked. Let
The substrate is immersed in a second plating solution having a higher embeddability than the first plating solution, and a second plating process for supplying current to the first plating layer is used to close the through hole. Growing the second plating layer so as to fill the recess,
A method of manufacturing a through electrode substrate, comprising polishing the first surface side until the first surface of the substrate is exposed.   2. The method of manufacturing a through electrode substrate according to claim 1, wherein the second plating solution has a sulfuric acid concentration lower than that of the first plating solution.   The first surface is shielded from the second plating solution in order to prevent growth of the second plating layer on the first surface side after at least a part of the through hole is closed. Item 2. A method for manufacturing a through electrode substrate according to Item 1.   2. The method for manufacturing a through electrode substrate according to claim 1, wherein the through hole can include a circle having a diameter of 60 μm in a planar shape.   The method for manufacturing a through electrode substrate according to claim 1, wherein the substrate is a glass substrate. A substrate having a through hole;
A first conductive layer filling a part of the through hole and having a recess on one opening edge side of the through hole;
A through electrode substrate comprising a second conductive layer filling the recess.   The through electrode substrate according to claim 6, wherein the through hole can include a circle having a diameter of 60 μm in a planar shape.   The through electrode substrate according to claim 6, wherein the substrate is a glass substrate.

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