JP2010098140A - Through electrode substrate, manufacturing method thereof, and semiconductor device using the through electrode substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a through electrode substrate wherein current loss in a conduction part making front and rear sides of a substrate conductive to each other is reduced, and a semiconductor device using the same. <P>SOLUTION: The through electrode substrate 100 includes the substrate 102 having a through hole 104 piercing through front and rear sides of the substrate and a conduction part 106 including a metal material filling the through hole 104, wherein the metal material of the conduction part 106 includes crystal particles having a particle size of ≥29 μm and an area-weighted average grain size of ≥13 μm. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a through electrode substrate provided with a through electrode penetrating the front and back of the substrate, a manufacturing method thereof, and a semiconductor device using the through electrode substrate. In this specification, a semiconductor device refers to all devices that can function using semiconductor characteristics, and a semiconductor integrated circuit and an electronic device are included in the scope of the semiconductor device.

In recent years, electronic devices have been increased in density and size, and LSI chips have been reduced to the same extent as semiconductor packages. Densification only by arranging LSI chips two-dimensionally is reaching its limit. Therefore, in order to increase the packaging density, it is necessary to divide LSI chips and stack them three-dimensionally. Further, in order to operate the entire semiconductor package in which LSI chips are stacked at high speed, it is necessary to bring the stacked circuits closer together and to shorten the wiring distance between the stacked circuits.

Accordingly, in order to meet the above requirements, a through electrode substrate having a conductive portion that conducts the front and back of the substrate as an interposer between LSI chips has been proposed (Patent Document 1). According to Patent Document 1, the through electrode substrate is formed by filling a through hole provided in the substrate with a conductive material (Cu) by electrolytic plating.
JP 2006-54307 A JP 2006-147971 A

When the through electrode substrate is used for connection between a plurality of LSI chips or between an LSI chip and a MEMS device, it is possible to ensure continuity in a conductive portion formed by electrolytic plating, and current loss is reduced. Less is required.

On the other hand, Patent Document 2 discloses a technique for reducing voids in the through electrode manufacturing process. However, in Patent Document 2, an approach to ensuring the conductivity of the conductive portion is studied, but no study is made regarding the current loss in the conductive portion.

Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a through electrode substrate in which a current loss is reduced in a conduction portion that conducts the front and back of the substrate, and a semiconductor device using the same.

According to one embodiment of the present invention, a substrate having a through hole penetrating the front and back, and a conductive portion filled in the through hole and including a metal material, the metal material of the conductive portion is a crystal grain There is provided a through electrode substrate including crystal grains having a diameter of 29 μm or more.

The metal material of the conductive portion preferably has an area-weighted average crystal grain size of 13 μm or more.

The cross section of the metal material of the conducting portion has an orientation rate of 21% or more expressed by the following formula (A) of the {101} plane detected by backscattered electron diffraction, and backscattered electron diffraction It is preferable that the orientation ratio represented by the following formula (B) of the {221} plane detected by is 11% or more.
Orientation ratio (%) = the sum of measurement points where the angle formed by the {101} plane and the cross-sectional surface of the conducting portion is within 8 ° / total number of measurement points (A)
Orientation ratio (%) = the sum of measurement points where the angle formed by the {221} plane and the cross-sectional surface of the conducting portion is within 8 ° / total number of measurement points (B)

The substrate may be made of silicon, and the conductive portion may be formed on at least an insulating layer provided on the substrate side.

It is preferable that the opening diameter of the through hole is 10 μm to 100 μm and the thickness of the substrate is 20 to 100 μm.

The opening diameter of the through hole is preferably 10 μm to 100 μm, and the thickness of the substrate is preferably 300 to 800 μm.

A plurality of the through electrode substrates may be stacked.

A semiconductor device may be configured by including at least one semiconductor chip provided with a connection terminal portion and connecting the connection terminal portion and a conduction portion of the through electrode substrate.

According to one embodiment of the present invention, a through hole penetrating front and back is formed in the substrate, an insulating film is formed on a surface of the substrate and the through hole, and at least one surface of the substrate and / or the through hole is formed. There is provided a method of manufacturing a through electrode substrate in which a metal material is filled in the through hole by an electrolytic plating method in which a seed film made of metal is formed in the hole and a pulse voltage is supplied to the seed film.

The electrolytic plating method may be performed by periodically applying a positive voltage and a negative voltage to the seed film.

ADVANTAGE OF THE INVENTION According to this invention, the through-electrode board | substrate which reduced the current loss in the conduction | electrical_connection part which conducts the front and back of a board | substrate, its manufacturing method, and a semiconductor device using the same can be provided.

Hereinafter, a through electrode substrate and a manufacturing method thereof according to the present invention will be described with reference to the drawings. However, the through electrode substrate of the present invention can be implemented in many different modes, and is not construed as being limited to the description of the embodiments and examples shown below. Note that in the drawings referred to in this embodiment mode and examples, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(1. Configuration of the through electrode substrate)
FIG. 1 is a cross-sectional view of a through electrode substrate 100 of the present invention according to this embodiment. The through electrode substrate 100 of the present invention according to this embodiment includes a through hole 104 penetrating the front and back of the substrate 102 serving as a core. A conduction portion 106 is formed inside the through hole 104. The substrate 102 is made of a semiconductor material such as silicon, and a through hole 104 is formed by a method such as etching, laser, or sandblasting, which will be described later. Although the thickness of the board | substrate 102 is 10-800 micrometers, for example, it is not limited to this. In FIG. 1, for convenience of explanation, only one through hole 104 is shown, but a plurality of through holes 104 are formed in the substrate 102, and a conduction portion 106 is formed in each through hole 104. May be. Preferably, a substrate having a thickness in the range of 300 to 800 μm or 20 to 100 μm may be appropriately selected according to the application.

In the present embodiment, an insulating film 108 for ensuring electrical insulation is provided on the inner wall of the through hole 104 and the surface of the substrate 102. The insulating film 108 is made of, for example, SiO ₂ and is formed by a thermal oxidation method, a CVD method, or the like. The thickness of the insulating film 108 is about 0.1 to 2 μm, and the thickness is not particularly limited as long as sufficient insulation can be secured.

In this embodiment, the opening diameter of the through hole 104 is about 10 to 100 μm. The opening diameter of the through hole 104 is not limited to this, and can be set as appropriate according to the use of the through electrode substrate 100 and the like.

In the present embodiment, the conductive portion 106 is a wiring that provides conduction between the front and back of the through electrode substrate 100 and is filled with a conductive material including a metal material. In the present embodiment, the conductive portion 106 is filled with a metal material by electrolytic plating as will be described later. As a metal material used for the conductive portion 106, for example, copper can be used.

In the through electrode substrate 100 of the present invention according to the present embodiment, the metal material of the conducting portion 106 includes crystal grains having a maximum crystal grain size of 29 μm or more, as will be described later. Further, in the through electrode substrate 100 of the present invention according to the present embodiment, the metal material of the conductive portion 106 includes crystal grains having an area-weighted average crystal grain size of 13 μm or more, as will be described later. In the through electrode substrate 100 of the present invention according to this embodiment, the current loss in the conductive portion 106 can be reduced by the above configuration.

Further, in the through electrode substrate 100 of the present invention according to the present embodiment, as will be described later, the cross-sectional area of the conducting part 106 is an angle formed with the surface of the conducting part cross section of the {101} plane detected by the backscattered electron diffraction method. Is 8% or less, and the ratio of the angle between the surface of the conducting part cross section of the {221} plane detected by the backscattered electron diffraction method is 8 degrees or less is 11% or more. Preferably there is. As described above, since the ratio of the crystal orientation in a specific direction is large, the current loss in the conductive portion 106 can be further reduced.

(2. Manufacturing method of through electrode substrate 100)
Here, with reference to FIG.2 and FIG.3, the manufacturing method of the penetration electrode substrate 100 of this invention which concerns on this embodiment is demonstrated.

(2-1. Manufacturing Method 1 of Through Electrode Substrate 100)
(1) Preparation of substrate 102 and drilling of through-hole 104 (FIG. 2A)
In this embodiment, a substrate 102 made of silicon is prepared. Although the thickness of the board | substrate 102 is not specifically limited, It is 300-800 micrometers. A mask (not shown) selected from a resist, a silicon oxide film, a silicon nitride film, a metal, or the like is formed on one surface side of the substrate 102, and then the substrate 102 is etched in the thickness direction through the mask and penetrated. Hole 104 is formed. As an etching method, an RIE method, a DRIE method, or the like can be used. Note that the through-hole 104 penetrating front and back with respect to the substrate 102 may be formed only by etching, or the through-hole 104 is formed by forming a bottomed hole in the substrate 102 and then polishing and opening it with a back grind. May be. The thickness of the substrate 102 may be reduced to 300 μm or less by polishing.

(2) Formation of the insulating film 108 (FIG. 2B)
An insulating film 108 is formed on the surface of the substrate 102. In this embodiment, the insulating film 108 is a silicon oxide film and is formed by a thermal oxidation method or a CVD method. As the insulating film 108, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a stacked film thereof, or the like may be used.

(3) Formation of seed layer (FIG. 2C)
A seed layer 110 is formed on at least one surface of the substrate 102. The seed layer 110 is composed of a Ti layer on the substrate 102 side, a Cu layer (hereinafter referred to as Cu / Ti layer), a Cu layer / TiN layer, or a Cu / Cr layer thereon. In the present embodiment, a Cu / Cr layer is used for the seed layer 110. A method for forming the seed layer 110 can be appropriately selected from PVD, sputtering, and the like. The metal material used for the seed layer 110 can be appropriately selected depending on the metal material of the conductive portion 106. The seed layer 110 becomes a seed part and a power feeding part for forming the conductive part 106 by electrolytic plating.

(4) Formation of conductive portion 106 (FIG. 2D)
Electric power is supplied to the seed layer 110 using an electrolytic plating method, and the through hole 104 is filled with a metal material. In the present embodiment, copper (Cu) is used as the metal material that fills the through hole 104. In this embodiment, as shown in FIG. 4 or FIG. 5, the through hole 104 is filled with a metal material by an electrolytic plating method that supplies current to the seed layer 110 in a pulsed manner. The pulse current supply method shown in FIG. 4 is a method of supplying a pulse current that does not reverse the polarity to the seed layer 110. The pulse current supply method shown in FIG. 5 is a method in which a pulse current whose polarity is periodically reversed is applied to the seed layer 110. The plating method by supplying a pulse current shown in FIG. 5 is called a PRC (Periodical Reversed Current) method. By periodically applying a positive voltage and a negative voltage to the seed layer 110, the current flowing through the seed layer 110 is constant. Forward (the state where the plating side, ie, the seed layer 110 side has a negative potential (a state where a positive current flows)) and the reverse (the state where the plating side, ie, the seed layer 110 side becomes a positive potential) This is one of the plating methods performed by switching the flowing state)), and is a preferred plating method. In the electroplating using the pulse current of the present embodiment, the applied voltage, supply current, current density, and pulse switching time (duty ratio) can be appropriately selected. Further, the applied voltage, current density, and pulse switching time (duty ratio) may be changed during the electrolytic plating. The current flowing through the seed layer 110 by supplying a pulse current flows between 0.5 and 1.5 A when a positive voltage is applied, and between −6 and −2 A when a negative voltage is applied. The current may flow.

Before supplying the pulse current, as shown in FIG. 6, a lid is formed on the bottom of the through hole 104 on the surface where the seed layer 110 is formed by an electrolytic plating method in which a constant direct current is supplied to the seed layer 110. A metal layer may be formed. As a metal material filling the through-hole 104, in addition to Cu, gold (Au), rhodium (Rh), silver (Ag), platinum (Pt), tin (Sn), aluminum (Al), nickel (Ni), A material selected and combined from metals such as chromium (Cr) and alloys thereof can be used.

(5) Removal of unnecessary parts (FIG. 2E)
By removing unnecessary portions of the seed layer 110 and the conductive portion 106 by etching or CMP (Chemical Mechanical Polishing), the conductive portion 106 is formed. Through the above process, the through electrode substrate 100 of the present invention according to the present embodiment can be obtained.

(2-2. Manufacturing method 2 of through electrode substrate)
Here, another example of the manufacturing method of the through electrode substrate 100 of the present invention according to this embodiment will be described. The same configuration as the manufacturing method 1 of the through electrode substrate 100 described above may not be described again. In addition, in the manufacturing method 2 of the through electrode substrate 100 of the present invention according to the present embodiment described here, the depth of the through hole is relatively shallow (for example, about 20 μm to 100 μm) or the thickness is 20 to 100 μm. It is often used when it is desired to obtain a through electrode substrate having a thin thickness.

(1) Preparation of substrate 102 and formation of holes (FIG. 3A)
A mask (not shown) selected from a resist, a silicon oxide film, a silicon nitride film, a metal, and the like is formed on one surface side of the substrate 102, and then the substrate 102 is etched in the thickness direction through the mask. A bottomed hole 112 that does not penetrate 102 is formed. As an etching method, an RIE method, a DRIE method, or the like can be used.

(2) Formation of the insulating film 108 (FIG. 3B)
An insulating film 108 is formed on the surface of the substrate 102.

(3) Formation of seed layer (FIG. 3C)
A seed layer 114 is formed on the surface of the substrate 102 over which the insulating film 108 is formed. The seed layer 114 is also formed inside the hole 112 as shown in FIG. The seed layer 114 is formed of a Cu layer / Ti layer or the like, similar to the seed layer 110 described above. As with the seed layer 110, the seed layer 114 serves as a seed portion and a power feeding portion for forming the conductive portion 106 by electrolytic plating. The seed layer 114 is formed by MOCVD, sputtering, vapor deposition, or the like.

(4) Formation of conductive portion 106 (FIG. 3D)
Power is supplied to the seed layer 114 using an electrolytic plating method, and the hole 112 is filled with a metal material. Also in the through electrode substrate manufacturing method 2 of the present embodiment, as in the through electrode substrate manufacturing method 1, as shown in FIG. 4 or FIG. 5, by an electroplating method for supplying current to the seed layer 110 in a pulsed manner, The through hole 112 is filled with a metal material. Before supplying the pulse current, a constant direct current may be supplied to the seed layer 110 as shown in FIG. In the present embodiment, copper (Cu) is used as the metal material filling the holes 112. As a metal material filled in the through hole 104, in addition to copper, gold (Au), rhodium (Rh), silver (Ag), platinum (Pt), tin (Sn), aluminum (Al), nickel (Ni), A material selected and combined from metals such as chromium (Cr) and alloys thereof can be used.

(5) Removal of unnecessary portions (FIG. 3E)
Unnecessary portions of the seed layer 114 and the conductive portion 106 are removed by etching or CMP. Further, the conductive portion 106 is formed by polishing the surface of the substrate 102 opposite to the side where the holes 112 are formed until the surface of the conductive portion 106 is exposed by back grinding. The thickness of the substrate 102 may be reduced by polishing. Through the above process, the through electrode substrate 100 of the present invention according to the present embodiment can be obtained.

Example 1
Hereinafter, examples of the through electrode substrate 100 of the present invention will be described. After the substrate 102 having a thickness of 650 μm is washed, a resist is applied to one surface side of the substrate 102, exposed and developed to form a mask (not shown). After that, the substrate 102 is etched in the thickness direction by the DRIE method through the mask to form a bottomed hole 112 of 430 μm (FIG. 2A). After removing the resist mask, the substrate 102 is polished to a thickness of 400 μm by back grinding.

After cleaning the substrate 102, a thermal oxide film having a thickness of 1 μm is formed on the surface of the substrate 102 by thermal oxidation. Thereafter, a silicon nitride film having a thickness of 200 nm is formed by LPCVD. These thermal oxide film and silicon nitride film form the insulating film 108 (FIG. 2B).

A seed layer 110 is formed by sequentially depositing Cr having a thickness of 30 nm and Cu having a thickness of 200 nm on one surface of the substrate 102 (FIG. 2C).

Thereafter, the substrate 102 is ashed. Next, power is supplied to the seed layer 110 using an electrolytic plating method by supplying a direct current shown in FIG. 6, and a lid-like metal layer is formed at the bottom of the through hole 104 on the surface where the seed layer 110 is formed. . In Example 1, a direct current having a current of 1.54 A and a current density of 1 A / dm ² was supplied, and then power was supplied to the seed layer 110 using an electrolytic plating method by applying a pulse voltage shown in FIG. The hole 104 is filled with Cu (FIG. 2D). The pulse switching time was such that a positive current was supplied for 80 msec and a negative current was supplied for 2 msec. When a positive current is supplied, a current of 1.05 A flows (current density 3 A / dm ² ), and when a negative current is supplied, a current of -4.2 A (current density −12 A / dm ² ) flows. .

When starting to fill Cu by the electrolytic plating method by supplying the pulse current shown in FIG. 5, a small current is supplied for the first hour or so, and when a positive current is supplied, a current of 0.35 A flows ( Current density 1 A / dm ² ), and when a negative current is supplied, a current of −1.4 A (current density −4 A / dm ² ) may flow.

After cleaning the substrate 102, unnecessary portions of the seed layer 110 and the conductive portion 106 are removed by CMP to form the conductive portion 106. Through the above process, the through electrode substrate 100 of the present invention according to this example was obtained.

(3. Analysis of crystal state by electron backscatter diffraction pattern (EBSD))
Here, referring to FIG. 7 and FIG. 8, a backscatter diffraction pattern (EBSD) used for analyzing the crystal grain size and crystal orientation state of the metal material of the conductive portion 106 according to the present embodiment. Will be described.

(3-1. Explanation of EBSD)
(A) Measurement of crystal orientation The crystal orientation of the cross section of the conducting portion 106 according to the present embodiment is measured by the EBSD method. FIG. 7 is a diagram illustrating the configuration of the EBSD device. FIG. 8 is a diagram for explaining the concept of sample measurement measured by an EBSD device. In measuring the crystal orientation of the cross section of the conducting portion 106 according to the present embodiment, adjustment is made so that the electron beam 212 is irradiated to the cross section of the penetrating portion 106.

The EBSD device 200 is a technique in which a dedicated detector 204 is provided in a scanning electron microscope (SEM) 202 and the crystal orientation is analyzed from backscattered electrons of primary electrons. Specifically, when an electron beam 212 emitted from the electron gun 210 is incident (irradiated) on the sample 208 having a crystal structure placed on the sample stage 206 in the sample chamber 205 through the mirror body 214, the sample is irradiated. Inelastic scattering occurs at 208 and backscattered electrons 216 are generated. Among them, a linear pattern (generally called a Kikuchi image) peculiar to the crystal orientation by Bragg diffraction is also observed in the sample 208. The backscattered electrons 216 are detected by the detector 204 of the SEM 202 through the screen 218. Then, the crystal orientation of the sample 208 can be obtained by analyzing the detected Kikuchi image.

In the case of a polycrystalline structure in which each crystal grain has a different crystal orientation, the orientation analysis is repeated while moving the position of the electron beam 212 applied to the sample 208 (mapping measurement), whereby the planar sample 208 is obtained. Information on crystal orientation or orientation can be obtained. When all the crystal orientations are determined by the mapping measurement, the crystal orientation state with respect to the film on the sample 208 can be statistically displayed. Note that a reverse pole figure (an example of a reverse pole figure is shown in FIG. 12) is often used as a diagram for displaying the orientation distribution of a crystal body having a polycrystalline structure. From the reverse pole point, a specific surface of the measurement sample is Information on which lattice plane is preferentially oriented can be obtained.

By mapping measurement and inverse pole figure, for a specific index ({100}, {110}, {111}, etc.) on each lattice plane, how much crystal grains are gathered in the vicinity of the index is quantified By doing so, it becomes easier to image the existence ratio of each orientation. Therefore, in the inverse pole figure, the following formula (1) is obtained as the ratio of each of the total number of points existing in the range (allowable value) where the deviation angle from each index of each lattice plane is 8 ° or less. Can be shown. Here, the allowable value is set to 8 ° because the crystal orientation indicated by the crystal grains is expected to fluctuate.

Orientation rate (%) =
Total number of measurement points / total number of measurement points where the angle between the lattice plane and the film surface is within the allowable range (8 ° or less)
... (1)

(B) Measurement of crystal grain size The crystal grain size of the metal material constituting the conductive portion 106 of the through electrode substrate 100 of the present invention according to this embodiment is measured by the EBSD method. In the case of a crystal structure in which each crystal grain size is different, the crystal grain size measurement is repeated while moving the position of the electron beam irradiated to the sample 208 (mapping measurement), whereby the crystal grain size of the planar sample 208 is changed. Information can be obtained. The area (A) of the crystal grains is calculated by multiplying the number (N) of crystal grains by the area of the measurement point determined by the measurement step size (s). In the EBSD measurement, the measurement point is expressed as a hexagon, and the area (A) of the crystal grains can be expressed by the following formula (2).

A = N × √3 / (2s ² ) (2)

The crystal grain size (D) is calculated as the diameter of a circle having an area equal to the crystal grain area (A). The crystal grain size (D) can be expressed by the following formula (3).

D = (4A / π) ^1/2 (where π is the circumference) (3)

“Crystal orientation” and “crystal grain size” defined in the present specification refer to values measured as described above. Further, in the measurement of the crystal grain size, it is assumed that edge grains are included.

Next, the results of EBSD measurement of the metal material forming the conductive portion 106 of the through electrode substrate 100 of the present invention according to Example 1 and the metal material forming the conductive portion of the through electrode substrate according to Comparative Examples 1 and 2 will be described. . Here, a measurement sample was produced by a so-called ion polishing method in which a cross section of a metal material constituting each conductive portion was processed with argon ions. Moreover, the measurement points in the EBSD measurement are each around the central part in the depth direction of the conduction part.

FIG. 9 is an area-weighted crystal grain size distribution diagram of the metal material crystal constituting the conducting portion 106 of the through electrode substrate 100 of the present invention according to the first embodiment. The maximum value and the average value of the crystal grain sizes constituting the conducting portion 106 can be calculated by a histogram with the crystal grain size (D) on the horizontal axis and the area ratio (R _s ) on the vertical axis.

Here, the area ratio R _s (ratio including the crystal grain size (area weighting)) can be expressed by the following formula (4) using the area (S _m ) of the measurement region.

R _s = A × (N / S _m ) (4)

The horizontal axis of the histogram shown in FIG. 9 indicates the value (D) of the crystal grain size, and the vertical axis (area fraction) indicates the ratio including the crystal grains of that value by area weighting. For example, 0.15 on the vertical axis in FIG. 9 means a ratio of 15%. Then, by multiplying each crystal grain size (D) by the product of the ratio (R _s ), the area-weighted average crystal grain size (D _s ) is determined as in the following formula (5).

D _s = Σ {R _s * D} (5)

In the present embodiment, in the measurement of the crystal grain size, since the measurement region is limited (in this embodiment, a region of 50 μm × 150 μm), the above-mentioned area region is cut out from the desired region and observed. In this specification, the crystal grain size is a value including the crystal grain (Grain) included in the edge (Edge) of the measurement region. In addition, since the analysis result includes an error, the rounded down numerical value is used without considering the decimal point.

The measurement conditions are as follows.
Used analyzer SEM JSM-7000F made by JEOL
EBSD TSL OIM Software Ver. 4.6
Observation condition EBSD measurement
Acceleration voltage 25kV
Sample tilt angle 70 °
Measurement step 0.3μm

The maximum particle size of the metal material of the conductive portion 106 of the through electrode substrate 100 of the present invention according to Example 1 was 29 μm, and the average particle size (area weighting) was 13 μm. As a result of the evaluation of the transmission characteristics in the high frequency region, it was confirmed that the current loss of the conductive portion 106 of the through electrode substrate 100 of the present invention according to Example 1 was small, and the conductive portion 106 had excellent electrical characteristics and superiority. It was.

On the other hand, FIG. 10 shows an area weighted crystal grain size distribution diagram of a metal material crystal constituting the conductive portion of the through electrode substrate according to Comparative Example 1 (details of the process will be described later). The maximum particle size of the metal material constituting the conductive portion of the through electrode substrate according to Comparative Example 1 was 10 μm, and the average particle size (area weighting) was 2 μm. The current loss of the conduction part 106 of the through electrode substrate according to Comparative Example 1 was high, and the electrical characteristics of the conduction part were poor.

In addition, FIG. 11 shows an area weighted crystal grain size distribution diagram of the metal material crystal constituting the conductive portion of the through electrode substrate according to Comparative Example 2 (details of the process will be described later). The maximum particle size of the metal material constituting the conducting portion of the through electrode substrate according to Comparative Example 2 was 11 μm, and the average particle size (area weighting) was 2 μm. The current loss of the conduction part 106 of the through electrode substrate according to Comparative Example 2 was high, and the electrical characteristics of the conduction part were poor.

FIG. 12 is an example of a reverse pole figure of the conduction part 106 of the through electrode substrate 100 of the present invention according to Example 1 obtained by EBSD. The measurement points in the mapping are plotted in a fan-shaped frame called a standard triangle. The degree of orientation is shown as a contour map.

13A, 13B, and 13C are crystal orientation maps obtained by mapping measurement and reverse pole figure of the conductive portion 106 of the through electrode substrate 100 of the present invention according to Example 1. FIG. As shown in FIG. 14, from the obtained EBSD pattern, not only the crystal orientation map in the ND (Normal Direction) direction (Z-axis direction) but also the TD (Transverse Direction) direction (Y-axis direction), RD ( A crystal orientation map in the Reference Direction) direction (X-axis direction) can be obtained. In this embodiment, the direction perpendicular to the substrate surface is the ND direction (Z-axis direction), and the direction parallel to the substrate surface is the TD direction (Y-axis direction) and RD direction (X-axis direction) (however, the TD direction and RD direction). Directions are perpendicular to each other). 13A, 13B, and 13C are crystal orientation maps in the ND direction, the TD direction, and the RD direction, respectively. In the crystal orientation map in the ND axis direction of the conductive portion 106 of Example 1, the orientation ratio according to the above formula (1) is 21% for the orientation having the {101} plane, 1% for the orientation having the {111} plane, { The orientation having the 001} plane was 0%, the orientation having the {221} plane was 11%, and the orientation having the {511} plane was 1%.

On the other hand, FIG. 15A, FIG. 15B, and FIG. 15C are crystal orientation maps by mapping measurement and reverse pole figure of the conduction | electrical_connection part of the penetration electrode board | substrate which concerns on the comparative example 1. FIG. 15A, 15B, and 15C are crystal orientation maps in the ND direction, the TD direction, and the RD direction, respectively. In the crystal orientation map in the ND axis direction of the conductive portion of Comparative Example 1, the orientation ratio according to the above-described formula (1) is 14% for the orientation having the {101} plane, 2% for the orientation having the {111} plane, {001 } Orientation having a {plane} plane was 1%, orientation having a {221} plane was 14%, and orientation having a {511} plane was 3%.

16A, FIG. 16B, and FIG. 16C are crystal orientation maps obtained by mapping measurement and reverse pole figure of the conduction part of the through electrode substrate according to Comparative Example 2. 15A, 15B, and 15C are crystal orientation maps in the ND direction, the TD direction, and the RD direction, respectively. In the crystal orientation map in the ND axis direction of the conductive portion of Comparative Example 2, the orientation ratio according to the above-described formula (1) is 6% for the orientation having the {101} plane, 2% for the orientation having the {111} plane, {001 } The orientation having a plane is 1%, the orientation having a {221} plane is 22%, and the orientation having a {511} plane is 2%.

Here, when attention is paid to the maximum particle size, the average particle size, the orientation rate having a {101} plane, and the orientation rate having a {221} plane in Example 1, Comparative Example 1 and Comparative Example 2, they are shown in the following table. be able to.

From the above results, it can be seen that when the maximum particle size of the conductive portion 106 of the through electrode substrate 100 is 29 μm or more, the current loss is small and the conductive portion 106 has excellent electrical characteristics. This is considered to be because when the metal particle size of the conductive portion 106 of the through electrode substrate 100 is large, the current loss is small and the resistance is small. Moreover, when the average particle diameter (area weighting) of the conduction | electrical_connection part 106 of the penetration electrode substrate 100 is 13 micrometers or more, it turns out that a current loss is small and the conduction | electrical_connection part 106 has the outstanding electrical property. Further, when the orientation ratio of the {101} plane detected by the backscattered electron diffraction method of the conductive portion 106 of the through electrode substrate 100 is 21% or more and the orientation ratio of the {221} plane is 11% or more, It can be seen that the loss is small and the conductive portion 106 has excellent electrical characteristics.

This is presumably because the metal material filled in the through-holes of the through-electrode substrate of the present invention has a large orientation ratio of metal crystals in the direction in which current flows and few crystal grain boundaries. In the method for manufacturing a through electrode substrate of the present invention, a plated metal layer is grown in one direction of the through hole. Therefore, a crystal having a high crystal orientation ratio along the through-hole direction is formed.

In an ideal state, the metal crystals are all oriented in the direction in which the current flows and there are no crystal grain boundaries. It is desirable that all are oriented in {001} in the ND direction (Z-axis direction) of EBSD. The {101} orientation is also oriented in the direction in which current flows, and is an important orientation plane following the {001} plane in terms of the ease of current flow. The higher the {001} or {101} orientation ratio, the better the electrical flow between the upper and lower sides of the through hole, which is desirable. In general, polycrystals are mostly in a randomly oriented state, but the through holes of the through electrode substrate of the present invention have a high orientation ratio of {101} planes close to the horizontal in the direction of current flow. It can be seen that there is an effect of reducing the current loss as compared with.

Hereinafter, Comparative Examples 1 and 2 described above will be described.
(Comparative Example 1)
The process before filling the through hole with the metal material is the same as that of the first embodiment. After the seed layer is formed on the substrate, the direct current shown in FIG. 6 is supplied to the seed layer using an electrolytic plating method, and the conductive portion is filled with a metal material. The current at this time was 1.54 (current density 1 A / dm ² ). Subsequent steps were the same as in Example 1.

(Comparative Example 2)
About the process before filling the through hole with the metal material, 2-2. After a seed layer is formed on the same substrate as in the through electrode substrate manufacturing method 2, a direct current shown in FIG. 6 is supplied to the seed layer using an electrolytic plating method, and a conductive material is filled with a metal material. The current at this time was 1.54 A (current density 1 A / dm ² ). Subsequent steps were the same as in Example 1.

(Embodiment 2)
In the second embodiment, an example of a semiconductor device in which LSI chips are stacked on the through electrode substrate 100 of the present invention according to the first embodiment and a semiconductor in which a plurality of through electrode substrates 100 of the present invention according to the first embodiment are stacked. An example of the apparatus will be described. The configuration and manufacturing method similar to those of the first embodiment will not be described again here.

Referring to FIGS. 17A and 17B. FIG. 17A shows a semiconductor device according to the present embodiment in which three through electrode substrates 100 according to the present invention according to the first embodiment are stacked. A semiconductor element such as a DRAM is formed on the through electrode substrate 100. The three through electrode substrates 100 are stacked and connected to each other through bumps 302. The through electrode substrate 100 plays a role as an interposer for electrically connecting the DRAMs formed therein. The through electrode substrate 100 laminated in three layers is connected to the LSI substrate 304 via the bumps 302. Note that the number of through electrode substrates 100 to be stacked is not limited to three layers. A metal such as In (indium), Cu, or Au can be used for the bump 304. Further, for bonding between the through electrode substrates 100, a resin such as polyimide or BCB (benzocyclobutene) may be mainly used for application and baking to bond them. Moreover, you may use an epoxy resin for joining of the penetration electrode substrates 100. Further, for the bonding between the through electrode substrates 100, bonding by plasma activation, eutectic bonding, or the like may be used.

When the through electrode substrate 100 of the present invention is stacked as in the present embodiment, the resistance of the conductive portion 106 (through hole) of the through electrode substrate 100 of the present invention is Ri, and the through electrode substrate 100 of the present invention is stacked and connected. When the number of stacked layers is N, the resistance of the entire conductive portion 106 (through hole) connected in series is N × Ri, and the resistance of the conductive portion 106 (through hole) can be reduced.

FIG. 17B shows an example of a semiconductor device having a through electrode substrate 100 on which LSI chips (semiconductor chips) 306-1 and 306-2 such as a MEMS device, a CPU, and a memory are mounted. Electrode pads 308-1 and 308-2, which are connection terminals of the LSI chips 306-1 and 306-2, are electrically connected to the conductive portion 106 of the through electrode substrate 100 via bumps 304, respectively. The through electrode substrate 100 on which the LSI chips 306-1 and 306-2 are mounted is mounted on the LSI substrate 306, and the LSI substrate 306 and the LSI chip 306-1 are connected by wire bonding. For example, by using the LSI chip 306-1 as a 3-axis acceleration sensor and the LSI chip 306-2 as a 2-axis magnetic sensor, a 5-axis motion sensor can be realized with one module. As described above, the through electrode substrate 100 according to the first embodiment of the present invention can be used as an interposer for three-dimensionally mounting a plurality of LSI chips.
(Embodiment 3)
In the third embodiment, a case where a MEMS device is used as an LSI chip mounted on the through electrode substrate of the first and second embodiments will be described. In this embodiment, the MEMS device will be described by taking the physical quantity sensor 302-1 as an example.

Hereinafter, a processing circuit for processing an acceleration displacement signal detected by the physical quantity sensor 302-1 will be described.

<Processing circuit>
A configuration example of each processing circuit that processes a displacement signal of acceleration detected by the physical quantity sensor 302-1 will be described with reference to FIG.

FIG. 18 is a diagram illustrating a circuit configuration of an acceleration processing circuit 400 that processes an acceleration displacement signal detected by the physical quantity sensor 302-1. In this case, the physical quantity sensor is a piezoresistive acceleration sensor. In FIG. 18, the acceleration processing circuit 400 includes an amplifier circuit 401, sample and hold circuits (S / H) 402 to 404, an output resistor Rout, and capacitors Cx, Cy, and Cz. The X-axis output, Y-axis output, and Z-axis output in the figure are displacement signals in the X-axis direction, Y-axis direction, and Z-axis direction that are output from the physical quantity sensor 302-1 according to the applied acceleration. is there. The output resistor Rout and the capacitors Cx, Cy, Cz function as a low-pass filter that allows a frequency component corresponding to the acceleration signal to pass.

The amplification circuit 401 amplifies each displacement signal (capacitance change) in the X-axis direction, the Y-axis direction, and the Z-axis direction output from the physical quantity sensor 302-1 according to the applied acceleration at a predetermined amplification factor. Output to the sample hold circuits 402 to 404 respectively. The sample hold circuit 402 samples / holds the X axis direction displacement signal amplified by the amplifier circuit 401 at a predetermined timing, and outputs an X direction acceleration detection signal Xout via the output resistor Rout and the capacitor Cx. The sample hold circuit 403 samples / holds the Y-axis direction displacement signal amplified by the amplifier circuit 401 at a predetermined timing, and outputs a Y-direction acceleration detection signal Yout through the output resistor Rout and the capacitor Cy. The sample hold circuit 404 samples / holds the Z-axis direction displacement signal amplified by the amplifier circuit 401 at a predetermined timing, and outputs an acceleration detection signal Zout in the Z direction via the output resistor Rout and the capacitor Cz.

The through electrode substrate 100 of the present invention or the stacked through electrode substrate 300 of the present invention on which the physical quantity sensor 302-1 and the processing circuit 400 are mounted is mounted as a sensor module on a portable information terminal, a mobile phone, or the like. FIG. 19 shows an example of a portable information terminal 500 that is an example of a semiconductor device on which the through electrode substrate 100 of the present invention on which the physical quantity sensor 302-1 and the processing circuit 400 are mounted, or the stacked through electrode substrate 300 of the present invention is mounted. FIG. In FIG. 19, the portable information terminal 500 includes a housing 501, a display unit 502, and a keyboard unit 503. The sensor module is mounted inside the keyboard unit 502. The portable information terminal 500 has a function of storing various programs therein and executing communication processing, information processing, and the like by the various programs. In this portable information terminal 500, for example, the acceleration at the time of falling is detected by using the acceleration and the angular velocity detected by the sensor module in which the physical quantity sensor 302-1 and the processing circuit 400 are mounted in the application program. A function such as turning off the power can be added.

By mounting the sensor module on which the physical quantity sensor 302-1 and the processing circuit 400 are mounted on the mobile terminal as described above, new functions can be realized, and the convenience and reliability of the mobile terminal can be improved. It becomes possible to improve.

It is sectional drawing of the penetration electrode substrate 100 of this invention which concerns on one Embodiment. It is a figure explaining the manufacturing process of the penetration electrode substrate 100 of the present invention concerning one embodiment. It is a figure explaining the manufacturing process of the penetration electrode substrate 100 of the present invention concerning one embodiment. It is a figure explaining the pulse voltage used for the electroplating for filling the penetration part 106 of the penetration electrode substrate 100 of the present invention concerning one embodiment with a metal material. It is a figure explaining the pulse voltage used for the electroplating for filling the penetration part 106 of the penetration electrode substrate 100 of the present invention concerning one embodiment with a metal material. It is a figure explaining the DC voltage used for the electroplating for filling the penetration part 106 of the penetration electrode substrate 100 of the present invention concerning one embodiment with a metal material. It is a figure explaining the structure of an EBSD apparatus. It is a figure explaining the concept of the sample measurement measured by EBSD. FIG. 3 is an area weighted crystal grain size distribution diagram of the metal material of the through-hole portion 106 of the through-electrode substrate 100 of the present invention related to Example 1. 6 is an area weighted crystal grain size distribution diagram of a metal material in a through portion of a through electrode substrate according to Comparative Example 1. FIG. 6 is an area weighted crystal grain size distribution diagram of a metal material in a through portion of a through electrode substrate according to Comparative Example 2. FIG. It is an example of a reverse pole figure measured by EBSD. It is a crystal orientation map (ND direction) by the mapping measurement of the conduction | electrical_connection part 106 of the penetration electrode substrate 100 of this invention which concerns on Example 1, and a reverse pole figure. It is a crystal orientation map by the mapping measurement and reverse pole figure of the conduction | electrical_connection part 106 of the penetration electrode substrate 100 of this invention which concerns on Example 1 (TD direction). It is a crystal orientation map (RD direction) by the mapping measurement of the conduction | electrical_connection part 106 of the penetration electrode substrate 100 of this invention which concerns on Example 1, and a reverse pole figure. It is explanatory drawing of the crystal orientation map of ND (Normal Direction) direction (Z-axis direction), TD (Transverse Direction) direction (Y-axis direction), and RD (Reference Direction) direction (X-axis direction) in an EBSD pattern. It is a crystal orientation map by the mapping measurement and reverse pole figure of the conduction | electrical_connection part of the penetration electrode board | substrate which concerns on the comparative example 1 (ND direction). It is a crystal orientation map by the mapping measurement and reverse pole figure of the conduction | electrical_connection part of the penetration electrode substrate which concerns on the comparative example 1 (TD direction). It is a crystal orientation map by the mapping measurement and reverse pole figure of the conduction | electrical_connection part of the penetration electrode substrate which concerns on the comparative example 1 (RD direction). It is a crystal orientation map by the mapping measurement and reverse pole figure of the conduction | electrical_connection part of the penetration electrode substrate which concerns on the comparative example 2 (ND direction). It is a crystal orientation map by the mapping measurement and reverse pole figure of the conduction | electrical_connection part of the penetration electrode substrate which concerns on the comparative example 2 (TD direction). It is a crystal orientation map by the mapping measurement and reverse pole figure of the conduction | electrical_connection part of the penetration electrode substrate which concerns on the comparative example 2 (RD direction). FIG. 4 is a cross-sectional view for explaining a semiconductor device in which LSI chips are stacked on a through electrode substrate 100 according to the present invention and a stacked through electrode substrate 300 in which the through electrode substrate 100 according to the present invention is stacked. It is a figure which shows an example of the acceleration process circuit which processes the displacement signal of the acceleration detected by a physical quantity sensor. It is a figure which shows an example of the mobile terminal which mounted the sensor module.

Explanation of symbols

100: Through electrode substrate 102: Substrate 104: Through hole 106: Conductive portion 108: Insulating film 110: Seed layer 302: Bump 304, 306: LSI substrates 306-1 and 306-2: Chips 308-1 and 308-2: Electrode pad

Claims (10)

A substrate having a through-hole penetrating the front and back;
A conductive portion filled in the through-hole and containing a metal material;
With
The through electrode substrate, wherein the metal material of the conductive portion includes crystal grains having a crystal grain size of 29 μm or more. 2. The through electrode substrate according to claim 1, wherein the metal material of the conductive portion has an area-weighted average crystal grain size of 13 μm or more. The cross section of the metal material of the conducting portion has an orientation rate of 21% or more expressed by the following formula (A) of the {101} plane detected by backscattered electron diffraction, and backscattered electron diffraction 3. The through electrode substrate according to claim 1, wherein an orientation rate represented by the following formula (B) of the {221} plane detected by: is 11% or more.
Orientation ratio (%) = the sum of measurement points where the angle formed by the {101} plane and the cross-sectional surface of the conducting portion is within 8 ° / total number of measurement points (A)
Orientation ratio (%) = the sum of measurement points where the angle formed by the {221} plane and the cross-sectional surface of the conducting portion is within 8 ° / total number of measurement points (B) The substrate is made of silicon;
4. The through electrode substrate according to claim 1, wherein the conducting portion is formed on at least an insulating layer provided on the substrate side. 5.   5. The through electrode substrate according to claim 1, wherein the through hole has an opening diameter of 10 μm to 100 μm and a thickness of the substrate of 20 to 100 μm.   5. The through electrode substrate according to claim 1, wherein an opening diameter of the through hole is 10 μm to 100 μm, and a thickness of the substrate is 300 to 800 μm.   7. A semiconductor device comprising a plurality of through electrode substrates according to claim 1, wherein the plurality of through electrode substrates are stacked. Including at least one semiconductor chip having a connection terminal portion;
The semiconductor device comprised by connecting the said connection terminal part and the conduction | electrical_connection part of the penetration electrode substrate as described in any one of Claims 1 thru | or 7. Form a through-hole that penetrates the front and back of the substrate,
Forming an insulating film on the surface of the substrate and the through hole;
Forming a metal seed film on at least one of the substrates and / or the through hole;
A method of manufacturing a through electrode substrate, wherein the through hole is filled with a metal material by an electrolytic plating method for supplying a pulse current to the seed film. The method of manufacturing a through electrode substrate according to claim 9, wherein the electrolytic plating method is performed by periodically applying a positive voltage and a negative voltage to the seed film.