JP2017098307A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an art to relax an electric field of a JFET gate structure on a drain side in a semiconductor device having the JFET gate structure.SOLUTION: A nitride semiconductor device 1 comprises a gate electrode 36 contacting a p type nitride semiconductor layer 18. The gate electrode 36 contacts part of a lateral face 18Sa of the p type nitride semiconductor layer 18 on a drain side at a part adjacent to the lateral face 18Sa of the p type nitride semiconductor layer 18 on the drain side and faces an electron supply layer 16c via a thin insulation film part 22a of the insulation film 22.SELECTED DRAWING: Figure 2

Description

  The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

  A semiconductor device including a semiconductor stacked body in which an electron transit layer and an electron supply layer are stacked has been developed. A semiconductor device uses a two-dimensional electron gas layer formed in the vicinity of a heterojunction surface between an electron transit layer and an electron supply layer as a channel. In a semiconductor device, a gate electrode is provided between a drain electrode and a source electrode, and the amount of current flowing between the drain electrode and the source electrode is controlled in accordance with the potential of the gate electrode.

  In this type of semiconductor device, a JFET (Junction Field Effect) type gate structure technology has been developed in which a p-type semiconductor layer is interposed between a gate electrode and an electron supply layer. In a semiconductor device having a JFET type gate structure, when the gate electrode is grounded, a depletion layer extending from the p type semiconductor layer depletes electrons in the two-dimensional electron gas layer below the p type semiconductor layer. On the other hand, when a positive potential is applied to the gate electrode, the depletion layer shrinks, a two-dimensional electron gas layer is formed below the p-type semiconductor layer, and the drain electrode and the source electrode are conducted through the two-dimensional electron gas layer. To do. Thus, a semiconductor device having a JFET type gate structure can operate normally off.

  In a semiconductor device having such a JFET type gate structure, electric field concentration on the drain side of the JFET type gate structure is a problem. The electric field has the maximum intensity in the vicinity of the drain-side end portion of the junction surface between the p-type semiconductor layer and the electron supply layer. Patent Document 1 discloses a technique of providing a field plate to alleviate such electric field concentration. The field plate extends from the gate electrode toward the drain electrode, and faces the electron supply layer through an insulating film coated on the electron supply layer. Such a field plate can disperse the peak of electric field concentration and reduce the maximum strength of the electric field.

JP 2012-33679 A (in particular, FIG. 1)

  In the semiconductor device disclosed in Patent Document 1, the insulating film is formed thick in a portion adjacent to the side surface on the drain side of the p-type semiconductor layer. This is for the following reason. In a semiconductor device having a JFET type gate structure, after patterning a p-type semiconductor layer on an electron supply layer, an insulating film is formed so as to cover the p-type semiconductor layer, and one of the insulating films covering the p-type semiconductor layer is formed. The portion is removed to expose a part of the upper surface of the p-type semiconductor layer, and a gate electrode is formed on the exposed portion. For this reason, in the part adjacent to the side surface on the drain side of the p-type semiconductor layer, the thickness of the insulating film is increased depending on the thickness of the p-type semiconductor layer.

  For this reason, in the semiconductor device disclosed in Patent Document 1, the distance between the field plate and the electron supply layer is long in the portion adjacent to the side surface on the drain side of the p-type semiconductor layer. As a result, the semiconductor device disclosed in Patent Document 1 has a problem that the field plate effect is not sufficiently exhibited, and the electric field on the drain side of the JFET type gate structure is high. The present specification provides a technique for relaxing an electric field on the drain side of a JFET type gate structure in a semiconductor device having a JFET type gate structure.

  The semiconductor device disclosed in this specification includes an electron transit layer, an electron supply layer heterojunction with the electron transit layer, a drain electrode on the electron supply layer, a source electrode on the electron supply layer at a position away from the drain electrode, A p-type semiconductor layer on the electron supply layer at a position between the drain electrode and the source electrode, an insulating film on the electron supply layer at a position between the p-type semiconductor layer and the drain electrode, and a p-type semiconductor layer A gate electrode is provided. The insulating film has a thin insulating film portion thinner than the thickness of the p-type semiconductor layer. The thin insulating film portion is in contact with the side surface on the drain side of the p-type semiconductor layer. The gate electrode is in contact with the side surface on the drain side of the p-type semiconductor layer and faces the electron supply layer through the thin insulating film portion.

  In the semiconductor device of the above embodiment, in the portion adjacent to the side surface on the drain side of the p-type semiconductor layer, the electron supply layer is interposed via the thin insulating film portion of the insulating film whose gate electrode is thinner than the thickness of the p-type semiconductor layer. Opposite to. For this reason, the distance between the gate electrode and the electron supply layer is short in the portion adjacent to the side surface on the drain side of the p-type semiconductor layer, and the electric field on the drain side of the JFET type gate structure is relaxed.

  A manufacturing method of a semiconductor device disclosed in this specification includes a step of forming a p-type semiconductor layer, a step of forming an insulating film, a step of removing a part of the insulating film, and a step of forming a gate electrode. In the step of forming the p-type semiconductor layer, the p-type semiconductor layer located between the formation position of the drain electrode and the formation position of the source electrode is formed on the electron supply layer that is heterojunction with the electron transit layer. In the step of forming the insulating film, the insulating film is formed on the electron supply layer so as to cover the p-type semiconductor layer. In the step of removing a part of the insulating film, a part of the insulating film is removed so that at least a part of the side surface on the drain side of the p-type semiconductor layer is exposed and a part of the insulating film remains on the electron supply layer. To do. In the step of forming the gate electrode, a gate electrode that is in contact with a part of the side surface on the drain side of the p-type semiconductor layer and faces the electron supply layer through the insulating film is formed.

  According to the above manufacturing method, the semiconductor device in which the gate electrode faces the electron supply layer through the insulating film thinner than the thickness of the p-type semiconductor layer in the portion adjacent to the side surface on the drain side of the p-type semiconductor layer Is manufactured.

The main part sectional drawing of the nitride semiconductor device of an Example is shown typically, and distribution of the electric field strength between the drain electrode and source electrode when a nitride semiconductor device is OFF is shown. The principal part expanded sectional view of the JFET type gate structure of the nitride semiconductor device shown in FIG. 1 is shown typically. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1. FIG. 2 schematically shows a cross-sectional view of a main part in one process for manufacturing the nitride semiconductor device shown in FIG. 1.

  As shown in FIG. 1, the nitride semiconductor device 1 is of a type called HFET (Heterostructure Field Effect Transistor) or HEMT (High Electron Mobility Transistor), and includes a substrate 12, a buffer layer 14, and a nitride semiconductor multilayer body. 16, a p-type nitride semiconductor layer 18, an insulating film 22, a drain electrode 32, a source electrode 34, a gate electrode 36, and a field plate 38.

  As the material of the substrate 12, a material capable of crystal growth of a nitride semiconductor-based semiconductor material is used. For example, gallium nitride, sapphire, silicon carbide, or silicon is used as the material of the substrate 12.

  The buffer layer 14 is provided in contact with the upper surface of the substrate 12. For example, non-doped gallium nitride (i-GaN), non-doped aluminum nitride (i-AlN), and non-doped aluminum gallium nitride (i-AlGaN) are used as the material of the buffer layer 14. The buffer layer 14 is laminated on the substrate 12 by using metal organic chemical vapor deposition (MOCVD).

  The nitride semiconductor multilayer body 16 includes a GaN layer 16a, an electron transit layer 16b, and an electron supply layer 16c. The GaN layer 16 a is provided in contact with the upper surface of the buffer layer 14. As an example of the material for the GaN layer 16a, carbon (C) -doped gallium nitride (GaN) is used. The GaN layer 16a is configured as a layer having high electrical resistance by being doped with carbon, and plays a role of suppressing a leakage current to the substrate 12. The electron transit layer 16b is provided in contact with the upper surface of the GaN layer 16a. For example, non-doped gallium nitride (i-GaN) is used as the material of the electron transit layer 16b. The electron supply layer 16c is provided in contact with the upper surface of the electron transit layer 16b. As an example of the material for the electron supply layer 16c, non-doped aluminum gallium nitride (i-AlGaN) is used. The band gap of the electron supply layer 16c is larger than the band gap of the electron transit layer 16b. For this reason, the electron transit layer 16b and the electron supply layer 16c form a heterojunction, and a two-dimensional electron gas layer is formed on the electron transit layer 16b side of the heterojunction surface. The GaN layer 16a, the electron transit layer 16b, and the electron supply layer 16c are sequentially stacked on the buffer layer 14 using metal organic vapor phase epitaxy.

  The p-type nitride semiconductor layer 18 is provided in contact with the upper surface of the electron supply layer 16 c and is disposed between the drain electrode 32 and the source electrode 34 and apart from both the drain electrode 32 and the source electrode 34. Yes. As a material of the p-type nitride semiconductor layer 18, for example, magnesium-doped gallium nitride (p-GaN) or aluminum gallium nitride (p-AlGaN) is used. The p-type nitride semiconductor layer 18 is laminated on the upper surface of the nitride semiconductor multilayer body 16 using metal organic vapor phase epitaxy.

  The insulating film 22 includes the upper surface of the nitride semiconductor multilayer body 16 between the p-type nitride semiconductor layer 18 and the drain electrode 32 and the nitride semiconductor multilayer body 16 between the p-type nitride semiconductor layer 18 and the source electrode 34. It is provided in contact with the upper surface. As an example of the material of the insulating film 22, a USG (Undoped Silicate Glasses) film is used. The insulating film 22 is formed on the upper surface of the nitride semiconductor multilayer body 16 by using chemical vapor deposition. As shown in FIG. 2, the insulating film 22 includes a thin insulating film portion 22 a, a thick insulating film portion 22 b, and a middle insulating film portion 22 c between the p-type nitride semiconductor layer 18 and the drain electrode 32. About the film thickness of the direction orthogonal to the upper surface of the nitride semiconductor laminated body 16, it becomes thick in order of the thin insulating film part 22a, the middle insulating film part 22c, and the thick insulating film part 22b. The thin insulating film portion 22 a is thinner than the p-type nitride semiconductor layer 18. The insulating film 22 has a similar structure between the p-type nitride semiconductor layer 18 and the source electrode 34.

  The thin insulating film portion 22a is disposed in a portion adjacent to the drain side of the p-type nitride semiconductor layer 18, and the lower portion of the side surface 18Sa on the drain side of the p-type nitride semiconductor layer 18 (in other words, the electron supply) Layer 16c side portion). The thick insulating film portion 22b is disposed between the thin insulating film portion 22a and the middle insulating film portion 22c. The middle insulating film portion 22 c is disposed between the thick insulating film portion 22 b and the drain electrode 32.

  As shown in FIG. 1, each of the drain electrode 32 and the source electrode 34 is provided in contact with the upper surface of the nitride semiconductor multilayer body 16. The drain electrode 32 and the source electrode 34 are arranged at positions facing each other with the p-type nitride semiconductor layer 18 interposed therebetween. The drain electrode 32 is preferably made of a material capable of making ohmic contact with a nitride semiconductor material. As an example of the material of the drain electrode 32, a laminated electrode of titanium and aluminum is used. It is desirable that the source electrode 34 be made of a material that can make ohmic contact with the nitride semiconductor material. As a material of the source electrode 34, for example, a laminated electrode of titanium and aluminum is used. Accordingly, each of the drain electrode 32 and the source electrode 34 is configured to be in ohmic contact with a two-dimensional electron gas layer formed in the vicinity of the heterojunction surface between the electron transit layer 16b and the electron supply layer 16c. Each of the drain electrode 32 and the source electrode 34 is laminated on the upper surface of the nitride semiconductor multilayer body 16 by using an electron beam evaporation technique.

  The gate electrode 36 is disposed between the drain electrode 32 and the source electrode 34 and away from both the drain electrode 32 and the source electrode 34, and is provided in contact with the p-type nitride semiconductor layer 18. The p-type nitride semiconductor layer 18 and the gate electrode 36 constitute a JFET type gate structure. As shown in FIG. 2, the gate electrode 36 has a drain side gate electrode part 36a, an upper gate electrode part 36b, and a source side gate electrode part 36c.

  The drain-side gate electrode portion 36 a is disposed in a portion adjacent to the drain side of the p-type nitride semiconductor layer 18 and is in contact with the upper portion of the side surface 18Sa on the drain side of the p-type nitride semiconductor layer 18. Thereby, in the portion adjacent to the drain side of the p-type nitride semiconductor layer 18, the nitride semiconductor stacked body 16, the thin insulating film portion 22a, and the drain side gate electrode portion 36a are stacked. Upper gate electrode portion 36b is disposed in a portion adjacent to the upper surface of p-type nitride semiconductor layer 18 and is in contact with the entire upper surface 18Sb of p-type nitride semiconductor layer 18. The source-side gate electrode portion 36 c is disposed in a portion adjacent to the source side of the p-type nitride semiconductor layer 18 and is in contact with the upper portion of the side 18 Sc on the source side of the p-type nitride semiconductor layer 18. As described above, the gate electrode 36 covers both the corner portion between the drain-side side surface 18Sa and the upper surface 18Sb and the corner portion between the source-side side surface 18Sc and the upper surface 18Sb of the p-type nitride semiconductor layer 18. , In contact with the p-type nitride semiconductor layer 18. In other words, the p-type nitride semiconductor layer 18 is within the range of the gate electrode 36 when observed from a direction orthogonal to the upper surface of the nitride semiconductor multilayer body 16 (hereinafter referred to as “when viewed in plan”). Is provided. The drain side surface 18Sa of the p-type nitride semiconductor layer 18 refers to a surface facing the drain electrode 32. Similarly, the side surface 18Sc on the source side of the p-type nitride semiconductor layer 18 is a surface facing the source electrode 34.

  The material of the gate electrode 36 is preferably a material that can make ohmic contact with a nitride semiconductor material. As an example of the material of the gate electrode 36, a laminated electrode of titanium and aluminum is used. Thereby, the gate electrode 36 is configured to be in ohmic contact with the p-type nitride semiconductor layer 18. The gate electrode 36 is formed on the upper surface of the p-type nitride semiconductor layer 18 and the upper surface of the insulating film 22 by using an electron beam evaporation technique. The material of the gate electrode 36 may be a material that can make a Schottky contact with a nitride semiconductor material.

  As shown in FIG. 1, the field plate 38 extends from the gate electrode 36 toward the drain electrode 32 and faces the nitride semiconductor stacked body 16 with the insulating film 22 interposed therebetween. That is, the nitride semiconductor multilayer body 16, the insulating film 22, and the field plate 38 are laminated. As shown in FIG. 2, the field plate 38 is in contact with the entire upper surfaces of the drain-side gate electrode portion 36a, the upper-side gate electrode portion 36b, and the source-side gate electrode portion 36c of the gate electrode 36, and has a thick wall of the insulating film 22. The insulating film part 22b is extended to a part of the upper surface of the middle insulating film part 22c beyond the insulating film part 22b.

  Next, the operation of the nitride semiconductor device 1 will be described. The nitride semiconductor device 1 is used with a positive potential applied to the drain electrode 32 and a ground potential applied to the source electrode 34. When the gate electrode 36 is grounded, the depletion layer extending from the p-type nitride semiconductor layer 18 is 2 below the p-type nitride semiconductor layer 18 in the vicinity of the heterojunction surface of the electron transit layer 16b and the electron supply layer 16c. Deplete electrons in the dimensional electron gas layer. Therefore, the current path between the drain electrode 32 and the source electrode 34 is cut off at the heterojunction surface where the p-type nitride semiconductor layer 18 faces, and the nitride semiconductor device 1 is turned off.

  When a positive potential is applied to the gate electrode 36, the depletion layer extending from the p-type nitride semiconductor layer 18 is reduced, and the electron transit layer 16b and the electron supply layer 16c are also below the p-type nitride semiconductor layer 18. A two-dimensional electron gas layer is generated in the vicinity of the heterojunction surface. Electrons injected from the source electrode 34 flow to the drain electrode 32 through the two-dimensional electron gas layer, and the nitride semiconductor device 1 is turned on. Thus, nitride semiconductor device 1 operates normally off.

  As shown in FIGS. 1 and 2, the nitride semiconductor device 1 is characterized in that the gate electrode 36 has a drain-side gate electrode portion 36a. The drain-side gate electrode portion 36a is configured to be in contact with the upper portion of the drain-side side surface 18Sa of the p-type nitride semiconductor layer 18. For this reason, the drain-side gate electrode portion 36 a faces the nitride semiconductor stacked body 16 through the thin insulating film portion 22 a thinner than the p-type nitride semiconductor layer 18. Thus, since the distance between the drain side gate electrode part 36a and the nitride semiconductor laminated body 16 is short, the drain side gate electrode part 36a can exhibit the field plate effect.

  In the nitride semiconductor device 1, the electric field strength is maximized in the vicinity of the drain-side end portion of the joint surface between the p-type nitride semiconductor layer 18 and the electron supply layer 16 c. For example, when the gate electrode 36 does not have the drain side gate electrode portion 36a, the field plate effect is not exhibited on the drain side of the p-type nitride semiconductor layer 18, and the electric field strength at that portion becomes high (FIG. 1). (Shown in broken lines). On the other hand, in the nitride semiconductor device 1, since the drain side gate electrode portion 36a can exhibit the field plate effect, the peak of the electric field concentration is dispersed and the maximum intensity of the electric field is reduced (shown by a solid line in FIG. 1). . Furthermore, in the nitride semiconductor device 1, since the field plate 38 extends to a part of the middle insulating film portion 22c, this also disperses the peak of the electric field concentration and decreases the maximum strength of the electric field ( (Indicated in FIG. 1 by a solid line). As described above, in the nitride semiconductor device 1, the occurrence of avalanche breakdown is suppressed on the drain side of the p-type nitride semiconductor layer 18, and the breakdown voltage is improved.

  Further, as shown in FIGS. 1 and 2, in the nitride semiconductor device 1, the drain side gate electrode portion 36 a is in contact with a part of the side 18 Sa on the drain side of the p-type nitride semiconductor layer 18, and the upper gate The electrode portion 36b is in contact with the entire upper surface 18Sb of the p-type nitride semiconductor layer 18, and the source-side gate electrode portion 36c is in contact with a part of the source-side side surface 18Sc of the p-type nitride semiconductor layer 18. Thus, a large contact area between the gate electrode 36 and the p-type nitride semiconductor layer 18 is ensured. Therefore, even if an avalanche breakdown occurs on the drain side of the p-type nitride semiconductor layer 18, a large current path for the hole current flowing through the gate electrode 36 through the p-type nitride semiconductor layer 18 is secured. Current concentration (increase in hole current density) at the contact surface between the type nitride semiconductor layer 18 and the gate electrode 36 is suppressed. Also in this respect, the nitride semiconductor device 1 can have a high breakdown voltage characteristic.

  Further, as shown in FIGS. 1 and 2, in the nitride semiconductor device 1, the field plate 38 is in contact with the entire upper surfaces of the drain side gate electrode portion 36a, the upper gate electrode portion 36b, and the source side gate electrode portion 36c. Thus, a large contact area between the field plate 38 and the gate electrode 36 is ensured. Therefore, even if an avalanche breakdown occurs on the drain side of the p-type nitride semiconductor layer 18, a large current path for the hole current flowing through the field plate 38 via the p-type nitride semiconductor layer 18 and the gate electrode 36 is secured. Therefore, current concentration (increase in hole current density) at the contact surface between the gate electrode 36 and the field plate 38 is suppressed. Also in this respect, the nitride semiconductor device 1 can have a high breakdown voltage characteristic.

  Next, a method for manufacturing the nitride semiconductor device 1 will be described. First, as shown in FIG. 3A, the buffer layer 14, the nitride semiconductor stacked body 16, and the p-type nitride semiconductor layer 18 are stacked on the substrate 12. The buffer layer 14, the nitride semiconductor stacked body 16, and the p-type nitride semiconductor layer 18 are sequentially grown on the substrate 12 by using metal organic vapor phase epitaxy.

  Next, as shown in FIG. 3B, the p-type nitride semiconductor layer 18 is patterned using a dry etching technique. The p-type nitride semiconductor layer 18 is patterned at a position between the formation position of the drain electrode and the formation position of the source electrode and away from both the formation position of the drain electrode and the formation position of the source electrode. A part of the p-type nitride semiconductor layer 18 is removed, and a part of the upper surface of the nitride semiconductor stacked body 16 is exposed. Further, after patterning the p-type nitride semiconductor layer 18, an insulating film 22 is formed on the upper surface of the nitride semiconductor stacked body 16 so as to cover the p-type nitride semiconductor layer 18 by using chemical vapor deposition. . Thereby, the insulating film 22 has a protruding portion 24 that protrudes from the remaining portion at the position where the p-type nitride semiconductor layer 18 is present.

  Next, as shown in FIG. 3C, a mask 42 is formed on the upper surface of the insulating film 22. In the mask 42, an opening 42a corresponding to the formation position of the drain electrode, an opening 42b corresponding to the formation position of the source electrode, and an opening 42c corresponding to the formation position of the gate electrode are formed. Here, the opening 42 c of the mask 42 corresponding to the formation position of the gate electrode is positioned within the range of the upper surface of the convex portion 24 of the insulating film 22. More specifically, the side surface on the drain side of the opening 42c of the mask 42 is between the side surface on the drain side of the p-type nitride semiconductor layer 18 and the side surface on the drain side of the protrusion 24 of the insulating film 22 when viewed in plan. Is positioned so that The side surface on the source side of the opening 42c of the mask 42 is positioned so as to be between the side surface on the source side of the p-type nitride semiconductor layer 18 and the side surface on the source side of the convex portion 24 of the insulating film 22 when viewed in plan. Is done.

  Next, as shown in FIG. 3D, a part of the insulating film 22 exposed in the openings 42a, 42b, and 42c of the mask 42 is removed using a dry etching technique. Thus, portions of the upper surface of the nitride semiconductor multilayer body 16 corresponding to the drain electrode formation position and the source electrode formation position are exposed. Further, a part of the side surface on the drain side, the entire upper surface, and a part of the side surface on the source side of the p-type nitride semiconductor layer 18 are exposed.

  Next, as shown in FIG. 3E, after the mask 42 is removed, the drain electrode 32 and the source electrode 34 are formed using an electron beam evaporation technique. Further, the gate electrode 36 is formed using an electron beam evaporation technique. Finally, when a field plate or the like is formed, the nitride semiconductor device 1 shown in FIG. 1 is completed.

  The technical features disclosed in this specification will be summarized below. The items described below have technical usefulness independently.

  The semiconductor device disclosed in this specification includes an electron transit layer, an electron supply layer heterojunction with the electron transit layer, a drain electrode on the electron supply layer, a source electrode on the electron supply layer at a position away from the drain electrode, A p-type semiconductor layer on the electron supply layer at a position between the drain electrode and the source electrode, an insulating film on the electron supply layer at a position between the p-type semiconductor layer and the drain electrode, and a p-type semiconductor layer A gate electrode may be provided. The insulating film has a thin insulating film portion thinner than the thickness of the p-type semiconductor layer. The thin insulating film portion is in contact with the side surface on the drain side of the p-type semiconductor layer. The gate electrode is in contact with the side surface on the drain side of the p-type semiconductor layer and faces the electron supply layer through the thin insulating film portion.

  The gate electrode may be in contact with the upper surface of the p-type semiconductor layer. More preferably, the gate electrode is in contact with the entire upper surface of the p-type semiconductor layer. More preferably, the gate electrode is also in contact with a part of the side surface on the source side of the p-type semiconductor layer. According to these aspects, since a large contact area between the gate electrode and the p-type nitride semiconductor layer is ensured, a large current path for the hole current when the avalanche breakdown occurs is ensured, and the p-type nitride semiconductor layer and the gate electrode Current concentration at the contact surface (increase in hole current density) is suppressed.

  The semiconductor device may further include a field plate that is in contact with the gate electrode, extends from the gate electrode toward the drain electrode, and faces the electron supply layer through an insulating film. In this case, the field plate includes the drain-side gate electrode portion of the gate electrode in the portion adjacent to the side surface on the drain side of the p-type semiconductor layer and the upper gate electrode portion of the gate electrode in the portion adjacent to the upper surface of the p-type semiconductor layer. May be in contact with both. More preferably, the gate electrode is also in contact with the source-side gate electrode portion of the gate electrode provided in a portion adjacent to the side surface on the source side of the p-type semiconductor layer. According to these embodiments, a large contact area between the field plate and the gate electrode is ensured, so that a large current path for the hole current when the avalanche breakdown occurs is secured, and current concentration at the contact surface between the gate electrode and the field plate (hole current) Density increase) is suppressed.

  The method for manufacturing a semiconductor device disclosed in this specification may include a step of forming a p-type semiconductor layer, a step of forming an insulating film, a step of removing part of the insulating film, and a step of forming a gate electrode. Good. In the step of forming the p-type semiconductor layer, the p-type semiconductor layer located between the formation position of the drain electrode and the formation position of the source electrode is formed on the electron supply layer that is heterojunction with the electron transit layer. In the step of forming the insulating film, the insulating film is formed on the electron supply layer so as to cover the p-type semiconductor layer. In the step of removing a part of the insulating film, a part of the insulating film is removed so that at least a part of the side surface on the drain side of the p-type semiconductor layer is exposed and a part of the insulating film remains on the electron supply layer. To do. In the step of forming the gate electrode, a gate electrode that is in contact with a part of the side surface on the drain side of the p-type semiconductor layer and faces the electron supply layer through the insulating film is formed.

  In the semiconductor device and the manufacturing method thereof disclosed in this specification, the material of the electron transit layer, the electron supply layer, and the p-type semiconductor layer may be a compound semiconductor, and in particular, a nitride semiconductor.

In the semiconductor device and the manufacturing method thereof disclosed in this specification, the semiconductor material of the electron transit layer is In _Xa Al _Ya Ga _1-Xa-YaN (0 ≦ Xa ≦ 1, 0 ≦ Ya ≦ 1, 0 ≦ Xa + Ya ≦ is 1), the semiconductor material of the electron supply layer _is an _{in Xb Al Yb Ga 1-Xb} -Yb N (0 ≦ Xb ≦ 1,0 ≦ Yb ≦ 1,0 ≦ Xb + Yb ≦ 1), in Xb Al Yb Ga _1-Xb-Yb bandgap of N is _{in Xa Al Ya Ga 1-Xa} -Ya N greater than the band gap is desired. semiconductor material of the p-type semiconductor layer _is an _{In Xc Al Yc Ga 1-Xc} -Yc N (0 ≦ Xc ≦ 1,0 ≦ Yc ≦ 1,0 ≦ Xc + Yc ≦ 1). The composition of the p-type semiconductor layer may be the same as that of the electron supply layer.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1: nitride semiconductor device 12: substrate 14: buffer layer 16: nitride semiconductor laminate 16a: GaN layer 16b: electron transit layer 16c: electron supply layer 18: p-type nitride semiconductor layer 22: insulating film 32: drain electrode 34: Source electrode 36: Gate electrode 36a: Drain side gate electrode part 36b: Upper gate electrode part 36c: Source side gate electrode part 38: Field plate

Claims (7)

An electronic travel layer,
An electron supply layer heterojunction to the electron transit layer;
A drain electrode on the electron supply layer;
A source electrode on the electron supply layer at a position away from the drain electrode;
A p-type semiconductor layer on the electron supply layer at a position between the drain electrode and the source electrode;
An insulating film on the electron supply layer at a position between the p-type semiconductor layer and the drain electrode;
A gate electrode in contact with the p-type semiconductor layer,
The insulating film has a thin insulating film portion thinner than the thickness of the p-type semiconductor layer,
The thin insulating film portion is in contact with the side surface on the drain side of the p-type semiconductor layer,
The gate electrode is in contact with the drain-side side surface of the p-type semiconductor layer and faces the electron supply layer through the thin insulating film portion.   The semiconductor device according to claim 1, further comprising a field plate that is in contact with the gate electrode, extends from the gate electrode toward the drain electrode, and faces the electron supply layer with the insulating film interposed therebetween.   The semiconductor device according to claim 1, wherein the gate electrode is also in contact with an upper surface of the p-type semiconductor layer. A field plate that is in contact with the gate electrode, extends from the gate electrode toward the drain electrode, and faces the electron supply layer via the insulating film;
The field plate includes a drain side gate electrode portion of the gate electrode in a portion adjacent to a side surface on the drain side of the p-type semiconductor layer and an upper gate of the gate electrode in a portion adjacent to the upper surface of the p-type semiconductor layer. The semiconductor device according to claim 3, wherein the semiconductor device is in contact with both electrode portions.   The semiconductor device according to claim 1, wherein materials of the electron transit layer, the electron supply layer, and the p-type semiconductor layer are nitride semiconductors. Forming a p-type semiconductor layer positioned between the formation position of the drain electrode and the formation position of the source electrode on the electron supply layer heterojunction with the electron transit layer;
Forming an insulating film on the electron supply layer so as to cover the p-type semiconductor layer;
Removing a part of the insulating film such that at least a part of the side surface on the drain side of the p-type semiconductor layer is exposed and a part of the insulating film remains on the electron supply layer;
Forming a gate electrode in contact with a part of the side surface on the drain side of the p-type semiconductor layer and facing the electron supply layer through the insulating film.   The method for manufacturing a semiconductor device according to claim 6, wherein materials of the electron transit layer, the electron supply layer, and the p-type semiconductor layer are nitride semiconductors.

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