JP2017085047A - Method of manufacturing epitaxial wafer, epitaxial wafer, method of manufacturing semiconductor device and semiconductor device - Google Patents

Method of manufacturing epitaxial wafer, epitaxial wafer, method of manufacturing semiconductor device and semiconductor device Download PDF

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JP2017085047A
JP2017085047A JP2015214758A JP2015214758A JP2017085047A JP 2017085047 A JP2017085047 A JP 2017085047A JP 2015214758 A JP2015214758 A JP 2015214758A JP 2015214758 A JP2015214758 A JP 2015214758A JP 2017085047 A JP2017085047 A JP 2017085047A
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layer
breakdown voltage
substrate
dopant
voltage maintaining
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JP2015214758A
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JP6706786B2 (en
Inventor
秀一 土田
Shuichi Tsuchida
秀一 土田
哲哉 宮澤
Tetsuya Miyazawa
哲哉 宮澤
米澤　喜幸
Yoshiyuki Yonezawa
喜幸 米澤
智久 加藤
Tomohisa Kato
智久 加藤
児島　一聡
Kazusato Kojima
一聡 児島
俵　武志
Takeshi Tawara
武志 俵
大月　章弘
Akihiro Otsuki
章弘 大月
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Central Research Institute of Electric Power Industry
Fuji Electric Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
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Central Research Institute of Electric Power Industry
Fuji Electric Co Ltd
National Institute of Advanced Industrial Science and Technology AIST
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Application filed by Central Research Institute of Electric Power Industry, Fuji Electric Co Ltd, National Institute of Advanced Industrial Science and Technology AIST filed Critical Central Research Institute of Electric Power Industry
Priority to JP2015214758A priority Critical patent/JP6706786B2/en
Priority to PCT/JP2016/082115 priority patent/WO2017073749A1/en
Priority to CN201680019145.3A priority patent/CN107430993B/en
Priority to DE112016001052.4T priority patent/DE112016001052T5/en
Publication of JP2017085047A publication Critical patent/JP2017085047A/en
Priority to US15/712,644 priority patent/US10354867B2/en
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Abstract

PROBLEM TO BE SOLVED: To provide an epitaxial wafer in which occurrence of a strip-like stacking fault, expanding from the interface of an epitaxial growth layer on a substrate and the substrate, is suppressed effectively, even if bipolar operation is carried out with a large current, while suppressing the thickness of the epitaxial growth layer.SOLUTION: A method of manufacturing an epitaxial wafer includes of steps (S1-S5) of epitaxially growing a buffer layer mainly composed of silicon carbide, having a lower resistance than a voltage sustaining layer, and promoting capture and extinction of minority carriers flowing from the voltage sustaining layer in the direction of the substrate, by adding main dopant determining the conductivity type on a silicon carbide substrate, and adding a sub-dopant for capturing the minority carriers a doping concentration lower than that of the main dopant, and a step of epitaxially growing the voltage sustaining layer on the buffer layer.SELECTED DRAWING: Figure 1

Description

本発明は、エピタキシャルウェハの製造方法、エピタキシャルウェハ、半導体装置の製造方法及び半導体装置に関し、特に炭化珪素半導体を用いたエピタキシャルウェハを製造する技術に関する。   The present invention relates to an epitaxial wafer manufacturing method, an epitaxial wafer, a semiconductor device manufacturing method, and a semiconductor device, and more particularly to a technique for manufacturing an epitaxial wafer using a silicon carbide semiconductor.

基板上に炭化珪素（ＳｉＣ）をエピタキシャル成長させたエピタキシャルウェハには、多くの結晶欠陥・転位が存在しており、これらがＳｉＣ半導体装置の特性に悪影響を与えていると考えられている。特にエピタキシャル成長層中の基底面転位（ＢＰＤ）は、半導体装置をバイポーラ動作させた際に積層欠陥に拡張し、電流を流れにくくすることにより半導体装置のオン電圧を上昇させ「バイポーラ劣化」の発生につながる。   An epitaxial wafer obtained by epitaxially growing silicon carbide (SiC) on a substrate has many crystal defects and dislocations, which are considered to have an adverse effect on the characteristics of the SiC semiconductor device. In particular, basal plane dislocations (BPD) in the epitaxial growth layer are expanded to stacking faults when the semiconductor device is operated in a bipolar manner, and the on-voltage of the semiconductor device is increased by making the current difficult to flow, resulting in the occurrence of “bipolar degradation”. Connected.

ＢＰＤは基板に数百〜数千個／ｃｍ２の密度で存在する。その多くはエピタキシャル成長中に貫通刃状転位（ＴＥＤ）に変換されるが、残ったＢＰＤは表面まで貫通し、三角形状の積層欠陥に拡張して問題となる。この問題は、エピタキシャル成長条件の工夫等により変換の効率が上昇し、ほぼ全てのＢＰＤが変換されるようになることで改善が進んでいる。しかしながら、近年、積層欠陥が帯状に広がることが報告されており、バイポーラ動作をするＳｉＣ半導体装置の実用化に向けた新たな問題となっている（非特許文献１参照。）。 BPD is present at a density of several hundred to several thousand pieces / cm 2 on the substrate. Most of them are converted to threading edge dislocations (TED) during epitaxial growth, but the remaining BPD penetrates to the surface and expands into a triangular stacking fault, which becomes a problem. This problem has been improved by improving the conversion efficiency by improving the epitaxial growth conditions, etc., and almost all BPDs are converted. However, in recent years, it has been reported that stacking faults spread in a band shape, which is a new problem for practical application of SiC semiconductor devices that perform bipolar operation (see Non-Patent Document 1).

非特許文献１には、帯状積層欠陥が広がる原因として、半導体基板中での電子―ホールの再結合が挙げられており、この再結合を抑制するため、半導体装置の半導体基板の上にエピタキシャル成長したバッファ層を厚くすることにより、半導体基板への過剰なホール注入を防ぐ対策が開示されている。しかしながら厚いバッファ層の成膜は、エピ成長のスループット低下によるコスト増大、欠陥密度増化による歩留まり低下及びエピタキシャルウェハの抵抗増大につながるため望ましくない。よって最小限のバッファ層の厚みで、帯状積層欠陥を防ぐ対策が必要とされていた。   Non-Patent Document 1 mentions that electron-hole recombination in a semiconductor substrate is a cause of spreading of band-like stacking faults. In order to suppress this recombination, epitaxial growth was performed on the semiconductor substrate of the semiconductor device. A countermeasure for preventing excessive hole injection into the semiconductor substrate by increasing the thickness of the buffer layer is disclosed. However, the formation of a thick buffer layer is undesirable because it leads to an increase in cost due to a decrease in the throughput of epi growth, a decrease in yield due to an increase in defect density, and an increase in resistance of the epitaxial wafer. Therefore, measures to prevent strip-like stacking faults have been required with the minimum buffer layer thickness.

Ｊ.Ｊ.スマーケリス（Sumakeris）他、「バイポーラ型ＳｉＣ半導体装置の順方向電圧安定化へのアプローチ（Approaches to Stabilizing the Forward Voltage of Bipolar SiC Devices）」、（米国）、マテリアルサイエンスフォーラム（Materials Science Forum）、オンライン 第４５７−４６０巻、２００４年、ｐ.１１１３−１１１６JJ Sumakeris et al., “Approaches to Stabilizing the Forward Voltage of Bipolar SiC Devices” (USA), Materials Science Forum ), Online 457-460, 2004, pp. 1113-1116.

本発明は上記した問題に着目して為されたものであって、エピタキシャル成長層の厚みを抑制しつつ、大電流でバイポーラ動作させても、基板上のエピタキシャル成長層と基板との界面から拡張する帯状積層欠陥の発生を効果的に抑制するエピタキシャルウェハの製造方法、エピタキシャルウェハ、半導体装置の製造方法及び半導体装置を提供することを目的とする。   The present invention has been made paying attention to the above-mentioned problem, and is a strip-like shape that extends from the interface between the epitaxial growth layer on the substrate and the substrate even when the bipolar operation is performed with a large current while suppressing the thickness of the epitaxial growth layer. An object of the present invention is to provide an epitaxial wafer manufacturing method, an epitaxial wafer, a semiconductor device manufacturing method, and a semiconductor device that effectively suppress the occurrence of stacking faults.

上記課題を解決するために、本発明に係るエピタキシャルウェハの製造方法のある態様は、炭化珪素の基板と耐圧維持層とを備えるエピタキシャルウェハの製造方法において、基板の上に、導電型を決める主ドーパントを添加すると共に少数キャリアを捕獲する副ドーパントを主ドーパントのドーピング濃度より低いドーピング濃度で添加して、耐圧維持層から基板の方向に流れる少数キャリアの捕獲及び消滅を促進する、耐圧維持層より低抵抗の、炭化珪素を主成分とするバッファ層をエピタキシャル成長するステップと、バッファ層の上に耐圧維持層をエピタキシャル成長するステップと、を含むことを要旨とする。   In order to solve the above-described problems, an aspect of the epitaxial wafer manufacturing method according to the present invention is an epitaxial wafer manufacturing method including a silicon carbide substrate and a breakdown voltage maintaining layer. More than the breakdown voltage maintaining layer, which adds a dopant and adds a sub-dopant that captures minority carriers at a doping concentration lower than the doping concentration of the main dopant to promote the capture and annihilation of minority carriers flowing from the breakdown voltage maintaining layer toward the substrate. The present invention includes a step of epitaxially growing a low-resistance buffer layer mainly composed of silicon carbide and a step of epitaxially growing a breakdown voltage maintaining layer on the buffer layer.

また本発明に係るエピタキシャルウェハの製造方法の他の態様は、炭化珪素の基板と耐圧維持層とを備えるエピタキシャルウェハの製造方法において、基板の上に、導電型を決める主ドーパントを添加しながら炭化珪素を主成分とする単結晶層をエピタキシャル成長するステップと、単結晶層に、少数キャリアを捕獲する副ドーパントのイオンを主ドーパントのドーピング濃度より低いドーピング濃度となるドーズ量でイオン注入するステップと、イオンを活性化して、耐圧維持層から基板の方向に流れる少数キャリアの捕獲及び消滅を促進する、耐圧維持層より低抵抗の、バッファ層を単結晶層によって形成するステップと、バッファ層の上に耐圧維持層をエピタキシャル成長するステップと、を含むことを要旨とする。   Another aspect of the epitaxial wafer manufacturing method according to the present invention is an epitaxial wafer manufacturing method comprising a silicon carbide substrate and a breakdown voltage maintaining layer, and carbonizing while adding a main dopant that determines the conductivity type on the substrate. A step of epitaxially growing a single crystal layer mainly composed of silicon, and a step of ion-implanting ions of a subdopant that captures minority carriers into the single crystal layer with a dose amount that is lower than a doping concentration of the main dopant; Activating ions to promote the capture and annihilation of minority carriers flowing from the breakdown voltage maintaining layer toward the substrate, forming a buffer layer with a single crystal layer having a lower resistance than the breakdown voltage maintaining layer; and on the buffer layer And a step of epitaxially growing the breakdown voltage maintaining layer.

また本発明に係る本発明に係るエピタキシャルウェハのある態様は、炭化珪素の基板と耐圧維持層とを備えるエピタキシャルウェハにおいて、基板と耐圧維持層の間に設けられた、導電型を決める主ドーパントと、少数キャリアを捕獲し主ドーパントのドーピング濃度より低いドーピング濃度の副ドーパントとが添加された、耐圧維持層から基板の方向に流れる少数キャリアの捕獲及び消滅を促進する、耐圧維持層より低抵抗の、炭化珪素を主成分とするバッファ層を備えることを要旨とする。   An aspect of the epitaxial wafer according to the present invention according to the present invention is an epitaxial wafer including a silicon carbide substrate and a breakdown voltage maintaining layer, and a main dopant for determining a conductivity type provided between the substrate and the breakdown voltage maintaining layer. The trapping of minority carriers and the addition of a sub-dopant with a doping concentration lower than the doping concentration of the main dopant promote the capture and annihilation of minority carriers flowing from the breakdown voltage maintaining layer toward the substrate. The gist is to provide a buffer layer mainly composed of silicon carbide.

また本発明に係る半導体装置の製造方法のある態様は、炭化珪素の基板と耐圧維持層とを備える半導体装置の製造方法において、基板の上に、導電型を決める主ドーパントを添加すると共に少数キャリアを捕獲する副ドーパントを主ドーパントのドーピング濃度より低いドーピング濃度で添加して、耐圧維持層から基板の方向に流れる少数キャリアの捕獲及び消滅を促進する、耐圧維持層より低抵抗の、炭化珪素を主成分とするバッファ層をエピタキシャル成長する工程と、バッファ層の上に第１導電型の耐圧維持層をエピタキシャル成長する工程と、耐圧維持層の上部の一部に第２導電型の半導体領域を形成する工程と、を含むことを要旨とする。   According to another aspect of the method for manufacturing a semiconductor device according to the present invention, there is provided a method for manufacturing a semiconductor device comprising a silicon carbide substrate and a breakdown voltage maintaining layer, wherein a main dopant for determining a conductivity type is added to the substrate and a minority carrier is added. A silicon carbide having a lower resistance than that of the breakdown voltage maintaining layer is added by adding a sub-dopant for trapping at a doping concentration lower than the doping concentration of the main dopant to promote capture and annihilation of minority carriers flowing from the breakdown voltage maintaining layer toward the substrate. A step of epitaxially growing a buffer layer as a main component; a step of epitaxially growing a first conductivity type breakdown voltage maintaining layer on the buffer layer; and forming a second conductivity type semiconductor region on a part of the upper portion of the breakdown voltage maintaining layer. And a process.

また本発明に係る半導体装置の製造方法の他の態様は、炭化珪素の基板と耐圧維持層とを備える半導体装置の製造方法において、基板の上に、導電型を決める主ドーパントを添加しながら炭化珪素を主成分とする単結晶層をエピタキシャル成長する工程と、単結晶層に、少数キャリアを捕獲する副ドーパントのイオンを主ドーパントのドーピング濃度より低いドーピング濃度となるドーズ量でイオン注入する工程と、イオンを活性化して、耐圧維持層から基板の方向に流れる少数キャリアの捕獲及び消滅を促進する、耐圧維持層より低抵抗の、バッファ層を単結晶層によって形成する工程と、バッファ層の上に第１導電型の耐圧維持層をエピタキシャル成長する工程と、耐圧維持層の上部の一部に第２導電型の半導体領域を形成する工程と、を含むことを要旨とする。   Another aspect of the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device comprising a silicon carbide substrate and a breakdown voltage maintaining layer, while carbonizing while adding a main dopant that determines the conductivity type on the substrate. A step of epitaxially growing a single crystal layer containing silicon as a main component; a step of ion-implanting ions of a sub-dopant that captures minority carriers into the single crystal layer at a dose amount that is lower than a doping concentration of the main dopant; A step of forming a buffer layer with a single crystal layer having a lower resistance than the withstand voltage maintaining layer, which activates ions and promotes the capture and annihilation of minority carriers flowing from the withstand voltage maintaining layer toward the substrate; and on the buffer layer A step of epitaxially growing a first conductivity type breakdown voltage maintaining layer; a step of forming a second conductivity type semiconductor region in a part of the upper portion of the breakdown voltage maintenance layer; And summary to include.

また本発明に係る半導体装置のある態様は、炭化珪素の基板と耐圧維持層とを備える半導体装置において、基板と耐圧維持層の間に設けられた、導電型を決める主ドーパントと、少数キャリアを捕獲し主ドーパントのドーピング濃度より低いドーピング濃度の副ドーパントとが添加された、耐圧維持層から基板の方向に流れる少数キャリアの捕獲及び消滅を促進する、耐圧維持層より低抵抗の、炭化珪素を主成分とするバッファ層と、第１導電型の耐圧維持層の上部の一部に設けられた第２導電型の半導体領域と、を備えることを要旨とする。   According to another aspect of the semiconductor device of the present invention, in a semiconductor device including a silicon carbide substrate and a breakdown voltage maintaining layer, a main dopant for determining a conductivity type provided between the substrate and the breakdown voltage maintaining layer and a minority carrier are provided. A silicon carbide having a lower resistance than the breakdown voltage maintaining layer, which has been added with a sub-dopant having a doping concentration lower than the doping concentration of the main dopant, promotes the capture and annihilation of minority carriers flowing from the breakdown voltage maintaining layer toward the substrate. The gist is to include a buffer layer as a main component and a second conductivity type semiconductor region provided in a part of the upper portion of the first conductivity type withstand voltage maintaining layer.

従って本発明に係るエピタキシャルウェハの製造方法、エピタキシャルウェハ、半導体装置の製造方法及び半導体装置によれば、エピタキシャル成長層の厚みを抑制しつつ、大電流でバイポーラ動作させても、基板上のエピタキシャル成長層と基板との界面から拡張する帯状積層欠陥の発生を効果的に抑制することができる。   Therefore, according to the epitaxial wafer manufacturing method, the epitaxial wafer, the semiconductor device manufacturing method, and the semiconductor device according to the present invention, the epitaxial growth layer on the substrate can be controlled even if a bipolar operation is performed with a large current while suppressing the thickness of the epitaxial growth layer. Generation | occurrence | production of the strip | belt-shaped lamination | stacking defect extended from the interface with a board | substrate can be suppressed effectively.

第１の実施の形態に係るエピタキシャルウェハの製造方法を説明するフローチャートである。It is a flowchart explaining the manufacturing method of the epitaxial wafer which concerns on 1st Embodiment. 図２（ａ）は、主ドーパント及び副ドーパントの設定に用いる不純物元素の組み合わせパターンの一例であり、図２（ｂ）は、主ドーパント及び副ドーパントの設定に用いる不純物元素の組み合わせパターンの他の例である。FIG. 2A is an example of a combination pattern of impurity elements used for setting the main dopant and the sub-dopant, and FIG. 2B shows another combination pattern of impurity elements used for setting the main dopant and the sub-dopant. It is an example. 主ドーパントのドーピング濃度と少数キャリア寿命との関係を示すグラフ図である。It is a graph which shows the relationship between the doping concentration of a main dopant, and a minority carrier lifetime. バッファ層の厚みと帯状積層欠陥の発生頻度との関係を示すグラフ図である。It is a graph which shows the relationship between the thickness of a buffer layer, and the occurrence frequency of a strip-like stacking fault. 少数キャリア寿命と帯状積層欠陥の発生頻度との関係を示すグラフ図である。It is a graph which shows the relationship between the minority carrier lifetime and the occurrence frequency of strip-like stacking faults. 少数キャリア寿命の温度依存性を示すグラフ図である。It is a graph which shows the temperature dependence of minority carrier lifetime. 第１の実施の形態に係る半導体装置の製造方法を説明する工程断面図である（その１）。It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 1). 第１の実施の形態に係る半導体装置の製造方法を説明する工程断面図である（その２）。It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 2). 第１の実施の形態に係る半導体装置の製造方法を説明する工程断面図である（その３）。It is process sectional drawing explaining the manufacturing method of the semiconductor device which concerns on 1st Embodiment (the 3). 比較例に係るエピタキシャルウェハに発生した積層欠陥のフォトルミネッセンス発光を撮影した上面図である。It is the top view which image | photographed the photoluminescence light emission of the stacking fault which generate | occur | produced in the epitaxial wafer which concerns on a comparative example. 第２の実施の形態に係るエピタキシャルウェハの製造方法を説明するフローチャートである。It is a flowchart explaining the manufacturing method of the epitaxial wafer which concerns on 2nd Embodiment.

以下に本発明の第１及び第２の実施の形態を説明する。以下の図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。但し、図面は模式的なものであり、厚みと平面寸法との関係、各装置や各部材の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判定すべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。   The first and second embodiments of the present invention will be described below. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and it should be noted that the relationship between the thickness and the planar dimensions, the ratio of the thickness of each device and each member, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

また、以下の説明における「左右」や「上下」の方向は、単に説明の便宜上の定義であって、本発明の技術的思想を限定するものではない。よって、例えば、紙面を９０度回転すれば「左右」と「上下」とは交換して読まれ、紙面を１８０度回転すれば「左」が「右」に、「右」が「左」になることは勿論である。また本明細書及び添付図面においては、ｎ又はｐを冠した領域や層では、それぞれ電子又は正孔が多数キャリアであることを意味する。またｎやｐに付す＋や−は、＋及び−が付記されていない半導体領域に比して、それぞれ相対的に不純物濃度が高い又は低い半導体領域であることを意味する。   Further, the directions of “left and right” and “up and down” in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present invention. Thus, for example, if the paper is rotated 90 degrees, “left and right” and “up and down” are read interchangeably, and if the paper is rotated 180 degrees, “left” becomes “right” and “right” becomes “left”. Of course. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in the region or layer bearing n or p, respectively. Further, + or − attached to n or p means a semiconductor region having a relatively high or low impurity concentration as compared with a semiconductor region not including + and −.

＜第１の実施の形態＞
（エピタキシャルウェハの製造方法）
第１の実施の形態に係るエピタキシャルウェハの製造方法を、図１のフローチャートを参照して説明する。
まずＳｉＣからなる基板を用意し、エピタキシャル成長炉内に搬送する（ステップＳ１）。次に炉内に水素（Ｈ２）ガスを導入し、１３００〜４００００Ｐａ程度の圧力を調整した後、１６００〜１７００℃に昇温する（ステップＳ２）。その後、ＳｉＣ原料ガスの導入（ステップＳ３）、導電型を決める主ドーパントを含む主ドーパントガスの導入（ステップＳ４）、少数キャリアを捕獲する副ドーパントを含む副ドーパントガスの導入（ステップＳ５）を行う。ステップＳ３〜Ｓ５は同時でも、或いは例えばステップＳ５をＳ４より僅かに遅らせて行う等タイミングをずらしても構わない。ここまでで基板の上に、耐圧維持層から基板の方向に流れる少数キャリアの捕獲及び消滅を促進する、ＳｉＣを主成分とするバッファ層が形成される。 <First Embodiment>
(Epitaxial wafer manufacturing method)
An epitaxial wafer manufacturing method according to the first embodiment will be described with reference to the flowchart of FIG.
First, a substrate made of SiC is prepared and transferred into an epitaxial growth furnace (step S1). Next, hydrogen (H 2 ) gas is introduced into the furnace, and after adjusting the pressure of about 1300 to 40000 Pa, the temperature is raised to 1600 to 1700 ° C. (step S2). Thereafter, introduction of a SiC source gas (step S3), introduction of a main dopant gas containing a main dopant that determines the conductivity type (step S4), and introduction of a subdopant gas containing a subdopant that captures minority carriers (step S5) are performed. . Steps S3 to S5 may be performed at the same time, or the timing may be shifted, for example, step S5 may be slightly delayed from S4. Up to this point, a buffer layer mainly composed of SiC that promotes the capture and annihilation of minority carriers flowing from the breakdown voltage maintaining layer toward the substrate is formed on the substrate.

続いて副ドーパントガスの供給を停止し、ＳｉＣ原料ガス、主ドーパントガスの流量を、耐圧維持層を形成するように調整する（ステップＳ６）。これによりバッファ層より高抵抗の耐圧維持層がバッファ層の上に形成される。すなわちバッファ層が耐圧維持層より低抵抗であるように、バッファ層及び耐圧維持層は構成されている。その後、降温、不活性ガス置換（ステップＳ７）を行った後に、ウェハ（基板）を炉外に搬出する（ステップＳ８）。上記はバッファ層と耐圧維持層を連続して形成する場合であるが、別々に形成する場合もあり得る。その際は、ステップＳ１〜Ｓ５の後にステップＳ７〜Ｓ８を行いバッファ層を形成した後に、ステップＳ１〜Ｓ４、Ｓ７〜Ｓ８とそれぞれ等価な処理を行い耐圧維持層を形成する処理を行う。以上のようにして第１の実施の形態に関わるエピタキシャルウェハが製造される。   Subsequently, the supply of the sub-dopant gas is stopped, and the flow rates of the SiC source gas and the main dopant gas are adjusted so as to form the pressure-resistant maintenance layer (step S6). As a result, a breakdown voltage maintaining layer having a higher resistance than the buffer layer is formed on the buffer layer. That is, the buffer layer and the withstand voltage maintaining layer are configured such that the buffer layer has a lower resistance than the withstand voltage maintaining layer. Thereafter, after the temperature is lowered and the inert gas is replaced (step S7), the wafer (substrate) is carried out of the furnace (step S8). The above is the case where the buffer layer and the breakdown voltage maintaining layer are formed continuously, but may be formed separately. In this case, after steps S1 to S5, steps S7 to S8 are performed to form a buffer layer, and then a process equivalent to steps S1 to S4 and S7 to S8 is performed to form a breakdown voltage maintaining layer. As described above, the epitaxial wafer according to the first embodiment is manufactured.

第１の実施の形態における主ドーパントと副ドーパントの組み合わせパターンとしては、例えば図２（ａ）に示すように、主ドーパントとしてドナーレベルを形成する不純物元素の窒素（Ｎ）を選択した場合には、副ドーパントとなる不純物元素としては、アルミニウム（Ａｌ）、ボロン（Ｂ）、バナジウム（Ｖ）、チタン（Ｔｉ）、鉄（Ｆｅ）及びクロム（Ｃｒ）等のうち、少なくとも１種類以上が選択可能である。
また図２（ｂ）に示すように、主ドーパントとしてアクセプタレベルを形成する不純物元素のＡｌを選択した場合には、副ドーパントとなる不純物元素としては、Ｎ、Ｂ、Ｖ、Ｔｉ、Ｆｅ及びＣｒ等のうち少なくとも１種類以上が選択可能である。 As a combination pattern of the main dopant and the sub-dopant in the first embodiment, for example, as shown in FIG. 2A, when the impurity element nitrogen (N) forming the donor level is selected as the main dopant. As an impurity element to be a sub-dopant, at least one or more of aluminum (Al), boron (B), vanadium (V), titanium (Ti), iron (Fe), and chromium (Cr) can be selected. It is.
In addition, as shown in FIG. 2B, when Al as an impurity element that forms an acceptor level is selected as a main dopant, N, B, V, Ti, Fe, and Cr are used as impurity elements as sub-dopants. Etc., at least one of them can be selected.

副ドーパントのドーピング濃度は、主ドーパントより低濃度、かつ、１×１０１４ｃｍ−３程度以上、５×１０１８ｃｍ−３程度未満であることが望ましい。副ドーパントのドーピング濃度が１×１０１４ｃｍ−３程度未満の場合、少数キャリアの捕獲が不十分であり、帯状積層欠陥の発生を有効に防止することができない。一方、副ドーパントのドーピング濃度が、主ドーパントのドーピング濃度以下であっても５×１０１８ｃｍ−３程度以上の場合、ドーピング濃度が高くなりすぎ、エピ層における抵抗の増加や絶縁破壊電界の低下等の問題が大きくなる。 The doping concentration of the sub-dopant is preferably lower than that of the main dopant and about 1 × 10 14 cm −3 or more and less than about 5 × 10 18 cm −3 . When the doping concentration of the sub-dopant is less than about 1 × 10 14 cm −3 , minority carriers are not sufficiently trapped, and the occurrence of strip stacking faults cannot be effectively prevented. On the other hand, if the doping concentration of the sub-dopant is not more than about 5 × 10 18 cm −3 even if it is lower than the doping concentration of the main dopant, the doping concentration becomes too high, increasing the resistance in the epi layer and decreasing the breakdown electric field. The problem such as becomes larger.

また図３のグラフ図に示すように、主ドーパントのドーピング濃度が高くなるほど、少数キャリアの寿命は短くなる。特に、ドーピング濃度が１×１０１７ｃｍ−３オーダレベルの領域における少数キャリアの寿命が７００ｎｓ程度や１０００ｎｓ程度であるのに対し、ドーピング濃度が１×１０１８ｃｍ−３程度以上の高濃度領域では、少数キャリアの寿命は約３００ｎｓ程度以下と、非常に短くなることがわかる。これはオージェ再結合メカニズムによるものと推測される。
一方、主ドーパントのドーピング濃度が、１×１０１９ｃｍ−３程度以上であると、ダブルショックレー（Double Shockley）型の積層欠陥が発生し易くなる。そのため主ドーパントのドーピング濃度は、１×１０１８ｃｍ−３程度以上、１×１０１９ｃｍ−３程度未満であることが望ましい。 Also, as shown in the graph of FIG. 3, the lifetime of minority carriers decreases as the doping concentration of the main dopant increases. In particular, the lifetime of minority carriers in a region where the doping concentration is on the order of 1 × 10 17 cm −3 is about 700 ns or 1000 ns, whereas in a high concentration region where the doping concentration is about 1 × 10 18 cm −3 or more. It can be seen that the lifetime of minority carriers is as short as about 300 ns or less. This is presumably due to the Auger recombination mechanism.
On the other hand, when the doping concentration of the main dopant is about 1 × 10 19 cm −3 or more, a Double Shockley type stacking fault is likely to occur. Therefore, the doping concentration of the main dopant is preferably about 1 × 10 18 cm −3 or more and less than about 1 × 10 19 cm −3 .

図４で採用したｐｉｎダイオードのバッファ層では、約２５０℃における少数キャリア寿命が１２０ｎｓ程度であるように、主ドーパントのドーピング濃度を高めて、ｎ型のバッファ層の厚みを変化させている。
またｐｉｎダイオードのバッファ層の上には、半導体装置の耐圧を維持するためのｎ―型の耐圧維持層を積層し、高抵抗のエピ層として成膜している。耐圧維持層の厚みは約１０μｍ、不純物元素のドーピング濃度は約１×１０１６ｃｍ−３程度である。 In the buffer layer of the pin diode employed in FIG. 4, the doping concentration of the main dopant is increased and the thickness of the n-type buffer layer is changed so that the minority carrier lifetime at about 250 ° C. is about 120 ns.
An n − type breakdown voltage maintaining layer for maintaining the breakdown voltage of the semiconductor device is stacked on the buffer layer of the pin diode, and is formed as a high resistance epi layer. The thickness of the breakdown voltage maintaining layer is about 10 μm, and the doping concentration of the impurity element is about 1 × 10 16 cm −3 .

また耐圧維持層の上部の一部には、Ａｌを不純物元素としてイオン注入して、ｐ型のアノード領域を形成している。アノード領域の厚みは約０．３μｍ、Ａｌのドーピング濃度は約１×１０２０ｃｍ−３程度のボックスプロファイルに設定している。またアノード領域の上面にはアノード電極を成膜して設けると共に、裏面側でｎ型のカソード領域をなす基板の下面には、カソード電極を成膜して設けている。またｐｉｎダイオードの端部の耐圧を向上させるために、耐圧維持層の上部のアノード領域の周囲にＡｌをイオン注入して、アノード領域より低濃度のｐ型の半導体領域をさらに形成し、接合終端（ＪＴＥ）構造を具備させている。 A p-type anode region is formed on a part of the upper portion of the breakdown voltage maintaining layer by ion implantation of Al as an impurity element. The anode region has a thickness of about 0.3 μm, and the Al doping concentration is set to a box profile of about 1 × 10 20 cm −3 . An anode electrode is formed on the upper surface of the anode region, and a cathode electrode is formed on the lower surface of the substrate forming the n-type cathode region on the back side. In order to improve the breakdown voltage at the end of the pin diode, Al is ion-implanted around the anode region above the breakdown voltage maintaining layer to further form a p-type semiconductor region having a lower concentration than the anode region, thereby terminating the junction. (JTE) structure.

図４に示すように、エピタキシャルウェハのバッファ層の厚みが厚くなるほど、帯状積層欠陥の発生頻度は低下していることがわかる。図４の結果より、少数キャリア寿命が１２０ｎｓ程度である場合、帯状積層欠陥の発生を零（ゼロ）にするには、バッファ層の厚みは少なくとも１０μｍ以上、より確実性を高めるためには１５μｍ以上であることが望ましい。   As shown in FIG. 4, it can be seen that as the buffer layer of the epitaxial wafer becomes thicker, the occurrence frequency of strip-like stacking faults decreases. From the results shown in FIG. 4, when the minority carrier lifetime is about 120 ns, the thickness of the buffer layer is at least 10 μm or more in order to reduce the occurrence of strip stacking faults to zero, and 15 μm or more to increase the reliability. It is desirable that

しかしバッファ層の厚みを厚くすると、エピタキシャル成長時の成膜プロセスのコストが増大する。そこで本発明者らは、研究の結果、少数キャリア寿命を更に短くすることを試み、帯状積層欠陥の発生頻度が零となる変化点をなすバッファ層の厚みを小さくするように試みた。そして、例えば厚みを５μｍ程度以下に抑えてバッファ層を成膜した場合であっても、帯状積層欠陥の発生頻度を著しく低下させることができるという知見を得た。この知見に基づいて行われた実験結果の一例を図５のグラフ図に示す。   However, increasing the thickness of the buffer layer increases the cost of the film formation process during epitaxial growth. Accordingly, as a result of research, the present inventors have attempted to further shorten the minority carrier lifetime, and have attempted to reduce the thickness of the buffer layer forming the changing point at which the occurrence frequency of the band-like stacking fault becomes zero. Further, for example, even when the buffer layer is formed with the thickness being suppressed to about 5 μm or less, it has been found that the occurrence frequency of the band-like stacking fault can be remarkably reduced. An example of the results of experiments conducted based on this finding is shown in the graph of FIG.

図５中には、エピタキシャルウェハに、厚みを約５μｍとし、少数キャリア寿命を変化させて成膜したバッファ層を設け、このエピタキシャルウェハを半導体ウェハとして用いたｐｉｎダイオードに、６００Ａ／ｃｍ２で１時間程度の通電を行い、少数キャリア寿命と帯状積層欠陥の発生頻度との相関を調べた結果が示されている。 In FIG. 5, a buffer layer is formed on an epitaxial wafer with a thickness of about 5 μm and a minority carrier lifetime being changed, and a pin diode using this epitaxial wafer as a semiconductor wafer is provided with 1 at 600 A / cm 2 . The figure shows the result of conducting the energization for about an hour and investigating the correlation between the minority carrier lifetime and the occurrence frequency of the band-like stacking fault.

図５に示したように、少数キャリア寿命を短くするほど、帯状積層欠陥の発生頻度が低下する。特に、少数キャリア寿命が１００ｎｓ以下である場合、帯状積層欠陥の発生頻度が零となることがわかる。少数キャリア寿命を短くする方法としては、主ドーパントの濃度を高める方法が挙げられるが、先に述べたダブルショックレー（Double Shockley）型積層欠陥の発生の懸念があるために少数キャリア寿命を十分に小さくすることが困難である。そこで筆者らは深い準位を形成する副ドーパントの濃度を高めることにより、１００ｎｓ以下の短い少数キャリア寿命を得ることができた。このようにして筆者らは５μｍ程度の実用的な膜厚のバッファ層で帯状積層欠陥の発生を防止することができた。原理的には少数キャリア寿命が短くなるほど、バッファ層膜厚を薄くすることができるが、０．１μｍ以下に薄くなると膜厚の制御が難しくなる。バッファ層膜厚としては０．１μｍ以上５μｍ以下程度が望ましい。   As shown in FIG. 5, as the minority carrier lifetime is shortened, the frequency of occurrence of strip-like stacking faults decreases. In particular, it can be seen that when the minority carrier lifetime is 100 ns or less, the occurrence frequency of the strip-like stacking fault becomes zero. As a method of shortening the minority carrier lifetime, there is a method of increasing the concentration of the main dopant. However, since there is a concern of occurrence of the Double Shockley type stacking fault described above, the minority carrier lifetime is sufficiently increased. It is difficult to make it smaller. Therefore, the authors were able to obtain a short minority carrier lifetime of 100 ns or less by increasing the concentration of the subdopant that forms a deep level. In this way, the authors were able to prevent the occurrence of strip stacking faults with a buffer layer having a practical thickness of about 5 μm. In principle, the shorter the minority carrier lifetime, the thinner the buffer layer thickness. However, when the thickness becomes 0.1 μm or less, it becomes difficult to control the film thickness. The buffer layer thickness is preferably about 0.1 μm or more and 5 μm or less.

特許第４３６４９４５号公報では少数キャリア寿命を短くするために、エピタキシャル成長時に再結合中心を形成する不純物を導入することが示されている。しかしながら、発明者らが検討した結果、従来の再結合中心による少数キャリア寿命の低減は、１５０℃程度以上の高温にすると効果が薄れ、長寿命になってしまうことが判明した。例えば図６のグラフ図中の○印のデータ点で例示するように、主ドーパントであるＮの濃度を５×１０１７ｃｍ−３程度としたときエピタキシャルウェハの場合、少数キャリア寿命は、温度が１５０℃では４０ｎｓを超え、更に温度が２５０℃では１７０ｎｓ以上に到達する。 Japanese Patent No. 4364945 discloses introducing impurities that form recombination centers during epitaxial growth in order to shorten the minority carrier lifetime. However, as a result of investigations by the inventors, it has been found that the reduction of the minority carrier lifetime due to the conventional recombination center is less effective at a high temperature of about 150 ° C. or more, resulting in a long lifetime. For example, as exemplified by the data points marked with a circle in the graph of FIG. 6, when the concentration of N as the main dopant is about 5 × 10 17 cm −3 , the minority carrier lifetime is At 150 ° C., it exceeds 40 ns, and when the temperature is 250 ° C., it reaches 170 ns or more.

一方で、発明者らが提案する主ドーパントの濃度を１×１０１８ｃｍ−３程度以上に高める方法では、図６中の菱形のデータ点で示すように、１５０℃程度以上の高温においても短い少数キャリア寿命を保てることが判明した。菱形のデータ点で示したエピタキシャルウェハは、主ドーパントであるＮの濃度を５×１０１８ｃｍ−３程度とした。また少数キャリア寿命は、温度が１５０℃であっても２０ｎｓ程度に留まると共に、更に温度が２５０℃に上昇しても、６０ｎｓ未満に抑えることができた。これは再結合中心による再結合メカニズムは高温では有効に働かなくなる一方、発明者らの提案する手法はオージェ再結合メカニズムを利用しており温度依存性が小さいためと考えられる。 On the other hand, the method proposed by the inventors to increase the concentration of the main dopant to about 1 × 10 18 cm −3 or more is short even at a high temperature of about 150 ° C. or more as shown by the diamond data points in FIG. It has been found that the minority carrier life can be maintained. In the epitaxial wafer indicated by the diamond data points, the concentration of N as the main dopant was set to about 5 × 10 18 cm −3 . Further, the minority carrier lifetime remained at about 20 ns even when the temperature was 150 ° C., and even when the temperature further increased to 250 ° C., it could be suppressed to less than 60 ns. This is thought to be because the recombination mechanism due to the recombination centers does not work effectively at high temperatures, whereas the method proposed by the inventors uses the Auger recombination mechanism and is less temperature dependent.

（半導体装置の製造方法）
次に、第１の実施の形態に係る半導体装置の製造方法を、ｐｉｎダイオードを製造する場合を例として、図７〜図９を参照して説明する。
まず、図７の断面図で示したようなエピタキシャルウェハを半導体ウェハとして用意する。図７中には、カソード領域となるｎ＋型のＳｉＣからなる基板２１、この基板２１の上に設けられた高濃度のｎ＋型のバッファ層２２及びこのバッファ層２２の上に設けられた低濃度のｎ−型の耐圧維持層２３の３層構造を有するエピタキシャルウェハが例示されている。耐圧維持層２３は、ｐｉｎダイオードの真性半導体層（ｉ層）として機能する。 (Method for manufacturing semiconductor device)
Next, the manufacturing method of the semiconductor device according to the first embodiment will be described with reference to FIGS. 7 to 9 by taking as an example the case of manufacturing a pin diode.
First, an epitaxial wafer as shown in the sectional view of FIG. 7 is prepared as a semiconductor wafer. In FIG. 7, a substrate 21 made of n + type SiC serving as a cathode region, a high concentration n + type buffer layer 22 provided on the substrate 21, and a buffer layer 22 provided on the buffer layer 22. An epitaxial wafer having a three-layer structure of a low concentration n − -type breakdown voltage maintaining layer 23 is illustrated. The breakdown voltage maintaining layer 23 functions as an intrinsic semiconductor layer (i layer) of the pin diode.

次に図８の断面図に示すように、ｐ型を呈するＡｌイオンを耐圧維持層２３のバッファ層２２と反対側の表面に、例えばイオン注入法により注入すると共に、注入後に所定の活性化処理を施して、耐圧維持層２３の上部の一部に高濃度のｐ＋型のアノード領域２４を形成する。アノード領域２４は、本発明の「第２導電型の半導体領域」に相当する。尚、図８中には、アノード領域２４の周囲の耐圧維持層２３の上部にＪＴＥ構造をなすために、更にＡｌイオンを注入して、アノード領域２４より低濃度のｐ型の半導体領域２５，２５が形成された場合のｐｉｎダイオードが例示されている。 Next, as shown in the cross-sectional view of FIG. 8, p-type Al ions are implanted into the surface of the breakdown voltage maintaining layer 23 opposite to the buffer layer 22 by, for example, ion implantation, and a predetermined activation process is performed after the implantation. As a result, a high-concentration p + -type anode region 24 is formed in part of the upper portion of the breakdown voltage maintaining layer 23. The anode region 24 corresponds to the “second conductivity type semiconductor region” of the present invention. In FIG. 8, in order to form a JTE structure above the breakdown voltage maintaining layer 23 around the anode region 24, Al ions are further implanted to form p-type semiconductor regions 25, having a lower concentration than the anode region 24. A pin diode when 25 is formed is illustrated.

次に図９の断面図に示すように、ニッケル（Ｎｉ）等で、アノード領域２４の上面にアノード電極２７を成膜すると共に、裏面側をなす基板２１をカソード領域として、カソード領域の下面にカソード電極２６を成膜する。図７〜図９を参照して説明した一連の工程により、バッファ層２２をカソード側に有するｐｉｎダイオードが、半導体装置として製造できる。   Next, as shown in the cross-sectional view of FIG. 9, an anode electrode 27 is formed on the upper surface of the anode region 24 with nickel (Ni) or the like, and the substrate 21 on the back surface side is used as the cathode region and is formed on the lower surface of the cathode region. A cathode electrode 26 is formed. Through the series of steps described with reference to FIGS. 7 to 9, a pin diode having the buffer layer 22 on the cathode side can be manufactured as a semiconductor device.

第１の実施の形態に係る半導体装置の製造方法によれば、エピタキシャルウェハのバッファ層２２によって少数キャリアの捕獲を積極的に促進させることにより、バッファ層２２の厚みを抑制しつつ、大電流でバイポーラ動作させた際にバッファ層２２と基板２１との界面から拡張する帯状積層欠陥の発生を効果的に抑制できる半導体装置を製造することができる。   According to the manufacturing method of the semiconductor device according to the first embodiment, the buffer layer 22 of the epitaxial wafer is actively promoted to capture minority carriers, thereby suppressing the thickness of the buffer layer 22 and increasing the current. A semiconductor device that can effectively suppress the occurrence of strip-like stacking faults extending from the interface between the buffer layer 22 and the substrate 21 when the bipolar operation is performed can be manufactured.

次に、第１の実施の形態に係る半導体装置の製造方法を用いた実施例１を説明する。まず＜１１−２０＞方向に４°オフしたｎ＋型の４Ｈ−ＳｉＣからなる基板２１のＳｉ面を、化学的機械研磨（ＣＭＰ）した径（φ）３インチのＳｉＣ基板からなる基板２１を、エピタキシャル成長装置の中に入れた。そして温度約１６８０℃で圧力１０．３ｋＰａ程度の雰囲気中に、原料ガスとしてＨ２を流量約１．６９×１０２Ｐａ・ｍ３／ｓ（約１００ｓｌｍ）、モノシラン（ＳｉＨ４）を流量約１４３．６５×１０−３Ｐａ・ｍ３／ｓ（約８５ｓｃｃｍ）、プロパン（Ｃ３Ｈ８）を流量約３８．８７×１０−３Ｐａ・ｍ３／ｓ（約２３ｓｃｃｍ）、窒素（Ｎ２）を流量約８４．５×１０−３Ｐａ・ｍ３／ｓ（約５０ｓｃｃｍ）及びトリエチルボロン（Ｃ６Ｈ１５Ｂ）を流量約１６．９×１０−３Ｐａ・ｍ３／ｓ（約１０ｓｃｃｍ）でそれぞれ導入して、３０分間程度、ＳｉＣの単結晶層のエピタキシャル成長を行った。Ｎは主ドーパントであり、Ｂは副ドーパントである。 Next, Example 1 using the method for manufacturing a semiconductor device according to the first embodiment will be described. First, a substrate 21 made of an SiC substrate having a diameter (φ) of 3 inches obtained by chemically and mechanically polishing (CMP) the Si surface of the substrate 21 made of n + -type 4H—SiC that is turned off by 4 ° in the <11-20> direction. In an epitaxial growth apparatus. Then, in an atmosphere at a temperature of about 1680 ° C. and a pressure of about 10.3 kPa, H 2 as a raw material gas has a flow rate of about 1.69 × 10 2 Pa · m 3 / s (about 100 slm), and monosilane (SiH 4 ) has a flow rate of about 143. .65 × 10 −3 Pa · m 3 / s (about 85 sccm), propane (C 3 H 8 ) at a flow rate of about 38.87 × 10 −3 Pa · m 3 / s (about 23 sccm), nitrogen (N 2 ) The flow rate is about 84.5 × 10 −3 Pa · m 3 / s (about 50 sccm) and the triethyl boron (C 6 H 15 B) is about 16.9 × 10 −3 Pa · m 3 / s (about 10 sccm). Then, the SiC single crystal layer was epitaxially grown for about 30 minutes. N is a main dopant and B is a subdopant.

そして基板２１のＳｉ面側に、エピタキシャル成長層を厚さ約５μｍ成膜し、Ｎをドーピング濃度５×１０１８ｃｍ−３程度、Ｂをドーピング濃度１×１０１５ｃｍ−３程度でそれぞれ添加したバッファ層２２を形成した。すなわち実施例１では、エピタキシャル成長装置の内側で、Ｎ及びＢを並行して同時に、かつ、それぞれのドーピング濃度を制御してＳｉＣの単結晶層に添加し、バッファ層２２をエピタキシャル成長した。 Then, an epitaxial growth layer having a thickness of about 5 μm is formed on the Si surface side of the substrate 21, and N is added at a doping concentration of about 5 × 10 18 cm −3 and B is added at a doping concentration of about 1 × 10 15 cm −3. Layer 22 was formed. That is, in Example 1, the buffer layer 22 was epitaxially grown inside the epitaxial growth apparatus by simultaneously adding N and B to the SiC single crystal layer simultaneously while controlling the respective doping concentrations.

次に、バッファ層２２のエピタキシャル成長条件のうち、ＳｉＨ４を流量約３１２．６５×１０−３Ｐａ・ｍ３／ｓ（約１８５ｓｃｃｍ）、Ｃ３Ｈ８を流量約１１６．６１×１０−３Ｐａ・ｍ３／ｓ（約６９ｓｃｃｍ）及びＮ２を流量約８．４５×１０−３Ｐａ・ｍ３／ｓ（約５ｓｃｃｍ）にそれぞれ変更すると共に、他の原料ガスの導入条件は同じ条件で、７時間程度、ＳｉＣの単結晶層のエピタキシャル成長を行った。そしてバッファ層２２の上に、Ｎをドーピング濃度１×１０１４ｃｍ−３程度で添加した耐圧維持層２３を厚さ約１２０μｍでエピタキシャル成長した。 Next, among the epitaxial growth conditions of the buffer layer 22, SiH 4 has a flow rate of about 312.65 × 10 −3 Pa · m 3 / s (about 185 sccm), and C 3 H 8 has a flow rate of about 116.61 × 10 −3 Pa.・ M 3 / s (about 69 sccm) and N 2 were respectively changed to a flow rate of about 8.45 × 10 −3 Pa · m 3 / s (about 5 sccm), and the other source gas introduction conditions were the same, The SiC single crystal layer was epitaxially grown for about 7 hours. On the buffer layer 22, a breakdown voltage maintaining layer 23 to which N was added at a doping concentration of about 1 × 10 14 cm −3 was epitaxially grown to a thickness of about 120 μm.

そして耐圧維持層２３の上部の一部に、Ａｌを不純物元素としてイオン注入して、厚みを約０．３μｍ、ドーピング濃度を約１×１０２０ｃｍ−３程度のボックスプロファイルに設定したアノード領域２４を形成した。またアノード領域２４の上面にアノード電極２７を成膜すると共に、基板２１の下面にカソード電極２６を成膜した。また半導体装置の端部の耐圧を向上させるために、耐圧維持層２３の上部のアノード領域２４の周囲にＡｌをイオン注入して、アノード領域２４より低濃度のｐ型の半導体領域２５，２５をさらに形成し、ＪＴＥ構造を備えるｐｉｎダイオードを複数個製造した。 Then, an anode region 24 having a box profile with a thickness of about 0.3 μm and a doping concentration of about 1 × 10 20 cm −3 is implanted into a part of the upper portion of the breakdown voltage maintaining layer 23 by ion implantation of Al as an impurity element. Formed. An anode electrode 27 was formed on the upper surface of the anode region 24, and a cathode electrode 26 was formed on the lower surface of the substrate 21. In order to improve the breakdown voltage of the end portion of the semiconductor device, Al ions are implanted around the anode region 24 above the breakdown voltage maintaining layer 23 to form p-type semiconductor regions 25 and 25 having a lower concentration than the anode region 24. Further, a plurality of pin diodes having a JTE structure were formed.

尚、バッファ層２２の２５０℃における少数キャリア寿命は、主ドーパント及び副ドーパントのドーピング濃度の調節により５０ｎｓに制御して設定した。そして、それぞれのｐｉｎダイオードに６００Ａ／ｃｍ２で１時間程度の通電実験を行い、帯状積層欠陥の発生頻度を調べた。
通電実験の結果、実施例１に係るｐｉｎダイオードには、バッファ層２２が５μｍ程度の厚みであっても、帯状積層欠陥は一切発生せず、バッファ層２２の厚みの抑制と、製品としてのｐｉｎダイオードの品質の向上とを好適に両立できることがわかった。 The minority carrier lifetime at 250 ° C. of the buffer layer 22 was set to 50 ns by adjusting the doping concentrations of the main dopant and the sub-dopant. Then, each pin diode was subjected to an energization experiment at 600 A / cm 2 for about 1 hour, and the occurrence frequency of strip-like stacking faults was examined.
As a result of the energization experiment, even when the buffer layer 22 has a thickness of about 5 μm, no strip-like stacking fault occurs in the pin diode according to Example 1, and the thickness of the buffer layer 22 is suppressed and the pin as a product is produced. It has been found that the improvement in the quality of the diode can be suitably achieved.

（比較例）
一方、主ドーパント、副ドーパントのドーピング濃度の調節による少数キャリア寿命の制御を行わなかったｐｉｎダイオードを比較例として用意した。そして比較例に係るｐｉｎダイオードを、実施例１の場合と同様の通電実験を行ってバイポーラ動作させた後、アノード電極を剥離し、室温で４２０ｎｍ近傍のバンドパスフィルターを用いて、エピタキシャルウェハに対してフォトルミネッセンス発光の測定を行った。その結果、比較例に係るｐｉｎダイオードには、図１０の上面図中に白みがかった略台形状の領域で示すように、バッファ層２２と基板２１との界面から拡がる帯状積層欠陥ＳＦｂが観察された。図１０中には、エピタキシャルウェハの上下の両端に亘って長く延びた帯状積層欠陥ＳＦｂが、三角形状積層欠陥ＳＦｔ１，ＳＦｔ２と共に発光した状態が示されている。 (Comparative example)
On the other hand, a pin diode in which the minority carrier lifetime was not controlled by adjusting the doping concentrations of the main dopant and the sub-dopant was prepared as a comparative example. The pin diode according to the comparative example was subjected to a bipolar operation by conducting the same energization experiment as in Example 1. Then, the anode electrode was peeled off, and a band-pass filter near 420 nm at room temperature was used for the epitaxial wafer. The photoluminescence emission was measured. As a result, in the pin diode according to the comparative example, as shown by the substantially trapezoidal region that is whitened in the top view of FIG. 10, the band-like stacking fault SFb extending from the interface between the buffer layer 22 and the substrate 21 is observed. It was done. FIG. 10 shows a state in which the strip-like stacking fault SFb extending long across the upper and lower ends of the epitaxial wafer emits light together with the triangular stacking faults SFt 1 and SFt 2 .

＜第２の実施の形態＞
第２の実施の形態における主ドーパントと副ドーパントの組み合わせパターン及びそれぞれの濃度は、第１の実施の形態の場合と同じである。
（エピタキシャルウェハの製造方法）
次に第２の実施形態に関わるエピタキシャルウェハの製造方法を図１１をもとに説明する。 <Second Embodiment>
The combination pattern and the concentration of the main dopant and the sub-dopant in the second embodiment are the same as those in the first embodiment.
(Epitaxial wafer manufacturing method)
Next, an epitaxial wafer manufacturing method according to the second embodiment will be described with reference to FIG.

まず図１のステップＳ１〜Ｓ４、Ｓ７〜Ｓ８を行い（ステップＳａ）、基板２１上に主ドーパントのみをドープしたバッファ層２２を形成したウェハ（下地基板）を作製する。その後、当該ウェハに対し、イオン注入装置を用いて副ドーパントのイオン注入を実施する（ステップＳ９〜Ｓ１１）。続いて活性化熱処理装置を用いて当該ウェハの熱処理を行い、注入したイオンを活性化する（ステップＳ１２〜Ｓ１４）その後、図１のステップＳ１〜Ｓ４、Ｓ７〜Ｓ８を行い、耐圧維持層２３を形成する（ステップＳｂ）。上記はイオン注入の後に引き続いて活性化熱処理を実施する場合であるが、活性化熱処理を耐圧維持層２３形成後に実施してもよい。その際は、Ｓ１２〜Ｓ１４をステップＳｂの後に実施する。以上のようにして第２の実施形態に関わるエピタキシャルウェハを製造する。   First, steps S1 to S4 and S7 to S8 of FIG. 1 are performed (step Sa), and a wafer (underlying substrate) in which the buffer layer 22 doped only with the main dopant is formed on the substrate 21 is manufactured. Thereafter, ion implantation of a sub-dopant is performed on the wafer using an ion implantation apparatus (steps S9 to S11). Subsequently, the wafer is heat-treated using an activation heat treatment apparatus to activate the implanted ions (steps S12 to S14). Thereafter, steps S1 to S4 and S7 to S8 in FIG. Form (step Sb). The above is a case where the activation heat treatment is performed subsequently after the ion implantation. However, the activation heat treatment may be performed after the breakdown voltage maintaining layer 23 is formed. In that case, S12-S14 are implemented after step Sb. As described above, the epitaxial wafer according to the second embodiment is manufactured.

（半導体装置の製造方法）
第２の実施の形態に係る半導体装置の製造方法については、図７〜図９を参照して説明した第１の実施の形態に係る半導体装置の製造方法と同様であるため、重複説明を省略する。第２の実施の形態に係る半導体装置の製造方法によれば、第１の実施の形態に係る半導体装置の製造方法と同様に、バッファ層２２の厚みを抑制しつつ、大電流でバイポーラ動作させた際にバッファ層２２と基板２１との界面から拡張する帯状積層欠陥の発生を効果的に抑制できる半導体装置を製造することができる。 (Method for manufacturing semiconductor device)
The method for manufacturing the semiconductor device according to the second embodiment is the same as the method for manufacturing the semiconductor device according to the first embodiment described with reference to FIGS. To do. According to the method for manufacturing a semiconductor device according to the second embodiment, as in the method for manufacturing a semiconductor device according to the first embodiment, a bipolar operation is performed with a large current while suppressing the thickness of the buffer layer 22. In this case, it is possible to manufacture a semiconductor device that can effectively suppress the occurrence of strip-like stacking faults extending from the interface between the buffer layer 22 and the substrate 21.

次に、第２の実施の形態に係る半導体装置の製造方法を用いた実施例２を説明する。＜１１−２０＞方向に４°オフしたｎ＋型の４Ｈ−ＳｉＣからなる基板２１のＳｉ面を、化学的機械研磨（ＣＭＰ）した径（φ）３インチのＳｉＣ基板からなる基板２１を、エピタキシャル成長装置の中に入れた。そして温度約１６８０℃で圧力１０．３ｋＰａ程度の雰囲気中に、原料ガスとしてＨ２を流量約１．６９×１０２Ｐａ・ｍ３／ｓ（約１００ｓｌｍ）、ＳｉＨ４を流量約１４３．６５×１０−３Ｐａ・ｍ３／ｓ（８５ｓｃｃｍ）、Ｃ３Ｈ８を流量約３８．８７×１０−３Ｐａ・ｍ３／ｓ（約２３ｓｃｃｍ）及びＮ２を流量約８４．５×１０−３Ｐａ・ｍ３／ｓ（約５０ｓｃｃｍ）でそれぞれ導入して、３０分間程度、ＳｉＣの単結晶層のエピタキシャル成長を行って、単結晶層を厚さ約５μｍ成膜した。Ｎは主ドーパントである。 Next, Example 2 using the semiconductor device manufacturing method according to the second embodiment will be described. A substrate 21 made of a SiC substrate having a diameter (φ) of 3 inches obtained by chemically and mechanically polishing (CMP) the Si surface of the substrate 21 made of n + -type 4H—SiC, which is turned off by 4 ° in the <11-20> direction, Placed in an epitaxial growth apparatus. Then, in an atmosphere at a temperature of about 1680 ° C. and a pressure of about 10.3 kPa, H 2 as a source gas has a flow rate of about 1.69 × 10 2 Pa · m 3 / s (about 100 slm), and SiH 4 has a flow rate of about 143.65 ×. 10 −3 Pa · m 3 / s (85 sccm), C 3 H 8 with a flow rate of about 38.87 × 10 −3 Pa · m 3 / s (about 23 sccm), and N 2 with a flow rate of about 84.5 × 10 −3. Each was introduced at Pa · m 3 / s (about 50 sccm), and the SiC single crystal layer was epitaxially grown for about 30 minutes to form a single crystal layer having a thickness of about 5 μm. N is the main dopant.

次に、ＳｉＣの単結晶層が成膜された基板２１をイオン注入装置５０に搬送し、注入室５７の内部に固定して、単結晶層にＶイオンを、７×１０１１ｃｍ−２程度のドーズ量で注入した。Ｖは副ドーパントである。その後、基板２１に活性化のための熱処理を施し、Ｖが主ドーパントのドーピング濃度より低く、１×１０１４ｃｍ−３程度以上、５×１０１８ｃｍ−３程度未満の範囲内で添加されたバッファ層２２を形成した。 Next, the substrate 21 on which the single crystal layer of SiC is formed is transported to the ion implantation apparatus 50 and fixed inside the implantation chamber 57, and V ions are about 7 × 10 11 cm −2 in the single crystal layer. The dose was injected at a dose of. V is a minor dopant. Thereafter, the substrate 21 was heat-treated for activation, and V was lower than the doping concentration of the main dopant, and was added within a range of about 1 × 10 14 cm −3 or more and less than about 5 × 10 18 cm −3 . A buffer layer 22 was formed.

次に実施例１の場合と同様に、バッファ層２２のエピタキシャル成長条件のうち、ＳｉＨ４を流量約３１２．６５×１０−３Ｐａ・ｍ３／ｓ（約１８５ｓｃｃｍ）、Ｃ３Ｈ８を流量約１１６．６１×１０−３Ｐａ・ｍ３／ｓ（約６９ｓｃｃｍ）及びＮ２を流量約８．４５×１０−３Ｐａ・ｍ３／ｓ（約５ｓｃｃｍ）にそれぞれ変更すると共に、他の原料ガスの導入条件は同じ条件で、７時間程度、ＳｉＣの単結晶層のエピタキシャル成長を行った。そしてバッファ層２２の上に、Ｎをドーピング濃度１×１０１４ｃｍ−３程度で添加した耐圧維持層２３を、厚さ約１２０μｍでエピタキシャル成長した。 Next, in the same manner as in Example 1, among the epitaxial growth conditions of the buffer layer 22, SiH 4 has a flow rate of about 312.65 × 10 −3 Pa · m 3 / s (about 185 sccm), and C 3 H 8 has a flow rate of about 116.61 × 10 −3 Pa · m 3 / s (about 69 sccm) and N 2 are respectively changed to a flow rate of about 8.45 × 10 −3 Pa · m 3 / s (about 5 sccm), and other source gases The same conditions were used for epitaxial growth of the SiC single crystal layer for about 7 hours. On the buffer layer 22, a breakdown voltage maintaining layer 23 to which N was added at a doping concentration of about 1 × 10 14 cm −3 was epitaxially grown to a thickness of about 120 μm.

そして耐圧維持層２３の上部の一部に、Ａｌを不純物元素としてイオン注入して、厚みを約０．３μｍ、ドーピング濃度を約１×１０２０ｃｍ−３程度のボックスプロファイルに設定したｐ＋型のアノード領域２４を形成した。またアノード領域２４の上面にアノード電極２７を成膜すると共に、基板２１の下面にカソード電極２６を成膜した。また半導体装置の端部の耐圧を向上させるために、耐圧維持層２３の上部のアノード領域２４の周囲にＡｌをイオン注入して、アノード領域２４より低濃度のｐ型の半導体領域２５をさらに形成し、ＪＴＥ構造を備えるｐｉｎダイオードを複数個製造した。 Then, a part of the upper portion of the breakdown voltage maintaining layer 23 is ion-implanted with Al as an impurity element. The p + type has a box profile of about 0.3 μm in thickness and about 1 × 10 20 cm −3 in doping concentration. The anode region 24 was formed. An anode electrode 27 was formed on the upper surface of the anode region 24, and a cathode electrode 26 was formed on the lower surface of the substrate 21. Further, in order to improve the breakdown voltage of the end portion of the semiconductor device, Al is ion-implanted around the anode region 24 above the breakdown voltage maintaining layer 23 to further form a p-type semiconductor region 25 having a lower concentration than the anode region 24. A plurality of pin diodes having a JTE structure were manufactured.

尚、バッファ層２２の２５０℃における少数キャリア寿命は、主ドーパントおよび副ドーパントのドーピング濃度の調節により８０ｎｓに制御して設定した。そして、それぞれのｐｉｎダイオードに６００Ａ／ｃｍ２で１時間程度の通電実験を行い、帯状積層欠陥の発生頻度を調べた。
通電実験の結果、イオン注入を用いてバッファ層２２を形成した実施例２に係るｐｉｎダイオードは、バッファ層２２が５μｍ程度の厚みであっても、帯状積層欠陥は一切発生せず、実施例１の場合と同様に、バッファ層２２の厚みの抑制と、製品としてのｐｉｎダイオードの品質の向上とを好適に両立できることがわかった。 The minority carrier lifetime at 250 ° C. of the buffer layer 22 was set by controlling it to 80 ns by adjusting the doping concentrations of the main dopant and the sub-dopant. Then, each pin diode was subjected to an energization experiment at 600 A / cm 2 for about 1 hour, and the occurrence frequency of strip-like stacking faults was examined.
As a result of the energization experiment, the pin diode according to Example 2 in which the buffer layer 22 was formed by ion implantation did not cause any strip-like stacking fault even when the buffer layer 22 had a thickness of about 5 μm. As in the case of, it has been found that the suppression of the thickness of the buffer layer 22 and the improvement of the quality of the pin diode as a product can be suitably achieved.

また第１及び第２の実施の形態に係る半導体装置の製造方法では、ｐｉｎダイオードを例として説明したが、半導体装置としてはｐｉｎダイオードに限定されるものではない。例えば、ｉ層若しくはｉ層に近似できる程度の低濃度の半導体層をｐｎ接合の間に挟まない「ｐｎダイオード」、又は、ツェナーダイオードやトンネルダイオードのような「ｐ＋ｎ＋ダイオード」等でも構わない。 In the semiconductor device manufacturing methods according to the first and second embodiments, the pin diode has been described as an example. However, the semiconductor device is not limited to the pin diode. For example, an “pn diode” in which an i layer or a semiconductor layer having a low concentration that can be approximated to an i layer is not sandwiched between pn junctions, or a “p + n + diode” such as a Zener diode or a tunnel diode may be used. Absent.

更に本発明は、バイポーラトランジスタ、ＩＧＢＴ、サイリスタ等、各種のバイポーラ動作を行う半導体装置や、これらをモノシリックに集積化した半導体集積回路等に適用できる。図７〜図９ではｎ＋型の基板２１の上にｎ＋型のバッファ層２２及びｎ−型の耐圧維持層２３を備えた半導体装置を例示したが、これに限定されず、例えばｐ＋型の基板の上にｐ＋型のバッファ層及びｎ−型の耐圧維持層が設けられた構成であってもよい。 Further, the present invention can be applied to semiconductor devices that perform various bipolar operations such as bipolar transistors, IGBTs, thyristors, and semiconductor integrated circuits in which these are monolithically integrated. Buffer layer 22 and n of the n + -type on the 7-9 in the n + -type substrate 21 - exemplifying a semiconductor device having the type of breakdown voltage sustaining layer 23, but not limited to, for example, p + A configuration in which a p + type buffer layer and an n − type breakdown voltage maintaining layer are provided on a type substrate may be employed.

またＳｉＣと、ＳｉＣとは禁制帯幅の異なる半導体材料とのヘテロ接合をエミッタ・ベース間等に用いたヘテロ接合バイポーラトランジスタ（ＨＢＴ）等にも適用できる。更にＭＯＳＦＥＴのようなユニポーラデバイスに適用した場合であっても、スイッチング時にＭＯＳＦＥＴのボディダイオードに順方向電流が流れるため、本発明を適用すれば、帯状積層欠陥の発生の抑制に効果的である。   The present invention can also be applied to a heterojunction bipolar transistor (HBT) or the like using a heterojunction of SiC and a semiconductor material having a different forbidden band width between an emitter and a base. Further, even when the present invention is applied to a unipolar device such as a MOSFET, a forward current flows through the body diode of the MOSFET at the time of switching. Therefore, the application of the present invention is effective in suppressing the occurrence of strip-like stacking faults.

また図１０中には帯状積層欠陥として、上面から見て上底及び下底が直線状の形態が例示されているが、本発明は他の形態を有する帯状積層欠陥の発生防止についても有効である。例えば矩形状の帯状積層欠陥、或いは矩形状であって矩形の長辺が鋸歯状であるような帯状積層欠陥、或いは台形の高さや矩形の短辺に相当する帯の幅が一定でない帯状積層欠陥等、各種の形態の帯状積層欠陥の発生を防止可能である。
以上のとおり本発明は、上記に記載していない様々な実施の形態等を含むとともに、本発明の技術的範囲は、上記の説明から妥当な特許請求の範囲に係る発明特定事項によってのみ定められるものである。 Further, in FIG. 10, as the strip-like stacking fault, a form in which the upper base and the lower base are linear when viewed from above is illustrated, but the present invention is also effective in preventing the occurrence of strip-like stacking faults having other forms. is there. For example, a rectangular belt-like stacking fault, or a strip-like stacking fault that has a rectangular shape with a long side of a rectangular sawtooth, or a strip-like stacking fault that has a trapezoidal height or a width corresponding to the short side of the rectangle is not constant. Thus, it is possible to prevent the occurrence of strip-like stacking faults in various forms.
As described above, the present invention includes various embodiments and the like not described above, and the technical scope of the present invention is defined only by the invention specifying matters according to the appropriate claims from the above description. Is.

２１ 基板（カソード領域）
２２ バッファ層
２３ 耐圧維持層
２４ アノード領域（半導体領域）
２５ ｐ型の半導体領域
２６ カソード電極
２７ アノード電極
ＳＦｂ 帯状積層欠陥
ＳＦｔ１，ＳＦｔ２ 三角形状積層欠陥 21 Substrate (cathode region)
22 Buffer layer 23 Withstand voltage maintaining layer 24 Anode region (semiconductor region)
25 p-type semiconductor region 26 cathode electrode 27 anode electrode SFb strip-like stacking fault SFt 1 , SFt 2 triangular stacking fault

Claims (13)

炭化珪素の基板と耐圧維持層とを備えるエピタキシャルウェハの製造方法において、
前記基板の上に、導電型を決める主ドーパントを添加すると共に少数キャリアを捕獲する副ドーパントを前記主ドーパントのドーピング濃度より低いドーピング濃度で添加して、前記耐圧維持層から前記基板の方向に流れる前記少数キャリアの捕獲及び消滅を促進する、前記耐圧維持層より低抵抗の、炭化珪素を主成分とするバッファ層をエピタキシャル成長するステップと、
前記バッファ層の上に前記耐圧維持層をエピタキシャル成長するステップと、
を含むことを特徴とするエピタキシャルウェハの製造方法。 In a method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a pressure-resistant maintenance layer,
A main dopant that determines the conductivity type is added on the substrate, and a sub-dopant that captures minority carriers is added at a doping concentration lower than the doping concentration of the main dopant, and flows from the breakdown voltage maintaining layer toward the substrate. Epitaxially growing a buffer layer mainly composed of silicon carbide having a lower resistance than the breakdown voltage maintaining layer, which promotes the capture and annihilation of the minority carriers;
Epitaxially growing the breakdown voltage maintaining layer on the buffer layer;
The manufacturing method of the epitaxial wafer characterized by including this. 前記主ドーパントを、１．０×１０１８ｃｍ−３以上１．０×１０１９ｃｍ−３未満のドーピング濃度で添加することを特徴とする請求項１に記載のエピタキシャルウェハの製造方法。 2. The method for producing an epitaxial wafer according to claim 1, wherein the main dopant is added at a doping concentration of 1.0 × 10 18 cm −3 or more and less than 1.0 × 10 19 cm −3 . 前記バッファ層を、０．１μｍ以上５μｍ以下の厚みで形成することを特徴とする請求項２に記載のエピタキシャルウェハの製造方法。   The method for producing an epitaxial wafer according to claim 2, wherein the buffer layer is formed with a thickness of 0.1 μm to 5 μm. 前記副ドーパントを、前記主ドーパントのドーピング濃度より低濃度となる、１．０×１０１４ｃｍ−３以上５．０×１０１８ｃｍ−３未満の範囲内のドーピング濃度で添加することを特徴とする請求項３に記載のエピタキシャルウェハの製造方法。 The sub-dopant is added at a doping concentration in the range of 1.0 × 10 14 cm −3 or more and less than 5.0 × 10 18 cm −3 , which is lower than the doping concentration of the main dopant. The method for manufacturing an epitaxial wafer according to claim 3. 前記主ドーパントの添加と前記副ドーパントの添加を同時に行うことを特徴とする請求項４に記載のエピタキシャルウェハの製造方法。   The method for producing an epitaxial wafer according to claim 4, wherein the addition of the main dopant and the addition of the sub-dopant are performed simultaneously. 前記主ドーパントの添加を行った後、前記副ドーパントを添加することを特徴とする請求項４に記載のエピタキシャルウェハの製造方法。   The method for producing an epitaxial wafer according to claim 4, wherein the sub-dopant is added after the addition of the main dopant. 前記主ドーパントは、窒素であり、
前記副ドーパントは、アルミニウム、ボロン、バナジウム、チタン、鉄、クロムのうち少なくとも１種類を含むことを特徴とする請求項５又は６に記載のエピタキシャルウェハの製造方法。 The main dopant is nitrogen;
The epitaxial wafer manufacturing method according to claim 5, wherein the sub-dopant includes at least one of aluminum, boron, vanadium, titanium, iron, and chromium. 前記主ドーパントは、アルミニウムであり、
前記副ドーパントは、窒素、ボロン、バナジウム、チタン、鉄、クロムのうち少なくとも１種類を含むことを特徴とする請求項５又は６に記載のエピタキシャルウェハの製造方法。 The main dopant is aluminum;
The epitaxial wafer manufacturing method according to claim 5, wherein the sub-dopant includes at least one of nitrogen, boron, vanadium, titanium, iron, and chromium. 炭化珪素の基板と耐圧維持層とを備えるエピタキシャルウェハの製造方法において、
前記基板の上に、導電型を決める主ドーパントを添加しながら炭化珪素を主成分とする単結晶層をエピタキシャル成長するステップと、
前記単結晶層に、少数キャリアを捕獲する副ドーパントのイオンを前記主ドーパントのドーピング濃度より低いドーピング濃度となるドーズ量でイオン注入するステップと、
前記イオンを活性化して、前記耐圧維持層から前記基板の方向に流れる前記少数キャリアの捕獲及び消滅を促進する、前記耐圧維持層より低抵抗の、バッファ層を前記単結晶層によって形成するステップと、
前記バッファ層の上に前記耐圧維持層をエピタキシャル成長するステップと、
を含むことを特徴とするエピタキシャルウェハの製造方法。 In a method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a pressure-resistant maintenance layer,
Epitaxially growing a single crystal layer mainly composed of silicon carbide on the substrate while adding a main dopant that determines a conductivity type;
Ion-implanting ions of a subdopant that captures minority carriers into the single crystal layer at a dose that provides a doping concentration lower than the doping concentration of the main dopant;
Activating the ions to promote capture and annihilation of the minority carriers flowing from the breakdown voltage maintaining layer toward the substrate, and forming a buffer layer having a lower resistance than the breakdown voltage maintaining layer by the single crystal layer; ,
Epitaxially growing the breakdown voltage maintaining layer on the buffer layer;
The manufacturing method of the epitaxial wafer characterized by including this. 炭化珪素の基板と耐圧維持層とを備えるエピタキシャルウェハにおいて、
前記基板と前記耐圧維持層の間に設けられた、導電型を決める主ドーパントと、少数キャリアを捕獲し前記主ドーパントのドーピング濃度より低いドーピング濃度の副ドーパントとが添加された、前記耐圧維持層から前記基板の方向に流れる前記少数キャリアの捕獲及び消滅を促進する、前記耐圧維持層より低抵抗の、炭化珪素を主成分とするバッファ層を備えることを特徴とするエピタキシャルウェハ。 In an epitaxial wafer comprising a silicon carbide substrate and a pressure-resistant maintenance layer,
The breakdown voltage maintaining layer provided between the substrate and the breakdown voltage maintaining layer, to which a main dopant that determines a conductivity type and a sub-dopant that captures minority carriers and has a doping concentration lower than the doping concentration of the main dopant is added. An epitaxial wafer comprising a buffer layer mainly composed of silicon carbide having a lower resistance than the breakdown voltage maintaining layer, which promotes the capture and annihilation of the minority carriers flowing in the direction from the substrate to the substrate. 炭化珪素の基板と耐圧維持層とを備える半導体装置の製造方法において、
前記基板の上に、導電型を決める主ドーパントを添加すると共に少数キャリアを捕獲する副ドーパントを前記主ドーパントのドーピング濃度より低いドーピング濃度で添加して、前記耐圧維持層から前記基板の方向に流れる前記少数キャリアの捕獲及び消滅を促進する、前記耐圧維持層より低抵抗の、炭化珪素を主成分とするバッファ層をエピタキシャル成長する工程と、
前記バッファ層の上に第１導電型の前記耐圧維持層をエピタキシャル成長する工程と、
前記耐圧維持層の上部の一部に第２導電型の半導体領域を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 In a method for manufacturing a semiconductor device comprising a silicon carbide substrate and a pressure-resistant maintenance layer,
A main dopant that determines the conductivity type is added on the substrate, and a sub-dopant that captures minority carriers is added at a doping concentration lower than the doping concentration of the main dopant, and flows from the breakdown voltage maintaining layer toward the substrate. A step of epitaxially growing a buffer layer mainly composed of silicon carbide having a lower resistance than the breakdown voltage maintaining layer, which promotes the capture and annihilation of the minority carriers;
Epitaxially growing the breakdown voltage maintaining layer of the first conductivity type on the buffer layer;
Forming a second conductivity type semiconductor region in a part of the upper portion of the breakdown voltage maintaining layer;
A method for manufacturing a semiconductor device, comprising: 炭化珪素の基板と耐圧維持層とを備える半導体装置の製造方法において、
前記基板の上に、導電型を決める主ドーパントを添加しながら炭化珪素を主成分とする単結晶層をエピタキシャル成長する工程と、
前記単結晶層に、少数キャリアを捕獲する副ドーパントのイオンを前記主ドーパントのドーピング濃度より低いドーピング濃度となるドーズ量でイオン注入する工程と、
前記イオンを活性化して、前記耐圧維持層から前記基板の方向に流れる前記少数キャリアの捕獲及び消滅を促進する、前記耐圧維持層より低抵抗の、バッファ層を前記単結晶層によって形成する工程と、
前記バッファ層の上に第１導電型の前記耐圧維持層をエピタキシャル成長する工程と、
前記耐圧維持層の上部の一部に第２導電型の半導体領域を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 In a method for manufacturing a semiconductor device comprising a silicon carbide substrate and a pressure-resistant maintenance layer,
Epitaxially growing a single crystal layer mainly composed of silicon carbide while adding a main dopant that determines a conductivity type on the substrate;
A step of ion-implanting ions of a sub-dopant that captures minority carriers into the single crystal layer at a dose that provides a doping concentration lower than the doping concentration of the main dopant;
Activating the ions to promote capture and annihilation of the minority carriers flowing from the breakdown voltage maintaining layer toward the substrate, and forming a buffer layer having a lower resistance than the breakdown voltage maintaining layer by the single crystal layer; ,
Epitaxially growing the breakdown voltage maintaining layer of the first conductivity type on the buffer layer;
Forming a second conductivity type semiconductor region in a part of the upper portion of the breakdown voltage maintaining layer;
A method for manufacturing a semiconductor device, comprising: 炭化珪素の基板と耐圧維持層とを備える半導体装置において、
前記基板と前記耐圧維持層の間に設けられた、導電型を決める主ドーパントと、少数キャリアを捕獲し前記主ドーパントのドーピング濃度より低いドーピング濃度の副ドーパントとが添加された、前記耐圧維持層から前記基板の方向に流れる前記少数キャリアの捕獲及び消滅を促進する、前記耐圧維持層より低抵抗の、炭化珪素を主成分とするバッファ層と、
第１導電型の前記耐圧維持層の上部の一部に設けられた第２導電型の半導体領域と、
を備えることを特徴とする半導体装置。 In a semiconductor device comprising a silicon carbide substrate and a breakdown voltage maintaining layer,
The breakdown voltage maintaining layer provided between the substrate and the breakdown voltage maintaining layer, to which a main dopant that determines a conductivity type and a sub-dopant that captures minority carriers and has a doping concentration lower than the doping concentration of the main dopant is added. A buffer layer mainly composed of silicon carbide having a lower resistance than the breakdown voltage maintaining layer, which promotes the capture and annihilation of the minority carriers flowing in the direction of the substrate from
A semiconductor region of a second conductivity type provided in a part of the upper portion of the breakdown voltage maintaining layer of the first conductivity type;
A semiconductor device comprising:
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