JP2012004318A - Bipolar semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bipolar semiconductor device arranged to prevent minority carriers from reaching a substrate and the forward voltage from increasing even under conditions such as a high temperature and a high current density.SOLUTION: A SiC pin diode 20 has: an n-type SiC substrate 21; an n-type drift layer 23; and an n-type buffer layer 22 formed between the n-type SiC substrate 21 and n-type drift layer 23 and having a thickness of 20 μm. The n-type buffer layer 22 serves as a trap of holes from p-type anode layers 24 and 25, and prevents the holes (minority carriers) from reaching the n-type SiC substrate 21. Since the holes (minority carriers) are prevented from reaching the n-type SiC substrate 21 in this way, a stacking fault can be prevented from spreading from the n-type SiC substrate 21 and therefore the forward voltage can be prevented from increasing.

Description

  The present invention relates to a bipolar semiconductor device capable of reducing defects that become the core of stacking faults, which are factors that cause forward voltage to increase with current application.

  Wide-gap semiconductor materials such as silicon carbide (SiC) have excellent characteristics such as about 10 times higher dielectric breakdown field strength than silicon (Si), and high breakdown voltage bipolar with high reverse voltage resistance. It attracts attention as a suitable material for power semiconductor elements.

  Bipolar semiconductor elements such as pin diodes, bipolar transistors, GTO (gate turn-off transistor), and GCT (gate commutation type turn-off transistors) have a higher built-in voltage than unipolar semiconductor elements such as Schottky diodes and MOSFETs. The on-resistance is significantly reduced by the conductivity modulation of the drift layer by the implantation of.

  Accordingly, bipolar semiconductor elements are used in high voltage and large current regions such as power applications in order to reduce loss. When these bipolar semiconductor elements are made of SiC, it is possible to achieve performance that is significantly superior to that of Si elements.

  For example, in the case of a 10 kV high voltage pin diode element composed of SiC, the forward voltage is about 1/3 that of a Si pin diode, and the reverse recovery time corresponding to the off-time speed is as fast as about 1/20 or less. It is. In addition, power loss can be reduced to about 1/5 or less of Si pin diodes, which can greatly contribute to energy saving. In addition to SiC pin diodes, SiC npn transistors, SiC SIAFETs, SiC SIJFETs, and the like have been developed and similar power loss reduction effects have been reported (for example, Non-Patent Document 1). In addition, SiC GTO using a p-type semiconductor layer of opposite polarity as a drift layer has been developed (for example, Non-Patent Document 2).

  By the way, in the SiC bipolar semiconductor element, there is a phenomenon called “forward voltage drift” in which the forward voltage increases when a current flows in the forward direction. This forward voltage drift is generated by stacking faults expanding into the drift layer. Defects that become seeds of this stacking fault include basal plane dislocations (basal plane dislocations) and surface defects (half loops). Among these, many basal plane dislocations exist in the substrate. When minority carriers reach this substrate, stacking faults expand from the substrate into the drift layer.

Therefore, in Patent Document 1 (US Pat. No. 6,889,874), a buffer layer having an impurity concentration similar to that of the substrate is formed between the drift layer and the substrate, and minority carriers reach the substrate from the drift layer. Technology to prevent this is shown. A semiconductor laminated structure of an SiC bipolar semiconductor device according to this technique is schematically shown on the left side of FIG. 8, and an electron density distribution K1 and a hole density distribution K2 corresponding to each semiconductor layer of the semiconductor laminated structure are schematically shown on the right side of FIG. Indicate. The right side of FIG. 8 shows an electron density distribution K1 and a hole density distribution K2 when a current of about 100 A / cm ² is passed at room temperature.

In the SiC bipolar semiconductor device having this buffer layer, as shown on the right side of FIG. 8, when a current having a current density of about 100 A / cm ² flows at room temperature, holes as minority carriers do not reach the substrate. No expansion of stacking faults from the substrate was observed.

However, when energizing a current having a current density of 200 A / cm ² or higher under a high temperature exceeding 200 ° C., as indicated by a symbol M on the right side of FIG. 9, holes as minority carriers have reached the substrate, An increase in stacking faults from the substrate occurred. This is not only due to an increase in temperature and current, but also because stacking faults form continuous levels and the diffusion coefficient increases, so that minority carriers are carried to the substrate. That is, the buffer layer alone could not prevent holes (minority carriers) from reaching the substrate, the stacking faults expanded from the substrate, and forward voltage drift occurred.

US Pat. No. 6,849,874

Edited by Hiroyuki Matsunami, “Semiconductor SiC Technology and Applications”, pages 218-221, published by Nikkan Kogyo Shimbun A. K. Agarwal et. al, Materials Science Forum Volume 389-393, 2000, pp. 1349-1352.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a bipolar semiconductor device capable of preventing minority carriers from reaching a substrate even under conditions of high temperature and high current density and preventing an increase in forward voltage.

In order to solve the above problems, a bipolar semiconductor element of the present invention includes a substrate made of a silicon carbide semiconductor,
A buffer layer of a first conductivity type formed on the substrate and made of a silicon carbide semiconductor;
A drift layer of a first conductivity type formed on the buffer layer and made of a silicon carbide semiconductor;
A second conductivity type semiconductor layer formed on the drift layer and made of a silicon carbide semiconductor;
The thickness of the first conductivity type buffer layer is 13 μm or more.

  According to the present invention, the thickness of the first conductivity type buffer layer formed between the substrate and the first conductivity type drift layer and serving as a trap for minority carriers from the second conductivity type semiconductor layer. By setting the thickness to 13 μm or more, minority carriers can be prevented from reaching the substrate even under conditions of high temperature and high current density. Thereby, it is possible to realize a bipolar semiconductor element capable of preventing the stacking fault from expanding from the substrate and preventing the forward voltage from increasing.

  In one embodiment, the thickness of the first conductivity type buffer layer is 20 μm or more.

  According to this embodiment, an increase in the forward voltage can be prevented almost completely.

  In one embodiment, the thickness of the first conductivity type buffer layer is 50 μm or less.

  According to this embodiment, since the thickness of the first conductivity type buffer layer is set to 50 μm or less, the crystal growth time can be suppressed and the resistance of the buffer layer can be suppressed to suppress an increase in the loss of the element.

  In one embodiment, the bipolar semiconductor device is a diode in which the second conductivity type semiconductor layer formed on the drift layer is an anode.

  According to this embodiment, the minority carriers can be prevented from reaching the substrate even under conditions of high temperature and high current density, and the stacking fault can be prevented from expanding from the substrate, so that the forward voltage can be prevented from increasing. Can be realized.

In one embodiment, the first conductivity type substrate is a collector layer, and the second conductivity type semiconductor layer formed on the drift layer is a base layer.
Further, the transistor has a first conductivity type emitter layer formed on the base layer and made of a silicon carbide semiconductor.

  According to this embodiment, the minority carriers can be prevented from reaching the substrate even under conditions of high temperature and high current density, and the stacking fault can be prevented from expanding from the substrate, so that the forward voltage can be prevented from increasing. Can be realized.

In one embodiment of the bipolar semiconductor device, the substrate is a collector layer,
The IGBT is formed on the second conductivity type semiconductor layer and has an emitter layer made of the first conductivity type silicon carbide semiconductor.

  According to this embodiment, since minority carriers can be prevented from reaching the substrate even under conditions of high temperature and high current density, and stacking faults can be prevented from expanding from the substrate, it is possible to maintain stable characteristics for a long time. IGBT with high property is obtained.

  According to the bipolar semiconductor element of the present invention, the buffer layer of the first conductivity type formed between the substrate and the drift layer of the first conductivity type and serves as a trap for minority carriers from the semiconductor layer of the second conductivity type. The thickness was 20 μm or more. As a result, it is possible to realize a bipolar semiconductor device capable of preventing minority carriers from reaching the substrate even under conditions of high temperature and high current density, preventing a stacking fault from expanding from the substrate, and preventing an increase in forward voltage. .

It is sectional drawing which shows the cross section of the SiC pin diode as 1st Embodiment of the bipolar semiconductor element of this invention. It is sectional drawing which shows the cross section of the npn bipolar transistor as 2nd Embodiment of the bipolar semiconductor element of this invention. It is sectional drawing which shows the cross section of IGBT as 3rd Embodiment of the bipolar semiconductor element of this invention. It is a figure which shows the current-voltage characteristic after the stress test of the SiC bipolar semiconductor element of the said 1st Embodiment. It is a figure which shows the current-voltage characteristic after the stress test of the SiC bipolar semiconductor element of a comparative example. It is a characteristic view showing the relationship between the thickness of the buffer layer and the increase ΔVf of the forward voltage. It is a figure which shows typically the carrier density distribution corresponding to the semiconductor laminated structure of the SiC bipolar semiconductor element of the said 1st Embodiment. It is a figure which shows typically the carrier laminated distribution (room temperature, low current density) corresponding to the semiconductor laminated structure of the conventional SiC bipolar semiconductor element. It is a figure which shows typically the carrier density distribution (high temperature, high current density) corresponding to the semiconductor laminated structure of the conventional SiC bipolar semiconductor element.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a cross-sectional view of a pn junction diode (pin diode) 20 as a first embodiment of a bipolar semiconductor device of the present invention. In the first embodiment, a semiconductor layer described below is formed on a substrate 21 made of n-type 4H SiC as the first conductivity type. The 4H type “H” represents a hexagonal crystal, and the 4H type “4” represents a crystal structure in which the atomic stacking has a four-layer period.

  On the n-type 4H-type SiC substrate 21, n-type 4H—SiC and p-type (second conductivity type) 4H—SiC are epitaxially grown in sequence to produce an epitaxial pin diode 20 as described later.

The n-type 4H SiC substrate 21 shown in FIG. 1 was prepared by slicing an ingot grown by the modified Rayleigh method with an off angle θ of 8 degrees and mirror-polishing. The carrier density of the SiC substrate 21 determined by the Hall effect measurement method is 8 × 10 ¹⁸ cm ⁻³ and the thickness is 400 μm.

A nitrogen-doped n-type SiC layer (n-type growth layer) and an aluminum-doped p-type SiC layer (p-type growth layer) are sequentially formed by epitaxial growth on the C-plane (carbon surface) of the substrate 21 serving as the cathode. The n-type growth layer, which is the nitrogen-doped n-type SiC layer, becomes the n-type buffer layer 22 and the n-type drift layer 23 shown in FIG. The buffer layer 22 has a donor density of 7 × 10 ¹⁷ cm ⁻³ and a film thickness of 20 μm. The drift layer 23 has a donor density of about 5 × 10 ¹⁵ cm ⁻³ and a film thickness of 300 μm.

On the other hand, the p-type growth layer, which is the aluminum-doped p-type SiC layer, becomes the p-type junction layer 24 and the p + -type contact layer 25 that become the anode. The p-type bonding layer 24 has an acceptor density of 5 × 10 ¹⁷ cm ⁻³ and a film thickness of 1.5 μm. The p + type contact layer 25 has an acceptor density of about 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.5 μm.

  The pin diode 20 of this embodiment is formed by sequentially forming an n-type buffer layer 22, an n-type drift layer 23, a p-type junction layer 24, and a p + type contact layer 25 on the SiC substrate 21. The processing conditions will be described in more detail below.

First, the pin diode 20 of this embodiment uses silane (SiH ₄ ) and propane (C ₃ H ₈ ) as material gases. Nitrogen (N ₂ ) and trimethylaluminum (Al (CH ₃ ) ₃ ) are used as dopant gases. Further, hydrogen (H ₂ ) is used as a carrier gas. The flow rate of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute). The pressure is expressed in kPa (kilo pascal). Moreover, in the following description, the numerical value in the parenthesis attached after the name of each gas represents a flow rate. Further, the temperature of the substrate 21 is maintained at 1550 ° C., and the pressure in the processing chamber is maintained at 5.6 kPa.

  In the step of forming the buffer layer 22 on the C-plane of the n-type 4HSiC substrate 21 serving as the cathode, silane (30 sccm), propane (12 sccm), nitrogen (30 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 80 minutes.

  In the step of forming the drift layer 23, silane (30 sccm), propane (12 sccm), nitrogen (0.2 sccm), and hydrogen (10 slm) are supplied. The processing time for this step is 1200 minutes. In the step of forming the P-type bonding layer 24, silane (30 sccm), propane (12 sccm), trimethylaluminum (15 sccm), and hydrogen (10 slm) are supplied. The processing time for this step is 6 minutes. In the step of forming the p + -type contact layer 25, silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 2 minutes.

  The SiC epitaxial wafer for pin diode of this 1st Embodiment is producible by the process of each said formation process.

  On the other hand, a SiC epitaxial wafer for a pin diode as a comparative example with respect to the SiC epitaxial wafer for the epitaxial pin diode 20 of the first embodiment was produced. The SiC epitaxial wafer for pin diodes of this comparative example is only that the n-type buffer layer having a film thickness of 2.5 μm is formed on the n-type 4H SiC substrate 21 instead of the n-type buffer layer 22 having a film thickness of 20 μm. Is different from the first embodiment. Therefore, here, only the step of forming a buffer layer on the SiC substrate will be described as a processing condition for producing the SiC epitaxial wafer for the comparative pin diode.

  First, the temperature of the substrate is maintained at 1550 ° C., and the pressure in the processing chamber is maintained at 5.6 kPa. In the step of forming a buffer layer on the C-plane of the substrate, silane (30 sccm), propane (12 sccm), nitrogen (30 sccm), and hydrogen (10 slm) are supplied. The processing time for this step is 10 minutes.

  Next, each of the SiC epitaxial wafer according to the first embodiment and the comparative SiC epitaxial wafer are processed as described below, whereby the pin diode 20 of this embodiment shown in FIG. A pin diode can be fabricated.

First, both ends of the SiC epitaxial wafer are removed by reactive ion etching (RIE) and processed into a mesa structure. As an etching gas in this RIE, CF ₄ (carbon tetrafluoride) and O ₂ were used, and etching was performed to a depth of about 2.5 μm by a plasma processing apparatus under conditions of a pressure of 5 Pa and a high frequency power of 260 W. Further, as a mask material at this time, a SiO ₂ film (thickness 10 μm) deposited by CVD was used.

Next, in order to alleviate electric field concentration at the bottom of the mesa formed by etching, a p-type JTE (junction termination extension) 26 having a width of 250 μm and a depth of 0.7 μm was provided on the mesa bottom. The p-type JTE 26 was formed by Al ion implantation. The energy of the Al ion implantation is changed in six steps between 30 to 450 keV, and the total dose is 1.2 × 10 ¹³ cm ⁻² . In addition, when the p-type JTE 26 was formed, the JTE 26 injection layer was designed to have a box profile. Ion implantation was all performed at room temperature, and graphite (thickness 5 μm) was used as a mask for ion implantation. Heat treatment for activating the implanted ions was performed in an argon gas atmosphere at 1700 ° C. for 3 minutes. After the annealing, a thermal oxide film 27 as a protective film was formed by wet oxidation at a temperature of 1200 ° C. for 3 hours. In FIG. 1, reference numeral 30 denotes an insulating protective film (or oxide film).

  Next, Ni (thickness 350 nm) is formed on the lower surface of the substrate 21 to form the cathode electrode 28. A film of Ti (titanium: thickness 350 nm) and Al (aluminum: thickness 100 nm) is deposited on the P + type contact layer 25 to form an anode electrode 29. The anode electrode 29 is composed of a Ti layer 29a and an Al layer 29b. Finally, heat treatment is performed at 1000 ° C. for 20 minutes to make the cathode electrode 28 and the anode electrode 29 ohmic electrodes, respectively. The size of the pn junction is 2.6 mmφ and is almost circular. In this embodiment, the p-type JTE 26 is formed by aluminum ion implantation. However, the same effect can be obtained even when boron (B) ion implantation is used.

The pin diode 20 of the first embodiment has a withstand voltage of 20 kV and an on-voltage of 5.0V. The pin diode 20 was energized in the forward direction at a current density of 200 A / cm ² for 1 hour, and the current-voltage characteristics at room temperature immediately after starting energization and after energization for 1 hour were measured with a curve tracer. As a result of this measurement, the forward voltage difference ΔVf between the forward current voltage characteristic immediately after the start of energization at a forward current density of 200 A / cm ² and the forward current voltage characteristic after 1 hour energization is 0.1 V or less. There was almost no difference. Therefore, the pin diode 20 of the first embodiment hardly deteriorated even after the energization for 1 hour described above.

  On the other hand, the comparative pin diode was energized under the same conditions as those described for the first embodiment, and the current-voltage characteristics at room temperature immediately after energization and after 1 hour energization were measured with a curve tracer. It was measured. As a result of this measurement, the forward voltage difference ΔVf was 20 V or less, and an increase in the forward voltage was observed.

(Experimental example)
Next, a comparison experiment was conducted between the pin diode corresponding to the first embodiment and the diode corresponding to the comparison pin diode. The experimental conditions of this comparative experiment were as follows. First, the size of the diode of this embodiment and the comparative diode was 10 mm × 10 mm and mounted in a high temperature package, and the current-voltage characteristics of each diode at room temperature were measured. Next, the temperature of the high temperature package was set to 70 ° C., and a current of 50 A DC was applied to each diode for 10 hours. After this energization, the current-voltage characteristics of each diode at room temperature were measured. As a result of this measurement, the current-voltage characteristic of the diode of this embodiment having a buffer layer thickness of 20 μm is the difference between the current-voltage characteristic S1 before energization and the current-voltage characteristic S2 after energization, as shown in FIG. There was almost no. In the above experiment, even when the thickness of the n-type buffer layer 22 is 20 μm or more (for example, 30 μm, 40 μm, 50 μm), the difference between the current-voltage characteristics before energization and the current-voltage characteristics after energization is There was almost no.

  On the other hand, the current-voltage characteristic of the comparative diode having a buffer layer thickness of 2.5 μm is forward in the current-voltage characteristic S12 after energization as compared to the current-voltage characteristic S11 before energization, as shown in FIG. The directional voltage increased significantly.

FIG. 6 shows the result of determining the buffer layer thickness dependence characteristics of the forward voltage increase width ΔVf by changing the thickness of the buffer layer from 0 to 20 μm in the above experiment. In FIG. 6, the horizontal axis indicates the thickness (μm) of the buffer layer, the vertical axis indicates the forward voltage increase width ΔVf at each buffer layer thickness, and the buffer layer thickness (μm) is zero ( That is, the value ΔVf / ΔVfmax normalized by the forward voltage increase width ΔVfmax when there is no buffer layer is shown. The forward voltage increase width ΔVf is the forward voltage increase width when the forward current is 100 (A / cm ² ). As shown in FIG. 6, when the buffer layer thickness is 20 μm, the forward voltage increase width ΔVf is zero, and when the buffer layer thickness is less than 13 μm, the forward voltage increase width ΔVf increases rapidly. .

  Next, referring to FIG. 7, the effect of preventing the increase in the forward voltage due to the presence of the buffer layer 22 having a thickness of 20 μm will be qualitatively described. The left side of FIG. 7 schematically shows the laminated structure of the pin diode 20 of the first embodiment, and the right side of FIG. 7 schematically shows the carrier density distribution corresponding to the laminated structure. In FIG. 7, a curve K1 represents an electron density distribution, and a curve K2 represents a hole density distribution. As described above, the n-type buffer layer 22 having a thickness of 20 μm formed between the n-type SiC substrate 21 and the n-type drift layer 23 is formed from the p-type anode layer 24 and the contact layer 25. It works as a trap for holes that are minority carriers. As a result, as indicated by the symbol G on the right side of FIG. 7, holes (minority carriers) can be prevented from reaching the n-type SiC substrate 21 even under conditions of high temperature and high current density. It is possible to realize the pin diode 20 that can prevent the stacking fault from expanding and prevent the forward voltage from increasing.

Since the SiC buffer layer has a high impurity concentration and is susceptible to scattering, the mobility of the SiC buffer layer decreases to about 100 cm ² / Vs (“Step-controlled epitaxial growth of SiC: high quality homoepiaxy,” H. Matsunami and T. Kimoto, materials Science and Engineering, R20 (1997), 125-166 (middle p152)). On the other hand, since the stacking fault behaves like a quantum well, the mobility in the stacking fault is not affected by the scattering of impurities and rises to about 1000 cm ² / Vs. Therefore, the diffusion coefficient of the stacking fault is about 10 times the diffusion coefficient of the buffer layer due to the Einstein relationship. Einstein's relationship is as follows. D / μ = kT / e, (D: diffusion coefficient, μ: mobility, k: Boltzmann constant, T: temperature, e: electron charge) On the other hand, the diffusion distance L of the stacking fault is L = (τD) ^{1 / 2} (L: diffusion distance, τ: lifetime), which is proportional to the 1/2 power of the diffusion coefficient. Accordingly, when the diffusion distance of the buffer layer is about 3.2 times and the diffusion distance of the buffer layer is 2.5 μm, the diffusion distance L of the stacking fault is about 8 μm.

  As described above, according to the SiC pin diode 20 of the first embodiment, the n-type buffer layer formed between the n-type SiC substrate 21 and the n-type drift layer 23 has a thickness of 20 μm. 22 acts as a trap for holes as minority carriers, preventing holes (minority carriers) from reaching the substrate 21. As a result, the stacking fault is prevented from expanding from the substrate 21 and the forward voltage deterioration hardly occurs, so that it can be used for a long time and the life is extended. In the first embodiment, since there is no increase in on-resistance due to forward voltage degradation, an internal loss does not increase, and a highly reliable pin diode that can maintain stable characteristics for a long time can be obtained.

  In the first embodiment, the n-type buffer layer 22 having a thickness of 20 μm is formed between the n-type substrate 21 and the n-type drift layer 23. However, the thickness of the n-type buffer layer 22 is reduced. It is good also as 20 micrometers or more (for example, 30 micrometers, 40 micrometers, 50 micrometers, etc.). However, the thickness of the n-type buffer layer 22 is desirably 50 μm or less. If the thickness of the n-type buffer layer 22 is thicker than 50 μm, the crystal growth time is increased and the resistance of the buffer layer increases, leading to an increase in device loss.

(Second embodiment)
Next, FIG. 2 shows a second embodiment of the bipolar semiconductor device of the present invention. FIG. 2 is a cross-sectional view of an npn bipolar transistor 50 as the second embodiment. The second embodiment also employs an n-type 4H SiC substrate. On this n-type 4H-type SiC substrate, n-type 4H-SiC, p-type 4H-SiC, and n-type 4H-SiC were successively epitaxially grown in this order to produce an npn bipolar transistor 50.

  In the npn bipolar transistor of the second embodiment, n-type 4H-SiC, p-type 4H-SiC, and n-type 4H-SiC are formed on a (000-1) carbon surface of a substrate using n-type 4H-type SiC. The npn bipolar transistor 50 was manufactured by epitaxial growth continuously in the order of.

The n-type 4H-type SiC substrate 51 was prepared by slicing an ingot grown by the modified Rayleigh method so that the off angle θ was 8 degrees, and mirror polishing. The substrate 51 serving as a collector is n-type, the carrier density measured by the Hall effect measurement method is 8 × 10 ¹⁸ cm ⁻³ , and the thickness is 400 μm. A buffer layer 52 and a drift layer 53 of a nitrogen-doped n-type SiC layer are formed on the C surface of the substrate 51 by a CVD method.

  On this drift layer 53, an aluminum-doped p-type SiC p-type growth layer 54 and a nitrogen-doped n-type SiC layer n-type growth layer 55 were sequentially formed by an epitaxial growth method. The buffer layer 52 and the drift layer 53 become an n-type collector layer.

The buffer layer 52 has a donor density of 7 × 10 ¹⁷ cm ⁻³ and a film thickness of 20 μm. The drift layer 53 has a donor density of about 5 × 10 ¹⁵ cm ⁻³ and a film thickness of 15 μm. The p-type growth layer 54 to be the p-type base layer has an acceptor density of 2 × 10 ¹⁷ cm ⁻³ and a film thickness of 1 μm. The n-type growth layer 55 has a donor density of about 7 × 10 ¹⁷ cm ⁻³ and a film thickness of 0.75 μm.

Next, processing conditions for manufacturing the npn bipolar transistor 50 of this embodiment will be described. Silane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as material gases. Nitrogen (N ₂ ) and trimethylaluminum {Al (CH ₃ ) ₃ } are used as dopant gases. Further, hydrogen (H ₂ ) is used as a carrier gas. The temperature of the substrate is kept at 1550 ° C., and the pressure in the processing chamber is kept at 5.6 kPa. The flow rate of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute). The pressure is expressed in kPa (kilo pascal). In the following description, the numerical value in parentheses after the name of each gas represents the flow rate.

  In the step of forming the buffer layer 52 on the C-plane of the n-type 4HSiC substrate 51 serving as a collector, silane (30 sccm), propane (12 sccm), nitrogen (30 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 80 minutes. In the step of forming the drift layer 53, silane (30 sccm), propane (12 sccm), nitrogen (0.2 sccm), and hydrogen (10 slm) are supplied. The processing time for this step is 60 minutes.

  In the step of forming the P-type growth layer 54, silane (30 sccm), propane (12 sccm), trimethylaluminum (6 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 4 minutes. In the step of forming the n-type growth layer 55, silane (30 sccm), propane (12 sccm), nitrogen (30 sccm), and hydrogen (10 slm) are supplied. The processing time for this step is 3 minutes. The SiC epitaxial wafer for the npn bipolar transistor of the second embodiment can be obtained by the processing of each of the above steps.

  On the other hand, a SiC epitaxial wafer for an npn bipolar transistor as a comparative example with respect to the SiC epitaxial wafer for the npn bipolar transistor 50 of the second embodiment was manufactured. The SiC epitaxial wafer for the npn bipolar transistor of this comparative example is only that an n-type buffer layer having a film thickness of 2.5 μm is formed on the n-type 4H SiC substrate 51 in place of the n-type buffer layer 52 having a film thickness of 20 μm. Is different from the second embodiment. Therefore, here, only the step of forming the buffer layer on the SiC substrate will be described as a processing condition for producing the SiC epitaxial wafer for the comparative npn bipolar transistor.

  First, the temperature of the substrate is maintained at 1550 ° C., and the pressure in the processing chamber is maintained at 5.6 kPa. In the step of forming a buffer layer on the C-plane of the substrate, silane (30 sccm), propane (12 sccm), nitrogen (30 sccm), and hydrogen (10 slm) are supplied. The processing time for this step is 10 minutes.

  Then, the npn bipolar transistor 50 and the comparative example of the second embodiment shown in FIG. 2 can be produced by performing the following processing on the second embodiment and the SiC epitaxial wafer for comparison.

First, the n-type growth layer 55 is etched by reactive ion etching (RIE) with a width of 10 μm, a depth of 0.75 μm, and a pitch of 23 μm, leaving an n-type growth layer 55 that becomes an emitter. As the etching gas for RIE, CF ₄ and O ₂ were used, and the etching was performed under the conditions of a pressure of 0.05 Torr and a high frequency power of 260 W. Further, as a mask material at this time, a SiO ₂ film (thickness 10 μm) deposited by CVD was used.

Next, in order to perform element isolation in the base region, a mesa structure is formed by reactive ion etching (RIE). CF ₄ and O ₂ were used as the etching gas for this RIE, and the etching was performed to a depth of about 1 μm under the conditions of a pressure of 0.05 Torr and a high frequency power of 260 W. As a mask material at this time, a SiO ₂ film (thickness 10 μm) deposited by CVD was used.

  In the second embodiment, the guard ring 56 for relaxing the electric field concentration at the base end and the base contact region 57 are formed by Al (aluminum) ion implantation in the same process. The base contact region 57 has a width of 3 μm, a distance from the emitter of 5 μm, and the p-type guard ring 56 has a width of 150 μm. Both the contact region 57 and the p-type guard ring 56 have a depth of 0.5 μm.

The energy of Al ion implantation when forming the p-type guard ring 56 and the base contact region 57 is 40 to 560 keV, and the total dose is 1.0 × 10 ¹³ cm ⁻² . As a mask for this ion implantation, a SiO ₂ film (thickness 5 μm) formed by CVD was used. All ion implantations were performed at room temperature, and the heat treatment for activating the implanted ions was performed under conditions of a temperature of 1600 ° C. in an argon gas atmosphere for 5 minutes.

Next, after annealing, a thermal oxide film was formed by wet oxidation at a temperature of 1150 ° C. for 2 hours, and a SiO ₂ film was further deposited by CVD to form an oxide film 58 having a total thickness of 2 μm.

  Next, collector electrode 59 </ b> C is formed on the lower surface of SiC substrate 51. A base electrode 59B is formed in the base contact region 57. Further, Ni is deposited on the emitter region 55 to form an emitter electrode 69. Next, heat treatment was performed at 1000 ° C. for 20 minutes to form ohmic junctions.

  Finally, the base electrode 59B and the emitter electrode 69 were covered with a Ti / Au electrode 70 to form each electrode terminal. The size of the joint is 3.2 mm × 3.2 mm. In the second embodiment, the guard ring 56 is formed by Al ion implantation, but the same effect can be obtained even when B (boron) ion implantation is used.

  In the npn bipolar transistor 50, all of the junction surfaces (surfaces extending in the horizontal direction in the figure) of the substrate 51, the buffer layer 52, the drift layer 53, the p-type growth layer 54, and the n-type growth layer 55 are (000). -1) It is parallel to the surface 2a having an off angle of 8 degrees from the carbon surface 2.

The npn bipolar transistor 50 thus fabricated has a withstand voltage of 1400V. The on-resistance was 8.0 mΩcm ² and the maximum current amplification factor was about 12. The npn bipolar transistor 50 was energized with a base current of 0.6 A and a collector current of 14 A (collector current density of 200 A / cm ² ) for 1 hour, and the collector characteristics at room temperature before and after the energization were measured with a curve tracer. In the npn bipolar transistor 50 of this embodiment, the on-resistance was 8.0 mΩ / cm ² immediately after the start of energization and after 1 hour of energization, and there was almost no change in the forward voltage.

On the other hand, the npn bipolar transistor of the comparative example (thickness of the n-type buffer layer of 2.5 μm) of the second embodiment was also tested by applying current at a base current of 0.6 A and a collector current density of 200 A / cm ² . The on-resistance at room temperature of this comparative npn bipolar transistor was 8.0 mΩ / cm ² immediately after the start of energization, but became very large at 15.0 mΩ / cm ² after energization for 1 hour. Further, the maximum current amplification factor at room temperature of the npn bipolar transistor of this comparative example was about 12 at the beginning of energization, but decreased to about 6 after energization for 1 hour.

  On the other hand, the maximum current amplification factor of the npn bipolar transistor 50 of the second embodiment was about 12 with almost no change immediately after energization and after energization for 1 hour. As described above, in the npn bipolar transistor 50 of the second embodiment, almost no forward voltage deterioration occurred even after a 1-hour energization test.

  As described above, according to the SiC npn bipolar transistor 50 of the second embodiment, an n-type transistor having a thickness of 20 μm formed between the n-type SiC substrate 51 and the n-type SiC drift layer 53 is used. The buffer layer 52 acts as a trap for holes as minority carriers, and prevents holes (minority carriers) from reaching the substrate 51. This prevents the stacking faults from expanding from the SiC substrate 51, and almost no forward voltage deterioration occurs, so that it can be used for a long time and the life is extended. In the second embodiment, since there is almost no increase in on-resistance due to forward voltage degradation, an internal loss is not increased, and a highly reliable npn bipolar transistor capable of maintaining stable characteristics for a long time is obtained. It is done.

  In the second embodiment, the n-type buffer layer 52 having a thickness of 20 μm is formed between the n-type substrate 51 and the n-type drift layer 53. However, the thickness of the n-type buffer layer 52 is 20 μm. It is good also as above (for example, 30 micrometers, 40 micrometers, 50 micrometers, etc.). However, the thickness of the n-type buffer layer 52 is preferably 50 μm or less. If the thickness of the n-type buffer layer 52 is greater than 50 μm, the crystal growth time is increased and the resistance of the buffer layer increases, leading to an increase in device loss.

  Also in the second embodiment, the buffer layer thickness is changed from 0 to 20 μm as in the first embodiment, and the forward voltage increase width ΔVf depends on the buffer layer thickness. As a result of obtaining the characteristics, it was the same as the dependence characteristics shown in FIG.

(Third embodiment)
Next, FIG. 3 shows a cross section of an IGBT (insulated gate bipolar transistor) 80 as a third embodiment of the bipolar semiconductor device of the present invention.

  The IGBT 80 has a p-type 6H-SiC layer, an n-type 6H-SiC layer, and a p-type 6H on a substrate 71 made of n-type 6H-type SiC at a film thickness increase rate of 15 μm / h. Three layers were epitaxially grown in the order of -SiC layers, and an IGBT 80 was produced as described in detail below. In this IGBT 80, the main joint surface of the p layer and the n layer (the surface extending in the direction perpendicular to the paper surface in the figure) is the {0001} plane.

  Next, a method for manufacturing the IGBT 80 will be described. That is, a p-type film is formed on a substrate using n-type 6H-type SiC having a surface orientation of an off angle θ of 3.5 degrees from the (000-1) carbon surface at a film formation rate of 15 μm / h. A 6H—SiC layer, an n-type 6H—SiC layer, and a p-type 6H—SiC layer are sequentially formed.

The SiC substrate 71 was prepared by slicing an ingot grown by the modified Rayleigh method at a surface inclined by 3.5 degrees from the (000-1) carbon surface and mirror polishing. The substrate 71 serving as a collector is n-type, has a thickness of 400 μm, and the carrier density obtained by the Hall effect measurement method is 5 × 10 ¹⁸ cm ⁻³ .

Three layers of an aluminum-doped p-type SiC layer, a nitrogen-doped n-type SiC layer, and an aluminum-doped p-type SiC layer were continuously epitaxially grown on this SiC substrate 71 by the CVD method. This p-type SiC layer becomes the buffer layer 72 and the drift layer 73 of FIG. The buffer layer 72 has an acceptor density of 1 × 10 ¹⁷ cm ⁻³ and a film thickness of 20 μm. The drift layer 73 has an acceptor density of about 5 × 10 ¹⁵ cm ⁻³ and a film thickness of 15 μm. The n-type growth layer 74 formed on the drift layer 73 has a donor density of 2 × 10 ¹⁷ cm ⁻³ and a film thickness of 2 μm. The p-type growth layer 75 formed on the n-type growth layer 74 has an acceptor density of about 1 × 10 ¹⁸ cm ⁻³ and a film thickness of 0.75 μm.

  Next, processing conditions when manufacturing this IGBT 80 will be described.

First, silane (SiH ₄ ) and propane (C ₃ H ₈ ) are used as material gases. Further, nitrogen (N ₂ ) and trimethylaluminum {Al (CH ₃ ) ₃ } are used as dopant gases. Further, hydrogen (H ₂ ) is used as a carrier gas. Here, the flow rate of each gas is represented by sccm (standard cc per minute) or slm (standard liter minute). The pressure is expressed in kPa (kilo pascal). Moreover, in the following description, the numerical value in the parenthesis attached after the name of each gas represents a flow rate.

  The temperature of the n-type SiC substrate 71 is kept at 1550 ° C., and the pressure in the processing chamber is kept at 5.6 kPa. In the step of forming the p-type SiC buffer layer 72 on the C-plane of the n-type SiC substrate 71, silane (30 sccm), propane (12 sccm), trimethylaluminum (3 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 80 minutes.

  Next, in the step of forming the p-type SiC drift layer 73, silane (30 sccm), propane (12 sccm), trimethylaluminum (0.15 sccm) and hydrogen (10 slm) are supplied. The processing time is 60 minutes.

  Next, in the step of forming the n-type growth layer 74, silane (30 sccm), propane (12 sccm), nitrogen (9 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 8 minutes. In the step of forming the p-type growth layer 75, silane (30 sccm), propane (12 sccm), trimethylaluminum (30 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 3 minutes. The SiC epitaxial wafer for IGBT 80 can be obtained by the processing in each of the above steps.

  On the other hand, a SiC epitaxial wafer for IGBT was produced as a comparative example for the SiC epitaxial wafer for IGBT 80 of the third embodiment. The SiC epitaxial wafer for IGBT of this comparative example is different from the third embodiment only in that a p-type buffer layer having a film thickness of 2.5 μm is formed in place of the p-type buffer layer 72 having a film thickness of 20 μm. Therefore, here, only the step of forming a buffer layer on the SiC substrate will be described as a processing condition for producing the above-described comparative IGBT epitaxial wafer for IGBT.

  First, the temperature of the substrate is maintained at 1550 ° C., and the pressure in the processing chamber is maintained at 5.6 kPa. In the step of forming the buffer layer on the C-plane of the substrate, silane (30 sccm), propane (12 sccm), trimethylaluminum (3 sccm) and hydrogen (10 slm) are supplied. The processing time for this step is 10 minutes.

  Next, the IGBT 80 shown in FIG. 3 and the IGBT of the comparative example can be manufactured by subjecting the SiC epitaxial wafers for the third embodiment and the comparative example to the processing described below.

First, by using photolithography, the central portion of the p + growth layer 75 is etched by RIE to form a hole 76a, and nitrogen is ion-implanted to form a contact region 76 to be an emitter. Next, in order to form a gate region, the p + growth layer 75 and the n + growth layer 74 are etched by RIE to form holes 78a (two in FIG. 3). Next, an SiO ₂ film is deposited by CVD to form an insulating film 77 in order to form a MOS structure on the wall surface of the hole 78a. Next, Ni is deposited on the collector region of the n-type SiC substrate 71 to form the collector terminal 79C. Further, an emitter electrode 79 is deposited on the contact region 76. Next, heat treatment is performed to form ohmic junctions. Further, a Mo electrode is formed on the insulating film 77 to form a gate electrode 78.

The IGBT 80 according to the present embodiment thus completed has a withstand voltage of 900 V, an on-resistance of 11 mΩcm ² , and a collector-emitter voltage of −14 V. Further, a gate voltage of −40 V was applied to the IGBT 80, a collector current of 1.4 A was applied for 1 hour, and the collector characteristics at room temperature at the start of energization and after the energization for 1 hour were measured with a curve tracer. In this IGBT 80, it was found that the collector-emitter voltage immediately after energization and after energization for 1 hour was -14 V, almost no change and therefore almost no deterioration.

On the other hand, in the IGBT of the comparative example, the withstand voltage is 900V, the on-resistance is 11 mΩcm ² , and the collector-emitter voltage is −14V. Further, a gate voltage of −40 V was applied to the IGBT of this comparative example, a collector current of 1.4 A was applied for 1 hour, and the collector characteristics at room temperature at the start of energization and after the energization for 1 hour were measured with a curve tracer. In the IGBT of this comparative example, the collector-emitter voltage immediately after energization was −14 V, whereas the collector-emitter voltage after 1 hour energization was as large as −29 V.

  On the other hand, according to the IGBT 80 of the present embodiment, as described above, the p-type buffer layer 72 formed between the n-type SiC substrate 71 and the p-type SiC drift layer 73 has a thickness of 20 μm. However, it acts as a trap for electrons as minority carriers, preventing electrons (minority carriers) from reaching the substrate 71. As a result, the stacking fault is prevented from expanding from the SiC substrate 71 and the forward voltage deterioration hardly occurs, so that it can be used for a long time and the life is extended. Further, in this third embodiment, since there is almost no increase in on-resistance due to forward voltage degradation, an internal loss is not increased, and a highly reliable IGBT that can maintain stable characteristics for a long time can be obtained.

  In the third embodiment, the p-type SiC buffer layer 72 having a thickness of 20 μm is formed between the n-type SiC substrate 71 and the p-type SiC drift layer 73. The thickness may be 20 μm or more (for example, 30 μm, 40 μm, 50 μm, etc.). However, the thickness of the p-type buffer layer 72 is preferably 50 μm or less. If the thickness of the p-type buffer layer 72 is greater than 50 μm, the crystal growth time is increased and the resistance of the buffer layer increases, leading to an increase in device loss.

  Also in the third embodiment, the buffer layer thickness is changed from 0 to 20 μm as in the first embodiment, and the forward voltage increase width ΔVf depends on the buffer layer thickness. As a result of obtaining the characteristics, it was the same as the dependence characteristics shown in FIG.

  In the above, the SiC pin diode, the npn bipolar transistor, and the IGBT have been described as the embodiments of the SiC bipolar semiconductor device of the present invention. However, the present invention is not limited to the above embodiment, and the SIAFET, SIJFET are not limited thereto. Applicable to various 4H-SiC bipolar semiconductor devices such as thyristors, GTO, MCT (Mos Controlled Thyristor), SiCGT (SiC Commutated Gate Thyristor), EST (Emitter Switched Thyristor), BRT (Base Resistance Controlled Thyristor) It is. Of course, the present invention can be applied to various 4H-SiC bipolar elements such as elements having opposite polarities (for example, pnp transistors for npn transistors), and can be applied to SiC bipolar elements using various crystal structures such as 6H-SiC. Is.

  Since the SiC bipolar semiconductor element of the present invention has a high withstand voltage and a low on-voltage, it can suppress current loss and can be used with a large current. As an example, a vehicle such as a home appliance field, an industrial field, or an electric vehicle When applied to a power control device incorporated in a power control device such as an inverter in the field, power system field such as power transmission, etc., switching loss can be reduced, and it can be used with a large current and is reliable. Can be improved.

20 pin diode 21 n-type SiC substrate 22 n-type SiC buffer layer 23 n-type SiC drift layer 24 p-type junction layer 25 p + type contact layer 26 p-type JTE
27 Thermal oxide film 28 Cathode electrode 29 Anode electrode 30 Insulating protective film 50 npn bipolar transistor 51 n-type SiC substrate (collector layer)
52 n-type SiC buffer layer (collector layer)
53 n-type SiC drift layer (collector layer)
54 p-type growth layer (base layer)
55 n-type growth layer (emitter layer)
56 p-type guard ring 57 contact region 58 oxide film 59B base electrode 69 emitter electrode 71 6H-type SiC substrate 72 p-type SiC buffer layer 73 p-type SiC drift layer 74 n-type growth layer 75 p-type growth layer 76 contact region 77 insulating film 78 Gate electrode 79 Emitter electrode 70 IGBT

Claims (6)

A substrate made of a silicon carbide semiconductor;
A buffer layer of a first conductivity type formed on the substrate and made of a silicon carbide semiconductor;
A drift layer of a first conductivity type formed on the buffer layer and made of a silicon carbide semiconductor;
A second conductivity type semiconductor layer formed on the drift layer and made of a silicon carbide semiconductor;
A bipolar semiconductor element, wherein a thickness of the first conductivity type buffer layer is 13 μm or more. The bipolar semiconductor device according to claim 1, wherein
A bipolar semiconductor element, wherein a thickness of the first conductivity type buffer layer is 20 μm or more. The bipolar semiconductor device according to claim 1 or 2,
A bipolar semiconductor element, wherein a thickness of the first conductivity type buffer layer is 50 μm or less. In the bipolar semiconductor device according to any one of claims 1 to 3,
A bipolar semiconductor device, wherein the substrate is a diode, and the second conductivity type semiconductor layer formed on the drift layer is an anode. In the bipolar semiconductor device according to any one of claims 1 to 3,
The substrate is the collector layer and the second conductivity type semiconductor layer formed on the drift layer is the base layer,
A bipolar semiconductor device comprising a transistor having a first conductivity type emitter layer formed on the base layer and made of a silicon carbide semiconductor. In the bipolar semiconductor device according to any one of claims 1 to 3,
The substrate is a collector layer,
A bipolar semiconductor device, characterized in that it is an IGBT formed on the second conductivity type semiconductor layer and having an emitter layer made of a first conductivity type silicon carbide semiconductor.

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