JP2017069995A - Digital protection controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital protection controller that detects failure in an input conversion board and an analog input circuit and to prevent a device from erroneously operating or not operating.SOLUTION: A digital protection controller 100 comprises: an input conversion board 1 including a known signal generation unit 11 for generating a known signal that cannot be generated in a system, and an input conversion unit 10 for superposing the known signal on an input analog signal of a power system, and applying a prescribed conversion process to the analog signal with the known signal superposed thereon by using hall elements 13a, 13b, ..., 13h; and a control board 2 including an analog input circuit 50 for removing unnecessary harmonics from the analog signal supplied via communication lines 15a, 15b, ..., 15h from the input conversion board 1, and converting the resultant signal into a digital signal, and an output comparison unit 27 for determining the soundness of the analog input circuit 50 including the hall elements 13a, 13b, ..., 13h on the basis of an attenuation rate of a known signal component after passing through the analog input circuit 50.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a digital protection control device that protects and controls a power system.

In general, in a plant such as a power plant or a substation, electric power supplied to an electric power system is protected and controlled by a digital protection control device.
Conventional digital protection control devices generally employ a winding transformer as an input converter in an analog input section.
However, with the trend of recent downsizing, weight reduction, and cost reduction of devices, protection control devices to which sensors such as Hall elements are applied have been used as an alternative to winding transformers (Patent Document 1). reference).

  Patent Document 1 includes a current transformer provided on each of a system side and a neutral point side of an electrical protection target device, and a protection relay that operates based on a difference between current values detected by the two current transformers. A protective relay system is described. The protective relay system described in Patent Document 1 is provided with a current detector having current saturation characteristics different from those of both current transformers, and is detected by the current transformer when the occurrence of a difference current is detected between the current transformers. If the trend of the transition of the current waveform detected by the current detector is similar, the output of the operation signal of the protection relay is stopped.

JP 2005-341770 A

However, the Hall element used in the conventional digital protection control device requires a control power supply for driving in principle, and thus it is inevitable to mount a large number of electronic components on the input converter.
For this reason, compared with the input converter which applied the conventional transformer, the risk that a device malfunctions or malfunctions due to a failure of an electronic component is increased.
In addition, since there is a case where the analog input is lost due to a failure on the system side outside the protection control device, there is a problem that it is not possible to determine whether the main failure point is an internal failure of the device or a failure on the system side.

  An object of the present invention is to provide a digital protection control device that detects a failure of an input conversion board and an analog input circuit and prevents malfunction and malfunction of the device.

  In order to solve the above-described problems, a digital protection control device according to the present invention includes a known signal generation unit that generates a known signal that cannot be generated in a system, and superimposes the known signal on an analog signal of an input power system. An input conversion board having an input conversion section that performs a predetermined conversion process using a Hall element on the analog signal on which the known signal is superimposed, and the input conversion board via the first communication line An analog input circuit that removes unnecessary harmonics from a supplied analog signal and converts the analog signal into a digital signal, and the analog input including the Hall element based on an attenuation rate of the known signal component after passing through the analog input circuit A control board having a first determination unit for determining the soundness of the circuit.

  ADVANTAGE OF THE INVENTION According to this invention, the digital protection control apparatus which detects the failure of an input conversion board | substrate and an analog input circuit, and prevents malfunctioning / malfunctioning of an apparatus can be provided.

It is a block diagram which shows the structure of the digital protection control apparatus which concerns on embodiment of this invention. It is a figure explaining the signal processing example of the digital protection control apparatus which concerns on the said embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a digital protection control apparatus according to an embodiment of the present invention. In the drawings, common components are denoted by the same reference numerals, and redundant description is omitted.
As shown in FIG. 1, the digital protection control device 100 includes an input conversion board 1, a control board 2, a settling unit 3, a digital input / output unit 4, and a control power supply unit 5 that supplies power to each unit. Prepare. The input conversion board 1 is connected to the control board 2 through communication lines 15a, 15b,..., 15h (h is a natural number) (first communication line) and communication line 15x (second communication line). Power is supplied from the control power supply unit 5 to the input conversion board 1 and the control board 2.

[Input conversion board 1]
The input conversion substrate 1 includes external elements 1a, 1b,..., 1h (h is a natural number) of each channel (A to H in this example), and Hall elements 13a, 13b, .., 13h (h is a natural number) is driven, and the power supply peripheral monitoring circuit unit 30 that monitors the voltage level, and the analog input from the outside (target to be protected) to the external input units 1a, 1b,. And an input conversion unit 10 for converting the signal into an analog signal having an appropriate voltage level.

The input conversion unit 10 includes a known signal generation unit 11 that generates a known signal that cannot be generated in the system, and adders 12a, 12b,..., 12h that apply the generated known signal to an external input (h is a natural number) ), Hall elements 13a, 13b,..., 13h (h is a natural number) for performing a predetermined conversion process on an analog signal such as an external current or current, and resistance circuits 14a, 14b having various resistance multipliers ..., 14h (h is a natural number).
The input conversion unit 10 superimposes a known signal on the analog signal of the input power system, and performs predetermined conversion processing on the analog signal on which the known signal is superimposed using the Hall elements 13a, 13b,. Do.
Each of the resistance circuits 14a, 14b,..., 14h provided corresponding to each channel (A to H in this example) of the input conversion unit 10 is connected to the control board 2 through the communication lines 15a, 15b,. Has been.
In the following description, the adders 12a, 12b,..., 12h of the respective channels will be referred to as adders 12 unless otherwise distinguished. The Hall elements 13a, 13b,..., 13h of each channel will be referred to as Hall elements 13 when not particularly distinguished. In addition, the resistor circuits 14a, 14b,.

  In some protective relay devices, to detect failure / degradation of the analog circuit on the control board 2, an f12 harmonic that is an AC signal having a frequency 12 times the rated frequency is applied to the analog circuit. It has a mechanism to check the soundness of the analog circuit by extracting the f12 harmonic after passing and detecting the attenuation rate. Here, the f12 harmonic is applied to the analog circuit by the adder 12 as a known signal that cannot be generated in the system. When f12 harmonics are used, when the calculation cycle of the protection calculation processing is set to an electrical angle of 30 °, the sampling timing becomes 0 (transmission zero point) in 12 cycles, which can be realized with a simple configuration.

The power supply periphery monitoring circuit unit 30 includes a DC / DC unit 31 that boosts the power supplied from the control power supply unit 5 to the drive voltages of the Hall elements 13a, 13b,..., 13h, and the Hall elements 13a, 13b,. A power supply monitoring circuit 32 (power supply monitoring unit) for notifying the control board 2 of a power supply abnormality when the drive voltage is out of a specified value.
The power monitoring circuit 32 is connected to the control board 2 through the communication line 15x. The power supply monitoring circuit 32 notifies the control board 2 of a power supply abnormality when the drive voltage of the Hall elements 13a, 13b,.

[Control board 2]
The control board 2 includes analog filters 16a, 16b,..., 16h provided for each channel (A to H), an A / D converter 17, an arithmetic processing unit 24, and a zero-phase monitoring unit 25 (third determination). Section), a balance monitoring section 26 (third determination section), an output comparison section 27 (first determination section), and a power supply peripheral circuit abnormality detection section 28 (second determination section).
The analog filters 16a, 16b,..., 16h and the A / D converter 17 remove unnecessary harmonics from the analog signals supplied from the input conversion board 1 via the first communication lines 15a, 15b,. Thus, an analog input circuit 50 for converting to a digital signal is configured.
In the following description, the analog filters 16a, 16b,...

  The arithmetic processing unit 24 includes a harmonic removal digital filter 18, an f12 harmonic extraction digital filter 19, buffers 20 and 21, a CPU (Central Processing Unit) 22, and a ROM (Read Only Memory) 23. The CPU 22, the ROM 23, and the buffers 20 and 21 are connected to a system bus (BUS), and are connected to each other through the system bus (BUS) so as to communicate with each other.

The analog filter 16 is a folding error prevention filter that removes unnecessary harmonic components from the input analog signal and outputs the result to the A / D converter 17. In this example, only the frequency component (including DC voltage) of 1/2 or less of the sampling frequency (for example, electrical angle 20 degrees) and the voltage (analog signal) in the rated frequency band pass, and the voltage of other frequency components (analog) Signal) is attenuated at a predetermined rate as noise.
The A / D converter 17 is an example of an analog / digital conversion unit, converts the supplied analog signal into a binary digital signal, and converts the harmonic removal digital filter 18 and f12 harmonic extraction digital of the arithmetic processing unit 24. Output to the filter 19.

The harmonic elimination digital filter 18 is a band-pass filter that passes only voltages in a predetermined rated frequency band and removes voltages and DC voltages in other frequency bands.
The f12 harmonic extraction digital filter 19 is a band-pass filter that passes only voltages in the f12 harmonic frequency band and removes voltages and DC voltages in other frequency bands.
The buffers 20 and 21 temporarily hold and output the data supplied from the harmonic removal digital filter 18 and the f12 harmonic extraction digital filter 19, respectively.

The CPU 22 controls the entire control board 2 and executes a program stored in the ROM 23, for example, to identify whether or not the analog input circuit has a failure based on the attenuation rate of the f12 harmonic component included in the analog input. I do.
The ROM 23 stores programs executed by the CPU 22 and various data. A part of the ROM 23 may be a rewritable nonvolatile memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory). The ROM 23 stores, for example, output value data that is referred to when identifying the presence or absence of a failure in the input conversion unit 10. The output value data is data obtained when the analog input circuit 50 attenuates the f12 harmonic signal output from the known signal generation unit 11. The ROM 23 stores a calculation formula for determining whether or not the analog input is in a three-phase equilibrium.

The zero phase monitoring unit 25 monitors the input zero phase of the three-phase alternating current and confirms the soundness of the three-phase alternating current.
The balance monitoring unit 26 monitors the balance of the input three-phase alternating current and confirms the soundness of the three-phase alternating current. The zero-phase monitoring unit 25 and the balance monitoring unit 26 determine that the analog input circuit 50 is in a three-phase equilibrium based on the three-phase AC digital signal that has passed through the analog input circuit 50. When the analog input circuit 50 is not in three-phase balance, the zero-phase monitoring unit 25 and the balance monitoring unit 26 output the comparison unit 27 (first determination unit) and the power supply peripheral circuit abnormality detection unit 28 (second determination unit). If no anomaly is detected in (), it is determined that there is a failure on the external system side.

  The output comparison unit 27 determines the soundness of the analog input circuit 50 by comparing the f12 harmonic component and the data value. Specifically, the output comparison unit 27 determines the soundness of the analog input circuit 50 including the Hall elements 13a, 13b,..., 13h based on the attenuation rate of the known signal component after passing through the analog input circuit 50.

  The power supply peripheral circuit abnormality detection unit 28 is connected to the power supply monitoring circuit 32 of the input conversion board 1 via the communication line 15x, and determines the power supply abnormality of the input conversion unit 10. For example, the power supply peripheral circuit abnormality detection unit 28 receives a notification from the power supply monitoring circuit 32 when the drive voltage of the Hall elements 13a, 13b,. To detect.

[Settling part 3]
The settling unit 3 sets a settling value that defines the operation of the external device 110 such as a relay in order to protect the power system and the power equipment. The settling unit 3 includes an operation unit 3a and a display unit 3b, and a monitor or the like sets the settling value using the operation unit 3a and the display unit 3b. The set value set by the settling unit 3 is stored in the ROM 23 via the system bus (BUS).

[Digital input / output unit 4]
Based on the control of the CPU 22, the digital input / output unit 4 controls the external device 110 such as a relay and acquires state information from the external device 110.

[Control power supply unit 5]
The control power supply unit 5 is a power supply that supplies power to each unit of the digital protection control device 100. For example, a DC-DC converter is applied to the control power supply unit 5. The control power supply unit 5 supplies a DC voltage of 5 V to each of the input conversion board 1, the control board 2, and the settling unit 3, and the digital input / output unit 4 has an input unit and an output unit (both not shown), respectively. Supply DC 5V and DC 15V.

Hereinafter, the operation of the digital protection control device 100 configured as described above will be described.
FIG. 2 is a diagram for explaining an example of signal processing of the digital protection control device 100. In FIG. 2, changes in analog input input to the input conversion board 1 and signals output from the known signal generation unit 11 are simply shown.
A predetermined voltage (for example, DC 15 V) is supplied from the control power supply unit 5 to the power supply periphery monitoring circuit unit 30 (see FIG. 1) of the input conversion board 1. The DC / DC unit 31 boosts the supplied voltage to the drive voltage of the Hall elements 13a, 13b,..., 13h, and supplies the boosted voltage to the Hall elements 13a, 13b,. The drive voltage is monitored by the power supply monitoring circuit 32. If the drive voltage deviates from a specified voltage value (for example, ± 12 to 18V), the power supply monitoring circuit 32 determines that a failure has occurred and the control board 2 is connected via the communication line 15x. The power peripheral circuit abnormality detection unit 28 is notified. The CPU 22 determines that the power supply is abnormal when the notification to the power supply peripheral circuit abnormality detection unit 28 is detected.

As shown in FIG. 2, for example, a voltage input (Si1) (see symbol a in FIG. 2) having a rated frequency of 10 V is applied to the external input portions 1a, 1b,..., 1h (see FIG. 1) of the input conversion board 1. To do. On the other hand, the known signal generation unit 11 (see FIG. 1) that generates a known signal in the input conversion board 1 is, for example, rated 12 as a signal (Sj1) that cannot be generated in the system (see symbol b in FIG. 2). Assume that an amplitude of 5 V is generated with a double harmonic.
The adders 12a, 12b,..., 12h superimpose a voltage input (Si1) and a signal (Sj1) that cannot be generated in the system, and superimpose an analog signal (Si1 + Sj1) (see symbol c in FIG. 2). Are output to the Hall elements 13a, 13b,.
Hall elements 13a, 13b,..., 13h and resistor circuits 14a, 14b,..., 14h convert input values at a specific ratio (for example, 50%). Here, an analog signal (Si2 + Sj2) (see reference symbol d in FIG. 2) in which the amplitude of the rated frequency of 5V and the amplitude of the 12th harmonic of 2.5V are combined.

The analog signal (Si2 + Sj2) is transmitted to the analog filters 16a, 16b,..., 16h in the control board 2 via the communication circuits 15a, 15b,.
The analog filters 16a, 16b,..., 16h pass, for example, only a frequency component (including a DC voltage) that is ½ or less of the sampling frequency and a voltage in the rated frequency band, and the other frequency component voltages are predetermined as noise. Attenuate at a rate of. In this example, the analog signal (Si2) is not affected because of the rated frequency. However, since the analog signal (Sj2) is an AC signal having a frequency 12 times the rated frequency, the analog signal (Sj2) is affected by the analog filters 16a, 16b,. The amplitude is 1V, and an analog signal (Si2 + Sj3) (see symbol e in FIG. 2) is obtained.

  After that, the A / D converter 17 converts this analog signal (Si2 + Sj3) into a digital signal (Si3 + Sj4) and outputs it. Here, the voltage value of the digital signal (Si3) (see symbol f in FIG. 2) is 5 V of the rated frequency, and the voltage value of the digital signal (Sj4) (see symbol g in FIG. 2) is the amplitude of the f12 harmonic. AC value of 1V. The digital signal (Si3 + Sj4) is transferred to the harmonic removal digital filter 18 and the f12 harmonic extraction digital filter 19.

  The harmonic rejection digital filter 18 passes only voltages in a predetermined rated frequency band, and removes voltages and DC voltages in other frequency bands. In this example, the digital signal (Si3) has the rated frequency and is not affected by the harmonic removal digital filter 18. However, since the digital signal (Sj4) is an AC signal having a frequency 12 times the rated frequency, it is cut by the harmonic elimination digital filter 18 and the digital signal (Si3) after passing (see symbol f in FIG. 2) is The rated frequency is 5V. The digital signal (Si3) that has passed through the harmonic removal digital filter 18 is temporarily stored in the buffer 20.

  The f12 harmonic extraction digital filter 19 passes only the voltage in the rated frequency band 12 times the rated frequency, and removes the voltage and DC voltage in the other frequency bands. In this example, since the digital signal (Sj4) is an AC signal having a frequency 12 times the rated frequency, it is not affected by the f12 harmonic extraction digital filter 19. However, since the digital signal (Si3) has the rated frequency, it is cut by the f12 harmonic extraction digital filter 19, and the digital signal (Sj4) after passing (see symbol g in FIG. 2) is an alternating current of f12 harmonic 1V. Value. The digital signal (Sj4) that has passed through the f12 harmonic extraction digital filter 19 is temporarily stored in the buffer 21.

When the CPU 22 is notified that all the digital signals are ready in the buffer 20 and the buffer 21, the CPU 22 reads out these data.
The CPU 22 transfers the three-phase AC digital signal (Si3) read from the buffer 20 to the zero-phase monitoring unit 25 and the balance monitoring unit 26, and the analog input is calculated from the calculation formula stored in the ROM 23 as the three-phase balanced. It is determined whether or not.
Further, the CPU 22 transfers the digital signal (Sj4) read from the buffer 21 to the output comparison unit 27, and the output comparison unit 27 collates with the theoretical output value stored in the ROM 13 in the control board 2. Thereby, the soundness of the analog input circuit 50 including the Hall elements 13a, 13b,..., 13h can be determined.

  When an abnormality occurs in any of the power supply peripheral circuit abnormality detection unit 28, the zero phase monitoring unit 25, the balance monitoring unit 26, and the output comparison unit 27, the CPU 22 determines that the protection control device is abnormal. Further, the CPU 22 can also identify the failure location. That is, the CPU 22 determines that the power supply peripheral circuit of the input conversion unit 10 is faulty when the location of the protection control device abnormality is the power supply peripheral circuit abnormality detection unit 28. When the location of the protection control device abnormality is the output comparison unit 27, the CPU 22 determines that the analog input circuit 50 including the Hall elements 13a, 13b,. In other cases, the CPU 22 determines that the failure is on the system side outside the apparatus.

  As described above, the digital protection control apparatus 100 according to the present embodiment superimposes a known signal on a known signal generation unit 11 that generates a known signal that cannot be generated in the system, and an analog signal of the input power system. An input conversion board 1 having an input conversion unit 10 that performs predetermined conversion processing on the analog signal on which the known signal is superimposed using the Hall elements 13a, 13b, ..., 13h, and the input conversion board 1 , 15h from analog signals supplied via communication lines 15a, 15b,..., 15h, an analog input circuit 50 for removing unnecessary harmonics and converting them into digital signals, and attenuation of known signal components after passing through the analog input circuit 50 A control board 2 having an output comparison unit 27 for determining the soundness of the analog input circuit 50 including the Hall elements 13a, 13b,. That.

  With this configuration, the output voltage of the power supplied to the Hall elements 13a, 13b,..., 13h and the outputs of the Hall elements 13a, 13b,. A failure can be determined, and malfunction / malfunction of the device can be prevented.

  In the present embodiment, the input conversion board 1 includes a power supply monitoring circuit 32 that notifies the control board 2 of a power supply abnormality when the drive voltage of the Hall elements 13a, 13b,. Since the control board 2 is connected to the power supply monitoring circuit 32 via the communication line 15x and determines the power supply abnormality of the input conversion unit 10, it is possible to determine the failure of the power supply peripheral circuit of the input conversion unit 10.

  In the present embodiment, the control board 2 determines that the analog input circuit 50 is in a three-phase equilibrium based on the three-phase AC digital signal after passing through the analog input circuit 50. The zero-phase monitoring unit 25 and the balance monitoring unit 26 are based on a three-phase AC digital signal after passing through the analog input circuit 50, and the analog input circuit 50 becomes three-phase balanced. Judge that there is. When the analog input circuit 50 is not in three-phase balance, the zero-phase monitoring unit 25 and the balance monitoring unit 26 output the comparison unit 27 (first determination unit) and the power supply peripheral circuit abnormality detection unit 28 (second determination unit). If no anomaly is detected in (), it is determined that there is a failure on the external system side. As a result, it is possible to distinguish between a fault on the system side outside the apparatus and a fault inside the apparatus.

  As described above, in the present embodiment, the digital protection control device 100 has an analog input based on the zero-phase monitoring unit 25 and the balance monitoring unit 26 that detect the three-phase balance on the control board 2 and the attenuation rate of the f12 harmonic component. Since the output comparison unit 27 for determining the soundness of the circuit 50 and the power supply peripheral circuit abnormality detection unit 28 are provided, a failure of the input conversion board 1 and the analog input circuit 50 can be detected, and malfunction / error of the device can be detected. Non-operation can be prevented, and the fault location can be isolated. In addition, it is possible to isolate a failure location inside the apparatus.

  The present invention is not limited to the above-described embodiments, and includes other modifications and application examples without departing from the gist of the present invention described in the claims.

  For example, the above-described exemplary embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, a part of the configuration of an embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of an embodiment. . Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each exemplary embodiment.

  Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Also, as shown in FIGS. 1 and 2, each of the above-described configurations, functions, and the like may be realized by software for interpreting and executing a program in which the processor realizes each function. Information such as programs, tables, and files for realizing each function is stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), an IC (Integrated Circuit) card, an SD (Secure Digital) card, an optical disk, etc. It can be held on a recording medium. Further, in this specification, the processing steps describing time-series processing are not limited to processing performed in time series according to the described order, but are not necessarily performed in time series, either in parallel or individually. The processing (for example, parallel processing or object processing) is also included.

  In addition, the control lines and information lines are those that are considered necessary for the explanation, and not all the control lines and information lines on the product are necessarily shown. Actually, it may be considered that almost all the components are connected to each other.

DESCRIPTION OF SYMBOLS 1 Input conversion board 1a, 1b, ..., 1h External input part 2 Control board 13a, 13b, ..., 13h Hall element 10 Input conversion part 11 Known signal generation part 12a, 12b, ..., 12h Adder 13a, 13b, ..., 13h Hall element 14a, 14b, ..., 14h Resistor circuit 15a, 15b, ..., 15h Communication line (first communication line)
15x communication line (second communication line)
16a, 16b,..., 16h Analog filter 17 A / D converter 18 Harmonic elimination digital filter 19 f12 harmonic extraction digital filter 20, 21 Buffer 22 CPU
23 ROM
24 arithmetic processing unit 25 zero phase monitoring unit (third determination unit)
26 Equilibrium monitoring unit (third determination unit)
27 Output comparison unit (first determination unit)
28 Power supply peripheral circuit abnormality detection unit (second determination unit)
30 Power supply periphery monitoring circuit unit 31 DC / DC unit 32 Power supply monitoring circuit (power supply monitoring unit)
50 Analog input circuit 100 Digital protection control device

Claims (4)

A known signal generator for generating a known signal that cannot be generated in the system;
An input conversion unit including: an input conversion unit that superimposes the known signal on an analog signal of an input power system and performs a predetermined conversion process using a Hall element on the analog signal on which the known signal is superimposed A substrate,
An analog input circuit that removes unnecessary harmonics from the analog signal supplied from the input conversion board via the first communication line and converts the analog signal into a digital signal;
A control board having a first determination unit for determining soundness of the analog input circuit including the Hall element based on an attenuation rate of the known signal component after passing through the analog input circuit;
A digital protection control device comprising: The input conversion board further includes a power supply monitoring unit for notifying a power supply abnormality to the control board when the driving voltage of the Hall element is outside a specified value,
2. The digital protection according to claim 1, wherein the control board further includes a second determination unit that is connected to the power supply monitoring unit via a second communication line and determines a power supply abnormality of the input conversion unit. Control device. The control board further includes a third determination unit that determines that the analog input circuit is in a three-phase equilibrium based on a three-phase AC digital signal after passing through the analog input circuit,
When the analog input circuit is not in a three-phase balance, the third determination unit determines that an external system side failure has occurred unless an abnormality is detected by the first determination unit and the second determination unit. The digital protection control apparatus according to claim 1 or 2, wherein The digital protection control device according to claim 1, wherein the known signal is an f12 harmonic signal which is an AC signal having a frequency 12 times the rated frequency.

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