JP2017049126A - Semiconductor integrated circuit and method for testing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit with which it is possible to construct a scan-path test circuit while reducing the number of dedicated external terminals of the scan-path test circuit, and a method for testing the same.SOLUTION: A semiconductor integrated circuit 10 comprises a plurality of flip-flops 14A-14I, test circuit construction means, and a driver 32 for current sink. The plurality of flip-flops 14A-14I share a clock signal, and have a data input terminal D and a data output terminal Q. The test circuit construction means, having a scan-in terminal SI and a scan-out terminal SO, connects the plurality of flip-flops 14A-14I by a scan chain to construct a scan-path test circuit 30. The driver 32 for current sink, connected to the scan-out terminal SO, changes the logical value of a scan-out signal outputted from the scan-out terminal SO from a voltage change to a current change.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit and a test method thereof.

  Patent Document 1 discloses a large scale integrated circuit capable of constructing a scan path test circuit. In a large scale integrated circuit, in order to construct a scan path test circuit and operate the scan path test circuit, a dedicated external terminal (external connection pin) for connecting the outside and the inside is required. The specific external terminals are the external terminal for input of the scan mode signal to be switched to the scan path test circuit, the external terminal for input of the scan-in signal for performing the scan test, and the scan-out signal for outputting the scan test result And an external terminal dedicated for output.

  By the way, in a large-scale integrated circuit or an integrated circuit, the number of external terminals is limited because the area of the peripheral portion of the semiconductor substrate is limited. For this reason, when there are severe restrictions, it is difficult not only to arrange a dedicated external terminal, but also to construct a scan path test circuit.

JP 2006-170663 A

  In consideration of the above-described facts, the present invention is to provide a semiconductor integrated circuit and a test method therefor capable of constructing a scan path test circuit by reducing the number of dedicated external terminals of the scan path test circuit.

  A semiconductor integrated circuit according to a first aspect of the present invention includes a plurality of flip-flops sharing a clock signal and having a data input terminal and a data output terminal, a plurality of flip-flops connected in a scan chain, a scan-in terminal, Test circuit construction means for constructing a scan path test circuit having a scan-out terminal, and a current sink driver connected to the scan-out terminal and changing the logical value of the scan-out signal output to the scan-out terminal into a current change I have.

  A semiconductor integrated circuit according to a first aspect includes a plurality of flip-flops and a test circuit construction unit. Each of the plurality of flip-flops has a data input terminal and a data output terminal. The test circuit construction means constructs a scan path test circuit by connecting a plurality of flip-flops in a scan chain. The scan path test circuit has a scan-in terminal and a scan-out terminal.

  Here, the semiconductor integrated circuit includes a current sink driver. The current sink driver is connected to the scan-out terminal and changes the logical value of the scan-out signal output to the scan-out terminal into a current change. For this reason, if the current change of the current sink driver is detected, the logical value of the scan-out signal can be determined, so that a dedicated external terminal for detecting the scan-out signal by voltage change can be eliminated.

  In a semiconductor integrated circuit according to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, the current sink driver has a gate electrode connected to the scan-out terminal and one main electrode connected to the reference power supply terminal. An insulated gate field effect transistor is connected and the other main electrode is connected to the operating power supply terminal.

  According to the semiconductor integrated circuit of the second aspect, the current sink driver is constituted by an insulated gate field effect transistor having a three-terminal structure. The insulated gate field effect transistor is turned on or off according to the logical value of the scan-out signal applied to the gate electrode. In the ON operation, a current flows from the operation power supply terminal to the reference power supply terminal via the insulated gate field effect transistor. In the off operation, the current from the operating power supply terminal to the reference power supply terminal is interrupted by the insulated gate field effect transistor. For this reason, a current change between the operating power supply terminal and the reference voltage terminal can be detected with a simple configuration.

  According to a third aspect of the present invention, there is provided a test method for a semiconductor integrated circuit, comprising: a step of constructing a scan path test circuit by connecting a plurality of flip-flops in a scan chain; and inputting a scan-in signal to the scan path test circuit; After the capture operation, the scan path test circuit outputs a scan-out signal, the logical value of the scan-out signal is detected by current change, and the detection result is compared with the expected value to determine whether there is a failure in the semiconductor integrated circuit And a step of performing.

  In the semiconductor integrated circuit test method according to the third aspect, a plurality of flip-flops are connected in a scan chain to form a scan path test circuit. When a scan-in signal is input to the scan path test circuit, a scan-out signal is output from the scan path test circuit after the capture operation.

  Here, the logical value of the scan-out signal is detected by a current change. The detection result is checked against the expected value to determine whether or not the semiconductor integrated circuit has failed. For this reason, even if the logic value of the scan-out signal is not detected by a voltage change, the logic value is detected by a current change, so that the number of dedicated external terminals of the scan path test circuit is reduced and whether there is a failure in the semiconductor integrated circuit. Can be determined.

  The semiconductor integrated circuit according to the invention described in claim 1 has an excellent effect that the scan path test circuit can be constructed by reducing the number of dedicated external terminals of the scan path test circuit.

  The semiconductor integrated circuit according to the second aspect of the invention has an excellent effect that a scan path test circuit can be constructed with a simple configuration.

  The method for testing a semiconductor integrated circuit according to the invention described in claim 3 is excellent in that the number of dedicated external terminals of the scan path test circuit is reduced, the scan path test circuit is constructed, and the scan path test can be executed. It has the effect.

1 is a schematic circuit block configuration diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a simplified plan view of a main part of a current sink driver connected to a scan path test circuit constructed in the semiconductor integrated circuit shown in FIG. 1. FIG. 2 is a schematic circuit block configuration diagram corresponding to FIG. 1 for explaining a test method of a scan path test circuit constructed in the semiconductor integrated circuit according to the first embodiment. It is a typical circuit block block diagram of the principal part of the scan path test circuit constructed | assembled in the semiconductor integrated circuit which concerns on 2nd Embodiment of this invention.

[First Embodiment]
The semiconductor integrated circuit and the test method thereof according to the first embodiment of the present invention will be described with reference to FIGS.

(Configuration of semiconductor integrated circuit)
As shown in FIG. 1, the semiconductor integrated circuit 10 according to the present embodiment is formed on the basis of a rectangular semiconductor substrate 12. As the semiconductor substrate 12, for example, a silicon single crystal substrate is used. The semiconductor integrated circuit 10 includes a plurality of flip-flops 14 </ b> A to 14 </ b> I disposed on the main surface 12 </ b> A of the semiconductor substrate 12, a combinational circuit 16, and a combinational circuit 18. Each of the combinational circuit 16 and the combinational circuit 18 is constructed as a single circuit such as a logic circuit or a storage circuit, or a composite circuit combining a logic circuit and a storage circuit.

  In the present embodiment, the plurality of flip-flops 14A to 14I are each configured by a D-type flip-flop. That is, the flip-flops 14A to 14I each include a clock signal terminal CLK, a data input terminal D, and a data output terminal Q. The clock signal (CLK) supplied from the outside of the semiconductor integrated circuit 10 to the external terminal 20A disposed in the peripheral portion of the semiconductor substrate 12 is supplied to the clock signal terminal CLK via the wiring 22A. The clock signal is shared by the flip-flops 14A to 14I, and the flip-flops 14A to 14I operate in synchronization with the clock signal.

  The data signal (D) supplied to the external terminal 20B is input to the data input terminal D of each of the flip-flops 14A to 14C via the wiring 22B. Although not shown in the drawing, a plurality of external terminals 20B and wirings 22B are provided corresponding to the flip-flops 14A to 14C, and separate data signals are supplied to the data input terminals D of the flip-flops 14A to 14C. Is entered. Similarly, different data signals are input to the data input terminals D of the flip-flops 14D to 14I, and different data signals are output from the data output terminals Q of the flip-flops 14A to 14I.

  The data output terminals Q of the flip-flops 14A to 14C are connected to the combinational circuit 16 via the wiring 22C, and output data signals to the combinational circuit 16. The data signal output from the combinational circuit 16 is input to the data input terminals D of the flip-flops 14D to 14F via the wiring 22D. The data output terminals Q of the flip-flops 14D to 14F are connected to the combinational circuit 18 via the wiring 22E and output data signals to the combinational circuit 18. The data signal output from the combinational circuit 18 is input to the data input terminals D of the flip-flops 14G to 14I via the wiring 22F. The data output terminals Q of the flip-flops 14G to 14I are output to the external terminals 20C disposed in the peripheral portion of the semiconductor substrate 12 through the wiring 22G. The data signal output to the external terminal 20C is output to the outside of the semiconductor integrated circuit 10.

  Each of the plurality of flip-flops 14A to 14I is provided with a scan-in terminal SI and a scan enable terminal SE. The scan-in terminal SI of the flip-flop 14A is connected to a dedicated external terminal (external pin) 24A to which a scan-in signal (SI) is input via a wiring 26A. The scan-in signal is a test data (serial data) signal of the scan path test circuit 30 constructed in the semiconductor integrated circuit 10. Each of the scan enable terminals SE of the flip-flops 14A to 14I is connected to a dedicated external terminal 24B to which a scan enable signal (SE) is input via a wiring 26K. In the semiconductor integrated circuit 10 according to the present embodiment, when a scan enable signal is input to the scan enable terminals SE of the flip-flops 14A to 14I, the flip-flops 14A to 14I are switched from the normal mode to the test mode. That is, in the test mode, the plurality of flip-flops 14A to 14I are scan chain connected as a kind of shift register, and the scan path test circuit 30 is constructed. In the present embodiment, each of the plurality of flip-flops 14A to 14I is provided with a selector function as test circuit construction means (not shown), and when a scan enable signal is input to the scan enable terminal SE, the scan path test circuit 30 Is built. In this embodiment, the full scan scan path test circuit 30 is constructed, but a partial scan scan path test circuit may be constructed.

  More specifically, the scan path test circuit 30 has the following connection structure. First, the data output terminal Q of the first-stage flip-flop 14A, which is the first stage of the scan chain connection, is connected to the scan-in terminal SI of the second-stage flip-flop 14B via the wiring 26B. Here, the scan-in terminal SI of the first-stage flip-flop 14 </ b> A is used as the scan-in terminal SI of the scan path test circuit 30.

  The data output terminal Q of the flip-flop 14B is connected to the scan-in terminal SI of the third-stage flip-flop 14C via the wiring 26C. The data output terminal Q of the flip-flop 14C is connected to the scan-in terminal SI of the fourth-stage flip-flop 14F via the wiring 26D. The data output terminal Q of the flip-flop 14F is connected to the scan-in terminal SI of the fifth-stage flip-flop 14E via the wiring 26E. The data output terminal Q of the flip-flop 14E is connected to the scan-in terminal SI of the sixth-stage flip-flop 14D through the wiring 26F. The data output terminal Q of the flip-flop 14D is connected to the scan-in terminal SI of the seventh-stage flip-flop 14G via the wiring 26G. The data output terminal Q of the flip-flop 14G is connected to the scan-in terminal SI of the eighth-stage flip-flop 14H via the wiring 26H. The data output terminal Q of the flip-flop 14H is connected to the scan-in terminal SI of the ninth-stage flip-flop 14I as the final stage via the wiring 26I. The data output terminal Q of the flip-flop 14I is connected to the current sink driver 32 via the wiring 26J. Here, the data output terminal Q of the flip-flop 14I at the final stage is used as the scan-out terminal SO of the scan path test circuit 30.

  As shown in FIG. 1 and FIG. 2, the current sink driver 32 is configured by an insulated gate field effect transistor (IGFET) having a three-terminal structure. In this embodiment, as shown in FIG. 2, the insulated gate field effect transistor has, for example, an n-channel conductivity type, and includes a gate electrode 32A, one main electrode (for example, a source region) 32B, and the other main electrode. An electrode (for example, a drain region) 32C is provided. The gate electrode 32A is connected to the scan-out terminal SO of the scan path test circuit 30 via the wiring 26J. Therefore, the logical value of the scan-out signal is applied as a voltage (high level or low level) to the gate electrode 32A. One main electrode 32B is connected to an external terminal 20E as a reference power supply terminal to which, for example, a 0V reference power supply (ground potential) is supplied from the outside via a reference power supply wiring 22I. On the other hand, the main electrode 32C is connected to an external terminal 20D as an operation power supply terminal to which, for example, several V to several tens of V operation power is supplied from the outside via the operation power supply wiring 22H. Therefore, in the current sink driver 32, when the logical value applied to the gate electrode 32A is at a high level, the current sink driver 32 is turned on, and a current flows from the main electrode 32C to the main electrode 32B. In the current sink driver 32, when the logical value applied to the gate electrode 32A is at a low level, the current sink driver 32 is turned off and no current flows from the main electrode 32C to the main electrode 32B.

  In the present embodiment, the specific element structures of the plurality of flip-flops 14A to 14I, the combinational circuit 16, and the combinational circuit 18 shown in FIGS. 1 and 2 are omitted. A transistor is included. The current sink driver 32 has the same structure as these field effect transistors and is formed by the same manufacturing process. Although the vertical cross-sectional structure of the semiconductor integrated circuit 10 is omitted, the dedicated external terminal 24A, the dedicated external terminal 24B, the wiring 26A used for the scan chain connection, the wiring 26B, and the like are external terminals. 20A to 20E, wirings 22A to 22I and the like are configured by the same wiring layer.

(Semiconductor integrated circuit test method)
A method for testing the semiconductor integrated circuit 10 according to the present embodiment will be briefly described. First, as shown in FIG. 3, a tester 40 is prepared for a scan test of the semiconductor integrated circuit 10. In the tester 40, a scan-in signal (SI) input probe 42A is connected to the dedicated external terminal 24A, and a scan enable signal (SE) input probe 42B is connected to the dedicated external terminal 24B. Further, the operation power supply probe 44 is connected to the external terminal 20D, and the reference power supply probe 46 is connected to the external terminal 20E. Here, the dedicated external terminal 24A and the dedicated external terminal 24B are dedicated external terminals of the scan path test circuit 30, but the external terminal 20D and the external terminal 20E also operate on the flip-flops 14A to 14I, the combinational circuit 16, and the combinational circuit 18. A common external terminal for supplying a power source and a reference power source.

  A scan enable signal (also called a shift enable signal or a test enable signal) is input from the input probe 42B of the tester 40 to the scan enable terminals SE of the flip-flops 14A to 14I via the dedicated external terminal 24B and the wiring 26K. The When the scan enable signal is input, the semiconductor integrated circuit 10 enters a scan mode, and a plurality of flip-flops 14 </ b> A to 14 </ b> I are connected in a scan chain, and the scan path test circuit 30 is constructed in the semiconductor integrated circuit 10. Subsequently, a scan-in signal (test pattern signal) is input from the input probe 42A to the scan-in terminal SI of the scan path test circuit 30 (scan-in terminal SI of the first flip-flop 14A) via the dedicated external terminal 24A and the wiring 26A. Entered. By inputting this scan-in signal, test patterns of the flip-flops 14A to 14I are set. The scan-in signal is a serial test data signal. Since the scan-in signal is input serially, a clock operation (shift operation) of the flip-flops is performed several times, and the scan-in signal is sent to all the flip-flops 14A to 14I. The clock operation is supplied from the external terminal 20A to the flip-flops 14A to 14I via the wiring 22A.

  Next, the scan path test circuit 30 shifts to the capture operation and enters the normal operation mode. The normal mode is switched by a scan enable signal. In the normal operation mode, the combinational circuit 16 between the flip-flops 14A to 14C and the flip-flops 14D to 14F and the combinational circuit 18 between the flip-flops 14D to 14F and the flip-flops 14G to 14I are operated. The logical value output from the combinational circuit 16 by this operation is taken into the flip-flops 14D to 14F. Similarly, the output of the combinational circuit 18 by this operation is taken into the flip-flops 14G to 14I.

  After the capture operation, the scan mode is set again by the scan enable signal, and the scan path test circuit 30 is constructed. Then, the clock operation is performed on all the flip-flops 14A to 14I, and the logical values taken in the flip-flops 14D to 14F and the flip-flops 14D to 14I are output from the scan-out terminal SO of the scan path test circuit 30. .

  The logical value output from the scan-out terminal SO is output to the current sink driver 32 via the wiring 26J. The logic value high level or low level is applied to the gate electrode 32A of the current sink driver 32 as a voltage change. When a high level is applied to the gate electrode 32A, the current sink driver 32 is turned on, and a current flows between the main electrode 32B and the main electrode 32C. When the low level is applied to the gate electrode 32A, the current sink driver 32 is turned off, and the current flowing between the main electrode 32B and the main electrode 32C is cut off. This change in current is detected by the tester 40, and the detection result is collated with an expected value in the tester 40. If the detection result matches the expected value, it is determined that there is no failure in the semiconductor integrated circuit 10. If the detection result does not match the expected value, it is determined that the semiconductor integrated circuit 10 has a failure.

(Operation and effect of the present embodiment)
As described above, the semiconductor integrated circuit 10 according to the present embodiment includes the plurality of flip-flops 14A to 14I and the test circuit construction unit as shown in FIG. Each of the plurality of flip-flops 14A to 14I has a data input terminal D and a data output terminal Q. The test circuit construction means constructs the scan path test circuit 30 by connecting a plurality of flip-flops 14A to 14I in a scan chain. In the present embodiment, the test circuit construction means has a dedicated external terminal 24B to which a scan enable signal is input, a wiring 26K, each scan enable terminal SE of the flip-flops 14A to 14I, and a selector function (not shown) connected thereto. is there. The scan path test circuit 30 has a scan-in terminal SI and a scan-out terminal SO.

  Here, the semiconductor integrated circuit 10 includes a current sink driver 32 as shown in FIGS. 1 and 2. The current sink driver 32 is connected to the scan-out terminal SO and changes the logical value of the scan-out signal output to the scan-out terminal SO from a voltage change to a current change. For this reason, if the current change of the current sink driver 32 is detected, the logical value of the scan-out signal can be determined, so that a dedicated external terminal for detecting the scan-out signal based on the voltage change can be eliminated.

  Therefore, according to the semiconductor integrated circuit 10 according to the present embodiment, the scan path test circuit 30 can be constructed by reducing the number of dedicated external terminals of the scan path test circuit 30.

  Further, in the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIGS. 1 and 2, the current sink driver 32 is constituted by an insulated gate field effect transistor having a three-terminal structure. The insulated gate field effect transistor is turned on or off according to the logical value of the scan-out signal applied to the gate electrode 32A. By the ON operation, a current flows from the operation power supply terminal (external terminal 20D) to the reference power supply terminal (external terminal 20E). Further, the current from the operating power supply terminal to the reference power supply terminal is cut off by the off operation. For this reason, a current change between the operating power supply terminal and the reference voltage terminal can be detected with a simple configuration.

  Therefore, according to the semiconductor integrated circuit 10 according to the present embodiment, the scan path test circuit 30 can be constructed with a simple configuration in addition to the above-described effects.

  Furthermore, in the test method of the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIG. 3, the scan path test circuit 30 is constructed by connecting a plurality of flip-flops 14A to 14I in a scan chain. When a scan-in signal is input to the scan-in terminal SI of the scan path test circuit 30, a scan-out signal is output from the scan-out terminal SO of the scan path test circuit after the capture operation.

  Here, the logical value of the scan-out signal is detected by a current change. The detection result is compared with an expected value in the tester 40 to determine whether or not the semiconductor integrated circuit 10 has failed. For this reason, even if the logical value of the scan-out signal is not detected by a voltage change, the logical value is detected by a current change, so that the failure of the semiconductor integrated circuit 10 is reduced while reducing the number of dedicated external terminals of the scan path test circuit 30. The presence or absence of can be determined.

  Therefore, the test method of the semiconductor integrated circuit 10 according to the present embodiment can reduce the number of dedicated external terminals of the scan path test circuit 30, construct the scan path test circuit 30, and execute the scan path test.

[Second Embodiment]
(Configuration of semiconductor integrated circuit)
A semiconductor integrated circuit and a test method thereof according to the second embodiment of the present invention will be described with reference to FIG. Note that, in the semiconductor integrated circuit according to the present embodiment, the same or equivalent components as those of the semiconductor integrated circuit according to the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  As shown in FIG. 4, the semiconductor integrated circuit 10 according to the present embodiment includes a plurality of flip-flops 50A and 50B, and a plurality of selectors provided as test circuit construction means corresponding to the flip-flops 50A and 50B. 52A and 52B. Here, two flip-flops 50A and 50B are shown in a simplified manner, but the number is not limited. The same applies to the selectors 52A and 52B. Although illustration of a combinational circuit corresponding to the combinational circuit 16 or the combinational circuit 18 of the semiconductor integrated circuit 10 according to the first embodiment is omitted, in the present embodiment, it is interposed between the flip-flop 50A and the selector 52B. Is done.

  Each of the plurality of flip-flops 50A and 50B is configured by a D-type flip-flop, and includes a clock signal terminal CLK, a data input terminal D, and a data output terminal Q. A clock signal (CLK) is supplied to the clock signal terminal CLK through the wiring 54A. A data signal (D) is input to the data input terminal D of the first flip-flop 50A through the wiring 54B, the selector 52A, and the wiring 54C. The data output terminal Q of the flip-flop 50A is connected to the data input terminal D of the final-stage flip-flop 50B via the wiring 54D, the selector 52B, and the wiring 54E. The data output terminal Q of the flip-flop 50B outputs a data signal (D) via the wiring 54F.

  The selectors 52A and 52B are constituted by a multiplexer having a scan mode terminal, a data input terminal, a scan-in terminal, and a data output terminal, although the reference numerals of the respective terminals are omitted. In the first-stage selector 52A, the data signal (D) is input to the data input terminal via the wiring 54B, and the scan-in signal (SI) is input to the scan-in terminal via the wiring 56B. When the scan mode signal (SM) is input to the scan mode terminal via the wiring 56A, the selector 52A is switched from the normal operation mode to the scan mode, and the scan path test circuit 30 is constructed. The scan mode signal is the same as the scan enable signal (SE) in the semiconductor integrated circuit 10 and the test method according to the first embodiment. The data output terminal of the selector 52A is connected to the data input terminal D of the flip-flop 50A via the wiring 54C. In addition to the selectors 52A and 52B, the test circuit construction means is similar to the test circuit construction means of the semiconductor integrated circuit 10 according to the first embodiment. 56A is included.

  On the other hand, the data output terminal Q of the flip-flop 50A is connected to the data input terminal of the selector 52B through the wiring 54D and to the scan-in terminal through the wiring 54D and the wiring 56C. Similarly to the selector 52A, the selector 52B switches between the normal operation mode and the scan mode in response to the input of the scan mode signal (SM). The data output terminal of the selector 52B is connected to the data input terminal D of the flip-flop 50B through the wiring 54E.

  The data output terminal Q of the flip-flop 50B is connected to an external terminal (not shown) via a wiring 54F, and is connected to the current sink driver 32 via a wiring 54F and a wiring 56D. The current sink driver 32 has the same configuration as that of the current sink driver 32 of the semiconductor integrated circuit 10 according to the first embodiment.

  The semiconductor integrated circuit 10 according to the present embodiment configured as described above includes the selectors 52A and 52B as test circuit construction means, and the scan path test circuit 30 by switching the selectors 52A and 52B by the scan mode signal (SM). Is built. Except for this point, the test method of the semiconductor integrated circuit 10 according to the present embodiment is the same as the test method of the semiconductor integrated circuit 10 according to the first embodiment described above.

(Operation and effect of the present embodiment)
According to the semiconductor integrated circuit 10 and the test method thereof according to the present embodiment, the same operational effects as the operational effects obtained by the semiconductor integrated circuit 10 according to the first embodiment and the test method can be obtained.

[Supplementary explanation of the above embodiment]
The present invention is not limited to the above-described embodiment, and can be modified as follows, for example, without departing from the gist thereof. For example, the present invention can use a p-channel conductivity type insulated gate field effect transistor as a current sink driver. Here, the insulated gate field effect transistor includes a field effect transistor (MOSFET) having a metal / oxide film / semiconductor structure and a field effect transistor (MISFET) having a metal / insulation film / semiconductor structure. The present invention is not limited to a semiconductor integrated circuit diced into chips and a test method thereof, but is a wafer level semiconductor integrated circuit in which a plurality of semiconductor integrated circuits are mounted on a wafer and a test method thereof. It is applicable to.

DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 12 Semiconductor substrate 14A-14I, 50A, 50B Flip-flop 16, 18 Combination circuit 20A-20E External terminal 24A, 24B Dedicated external terminal 32 Current sink driver 32A Gate electrode 32B, 32C Main electrode 52A, 52B Selector ( Test circuit construction means)
D data input terminal Q data output terminal SI scan-in terminal SE scan enable terminal (test circuit construction means)

Claims (3)

A plurality of flip-flops sharing a clock signal and having a data input terminal and a data output terminal;
Test circuit construction means for constructing a scan path test circuit having a scan-in terminal and a scan-out terminal by connecting the plurality of flip-flops in a scan chain;
A current sink driver connected to the scan-out terminal and changing a logical value of a scan-out signal output to the scan-out terminal into a current change;
A semiconductor integrated circuit.   The current sink driver is composed of an insulated gate field effect transistor in which a gate electrode is connected to the scan-out terminal, one main electrode is connected to a reference power supply terminal, and the other main electrode is connected to an operation power supply terminal. The semiconductor integrated circuit according to claim 1. A process of connecting a plurality of flip-flops in a scan chain to construct a scan path test circuit; and
Inputting a scan-in signal to the scan path test circuit and outputting a scan-out signal from the scan path test circuit after a capture operation;
Detecting the logical value of the scan-out signal by a current change, and determining the presence or absence of a failure in the semiconductor integrated circuit by comparing the detection result with an expected value;
A method for testing a semiconductor integrated circuit comprising:

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