JP2012251949A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of shortening a time for specifying a malfunctioning circuit block and measuring characteristic deterioration in a reliability acceleration test of each circuit block.SOLUTION: A semiconductor integrated circuit 100 includes a plurality of circuit blocks B1, B2, ...Bn, a plurality of switching circuits Sa1, Sa2, ...San corresponding to the plurality of circuit blocks to control connection between the circuit blocks and a power terminal 2, and a plurality of flip flop circuits DFF1, DFF2, ...DFFn corresponding to the plurality of switching circuits to output a circuit block selection signal to the switching circuits, the plurality of flip flop circuits constitute a shift register circuit, select two or more switching circuits to output a circuit block selection signal on the basis of an input of an external signal, and the two or more switching circuits receiving the circuit block selection signal connect a circuit block corresponding to each of the two or more switching circuits and the power terminal.

Description

  The present invention relates to a semiconductor integrated circuit such as a CMOS type semiconductor, its inspection, and a test method.

  When there is a circuit in which an abnormal leak current flows in a CMOS type integrated circuit, it is necessary to select a circuit in which an abnormal leak current flows because reliability becomes a problem. In addition, the normal leakage current may increase. In such a case, the abnormal leakage current that affects the reliability is buried in the normal leakage current. Have difficulty. In order to solve these problems, a CMOS integrated circuit has been devised in which an additional circuit for measuring a leakage current for each circuit block is incorporated (see Patent Document 1).

  The technique of Patent Document 1 will be described with reference to FIGS. 9 and 10. FIG. 9 is a circuit diagram of a conventional semiconductor integrated circuit. FIG. 10 is a time chart showing the input signal waveform and the state of the internal circuit in the circuit diagram of FIG.

  A conventional semiconductor integrated circuit includes a plurality of circuit blocks B1, B2,... Bn, a plurality of switch circuits Sc1, Sc2,... Scn, and a plurality of delay flip-flop circuits (DFF: Delay Flip Flop). Composed.

  A plurality of circuit blocks B1, B2,... Bn are obtained by dividing the main body integrated circuit into blocks, and are connected to the power supply terminal 1 in common.

  The plurality of switch circuits Sc1, Sc2,... Scn correspond to the respective circuit blocks B1, B2,... Bn, and connect the corresponding circuit block to the power supply terminal 2 (ground side) and the measurement terminal 3. . That is, the power supply terminal 2 and the measurement terminal 3 are connected to each circuit block through the switch circuits Sc1, Sc2,... Scn. The switch circuits Sc1, Sc2,... Scn are switch circuits for switching the power supply of each block circuit, and are configured by combining an N-channel MOS transistor and an inverter.

  The switch circuit Sci connects the circuit block Bi and the power supply terminal 2 when the circuit block selection signal SLi is (H: High), and measures the circuit block Bi when the circuit block selection signal SLi is (L: Low). Connect to terminal 3.

  The plurality of delay flip-flop circuits DFF1, DFF2,... DFFn are connected in series to operate as a shift register circuit. The S terminal of the delay flip-flop circuits DFF1, DFF2,. It is a terminal to accept. When the circuit block selection signal SLi becomes (L), the connection destination of the circuit block Bi is switched from the power supply terminal 2 to the measurement terminal 3 by the switch circuit Sci, and the characteristics of the circuit block Bi are measured. When measuring the plurality of circuit blocks B1, B2,... Bn, only one of the plurality of circuit block selection signals SL1, SL2,... SLn becomes (L), and the circuit becomes (L). Only one circuit block corresponding to the block selection signal is selected, and the measurement terminal 3 and only the circuit block are connected.

  The EN terminal 4 is a terminal for switching between a case where the characteristics of a plurality of circuit blocks B1, B2,... Bn are measured (circuit block characteristic measurement) and an operation based on the original function (normal operation). is there. The EN terminal 4 inputs (H) in the case of circuit block characteristic measurement, and inputs (L) in the case of normal operation, so that circuit block selection signals SL1, SL2, ... SLn becomes (H) and all circuit blocks B1, B2,... Bn are connected to the power supply terminal 2.

  The R / S terminal 5 is an input terminal for setting the output of the delay flip-flop circuit DFF1, and resetting the outputs of the delay flip-flop circuits DFF2, DFF3,. The CLK terminal 6 is a clock signal terminal for sending input data of the delay flip-flop circuits DFF1, DFF2,.

  In the shift register circuit composed of a plurality of delay flip-flop circuits DFF1, DFF2,... DFFn, one delay flip-flop circuit that becomes an output (H) every time a CLK signal is input to the delay flip-flop circuit on the right side. Shift in order. When the EN terminal 4 is inputting (H) and the output of the delay flip-flop circuit DFFi becomes (H), the circuit block selection signal SLi becomes (L), and the circuit block Bi is connected to the measurement terminal 3. . The Vcc terminal 7 is a Vcc power supply application terminal for operating a plurality of switch circuits Sc1, Sc2,... Scn inverters, a plurality of delay flip-flop circuits DFF1, DFF2,. It is.

  A method for selecting each circuit block will be described with reference to FIG. First, all the inputs from the EN terminal 4, the R / S terminal 5, and the CLK terminal 6 are set to (L). Next, a pulse signal generated by changing the input of the R / S terminal 5 in the order of (L), (H), and (L) is input, the output of the delay flip-flop circuit DFF1 is set to (H), and the remaining delay The outputs of the flip-flop circuits DFF2, DFF3,... DFFn are set to (L). Then, the input from the EN terminal 4 is set to (H). Thereby, the circuit block B1 is selected, and the characteristics of the circuit block B1 are measured. Next, a pulse signal is input by changing the input of the CLK terminal 6 in the order of (L), (H), and (L), and the input of the delay flip-flop circuit DFF1 is sent to the next delay flip-flop circuit DFF2. Circuit block B2 is selected. Then, the characteristics of the circuit block B2 are measured. In this way, the characteristics from the circuit blocks B3 to Bn are measured by using the pulse signal described above as the input from the CLK terminal 6 and sequentially inputting the pulse signals.

JP 7-37956 A

  However, in a conventional semiconductor integrated circuit, a plurality of circuit blocks cannot be selected at the same time. Therefore, when a defective circuit block is specified, it is necessary to measure characteristics sequentially for each circuit block, which takes time. Furthermore, when a reliability acceleration test is performed on a circuit block, it is necessary to apply a high voltage to the NAND circuit and the power supply switch circuit, which easily deteriorates the characteristics of the control circuit and accurately evaluates the characteristic fluctuation of the original circuit block. There was a problem that it was difficult to do.

  Therefore, the present invention has been made in view of such a situation, and it is possible to shorten the inspection time for identifying a defective circuit block, and also about the characteristic deterioration in the reliability acceleration test of each circuit block. An object of the present invention is to provide a semiconductor integrated circuit capable of measuring with high accuracy.

  In order to achieve the above object, a semiconductor integrated circuit according to an embodiment of the present invention is provided corresponding to each of a plurality of circuit blocks and the plurality of circuit blocks, and connection between the corresponding circuit block and a power supply terminal. And a plurality of flip-flop circuits provided corresponding to each of the plurality of switch circuits and outputting a circuit block selection signal to the corresponding switch circuit, the plurality of flip-flop circuits Forms a shift register circuit by being connected in series, and selects two or more switch circuits from among the plurality of switch circuits based on the input of an external signal, and selects the two or more switch circuits. The two or more switch circuits that output the circuit block selection signal indicating the selection and the circuit block selection signal indicating the selection are input. , Connected to the circuit block corresponding to each of the two or more switching circuits and said power supply terminal.

  Preferably, the external signal is input to an input terminal of the first flip-flop circuit in the shift register circuit and a terminal commonly connected to all clock terminals of the plurality of flip-flop circuits.

  According to this, for example, the same number of clock pulses as the number of mounted circuit blocks and a Data signal including information on a circuit block to be selected can be input as external signals. Therefore, a plurality of specific circuit blocks can be selected from the plurality of circuit blocks. As a result, the number of inspections for specifying a defective circuit block can be minimized, and the inspection time can be shortened. For this reason, the cost concerning an inspection can be reduced.

  Preferably, the plurality of switch circuits control connection between all the circuit blocks and power supply terminals based on an input from an external terminal.

  According to this, it is possible to perform an inspection for identifying a defective block due to reliability deterioration by simultaneously applying a high voltage to all circuit blocks.

  Preferably, the plurality of switch circuits include an N-channel MOS transistor for connecting the circuit block and a power supply terminal, and a gate terminal of the N-channel MOS transistor is connected to the external terminal.

  According to this, in the reliability acceleration test, the high voltage is applied only to the N-channel MOS transistor whose reliability deterioration due to the high temperature bias is small. For this reason, it is possible to obtain an effect that the fluctuation characteristics due to the reliability of the circuit block can be accurately evaluated.

  According to the semiconductor integrated circuit of the present invention, since a plurality of specific circuit blocks can be selected at the same time, the inspection for specifying a defective circuit block can be minimized. For this reason, inspection time can be shortened and inspection cost can be reduced.

  In addition, when the reliability acceleration test is performed, the high voltage is applied only to the N-channel MOS transistor whose reliability deterioration due to the high temperature bias is small. Therefore, it is possible to accurately evaluate the fluctuation characteristics due to the reliability of the circuit block Can be obtained.

1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment. 1 is a circuit diagram of a switch circuit used in a semiconductor integrated circuit according to a first embodiment. It is a time chart which shows the selection state of the signal waveform applied to the semiconductor integrated circuit of 1st Embodiment, and an internal circuit. 3 is a flowchart of a process (operation inspection process) for measuring characteristics of each circuit block of the semiconductor integrated circuit according to the first embodiment. FIG. 6 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment. It is a circuit diagram of the switch circuit used for the semiconductor integrated circuit of 2nd Embodiment. It is a time chart which shows the selection state of the signal waveform applied to the semiconductor integrated circuit of a 2nd embodiment, and an internal circuit. It is a flowchart of the process of the reliability accelerated test performed with respect to each circuit block of the semiconductor integrated circuit of 2nd Embodiment. It is a circuit diagram of a conventional semiconductor integrated circuit. It is a time chart which shows the selection state of the signal waveform applied to the conventional semiconductor integrated circuit, and an internal circuit.

  Hereinafter, embodiments of a semiconductor integrated circuit will be described with reference to the drawings. In addition, since the component which attached | subjected the same code | symbol in embodiment performs the same operation | movement, description may be abbreviate | omitted again.

(First embodiment)
A first embodiment of the present invention will be described.

  FIG. 1 is a circuit diagram of a semiconductor integrated circuit 100 according to the first embodiment when the selection circuit is constituted by a plurality of delay flip-flop circuits. FIG. 2 is a circuit diagram of the switch circuits Sa1, Sa2,... San used in the semiconductor integrated circuit 100 of FIG. FIG. 3 is a time chart showing a signal waveform applied to the semiconductor integrated circuit and a selection state of the internal circuit.

  The semiconductor integrated circuit 100 includes a power supply terminal 1 connected to the non-ground side (voltage side) of the power supply, a power supply terminal 2 connected to the ground side of the power supply, and a plurality of circuit blocks B1 in which the main body integrated circuit is divided into blocks. Bn and a plurality of switch circuits Sa1, Sa2,... San corresponding to each of the plurality of circuit blocks B1, B2,... Bn, and a plurality of switch circuits Sa1, Sa2,. A plurality of delay flip-flop circuits DFF1, DFF2,... DFFn, a CLK terminal 6 to which a clock pulse signal is input, a plurality of switch circuits Sa1, Sa2,. Vcc terminal 7 for applying a Vcc power supply for operating DFFn, DFF2,... DFFn, and a Data signal are input. A Data terminal 8 is constituted by a GND terminal 15 to be grounded.

  All of the plurality of circuit blocks B1, B2,... Bn are commonly connected to the power supply terminal 1. The plurality of circuit blocks B1, B2,... Bn are also connected to the power supply terminal 2 through the plurality of switch circuits Sa1, Sa2,. That is, the circuit block Bi is connected to the power supply terminal 2 via the switch circuit Sai corresponding to the circuit block Bi.

  The plurality of switch circuits Sa1, Sa2,... San are each composed of an N-channel MOS transistor 10, a P-channel MOS transistor 11, an N-channel MOS transistor 12, and an inverter circuit 13, as shown in FIG. . Hereinafter, the i-th switch circuit Sai will be described as a representative. In the switch circuit Sai, the gate terminal of the N-channel MOS transistor 10 is connected to the NQ terminal of the delay flip-flop circuit DFFi, and a voltage is applied to the gate terminal to output an NQi (hereinafter referred to as “circuit block selection signal”) of the NQ terminal. NQi ”) becomes (H), thereby connecting the power supply terminal 2 and the circuit block Bi. The P channel MOS transistor 11 has its gate terminal connected to the NQ terminal of the delay flip-flop circuit DFFi via the inverter circuit 13, and a voltage is applied to the gate terminal (that is, the circuit block selection signal of the NQ terminal). When NQi becomes (H) and the output of the inverter circuit 13 becomes (L), the power supply terminal 2 and the circuit block Bi are connected. The N-channel MOS transistor 12 has its gate terminal connected to the NQ terminal of the delay flip-flop circuit DFFi via the inverter circuit 13, and a voltage is applied to the gate terminal (that is, the output Qi of the NQ terminal is ( L) and the output of the inverter circuit 13 becomes (H)), thereby connecting the GND terminal 15 and the circuit block Bi.

  As described above, the switch circuit Sai switches ON / OFF of the N-channel MOS transistor 10, the P-channel MOS transistor 11, and the N-channel MOS transistor 12 based on the circuit block selection signal NQi of the delay flip-flop circuit DFFi. Do. Specifically, in the switch circuit Sai, when the circuit block selection signal NQi is (H), the N-channel MOS transistor 10 and the P-channel MOS transistor 11 are turned on and the N-channel MOS transistor 12 is turned off. As a result, the circuit block Bi is connected to the power supply terminal 2 and disconnected from the GND terminal 15. For this reason, the circuit block Bi is connected to the power supply terminal 2 by the switch circuit Sai, and the voltage from the power supply terminal 1 and the power supply terminal 2 is applied. On the other hand, in the switch circuit Sai, when the circuit block selection signal NQi is (L), the N-channel MOS transistor 10 and the P-channel MOS transistor 11 are turned off and the N-channel MOS transistor 12 is turned on. As a result, the circuit block Bi is disconnected from the power supply terminal 2 and connected to the GND terminal 15.

  The plurality of delay flip-flop circuits DFF1, DFF2,... DFFn function as a selection circuit by constituting a shift register circuit by being connected in series. Note that the selection circuit here refers to a plurality of switch circuits Sa1 based on external inputs (in this embodiment, a clock pulse signal input to the CLK terminal 6 and a Data signal input to the Data terminal 8). , Sa2,... San is a circuit that selects one or more switch circuits. The one or more switch circuits selected by the selection circuit connect the circuit block corresponding to the switch circuit and the power supply terminal 2. The D terminal (data terminal) of the first-stage delay flip-flop circuit DFF1 in the shift register circuit is connected to the Data terminal 8 and receives a Data signal as an external input through the Data terminal 8. A terminal in which all of the C terminals (clock terminals) of the plurality of delay flip-flop circuits DFF1, DFF2,... DFFn are connected in common is connected to the CLK terminal 6, and as an input from the outside via the CLK terminal 6. A clock pulse signal is received. As described above, each delay flip-flop circuit DFF1, DFF2,... DFFn is connected in series to form a shift register circuit, and each delay flip-flop circuit DFF1, DFF2,. Every time, the signal input to the D terminal is output to the Q terminal. For this reason, the signal output from the Q terminal is shifted to the delay flip-flop circuit on the right by one each time the clock pulse signal is input.

  In the semiconductor integrated circuit 100 according to the first embodiment, with the configuration as described above, a plurality of delay flip-flop circuits DFF1, DFF2,... Functioning as a selection circuit by controlling the Data signal and the clock pulse signal. One or more switch circuits are selected by DFFn, and the circuit block corresponding to the switch circuit and the power supply terminal 2 are electrically connected.

  Hereinafter, a method for simultaneously selecting a plurality of circuit blocks will be described with reference to FIG. FIG. 3 is a time chart showing signal waveforms applied to the semiconductor integrated circuit and internal circuit selection states when there are eight circuit blocks B1, B2,... Bn in FIG. is there. FIG. 3 shows waveforms of the clock pulse signal and the Data signal particularly when the circuit blocks B2 and B3 are selected.

  First, reset signals are input to all the delay flip-flop circuits DFF1 to DFF8, and the outputs Q of all the delay flip-flop circuits DFF1 to DFF8 are set to (L).

  Next, the same number (eight) of clock pulse signals as all the circuit blocks B1 to B8 are input to the CLK terminal 6, and a Data signal for selecting the circuit blocks B2 and B3 is input to the Data terminal 8. Each pulse of the eight clock pulse signals corresponds to each of the circuit blocks B1 to B8, and from the right end pulse to the left direction with respect to the circuit blocks B1, B2,... B8 arranged in the right direction from the left end. Corresponding to each pulse in order. That is, the rightmost pulse in the eight clock pulse signals corresponds to the leftmost circuit block B1, the second pulse from the right corresponds to the circuit block B2, and the third pulse from the right corresponds to the circuit block B3. The leftmost pulse corresponds to the circuit block B8. The Data signal is set so that an arbitrary circuit block is selected by setting (H) or (L) for each pulse of the clock pulse signal. When an arbitrary circuit block is selected, the (L) Data signal is set for the corresponding clock pulse signal. Specifically, when the circuit blocks B2 and B3 are selected, the Data signal is set to (L) for the sixth and seventh pulses from the left of the clock pulse signal, and for other pulses ( H) Data signal is set.

  When a clock pulse signal is input to this Data signal, the signals at the D terminal of all the delay flip-flop circuits DFF1 to DFF8 are output to the Q terminal. The inputs to the D terminals of the delay flip-flop circuits DFF1 to DFF8 are (H), and the outputs Q1 to Q8 output from the Q terminals of all the delay flip-flop circuits DFF1 to DFF8 are (L).

  Since the Data signal is (L) in the next sixth pulse period, when the sixth pulse is input, the output Q1 of the Q terminal of the delay flip-flop circuit DFF1 becomes (L), and the NQ terminal The output NQ1 (circuit block selection signal NQ1) is (H). On the other hand, when the sixth pulse is input, since the inputs to the D terminals of the other delay flip-flop circuits DFF2 to DFF8 are all (L), the outputs NQ2 to NQ8 (circuit block selection signal NQ1) of the NQ terminal ˜NQ8) becomes (L).

  Similarly, when the seventh pulse is input, the Data signal is (L) in the period of the seventh pulse, and the output Q1 is (L) when the seventh pulse is input. The output Q2 of the Q1 and the output Q2 of the Q terminal of the delay flip-flop circuit DFF2 becomes (L), and the circuit block selection signal NQ1 and the circuit block selection signal NQ2 of the delay flip-flop circuit DFF2 adjacent to the right become (H). When the seventh pulse is input, all the inputs to the D terminals of the other delay flip-flop circuits DFF3 to DFF8 are (H), so that the circuit block selection signals NQ3 to DFF3 of the delay flip-flop circuits DFF3 to DFF8 are input. NQ8 becomes (L).

  When the last 8th pulse is input, since the output Q1 and the output Q2 are (L) when the 8th pulse is input, the output Q1 is (H), and the output Q2 and the output Q2 are output. Q3 becomes (L), and the circuit block selection signal NQ2 and the circuit block selection signal NQ3 become (H). Further, the Data signal is (H) in the period of the eighth pulse, and all the inputs to the D terminals of the other delay flip-flop circuits DFF4 to DFF8 are (H) when the eighth pulse is input. The circuit block selection signals NQ1 and NQ4 to NQ8 of the delay flip-flop circuits DFF1 and DFF4 to DFF8 are (L).

  As a result, a clock pulse signal having the same number of pulses as the number of circuit blocks is input to the CLK terminal 6, and a Data signal for selecting the circuit blocks B2 and B3 is input to the D terminal of the first-stage delay flip-flop circuit DFF1. The circuit blocks B2 and B3 and the power supply terminal 2 are connected, and the characteristics of the circuit blocks B2 and B3 can be measured. In addition, for example, a clock pulse signal having the same number of pulses as the number of circuit blocks is input to the CLK terminal 6, and the Data signal is set to (L) for the entire period of the clock pulse signal, so that All circuit blocks can be selected by inputting to the terminals. In this way, the clock pulse signal having the same number of pulses as the number of circuit blocks and the Data signal for selecting an arbitrary circuit block are input to the external terminals (CLK terminal 6 and D terminal of the flip-flop circuit DFF1). Thus, an arbitrary circuit block can be selected, and the characteristics of the selected circuit block can be measured.

  By using the method of selecting one or more circuit blocks of the semiconductor integrated circuit 100 described above, the characteristics of each circuit block of the semiconductor integrated circuit 100 are measured as shown in FIG. FIG. 4 is a flowchart of processing (operation inspection processing) for measuring characteristics of each circuit block of the semiconductor integrated circuit 100 according to the first embodiment. FIG. 4 is a flowchart of the operation inspection process when there are eight circuit blocks.

  In this process, first, an operation inspection of all circuit blocks is performed to determine whether or not a defective circuit block is included (S11). If it is determined that the product is non-defective, the operation inspection process is terminated.

  If it is determined in step S11 that the product is defective, the following defective product specifying process in steps S12 to S28 is performed in order to specify a circuit block that is defective. That is, in the operation inspection process, a process for determining whether or not all circuit blocks are non-defective products and a defective product specifying process are performed.

  Hereinafter, the defective product specifying process will be described. In the defective product specifying process, four circuit blocks B1 to B4, which are half of the eight circuit blocks, are selected to perform operation inspection, and whether or not the selected circuit blocks B1 to B4 include defective circuit blocks. Is determined (S12).

  If it is determined in step S12 that a defective circuit block is included, two circuit blocks B1 and B2 which are half of the four circuit blocks B1 to B4 are selected to perform operation inspection, and the selected circuit is selected. It is determined whether or not defective blocks are included in the blocks B1 and B2 (S13).

  If it is determined in step S13 that a defective circuit block is included, an operation inspection is performed on the circuit block B1 (S14), an operation inspection is performed on the circuit block B2 (S15), and the circuit block B3 is detected. An operation inspection is performed on the circuit block B4 (S17). Here, if it is determined in step S13 that a defective circuit block is included, it is determined that at least one of the four circuit blocks B1 to B4 is defective. Then, by performing steps S14 to S17, a defective product among the four circuit blocks B1 to B4 is specified.

  If it is determined in step S13 that a defective circuit block is not included (that is, it is determined that the circuit block is a non-defective circuit block), an operation inspection is performed on the circuit block B3 (S18). An operation inspection is performed on the block B4 (S19). Here, if it is determined in step S13 that a defective circuit block is not included, at least one of the remaining two circuit blocks B3 and B4 out of the four circuit blocks B1 to B4 is defective. It is determined that the circuit block is included. Then, by performing step S18 and step S19, a defective product in the circuit block B3 and the circuit block B4 is specified.

  If it is determined in step S12 that the defective circuit block is not included, the remaining four circuit blocks B5 to B8 of the eight circuit blocks B1 to B8 are further divided into two circuit blocks B5 and B6. Is selected to determine whether or not a defective circuit block is included (S20).

  If it is determined in step S20 that a defective circuit block is included, an operation inspection is performed on the circuit block B5 (S21), an operation inspection is performed on the circuit block B6 (S22), and the circuit block B7 is detected. An operation test is performed on the circuit block B8 (S24). Here, if it is determined in step S20 that a defective circuit block is included, it is determined that at least one of the four circuit blocks B5 to B8 is defective. Then, by performing steps S21 to S24, defective products among the four circuit blocks B5 to B8 are specified.

  If it is determined in step S20 that no defective circuit block is included, an operation inspection is performed on the circuit block B7 (S25), and then an operation inspection is performed on the circuit block B8 (S26). Here, if it is determined in step S20 that no defective circuit block is included, one of the remaining half of the four circuit blocks B5 to B8 is not defective. It is determined that a circuit block is included. Then, by performing step S251 and step S26, a defective product in the circuit block B7 and the circuit block B8 is specified. When step S20 or step S26 ends, the defective product identification process ends, and the operation inspection process ends.

  When step S17 or step S19 is completed, the remaining four circuit blocks B5 to B8 of the eight circuit blocks B1 to B8 are selected to perform operation inspection, and defective circuit blocks are found in the selected circuit blocks B5 to B8. It is determined whether it is included (S27).

  If it is determined in step S27 that a defective circuit block is included, two circuit blocks B5 and B6, which are further half of the four circuit blocks B5 to B8, are selected to perform an operation inspection, and a defective circuit is selected. It is determined whether or not a block is included (S28). On the other hand, if it is determined in step S27 that no defective circuit block is included, the defective product specifying process is terminated, and the operation inspection process is terminated.

  If it is determined in step S28 that a defective circuit block is included, an operation inspection is performed on the circuit block B5 (S29), an operation inspection is performed on the circuit block B6 (S30), and the circuit block B7 is detected. An operation test is performed on the circuit block B8 (S32). Here, if it is determined in step S28 that a defective circuit block is included, it is determined that at least one of the four circuit blocks B5 to B8 is defective. Then, by performing steps S29 to S32, a defective product among the four circuit blocks B5 to B8 is specified.

  If it is determined in step S28 that no defective circuit block is included, an operation inspection is performed on the circuit block B7 (S33), and then an operation inspection is performed on the circuit block B8 (S34). Here, if it is determined in step S28 that no defective circuit block is included, one of the remaining two circuit blocks B7 and B8 out of the four circuit blocks B5 to B8 has a defective product block. It is determined that a circuit block is included. Then, by performing Step S33 and Step S34, it is specified that either the circuit block B7 or the circuit block B8 is a defective product. When step S32 or step S34 ends, the defective product identification process ends, and the operation inspection process ends.

  As described above, according to the first embodiment, the same number (n) of clock pulse signals as all the circuit blocks B1, B2,... Bn are input to the CLK terminal 6, and the Data signal for selecting an arbitrary circuit block is received. By inputting to the Data terminal 8, a specific plurality of circuit blocks can be selected. Then, when a defective circuit block is specified for the circuit block configured by the semiconductor integrated circuit 100 having the eight circuit blocks B1 to B8 as described above, it is used to select a specific plurality of circuit blocks. As a result, the number of inspections can be reduced as compared with the conventional semiconductor integrated circuit, and the inspection time can be shortened.

  Specifically, in the conventional semiconductor integrated circuit, since eight circuit blocks B1 to B8 are inspected for each block, eight inspections are always required. However, as shown in FIG. By performing the inspection of eight circuit blocks while selecting a plurality of circuit blocks by performing the above, it is possible to perform inspection 4 to 12 times in the defective product specifying process. Moreover, considering the low incidence of defective products, the inspection can be completed with only one inspection if no defective products occur in all circuit blocks, which is very effective in reducing the inspection time. . For this reason, when the inspection time for one circuit block is set to 1 sec, the inspection time can be shortened by up to 4 sec and half as compared with the conventional circuit. For this reason, the cost concerning an inspection can be reduced more than before.

(Second Embodiment)
A second embodiment will be described.

  FIG. 5 is a circuit diagram of the semiconductor integrated circuit 200 according to the second embodiment when the selection circuit is constituted by a plurality of delay flip-flop circuits, as in FIG. FIG. 6 is a circuit diagram of switch circuits Sb1, Sb2,... Sbn used in the semiconductor integrated circuit 200 of FIG. FIG. 7 is a time chart showing a signal waveform applied to the semiconductor integrated circuit 200 and a selection state of the internal circuit.

  The semiconductor integrated circuit 200 further includes a QC terminal 9 as an external terminal with respect to the semiconductor integrated circuit 100 of the first embodiment of FIG. The QC terminal 9 is connected in parallel to all the switch circuits Sb1, Sb2,... Sbn.

  The switch circuits Sb1, Sb2,... Sbn connect the corresponding circuit block and the power supply terminal 2 when a voltage is applied to the QC terminal 9, respectively. Different from Sb2,... Sbn. That is, the switch circuits Sb1, Sb2,... Sbn control connections between all the circuit blocks B1, B2,... Bn and the power supply terminal 2 based on the input from the QC terminal 9.

  Specifically, as shown in FIG. 6, the switch circuits Sb1, Sb2,... Sbn are composed of only N-channel MOS transistors whose reliability deterioration is small when high-temperature voltage is applied. A MOS transistor 12, an N-channel MOS transistor 14, and a resistor 16 are included. Hereinafter, the i-th switch circuit Sbi will be described as a representative. In the switch circuit Sbi, the gate terminal of the N-channel MOS transistor 10 is connected to the NQ terminal of the delay flip-flop circuit DFFi, and a voltage is applied to the gate terminal to output an NQi (hereinafter referred to as “circuit block selection signal”) of the NQ terminal. NQi ”) becomes (H), thereby connecting the power supply terminal 2 and the circuit block Bi. The N-channel MOS transistor 12 has a gate terminal connected to the Q terminal of the delay flip-flop circuit DFFi, and a voltage is applied to the gate terminal (that is, the output Qi of the Q terminal becomes (H)). Thus, the GND terminal 15 is connected to the circuit block Bi. Further, the N-channel MOS transistor 14 has a gate terminal connected to the QC terminal 9 and a voltage is applied to the gate terminal (that is, a voltage is applied to the QC terminal 9). And connect. That is, the switch circuit Sbi according to the second embodiment includes the N-channel MOS transistor 14 for connecting the circuit block Bi and the power supply terminal 2, and the QC terminal 9 in which the gate terminal of the N-channel MOS transistor is an external terminal. Connected to.

  As described above, the switch circuit Sbi switches ON / OFF of the N-channel MOS transistor 10 and the N-channel MOS transistor 12 based on the circuit block selection signal NQi of the delay flip-flop circuit DFFi. Specifically, in the switch circuit Sbi, when the circuit block selection signal NQi is (H), the N-channel MOS transistor 10 is turned on. At this time, the output Qi is (L). It becomes OFF. That is, when the circuit block selection signal NQi of the delay flip-flop circuit DFFi is switched to (H) or (L), the switch circuit Sbi according to the second embodiment is similar to the switch circuit Sbi according to the first embodiment. The connection destination of the block Bi is switched between the power supply terminal 2 and the GND terminal 15. Therefore, the method of selecting each circuit block B1, B2,... Bn is the same as the circuit of the first embodiment.

  Since the switch circuit Sbi according to the second embodiment has the N-channel MOS transistor 14 unlike the first embodiment, a voltage is applied to the gate terminal of the N-channel MOS transistor 14 by the QC terminal 9. Then, the circuit block Bi and the power supply terminal 2 are connected. Since the plurality of switch circuits Sb1, Sb2,... Sbn are all connected in common with the QC terminal 9, when a voltage is applied by the QC terminal 9, all the circuit blocks B1, B2,. And the power supply terminal 2 are connected. Thereby, all the circuit blocks B1, B2,... Bn and the power supply terminal 2 can be connected without operating the delay flip-flop circuits DFF1, DFF2,. Since the delay flip-flop circuits DFF1, DFF2,... DFFn are not operated and all the circuit blocks B1, B2,... Bn are connected to the power supply terminal 2, the state of the Q terminal at this time is Indefinite. At this time, the N-channel MOS transistor 12 of the switch circuit Sbi has a low potential (L) because its gate terminal is connected to the GND terminal 15 via the resistor 16, and the connection between the GND terminal 15 and the circuit block Bi is established. Cut off.

  Note that a GND potential is applied to the QC terminal 9 when performing an operation inspection process for measuring the characteristics of the circuit blocks B1, B2,... Bn. When a voltage is applied to all the circuit blocks B1, B2,... Bn, the same voltage as that of the power supply terminal 2 is applied to the QC terminal 9.

  FIG. 8 shows a method of connecting all the circuit blocks B1, B2,... Bn and the power supply terminal 2 by applying a voltage to the QC terminal 9 of the semiconductor integrated circuit 200 described above. As described above, a reliability acceleration test can be performed on the semiconductor integrated circuit 200. FIG. 8 is a flowchart of a reliability acceleration test process performed on each circuit block of the semiconductor integrated circuit 200.

  In the reliability acceleration test, first, a Vcc voltage (= 3.3 V) is applied to the Vcc terminal 7 and a GND potential is applied to the QC terminal 9 (S41).

  Next, by using the circuit block selection method described in the first embodiment, the process of measuring the initial characteristics of the circuit block (S43, S44) is performed on each circuit block B1, B2,... Bn. Repeatedly (loop 1: S42 to S45).

  First, an arbitrary circuit block is selected by inputting a clock pulse signal to the CLK terminal 6 and inputting a Data signal to the Data terminal 8 (S43). Then, the initial characteristics of the selected circuit block are measured (S44).

  For example, when the circuit block B3 is selected, as shown in FIG. 7, the input to the QC terminal 9 is set to (L) in all periods and the N-channel MOS transistor 14 is turned off and the clock pulse signal is turned off. A Data signal in which (L) is set in accordance with only the sixth pulse is input. Thus, when the eighth pulse of the clock pulse signal is input, the circuit block B3 and the power supply terminal 2 are connected by the switch circuit S3. Note that step S42 and step S43 are performed after the circuit blocks B1, B2,... Bn are selected one by one in order.

  Next, in order to hold for a long time in a high temperature state and a high voltage application state, the GND potential is applied to the Vcc terminal 7 in a high temperature state (S46). Then, the stress voltage Vs is applied to the power supply terminal 1, the power supply terminal 2, and the QC terminal 9 (S47). As a result, the stress voltage Vs is applied to all the circuit blocks B1, B2,... Bn. At this time, a high voltage is applied to the N-channel MOS transistors 14 of the switch circuits Sb1, Sb2,... Sbn, but no voltage is applied to the delay flip-flop circuits DFF1, DFF2,.

  Again, a Vcc voltage (= 3.3 V) is applied to the Vcc terminal 7 and GND is set to the QC terminal 9 (S48).

  Then, again, the process (S50, S51) of measuring the characteristics of the circuit block at a high temperature and after applying a high voltage is repeatedly performed on each circuit block B1, B2,... Bn (loop 2: S49 to S52). ).

  In this state, an arbitrary circuit block is selected by inputting a clock pulse signal to the CLK terminal 6 and inputting a Data signal to the Data terminal 8 (S50). Then, the characteristics of the selected circuit block at a high temperature and after application of a high voltage are measured (S51). Note that step S47 and step S48 are performed after the circuit blocks B1, B2,... Bn are selected one by one in order.

  As described above, according to the second embodiment, when performing a reliability acceleration test by applying a high voltage under a high temperature state, the stress voltage Vs is not applied to the plurality of delay flip-flop circuits DFF1, DFF2,. All the switch circuits Sb1, Sb2,... Sbn are composed of only N-channel MOS transistors that are in a high temperature state and have a small characteristic deterioration due to application of a high voltage. Therefore, it is possible to accurately measure the characteristic variation due to the application of the high voltage and the high temperature state of the plurality of circuit blocks B1, B2,... Bn. Further, by applying the same voltage as the power supply terminal 2 to the QC terminal 9, all the circuit blocks B1, B2,... Bn are operated without operating all the delay flip-flop circuits DFF1, DFF2,. The voltage of the power supply terminal 2 can be applied to.

  Although the semiconductor integrated circuit according to the present invention has been described based on the embodiment, the present invention is not limited to this embodiment.

  That is, the embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  For example, in the above embodiment, the measurement target is a circuit block, but it may be a single transistor.

  In the above-described embodiment, the semiconductor integrated circuits 100 and 200 are targeted for TEG (Test Element Group). However, by mounting in a product other than the TEG, the identification and reliability of the defective circuit block for the defective chip are provided. This makes it possible to evaluate the deterioration characteristics, and to easily analyze the cause of the failure.

  In the above embodiment, a shift register circuit configured by connecting a plurality of delay flip-flop circuits DFF1, DFF2,... DFFn in series is employed as the selection circuit. However, the present invention is not limited to this, and a plurality of other flip-flop circuits may be connected. For example, a shift register circuit may be adopted as a selection circuit by connecting a plurality of JK flip-flop circuits in series.

  The semiconductor integrated circuit according to the present invention can shorten the inspection time for specifying a defective circuit block, and also has an effect of accurately measuring characteristic deterioration in a reliability acceleration test of each circuit block. It is useful as a circuit.

DESCRIPTION OF SYMBOLS 1 Power supply terminal 2 Power supply terminal 3 Measuring terminal 4 EN terminal 5 R / S terminal 6 CLK terminal 7 Vcc terminal 8 Data terminal 9 QC terminal 10 N channel MOS transistor 11 P channel MOS transistor 12 N channel MOS transistor 13 Inverter circuit 14 N channel MOS transistor 15 GND terminal 16 Resistor 100, 200 Semiconductor integrated circuit B1, B2,... Bn Circuit block Bi Circuit block DFF1, DFF2,... DFFn Delay flip-flop circuit DFFi San switch circuits Sb1, Sb2,... Sbn switch circuits Sc1, Sc2,... Scn switch circuit Sai switch circuit Sbi switch circuit Sci switch circuit Qi output NQi output

Claims (4)

A plurality of circuit blocks;
A plurality of switch circuits provided corresponding to each of the plurality of circuit blocks and controlling connection between the corresponding circuit block and the power supply terminal;
A plurality of flip-flop circuits provided corresponding to each of the plurality of switch circuits and outputting a circuit block selection signal to the corresponding switch circuit,
The plurality of flip-flop circuits are connected in series to form a shift register circuit, and two or more switch circuits are selected from the plurality of switch circuits based on an input of an external signal, and the two or more flip-flop circuits are selected. Outputting the circuit block selection signal indicating selection to the switch circuit;
The two or more switch circuits to which a circuit block selection signal indicating the selection is input connect a circuit block corresponding to each of the two or more switch circuits and the power supply terminal. The external signal is input to an input terminal of the first flip-flop circuit in the shift register circuit and a terminal commonly connected to all clock terminals of the plurality of flip-flop circuits. Semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1, wherein the plurality of switch circuits control connection between all the circuit blocks and a power supply terminal based on an input from an external terminal. The plurality of switch circuits are:
An N-channel MOS transistor for connecting the circuit block and a power supply terminal;
The semiconductor integrated circuit according to claim 3, wherein a gate terminal of the N-channel MOS transistor is connected to the external terminal.

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