JP2012159454A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the speed of testing a power supply switch used for supplying power to an arbitrary function block provided on a semiconductor integrated circuit.SOLUTION: A power supply switch comprises two transistors which are serially connected between a power supply rail and a function block. The conductive states of those two transistors can be independently controlled. At a contact point between the two transistors, an observation node for detecting the result of a power supply switch test is provided. Reduced capacity of the observation node allows reduction of the time taken until the voltage change at the observation node is stabilized.

Description

  The present invention relates to a semiconductor integrated circuit and a test method using the semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a power switch and a test method using the semiconductor integrated circuit.

  With the recent miniaturization of semiconductor processes, the relative ratio of leakage power components in the total power of semiconductors has increased. In order to reduce the leakage power, many techniques for adding a power gating function are employed.

  A main component of the power gating function is a power switch. Since the conventional power switch test is performed in an analog manner, it cannot be integrated with other general logic circuit tests, and requires a long test time.

  In semiconductor integrated circuits where the power supply from the power supply can be cut off by the power switch, the test time is shortened along with the increase in low-cost requirements, especially the test time for guaranteeing the normal operation of the power switch, which has taken a long time. The need for is increasing.

  In relation to the above, Japanese Unexamined Patent Application Publication No. 2009-523229 discloses a conventional technique for a technique for detecting a failure of a power switch. FIG. 1 is a circuit diagram showing a configuration of an IC (Integrated Circuit) including a conventional technique.

  The IC 200 of FIG. 1 includes hardware for testing the switch 115 provided between the power supply rail 110 and an optional functional block 130. Note that a P-type MOS transistor 115 is actually mounted as the switch 115.

  The IC 200 further includes a multiplexer 220. The multiplexer 220 has a switching signal input unit, a first input unit, a second input unit, and an output unit. The output part of the multiplexer 220 is connected to the gate of the P-type MOS transistor 115. A first input of multiplexer 220 is coupled to controller 140 for receiving a function activation signal for transistor 115. A second input of multiplexer 220 is coupled to test controller 210 for receiving a test activation signal for transistor 115. The test controller 210 outputs a test operation signal from one output unit, and outputs a control signal from the other output unit.

  The IC 200 further includes a comparator 230. The comparator 230 inputs the reference signal from the reference signal source 215 to one input unit, and inputs the signal extracted from the node 225 connected between the transistor 115 and the functional block 130 to the other input unit. . The comparator 230 compares these two signals, generates a comparison result signal as a result, and outputs the comparison result signal to the output unit 240. Here, the reference signal source 215 is connected to one output section of the test controller 210 described above. That is, the test operation signal is also used as the reference signal.

  During normal operation of the IC 200, the control signal from the test controller 210 controls the multiplexer 220, and the multiplexer 220 outputs the control signal from the controller 140 to the switch 115. A control signal from the controller 140 controls the switch 115. As a result, the function block 130 is separated from the power supply rail 110 when it is determined that the function is unnecessary.

  When the IC 200 is tested, the output unit of the multiplexer 220 is connected to the second input unit in accordance with a control signal from the test controller 210. The output signal of the multiplexer 220 controls the transistor 115. At this time, the comparator 230 compares the reference signal from the reference signal source 215 with the signal extracted from the node 225 between the transistor 115 and the functional block 130, and generates and outputs a comparison result signal as a result. Output to the unit 240.

During the test, the failure of the transistor 115 is detected by observing the node 240 which is the output unit of the comparator 230 using the two test patterns shown in the following table (Table 1).

  A failure detection method using the above two test patterns will be described. First, in the first test pattern, the multiplexer 220 selects and outputs a test operation signal from the test controller 210 in accordance with a control signal from the test controller 210. In the first test pattern, the test activation signal has a value of “1”, ie a logic high. Therefore, the P-type MOS transistor 115 is switched off.

  As a result, the node 225 is grounded via the functional block 130 to the ground supply rail 120. At the first and second inputs of the comparator 230, on the one hand, the reference signal, ie the test activation signal, has a logic high value, and on the other hand, a logic low value is derived from the grounded node 225. Therefore, the comparison result signal generated based on these two input signals has a logic high value. This is a comparison result signal that should be obtained when the transistor 115 is functioning normally.

  Here, consider a case where the transistor 115 has a stuck-at fault in the logic high state. At this time, the node 225 generates a signal having a logic high value that is a state at the time of failure of the transistor 115. As a result, the comparison result signal generated by the comparator 230 has a logic low value.

  As described above, by using the first test pattern, the stuck-at fault related to the logic high state in the switch 115 can be detected.

  Next, the second test pattern will be described. Similar to the first test pattern, the multiplexer 220 selects and outputs the test operation signal input unit from the test controller 210 in accordance with the control signal from the test controller 210. However, in the second test pattern, the test activation signal has a value of “0”, that is, a logic low. Therefore, the P-type MOS transistor 115 is switched on.

  As a result, the node 225 is conducted through the switch 115 to the power supply rail 110 that supplies the power supply voltage Vdd. At the first and second inputs of the comparator 230, on the one hand, the reference signal, ie the test activation signal, has a logic low value, and on the other hand, the node 225 has a logic high value. Therefore, the comparison result signal generated based on these two input signals has a logic high value. This is a comparison result signal that should be obtained when the transistor 115 is functioning normally.

  Here, consider the case where the transistor 115 has a stuck-at fault in the logic low state. At this time, the node 225 generates a signal having a logic low value which is a state at the time of failure of the transistor 115. Thus, the comparison result signal generated by the comparator 230 has a logic low.

  As described above, by using the second test pattern, it is possible to detect the stuck-at fault related to the logic low state for the switch 115.

  Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2009-264948) discloses a description relating to a semiconductor device. The semiconductor device includes a circuit unit, a plurality of power switches, a control unit, and a response output unit. Here, the circuit portion operates by receiving supply of power supply voltage. The plurality of power switches are provided in a path of a power source current that flows when a power source voltage is supplied to the circuit unit. The control unit turns on or off the plurality of power switches via a common control line. The test switch unit is provided in the middle of the control line on the side close to the control unit, and electrically controls connection and disconnection of the control line. The response output unit is connected to the control line on the side far from the control unit, receives a change in the control line potential when the test switch unit cuts off or reconnects the control line, and outputs a test response.

Special table 2009-523229 JP 2009-264948 A

  The conventional technology described above as Patent Document 1 has a problem that the test time of the power switch shown as the switch 115 is long. As the cause, charging is accompanied by the operation of the power switch, and this charging takes time.

  In general, the power switch is often configured as a plurality of switches connected in parallel to functional blocks of about tens of thousands of logic cells. In this case, the ground capacitance of the observation node 225 in FIG. 1 is the sum of the source capacitances of all the transistors included in the various logic cells in the functional block 130, the drain capacitances of the plurality of power switches, the metal layer wiring capacitance, the parasitic capacitance, and the like. It becomes. It is not uncommon for the ground capacitance of the observation node 225 to increase to several hundred pF even in a fine manufacturing process.

A change in the voltage V ₂₂₅ (t) of the node 225 when the power supply line of the functional block in the ground is charged by turning on the switch 115 as the power switch is expressed by the following expression.
_V225 (t) = V (1-e- ^{t / RC} )
Here, V represents the power supply voltage, t represents time, R represents the ON resistance of the power switch, and C represents the ground capacitance of the node 225.

  As described above, the reason why the test time of the power switch according to the conventional technique shown in Patent Document 1 is long is summarized as follows. That is, when the observation node 225 is generally a power supply line having a large ground capacity and there is one switch 115 operating as a power switch as shown in FIG. 1, the ON resistance of the switch 115 cannot be reduced. For this reason, the voltage change time of the observation node 225 is long, and the failure of the power switch cannot be detected at high speed.

  The means for solving the problem will be described below using the numbers used in the (DETAILED DESCRIPTION). These numbers are added to clarify the correspondence between the description of (Claims) and (Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

  The semiconductor integrated circuit according to the present invention includes a first power source (110 and 120), a first power switch (115 and 116, 115: 11 and 116: 11), and a first observation node (240, 240: x1), a first initial voltage setting circuit (290, 290: x1), and a test controller (250). Here, the first and second power sources (110 and 120) supply power to an arbitrary functional block (130). The first power switch (115 and 116, 115: 11 and 116: 11) has two switches (115 and 116, 115: connected in series) operating in response to the first and second test time signals, respectively. 11 and 116: 11), and conducts or cuts off between the first power source (110) and the functional block (130). The first observation node (240, 240: x1) is connected to the midpoint of the two switches (115 and 116, 115: 11 and 116: 11), and the first power switch (115 and 116, 115: 11 and 116: 11). The first initial voltage setting circuit (290, 290: x1) conducts or cuts off between the first observation node (240, 240: x1) and the second power supply (120) according to the initial voltage setting signal. . The test controller (250) generates first and second test time signals and an initial voltage setting signal. For each of the two switches (115 and 116, 115: 11 and 116: 11), the test controller switches the states of the first and second test time signals and the initial voltage setting signal in a predetermined order. An abnormality at the time of transition from the ON state to the OFF state and an abnormality at the time of transition from the OFF state to the ON state are detected as a logical value abnormality in the first observation node (240, 240: x1).

  The method for testing a semiconductor integrated circuit according to the present invention includes a step in which the first and second power supplies (110 and 120) supply power to an arbitrary functional block (130), and a test controller (250). Generating a test time signal and an initial voltage setting signal; and a first power switch (115 and 116, 115: 11 and 116: 11), and a first power supply in response to the first and second test time signals (110) and the function block (130) are connected to or disconnected from each other, and the first initial voltage setting circuit (290, 290: x1) is connected to the first observation node (240, 240: x1) and the second power source (120) are connected to or disconnected from the first observation node (240, 240: x1). Switch (115 and 116,115: 11 and 116: 11) and a step of observing the state of. The step of conducting or cutting off between the first power source (110) and the functional block (130) is performed by a first switch (115, 115: 11) operating in response to a first test time signal. Conducting or cutting off between the power source (110) and the first observation node (240, 240: x1), and a second switch (116, 116: 11) operating in response to the second test time signal , Conducting or blocking between the first observation node (240, 240: x1) and the functional block (130). The generating step includes a step of switching the states of the first and second test time signals and the initial voltage setting signal in a predetermined order. The step of observing is the abnormality in transition from the ON state to the OFF state and the transition from the OFF state to the ON state for each of the first and second switches (115 and 116, 115: 11 and 116: 11). Is detected as a logical value abnormality in the first observation node (240, 240: x1).

  According to the semiconductor integrated circuit of the present invention, it is possible to increase the speed of the power switch test. The reason is that the capacitance of the observation node group (240, etc.) is connected to each connection part of the first switch group (115, etc.), the second switch group (116, etc.), and the initial voltage setting circuit group (290, etc.) and wiring. This is because it consists only of capacity. That is, the capacity of the observation node group (240, etc.) is smaller than that of the conventional observation node (225), and the time until the voltage change is stabilized is shortened.

FIG. 1 is a circuit diagram showing a configuration of an IC including a conventional technique. FIG. 2 is a circuit diagram showing a configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention.

  With reference to the accompanying drawings, a semiconductor integrated circuit according to the present invention and a test method using the semiconductor integrated circuit will be described below.

(First embodiment)
FIG. 2 is a circuit diagram showing a configuration of the semiconductor integrated circuit according to the first embodiment of the present invention. Components of the semiconductor integrated circuit 200 of FIG. 2 will be described. The semiconductor integrated circuit 200 of FIG. 2 includes a power supply rail 110, a first transistor 115 that operates as a first switch, a second transistor 116 that operates as a second switch, a ground supply rail 120, a function A block 130; a controller 150; a first multiplexer 220; a second multiplexer 221; an observation node 240; a test controller 250; and a voltage setting transistor 290 that operates as an initial voltage setting circuit 290. Yes.

  A connection relationship between the components of the semiconductor integrated circuit 200 of FIG. 2 will be described. The power supply rail 110 is connected to the source of the first transistor 115. The drain of the first transistor 115 is connected to the observation node 240, the source of the second transistor 116, and the drain of the voltage setting transistor 290. The drain of the second transistor 116 is connected to the first end of the functional block 130. A second end of the functional block 130 is connected to the ground supply rail 120 and the source of the voltage setting transistor 290. The first output unit in the test controller 250 is commonly connected to the switching signal input unit in each of the first and second multiplexers 220 and 221. A second output unit in the test controller 250 is connected to a first input unit in the first multiplexer 220. A third output unit in the test controller 250 is connected to a first input unit in the second multiplexer 221. A fourth output section in the test controller 250 is connected to the gate of the voltage setting transistor 290. An output unit of the controller 150 is commonly connected to a second input unit in each of the first and second multiplexers 220 and 221. The output portion of the first multiplexer 220 is connected to the gate of the first transistor 115. The output portion of the second multiplexer 221 is connected to the gate of the second transistor 116.

  The operation of the first and second multiplexers 220 and 221 in FIG. 2 will be described. The first input unit in the first multiplexer 220 receives the first test time signal output from the second output unit in the test controller 250. Further, the second input unit in the first multiplexer 220 receives the normal operation time control signal output from the controller 150. Further, the switching signal input unit of the first multiplexer 220 receives the test enable signal output from the first output unit in the test controller 250. The output unit of the first multiplexer 220 outputs a first test time signal from the test controller 250 during a test according to the test enable signal, and a normal operation time control signal from the controller 150 during a normal operation during non-test. Is output.

  Similarly, the first input unit in the second multiplexer 221 inputs the second test time signal output from the third output unit in the test controller 250. The second input unit in the second multiplexer 221 inputs a normal operation time control signal output from the controller 150. Further, the switching signal input unit of the second multiplexer 221 inputs the test enable signal output from the first output unit in the test controller 250. The output unit of the second multiplexer 221 outputs a second test time signal from the test controller 250 during the test in response to the test enable signal, and a normal operation time control signal from the controller 150 during the normal operation during the non-test. Is output.

  The operation of the first and second transistors 115 and 116 will be described. The first transistor 115 conducts or cuts off between the power supply rail 110 and the observation node 240 in accordance with a first test signal output from the test controller 250 via the first multiplexer 220. Similarly, the second transistor 116 conducts or cuts off between the observation node 240 and the functional block 130 in accordance with a second test time signal output from the test controller 250 via the second multiplexer 221.

  The function block 130 will be described. The functional block 130 is a circuit unit that is connected to a power supply rail and a ground supply rail to be supplied with electric power and perform an arbitrary operation. However, in the present invention, attention is paid to the operation of the first and second transistors 115 and 116, and the specific internal configuration of the functional block 130 is not important, and thus further detailed description is omitted. As will be described later, the functional block 130 preferably includes a virtual power supply line (not shown). This virtual power supply line is connected to the power supply rail 110 when both the first and second transistors 115 and 116 are in the ON state, and supplies power to the circuits inside the functional block 130.

  The operation of the voltage setting transistor 290 will be described. The voltage setting transistor 290 conducts or cuts off between the observation node 240 and the ground supply rail 120 according to the initial voltage setting signal output from the fourth output unit in the test controller 250.

  The overall operation of the semiconductor integrated circuit 200 of FIG. 2, that is, the semiconductor integrated circuit test method according to the first embodiment of the present invention will be described. First, in a normal operation during non-test, the test controller 250 outputs an inactive test enable signal from the first output unit. In response to the inactive test enable signal, both the first and second multiplexers 220 and 221 selectively output a normal operation control signal output from the controller 150. The control signal during normal operation from the controller 150 controls the first and second switches 115 and 116 simultaneously and similarly through the first and second multiplexers 220 and 221 so as to be in a conductive state or a cut-off state. . At this time, the initial voltage setting circuit 290 is turned off in response to the initial voltage setting signal output from the fourth output unit in the test controller 250. That is, the observation node 240 is disconnected from the ground supply rail 120.

Next, a case where the first and second switches 115 and 116 are normally operated during the test will be described. At the time of testing, it is performed by executing a plurality of steps in order. The following table (Table 2) summarizes the state of each part of the semiconductor integrated circuit according to the first embodiment of the present invention for each step executed during the test. Here, each column represents, in order from the left, the step name, the state of the first switch, the state of the second switch, the state of the initial voltage setting circuit 290, and the logical value of the observation node at the normal time. Steps 1 to 5 described in each row of this table (Table 2) are executed in this order.

  Step 1 will be described. Since both the first and second switches 115 and 116 are in the ON state, the power supply rail 110, the observation node 240, and the functional block 130 are all conducted. Furthermore, since the initial voltage setting circuit 290 is in the OFF state, the observation node 240 is not grounded to the ground supply rail. Accordingly, the logical value of the observation node 240 is 1. After step 1, step 2 is executed.

  Step 2 will be described. Both the first and second switches 115 and 116 are turned off, and the initial voltage setting circuit is turned on. Therefore, the voltage of the observation node 240 should be the ground voltage, that is, the logical value of the observation node 240 becomes zero. After step 2, execute step 3.

  Step 3 will be described. The first switch 115 maintains the OFF state, the second switch 116 enters the ON state, and the initial voltage setting circuit 290 enters the OFF state. At this time, the observation node 240 is separated from both the power supply rail and the ground supply rail, but is connected to the functional block 130. Therefore, the charge from the virtual power supply line in the functional block 130 flows back to the observation node 240, and the logical value of the observation node 240 is determined to be 1. After step 3, step 4 is executed.

  Step 4 will be described. The first switch 115 maintains the OFF state, the second switch 116 enters the OFF state, and the initial voltage setting circuit 290 enters the ON state. This state is the same as in step 2, and the logical value of the observation node 240 is zero. After step 4, step 5 is executed.

  Step 5 will be described. The first switch 115 is turned on, the second switch 116 is kept off, and the initial voltage setting circuit 290 is turned off. At this time, the observation node 240 is electrically connected to the power supply rail 110 and is separated from the ground supply rail and the functional block 130. Therefore, the charge from the power supply rail 110 flows into the observation node 240 and the logical value of the observation node 240 is determined to be 1. When step 5 ends, the test ends.

  In these steps 1 to 5, if the logical value of the observation node is as described above, it is guaranteed that both the first and second switches 115 and 116 are operating normally. Hereinafter, a case where the first and second switches 115 and 116 have a failure will be described.

  A case will be described in which the first switch 115 is out of order during the test and does not change from the OFF state to the ON state. In this case, in step 1, since the logical value of the observation node 240 cannot be 1, this failure is detected.

  A case where the first switch 115 is broken and does not change from the ON state to the OFF state during the test will be described. In this case, the logical value of the logical node 240 is 1 in Step 1, but the logical value of the observation node 240 cannot be 0 in Step 2. This is because the initial voltage setting circuit 290 attempts to set the logical value of the observation node 240 to 0, but the first switch 115 returns the logical value of the observation node 240 to 1. From this, this failure is detected.

  A case will be described in which the first switch 115 is normal and the second switch 116 is out of order and does not change from the OFF state to the ON state during the test. In this case, the logical value of the observation node 240 is 1 in Step 1 and 0 in Step 2, but cannot be 1 in Step 3. This is because the same state as step 2 is maintained if the second switch 116 remains OFF even in step 3. From this, this failure is detected.

  The case where the first switch 115 is normal and the second switch 116 is broken and does not change from the ON state to the OFF state during the test will be described. In this case, the logical value of the observation node 240 becomes 1 in Step 1 and 0 in Step 2, but does not change from 0 in Step 3. From this, this failure is detected.

  Note that the test controller 250 according to the present embodiment has a configuration capable of generating and outputting various signals as described above. More specifically, a configuration in which a predetermined program is executed by a general-purpose computer including a general input unit, a calculation unit, a storage unit, and an output unit may be used, or a configuration using a dedicated logic circuit may be used. In this case, the storage unit stores the table of Table 2 in advance, and the arithmetic unit controls various signals output from the output unit while referring to the storage unit according to the test start instruction input from the input unit, etc. Is desirable.

  The effect of the present invention will be described. The present invention has an effect of shortening the test time of the power switch test. The reason is that the capacity of the observation node 240 according to the present invention is sufficiently small as compared with the prior art, and the response speed is high. This is because the capacitance of the observation node 240 according to the present invention includes only the first and second switches 115 and 116, the initial voltage setting circuit 290, and the wiring capacitance.

  When the first switch 115 is OFF and the second switch 116 is ON, the observation node 240 is connected to the capacity of the virtual power supply line. However, the observation node 240 is disconnected from the power supply rail 110 and the ground supply rail 120. For this reason, the virtual power supply line separated from the power supply line 110 by the power switch composed of the first and second transistors 115 and 116 serves as a charge supply source, The observation node 240 having a sufficiently smaller capacity than the power supply line is charged. Therefore, the time until the voltage of the observation node 240 is stabilized is short.

  As a general configuration for shutting off the power, when the power switches are individually connected to each single logic cell, the power switches are inserted in the number corresponding to the number of logic cells to be shut off. In this case, since the circuit area increases, it is desirable to connect a single power switch to a functional block having at least several tens of logic cells.

  If the functional block has about several tens of logic cells, the capacity of the observation node of the present invention is 1/10 or less of the virtual power supply line capacity, and therefore the test time for one step proportional to the observation node capacity is also 1/10. It becomes as follows. At this time, even if the number of steps of the conventional test is 2 while the number of steps of the present invention is increased to 5, the total test time is ¼ or less of the time of the conventional example.

  Thus, the larger the circuit size of the functional block, the greater the effect of reducing the test time for one step, and the test total time is significantly shortened.

(Second Embodiment)
FIG. 3 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the second embodiment of the present invention. In the present embodiment, a case will be described in which a plurality of power switches are connected in parallel to a functional block 130 having a large circuit scale. In particular, FIG. 3 shows a configuration in which a plurality of power switches are surrounded by a broken line and the power switches are arranged in a two-dimensional array.

  Components of the semiconductor integrated circuit of FIG. 3 will be described. The semiconductor integrated circuit 200 of FIG. 3 includes a power supply rail 110, a first transistor 115: 11 that operates as a first switch, a second transistor 116: 11 that operates as a second switch, A third transistor 115: 12 operating as a switch, a fourth transistor 116: 12 operating as a fourth switch, a fifth transistor 115: 21 operating as a fifth switch, and a sixth switch A sixth transistor 116: 21 that operates, a seventh transistor 115: 22 that operates as a seventh switch, an eighth transistor 116: 22 that operates as an eighth switch, a ground supply rail 120, and a function Block 130, controller 150, first multiplexer 220: 1x, second Multiplexor 221: 1x, third multiplexer 220: 2x, fourth multiplexer 221: 2x, first observation node 240: x1, second observation node 240: x2, test controller 250, A first voltage setting transistor 290: x1 that operates as one initial voltage setting circuit 290: x1, and a second voltage setting transistor 290: x2 that operates as a second initial voltage setting circuit 290: x2. ing.

  A connection relationship between the components of the semiconductor integrated circuit 200 of FIG. 3 will be described. The power supply rail 110 is connected to the sources of the first, third, fifth, and seventh transistors 115: 11, 115: 12, 115: 21, and 115: 22. The first observation node 240: x1 includes the drain of the first transistor 115: 11, the source of the second transistor 116: 11, the drain of the fifth transistor 115: 21, and the sixth transistor 116: 21. And the drain of the first voltage setting transistor 290: x1. The second observation node 240: x2 includes the drain of the third transistor 115: 12, the source of the fourth transistor 116: 12, the drain of the seventh transistor 115: 22, and the eighth transistor 116: 22. And the drain of the second voltage setting transistor 290: x2.

  The first end of the functional block 130 is connected to the drain of the second transistor 116: 11. The second end of the functional block 130 is connected to the drain of the sixth transistor 116: 21. The third end of the functional block 130 is connected to the drain of the fourth transistor 116: 12. The fourth end of the functional block 130 is connected to the drain of the eighth transistor 116: 22. The ground supply rail 120 is connected to the fifth end of the functional block 130 and the sources of the first and second voltage setting transistors 290: x1, 290: x2.

  The first output unit in the test controller 250 is commonly connected to the switching signal input unit in each of the first to fourth multiplexers 220: 1x, 221: 1x, 220: 2x, 221: 2x. The second output of the test controller 250 is connected to the first input of the first multiplexer 220: 1x. The third output unit in the test controller 250 is connected to the first input unit in the second multiplexer 221: 1x. The fourth output section of the test controller 250 is commonly connected to the gates of the first and second voltage setting transistors 290: x1, 290: x2. The fifth output in the test controller 250 is connected to the first input in the third multiplexer 220: 2x. The sixth output section in the test controller 250 is connected to the first input section in the fourth multiplexer 221: 2x.

  The first output unit of the controller 150 is commonly connected to the second input unit of each of the first and second multiplexers 220: 1x and 221: 1x. The second output unit in the controller 150 is commonly connected to the second input unit in each of the third and fourth multiplexers 220: 2x and 221: 2x. The output of the first multiplexer 220: 1x is commonly connected to the gates of the first and third transistors 115: 11 and 115: 12. The output section of the second multiplexer 221: 1x is commonly connected to the gates of the second and fourth transistors 116: 11 and 116: 12. The output section of the third multiplexer 220: 2x is commonly connected to the gates of the fifth and seventh transistors 115: 21 and 115: 22. The output of the fourth multiplexer 221: 2x is commonly connected to the gates of the sixth and eighth transistors 116: 21, 116: 22.

  The above connection relationship can be rephrased as follows. That is, in FIG. 3, the first to fourth power switches are connected in parallel between the functional block 130 and the power supply rail 110. Here, the first power switch is constituted by a series connection of a first switch 115: 11 on the power supply rail 110 side and a second switch 116: 11 on the function block 130 side. The second power switch is constituted by a series connection of a third switch 115: 12 on the power supply rail 110 side and a fourth switch 116: 12 on the function block 130 side. The third power switch is constituted by a series connection of a fifth switch 115: 21 on the power supply rail 110 side and a sixth switch 116: 21 on the function block 130 side. The fourth power switch is constituted by a series connection of a seventh switch 115: 22 on the power supply rail 110 side and an eighth switch 116: 22 on the function block 130 side.

  The operation of the controller 150 in FIG. 3 will be described. 3 outputs a first normal operation control signal from the first output unit, and outputs a second normal operation control signal from the second output unit. Here, the first normal operation control signal is transmitted through the first and second multiplexers 220: 1x and 221: 1x during the non-test normal operation, and the first to fourth transistors 115: 11, 116: 11, 115: 12, 116: 12, that is, for controlling the conduction state of the first and second power switches. Similarly, the second normal operation control signal is supplied to the fifth to eighth transistors 115: 21, through the third and fourth multiplexers 220: 2x, 221: 2x during normal operation during non-test. 116: 21, 115: 22, 116: 22, that is, for controlling the conduction state of the third and fourth power switches.

  The operation of the test controller 250 in FIG. 3 will be described. The test controller 250 in FIG. 3 outputs a test enable signal from the first output unit, outputs a first test time signal from the second output unit, and outputs a second test time signal from the third output unit. And an initial voltage setting signal is output from the fourth output unit, a third test time signal is output from the fifth output unit, and a fourth test time signal is output from the sixth output unit. Here, the test enable signal is for controlling the first to fourth multiplexers 220: 1x, 221: 1x, 220: 2x, 221: 2x to be set to the test state or the normal operation state. The first test time signal is used to control the conduction state of the first and third transistors 115: 11 and 115: 12 via the first multiplexer 220: 1x during the test. The second test time signal is used to control the conduction state of the second and fourth transistors 116: 11 and 116: 12 via the second multiplexer 221: 1x during the test. The third test time signal is for controlling the conduction state of the fifth and seventh transistors 115: 21 and 115: 22 via the third multiplexer 220: 2x during the test. The fourth test time signal is used to control the conduction state of the sixth and eighth transistors 116: 21 and 116: 22 via the fourth multiplexer 221: 2x during the test. The initial voltage setting signal is used to control the conduction state of the first and second voltage setting transistors 290: x1, 290: x2.

  The operation of the first to fourth multiplexers 220: 1x, 221: 1x, 220: 2x, 221: 2x in FIG. 3 will be described. The switching signal input unit in the first multiplexer 220: 1x receives the test enable signal output from the first output unit in the test controller 250. The first signal input unit of the first multiplexer 220: 1x receives the first test time signal output from the second output unit of the test controller 250. The second signal input unit in the first multiplexer 220: 1x receives the first normal operation control signal output from the first output unit in the controller 150. In response to the test enable signal, the output section of the first multiplexer 220: 1x outputs a first test time signal from the test controller 250 during the test, and a first test signal from the controller 150 during the normal operation during the non-test. Outputs a control signal during normal operation.

  Similarly, the switching signal input unit in the second multiplexer 221: 1x receives the test enable signal output from the first output unit in the test controller 250. The first signal input unit in the second multiplexer 221: 1x inputs the second test time signal output from the third output unit in the test controller 250. The second signal input unit in the second multiplexer 221: 1x inputs the first normal operation control signal output from the first output unit in the controller 150. In response to the test enable signal, the output unit of the second multiplexer 221: 1x outputs a second test time signal from the test controller 250 during the test, and a first operation from the controller 150 during the non-test normal operation. Outputs a control signal during normal operation.

  In addition, the switching signal input unit in the third multiplexer 220: 2x inputs the test enable signal output from the first output unit in the test controller 250. The first signal input unit in the third multiplexer 220: 2 x receives the third test time signal output from the fifth output unit in the test controller 250. The second signal input unit in the third multiplexer 220: 2x receives the second normal operation time control signal output from the second output unit in the controller 150. In response to the test enable signal, the output unit of the third multiplexer 220: 2x outputs a third test time signal from the test controller 250 during the test, and a second test signal from the controller 150 during the normal operation during the non-test. Outputs a control signal during normal operation.

  Further, the switching signal input unit in the fourth multiplexer 221: 2x inputs the test enable signal output from the first output unit in the test controller 250. The first signal input unit in the fourth multiplexer 221: 2x inputs the fourth test time signal output from the sixth output unit in the test controller 250. The second signal input unit in the fourth multiplexer 221: 2x inputs the second normal operation time control signal output from the second output unit in the controller 150. In response to the test enable signal, the output unit of the fourth multiplexer 221: 2x outputs a fourth test signal from the test controller 250 during the test, and a second test signal from the controller 150 during the normal operation during the non-test. Outputs a control signal during normal operation.

  The operation of the first to fourth power switches in FIG. 3, that is, the first to eighth transistors 115: 11, 116: 11, 115: 12, 116: 12, 115: 21, 116: 21, 115: 22, The operation at 116: 22 will be described. The first and third transistors 115: 11 and 115: 12 conduct or block simultaneously between the drain and the source in response to a first test signal input to the gate during the test. The second and fourth transistors 116: 11 and 116: 12 conduct or block simultaneously between the drain and the source in accordance with a second test time signal input to the gate during the test. The fifth and seventh transistors 115: 21, 115: 22 conduct or block simultaneously between the drain and the source in accordance with a third test time signal input to the gate during the test. The sixth and eighth transistors 116: 21, 116: 22 simultaneously conduct or block between the drain and the source in accordance with a fourth test time signal input to the gate during the test.

  The operation of the first and second voltage setting transistors 290: x1, 290: x2 in FIG. 3 will be described. The first and second voltage setting transistors 290: x1, 290: x2 simultaneously conduct or block between the drain and the source according to the initial voltage setting signal from the test controller 250 input to the gate.

  Of the components in the semiconductor integrated circuit 200 of FIG. 3, the power supply rail 110, the first transistor 115: 11 operating as the first switch, the second transistor 116: 11, and the ground supply rail 120 are provided. A functional block 130; a controller 150; a first multiplexer 220: 1x; a second multiplexer 221: 1x; a first observation node 240: x1; a test controller 250; and a first initial voltage setting. When the first voltage setting transistor 290: x1 operating as the circuit 290: x1 is extracted, the semiconductor integrated circuit 200 according to the first embodiment of the present invention shown in FIG. 2 is obtained.

  Similarly, even if attention is paid to any one of the second to fourth power switches, and the components related to the power switches are appropriately selected, the first embodiment of the present invention shown in FIG. Thus, a semiconductor integrated circuit 200 can be obtained. As described above, the semiconductor integrated circuit 200 according to the present embodiment shown in FIG. 3 combines the four power switches according to the first embodiment of the present invention into a two-dimensional array of two rows and two columns as described above. Is equal to The number of rows and the number of columns in this two-dimensional array can naturally be set to arbitrary numbers, but hereinafter, the operation of the entire semiconductor integrated circuit 200 in the case of 2 rows and 2 columns as shown in FIG. A test method for a semiconductor integrated circuit according to a second embodiment of the present invention will be described.

  The operation modes of the semiconductor integrated circuit 200 according to the present embodiment include a first test mode, a second test mode, and a normal operation mode during non-test. In the first test mode, it is detected whether all the power switches mounted on the semiconductor integrated circuit are operating normally. Hereinafter, the first test is referred to as a total failure detection test. In the second test mode, when an abnormality is detected in any of the power switches during the entire test, it is specified which power switch has failed. Hereinafter, the second test is referred to as a failure location specifying test.

  First, at the time of the total failure detection test, Steps 1 to 5 in Table 2 are executed as in the test in the first embodiment of the present invention. However, the signal directed to the first switch in Table 2 is simultaneously output not only to the second output unit in the test controller 250 but also to the fifth output unit. That is, all the first, third, fifth, and seventh transistors 115: 11, 115: 12, 115: 21, and 115: 22 indicate that the first switch in Table 2 is turned on or off. Will be read as something that becomes ON or OFF. Similarly, not only the third output unit in the test controller 250 but also the sixth output unit simultaneously outputs a signal directed to the second switch in Table 2. That is, all the second, fourth, sixth, and eighth transistors 116: 11, 116: 12, 116: 21, and 116: 22 indicate that the second switch in Table 2 is turned on or off. Will be read as something that becomes ON or OFF. Further, the fact that the initial voltage setting circuit in Table 2 is in the ON state or OFF state is read as the case where both the first and second voltage setting transistors 290: x1, 290: x2 are in the ON state or OFF state. .

  If the logical values at the first and second observation nodes 240: x1, 240: x2 match the observation node logical values in Table 2 in all of Steps 1 to 5 under the above conditions, this implementation It is guaranteed that all the power switches in the semiconductor integrated circuit according to the form are operating normally. The reason is the same as in the case of the first embodiment of the present invention, and further detailed description is omitted.

  On the contrary, if the logical value at any of the first and second observation nodes 240: x1, 240: x2 is different from the observation node logical value in Table 2 in any of steps 1 to 5, the present embodiment It is detected that there is an abnormality in any of the power switches in the semiconductor integrated circuit.

  When it is detected that any power switch has an abnormality in the overall failure detection test, it is possible to identify which power switch has the abnormality by performing a failure location specifying test. Even in the failure location specifying test, Steps 1 to 5 in Table 2 are used, but Steps 2 to 5 are executed in two steps.

  First, step 1 is executed in the same manner as the total failure detection test.

  Next, step 2 is executed in two steps. First, in order to detect an abnormality in the first and third transistors, the first step 2 is performed. At this time, the test controller 250 changes the first test time signal output from the second output unit from the ON state to the OFF state, but keeps the third test time signal output from the fifth output unit. . In this way, the influence of the fifth and seventh transistors 115: 21 and 115: 22 is eliminated, and only the influence of the first and third transistors 115: 11 and 115: 12 is the first and second transistors. Appear at observation nodes 240: x1, 240: x2, respectively.

  Next, in order to detect an abnormality in the fifth and seventh transistors, the second step 2 is performed. At this time, the test controller 250 changes the third test time signal output from the fifth output unit from the ON state to the OFF state, but keeps the first test time signal output from the second output unit as it is. . This eliminates the influence of the first and third transistors 115: 11 and 115: 12, and only the influence of the fifth and seventh transistors 115: 21 and 115: 22 affects the first and second transistors. Appear at observation nodes 240: x1, 240: x2, respectively. It should be noted that in order to execute step 2 in two steps, the order of course may be either.

  Next, step 3 is executed in two steps. First, in order to detect an abnormality in the second and fourth transistors, the first step 3 is performed. At this time, the test controller 250 changes the second test time signal output from the third output unit from the OFF state to the ON state, but keeps the fourth test time signal output from the sixth output unit. . In this way, the influence of the sixth and eighth transistors 116: 21 and 116: 22 is eliminated, and only the influence of the second and fourth transistors 116: 11 and 116: 12 is the first and second transistors. Appear at observation nodes 240: x1, 240: x2, respectively.

  Next, in order to detect an abnormality in the sixth and eighth transistors, the second step 3 is performed. At this time, the test controller 250 changes the fourth test time signal output from the sixth output unit from the OFF state to the ON state, but keeps the second test time signal output from the third output unit as it is. . In this way, the influence of the second and fourth transistors 116: 11 and 116: 12 is eliminated, and only the influence of the sixth and eighth transistors 116: 21 and 116: 22 is the first and second transistors. Appear at observation nodes 240: x1, 240: x2, respectively. It should be noted that in order to execute step 3 in two steps, the order of course may be either.

  Next, step 4 is executed in two steps. First, in order to detect an abnormality in the second and fourth transistors, the first step 4 is performed. At this time, the test controller 250 changes the second test time signal output from the third output unit from the ON state to the OFF state, but keeps the fourth test time signal output from the sixth output unit. . In this way, the influence of the sixth and eighth transistors 116: 21 and 116: 22 is eliminated, and only the influence of the second and fourth transistors 116: 11 and 116: 12 is the first and second transistors. Appear at observation nodes 240: x1, 240: x2, respectively.

  Next, in order to detect an abnormality in the sixth and eighth transistors, the second step 4 is performed. At this time, the test controller 250 changes the fourth test time signal output from the sixth output unit from the ON state to the OFF state, but keeps the second test time signal output from the third output unit as it is. . In this way, the influence of the second and fourth transistors 116: 11 and 116: 12 is eliminated, and only the influence of the sixth and eighth transistors 116: 21 and 116: 22 is the first and second transistors. Appear at observation nodes 240: x1, 240: x2, respectively. It should be noted that in order to execute step 3 in two steps, the order of course may be either.

  Similarly, step 5 is executed in two steps. First, in order to detect an abnormality in the first and third transistors, the first step 5 is performed. At this time, the test controller 250 changes the first test time signal output from the second output unit from the OFF state to the ON state, but keeps the third test time signal output from the fifth output unit. . In this way, the influence of the fifth and seventh transistors 115: 21 and 115: 22 is eliminated, and only the influence of the first and third transistors 115: 11 and 115: 12 is the first and second transistors. Appear at observation nodes 240: x1, 240: x2, respectively.

  Next, in order to detect an abnormality in the fifth and seventh transistors, the second step 5 is performed. At this time, the test controller 250 changes the third test time signal output from the fifth output unit from the OFF state to the ON state, but keeps the first test time signal output from the second output unit as it is. . This eliminates the influence of the first and third transistors 115: 11 and 115: 12, and only the influence of the fifth and seventh transistors 115: 21 and 115: 22 affects the first and second transistors. Appear at observation nodes 240: x1, 240: x2, respectively. It should be noted that in order to execute step 5 in two steps, the order of course may be either.

  As described above, by executing the fault location specifying test, the first to eighth transistors 115: 11, 116: 11, 115: 12, 116: 12, 115: 21, 116: 21, 115: 22 are used. , 116: 22, an abnormality that does not change from the OFF state to the ON state and an abnormality that does not change from the OFF state to the ON state can be detected independently.

  Note that the test controller 250 according to the present embodiment has a configuration capable of generating and outputting various signals as described above. More specifically, a configuration in which a predetermined program is executed by a general-purpose computer including a general input unit, a calculation unit, a storage unit, and an output unit may be used, or a configuration using a dedicated logic circuit may be used. In this case, the storage unit stores the table of Table 2 in advance, and the arithmetic unit controls various signals output from the output unit while referring to the storage unit according to the test start instruction input from the input unit, etc. Is desirable.

  Also in the present embodiment, as in the case of the first embodiment of the present invention, an effect that the test time of the power switch can be shortened can be obtained. Although the test time increases as the number of power switches arranged in the vertical direction in FIG. 3 increases, the test time decreases as the number of power switches arranged in the horizontal direction in FIG. 3 increases. Even if the total number increases, it is possible to avoid a significant increase in test time.

  In the above description, the case where each switch is configured by a P-type MOS transistor has been described. However, some or all of the switches may be configured by N-type MOS transistors by appropriately inverting the logical value of each signal. Of course it is possible. Further, the power supply rail 110 and the ground supply rail 120 may be generalized and simply handled as the first and second power supplies 110 and 120. That is, it is not always necessary to supply the power supply voltage and the ground reference voltage as long as the difference between the voltages supplied by the first and second power supplies 110 and 120 can supply the voltage necessary for the operation of the functional block 130. . For example, even if the voltages of the power supply rail 110 and the ground supply rail 120 are reversed, the present invention is naturally effective even when both voltages are not ground reference voltages. Further, the total number and arrangement method of the power switches described above can be freely combined. In particular, the power switch shown in FIG. 3 can be arranged in the direction sharing the observation node or the arrangement sharing the multiplexer. The total number can be increased or decreased independently. In the semiconductor integrated circuit according to the present invention, these changes can be freely combined.

110 power supply rail, first power supply 115 (first) (P-type MOS) transistor, (first) switch 115: 11 (first) transistor, (first) switch 115: 12 (third Transistor), (third) switch 115: 21 (fifth) transistor, (fifth) switch 115: 22 (seventh) transistor, (seventh) switch 116 (second) (P Type MOS) transistor, (second) switch 116: 11 (second) transistor, (second) switch 116: 12 (fourth) transistor, (fourth) switch 116: 21 (sixth ) Transistor, (sixth) switch 116: 22 (eighth) transistor, (eighth) switch 120 ground supply rail, second power supply 130 functional block 14 Controller 150 controller 200 IC, semiconductor integrated circuit 210 test controller 220 (first) multiplexer 220: 1x (first) multiplexer 220: 2x (third) multiplexer 221 (second) multiplexer 221: 1x (second) ) Multiplexer 221: 2x (fourth) multiplexer 230 comparator 240 output unit, observation node 240: x1 (first) observation node 240: x2 (second) observation node 250 test controller 290 initial voltage setting circuit, Voltage setting transistor 290: x1 First initial voltage setting circuit, first voltage setting transistor 290: x2 Second initial voltage setting circuit, second voltage setting transistor

Claims (10)

First and second power supplies for supplying power to an arbitrary functional block;
A first power switch having two switches connected in series operating in response to the first and second test signals, respectively, and conducting or blocking between the first power supply and the functional block;
A first observation node connected to a midpoint of the two switches and observing a state of the first power switch;
A first initial voltage setting circuit which conducts or cuts off between the first observation node and the second power source in response to an initial voltage setting signal;
A test controller for generating the first and second test time signals and the initial voltage setting signal;
When the test controller transitions from the ON state to the OFF state for each of the two switches by switching the states of the first and second test time signals and the initial voltage setting signal in a predetermined order. And an abnormality at the time of transition from the OFF state to the ON state are detected as a logical value abnormality in the first observation node. The semiconductor integrated circuit according to claim 1,
One of the two switches is
A drain and a source are connected between the first power source and the first observation node, and the drain and the source are electrically connected or cut off according to the first test signal input to the gate. 1 transistor,
The other of the two switches is
A drain and a source are connected between the first observation node and the functional block, and the drain and the source are turned on or off in accordance with the second test time signal input to the gate. Comprising a transistor;
The first initial voltage setting circuit includes:
A drain and a source are connected between the first observation node and the second power source, and the drain and the source are turned on or off according to the initial voltage setting signal input to the gate. A semiconductor integrated circuit comprising a voltage setting transistor. The semiconductor integrated circuit according to claim 2,
A controller for generating a first normal operation time control signal for controlling the first power switch during normal operation during non-test;
A first multiplexer connected to the previous stage of the gate of the first transistor and outputting the first test signal during the test and outputting the first normal operation control signal during the normal operation; ,
A second multiplexer connected to the previous stage of the gate of the second transistor and outputting the second test signal during the test and outputting the first normal operation control signal during the normal operation; A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 2,
The first power switch includes two switches connected in series and operating in response to the first and second test signals, respectively, and the first power switch and the first power switch. A second power switch for conducting or blocking between the functional blocks;
A second observation node connected to a midpoint of the two switches and observing the state of the second power switch;
A second initial voltage setting circuit for conducting or blocking between the second observation node and the second power supply in response to the initial voltage setting signal;
When the test controller transitions from the ON state to the OFF state for each of the two switches by switching the states of the first and second test time signals and the initial voltage setting signal in a predetermined order. And an abnormality at the time of transition from the OFF state to the ON state are detected as a logical value abnormality in the second observation node. The semiconductor integrated circuit according to claim 4,
One of the two switches is
A drain and a source are connected between the first power source and the second observation node, and the drain and the source are electrically connected or cut off according to the first test signal input to the gate. 3 transistors,
The other of the two switches is
A drain and a source are connected between the second observation node and the functional block, and the drain and the source are turned on or off according to the second test time signal input to the gate. Comprising a transistor;
The second initial voltage setting circuit includes:
A drain and a source are connected between the second observation node and the second power source, and the drain and the source are turned on or off according to the initial voltage setting signal input to the gate. A semiconductor integrated circuit comprising a voltage setting transistor. The semiconductor integrated circuit according to claim 5,
A controller for generating a first normal operation time control signal for controlling the first and second power switches during a normal operation during a non-test;
The first and third transistors are connected to the previous stage of the gate, and output the first test signal during the test, and output the first normal operation control signal during the normal operation. One multiplexer,
The second and fourth transistors are connected to the previous stage of the gate, and output the second test signal during the test, and output the first normal operation control signal during the normal operation. A semiconductor integrated circuit further comprising two multiplexers. The semiconductor integrated circuit according to claim 2 or 5,
The first power switch is connected in parallel, and has two switches connected in series that operate in response to third and fourth test time signals generated by the test controller, respectively. A third power switch that conducts or cuts off between the power source of 1 and the functional block;
The first observation node is connected to a midpoint of the two switches;
When the test controller makes a transition from the ON state to the OFF state for each of the two switches by switching the states of the third and fourth test time signals and the initial voltage setting signal in a predetermined order. And an abnormality at the time of transition from the OFF state to the ON state are detected as a logical value abnormality in the first observation node. The semiconductor integrated circuit according to claim 7,
One of the two switches is
A drain and a source are connected between the first power source and the first observation node, and the drain and the source are electrically connected or cut off according to the third test signal input to the gate. 5 transistors,
The other of the two switches is
A drain and a source are connected between the first observation node and the functional block, and the drain and the source are turned on or off according to the fourth test time signal input to the gate. Comprising a transistor;
A controller for generating a first normal operation control signal for controlling the first power switch and a second normal operation control signal for controlling the third power switch during a normal operation during a non-test;
A first multiplexer connected to the previous stage of the gate of the first transistor and outputting the first test signal during the test and outputting the first normal operation control signal during the normal operation; ,
A second multiplexer connected to the previous stage of the gate of the second transistor and outputting the second test signal during the test and outputting the first normal operation control signal during the normal operation; ,
A third multiplexer connected to a preceding stage of the gate of the fifth transistor and outputting the third test signal during the test and outputting the second normal operation control signal during the normal operation; ,
A fourth multiplexer connected to the preceding stage of the gate of the sixth transistor and outputting the fourth test signal during the test and outputting the second normal operation control signal during the normal operation; A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 2,
A second power switch connected in parallel with the first power switch and conducting or blocking between the first power source and the functional block according to the first and second test signals; ,
The first power supply switch and the second power supply switch are connected in parallel, and the first power supply and the functional block are electrically connected in response to third and fourth test time signals further generated by the test controller. Or a third power switch to shut off;
The first, second, and third power switches are connected in parallel, and the first power source and the functional block are electrically connected in accordance with the third and fourth test time signals. A fourth power switch to shut off;
A second observation node for observing states of the second and fourth power switches;
A second initial voltage setting circuit for conducting or blocking between the second observation node and the second power supply in response to the initial voltage setting signal;
The first observation node further observes a state of the third power switch;
The second power switch is
A drain and a source are connected between the first power source and the second observation node, and the drain and the source are electrically connected or cut off according to the first test signal input to the gate. 3 transistors,
A drain and a source are connected between the second observation node and the functional block, and the drain and the source are turned on or off according to the second test time signal input to the gate. A transistor,
The third power switch is
A drain and a source are connected between the first power source and the first observation node, and the drain and the source are electrically connected or cut off according to the third test signal input to the gate. 5 transistors,
A drain and a source are connected between the first observation node and the functional block, and the drain and the source are turned on or off according to the fourth test time signal input to the gate. A transistor,
The fourth power switch is
A drain and a source are connected between the first power source and the second observation node, and the drain and the source are electrically connected or cut off according to the third test signal input to the gate. 7 transistors,
A drain and a source are connected between the second observation node and the functional block, and the drain and the source are turned on or off according to the fourth test time signal input to the gate. A transistor,
The second initial voltage setting circuit includes:
A drain and a source are connected between the second observation node and the second power source, and the drain and the source are turned on or off according to the initial voltage setting signal input to the gate. A voltage setting transistor;
A first normal operation control signal for controlling the first and second power switches and a second normal operation control for controlling the third and fourth power switches during normal operation during non-test. A controller for generating a signal;
The first and third transistors are connected to the previous stage of the gate, and output the first test signal during the test, and output the first normal operation control signal during the normal operation. A multiplexer of
The second and fourth transistors are connected to the previous stage of the gate and output the second test signal during the test and the first normal operation control signal during the normal operation. A multiplexer of
The third and seventh transistors are connected in front of the gates of the fifth and seventh transistors, and output the third test signal during the test, and output the second normal operation control signal during the normal operation. A multiplexer of
The fourth and eighth transistors are connected in front of the gates of the sixth and eighth transistors, and output the fourth test signal during the test, and output the second normal operation control signal during the normal operation. And a multiplexer.
The test controller switches the states of the first to fourth test time signals and the initial voltage setting signal in a predetermined order so that each of the first to eighth transistors is switched from an ON state to an OFF state. An abnormality at the time of transition to a state and an abnormality at the time of transition from the OFF state to the ON state are detected as a logical value abnormality in the first and second observation nodes. The first and second power supplies supplying power to any functional block;
Generating first and second test time signals and an initial voltage setting signal in a test controller;
Conducting or blocking between the first power source and the functional block in response to the first and second test time signals by a first power switch;
In a first initial voltage setting circuit, conducting or blocking between the first observation node and the second power supply in accordance with the initial voltage setting signal;
Observing the state of the first power switch at the first observation node,
Conducting or interrupting between the first power source and the functional block comprises:
Conducting or blocking between the first power source and the first observation node with a first switch operating in response to the first test time signal;
A second switch that operates in response to the second test time signal, comprising conducting or blocking between the first observation node and the functional block;
The generating step includes
Switching the state of the first and second test time signals and the initial voltage setting signal in a predetermined order;
The observing step comprises:
For each of the first and second switches, an abnormality at the time of transition from the ON state to the OFF state and an abnormality at the time of transition from the OFF state to the ON state are represented by logical values at the first observation node. A method for testing a semiconductor integrated circuit, comprising a step of detecting an abnormality.

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