JP2009188371A - Semiconductor device and evaluation method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device having a circuit constitution which allows a faulty part to be more easily detected when electrically measuring a plurality of elements in a large-scale contact chain or a large-scale wiring pattern, and to provided an evaluation method thereof. <P>SOLUTION: The semiconductor device includes: a measurement target element circuit comprising a plurality of measurement target unit elements 101 connected in series; a plurality of selecting elements 104 connected to nodes between adjacent measurement target unit elements respectively; and a node information transmission circuit 107 connected to the plurality of selecting elements 104. Potentials generated in respective nodes by applying a voltage to one of a first test pad 102 and a second test pad 103 in both ends of the measurement target circuit are input to the node information transmission circuit 107, and the input potentials of respective nodes are output in the connection order. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device for performing electrical measurement of an element and an evaluation method thereof.

  In the semiconductor integrated circuit manufacturing process, there is a test element that simply measures the characteristics of each element constituting the semiconductor integrated circuit on the semiconductor substrate in order to manage the state of the manufacturing line and analyze the cause of the characteristic failure. Is provided. These test elements are measured during the wafer manufacturing process or at the end of the manufacturing process to test whether each element fulfills a predetermined function and whether the manufacturing process has been performed normally. By performing this test, the state of the production line can be confirmed. In addition, these test elements are used for further detailed evaluation of the test element when an abnormality is recognized in the characteristics of each element and for identifying the cause of the abnormality.

  In general, the test element is often formed in a cutting region for cutting a semiconductor integrated circuit chip called a scribe line from a wafer and dividing it into one chip. The scribe line needs to have a sufficient width that allows the chips to be easily divided. At the same time, it is desirable to obtain as many semiconductor integrated circuit chips as possible from a single wafer. It needs to be small. For this reason, the region used for the test element must be a region with a limited area. Further, a test pad used for measurement is also formed on the scribe line. In order to form test elements and test pads in a limited area, the number of test pads is limited, and it is difficult to provide a large number of test pads on a scribe line. Therefore, it is important to provide the elements to be measured so as to efficiently use a limited number of test pads.

  With the recent miniaturization, higher performance, and higher integration of semiconductor processes, the scale of semiconductor elements formed on a wafer is constantly expanding. As the scale of semiconductor elements increases, test elements for detecting process failures or test elements for monitoring the state of a production line must be expanded. However, when the number of test elements increases as the scale of semiconductor elements increases, it is extremely difficult to detect a defective part from a vast number of test elements when a problem occurs, and the cause is investigated. It is difficult.

  For example, FIG. 14 shows a contact chain as an example of a conventional test pattern for evaluating and inspecting the resistance of the contact hole 13 (or via) connecting the upper wiring layer 11 and the lower wiring layer 12. FIG. 14A shows a planar configuration, and FIG. 14B shows a cross-sectional configuration. In the conventional test pattern, an abnormally high resistance or an open defect is detected by connecting a large number of contact holes in a chain shape and measuring the resistance value, thereby determining the quality of the wafer. When the contact scale of the contact chain is small, it is possible to physically observe the wafer using an observation tool such as an electron microscope to identify the defective part, but the scale is several hundred thousand to several million. When it becomes large-scale, it is impossible to specify the location by physical analysis.

  FIG. 15A and FIG. 15B schematically show test patterns. In FIG. 15A, one resistance symbol represents one contact or a plurality of contact chains. As shown in FIG. 15 (a), it is possible to find a disconnection defect by connecting the contacts in a plurality of chains and measuring the resistance value, but it is difficult to specify the occurrence location.

  FIG. 15B schematically shows a circuit in which nodes between contacts or between contact chains are drawn to a test pad. Since the contacts or contact chains divided by the nodes shown in FIG. 15B can be sequentially measured, it is possible to more easily detect a defective portion. However, as described above, since the area of the scribe line is limited and the number of test pads formed on the scribe line is also limited, a circuit as shown in FIG. 15B is formed on the scribe line. Therefore, it is practically difficult to detect the defective part of the wafer.

  It is also possible to specify a defective part by providing a plurality of small test circuits capable of detecting the defective part and measuring them sequentially. However, as in FIG. 15B, it is practically difficult to provide a plurality of test circuits and test pads due to the limitation of the area of the scribe line region.

  Note that the contact chain shown in FIG. 14 has been described as an example of a target for detecting a defective portion, but the same problem occurs in the test pattern including the snake-like wiring layer shown in FIG. The same problem occurs in the stacked contact chain as shown in FIG. FIG. 17A is a plan view of the stacked contact chain, and FIG. 17B is a cross-sectional view of the stacked contact chain. The stacked contact chain has a structure in which a plurality of contact holes and a wiring layer are laminated as shown in FIGS.

  The prior art shown in FIGS. 14 to 17 shows a test element for detecting a contact or via open failure or a wiring disconnection failure. FIG. 18 shows a case where a short circuit failure is detected. The test element shown is used. The test element shown in FIG. 18 is a test element generally called a snake & comb, and a predetermined voltage between the “O1” terminal and the “O2” terminal, which are the respective terminals of the first wiring pattern 1. Is applied to measure the value of the current flowing between the two terminals to detect the presence of an open defect, and a predetermined interval between the “O1” terminal or “O2” terminal and the “S1” terminal of the second wiring pattern 2 is detected. The presence or absence of a short circuit failure is detected based on whether or not a short circuit current flows by applying a voltage. In general, the first wiring pattern 1 is called a snake, and the second wiring pattern 2 is called a comb.

  Also in the test element for detecting a short-circuit failure shown in FIG. 18, it is difficult to specify the physical location of the failure as the scale thereof increases.

  In addition, a method has been proposed in which as many test circuits as possible with limited measurement pads are provided in a limited area, a wafer is measured, and a defective portion is detected from the measured wafer. Here, an example will be described (for example, refer to Patent Document 1).

  FIG. 19 shows the configuration of a conventional test circuit.

  As shown in FIG. 19, in the conventional test circuit, a plurality of measured elements 201 are provided in a matrix on a semiconductor substrate, and a selection switch 202 is connected to both ends of each measured element 201. . Each measured element 201 is connected to a column selection circuit 203 and a row selection circuit 204, and an address generation circuit 205 is connected to the column selection circuit 203 and the row selection circuit 204. The address generation circuit 205 generates a column address and a row address for selecting one selected element 201 from among a plurality of selected elements 201 provided in a matrix by an external control signal. By outputting to the row selection circuit 204, a specific selected element 201 is selected by the column selection circuit 203 and the row selection circuit 204. Each device under test 201 is connected to a common bus line 207 via a switch circuit 206 and is connected to a measuring device 208 outside the semiconductor device. The address generation circuit 205 is specifically composed of a shift register circuit, and has a function of counting up address signals one address at a time using an external clock signal.

In the conventional test circuit shown in FIG. 19, a specific device under measurement selected by an address control signal input from the outside is sequentially connected to an external measurement terminal, and the electrical characteristics of the device under test are measured by an external measuring instrument. Can be measured. As described above, in the configuration of the conventional test circuit, a generation circuit for generating an address for selecting one element to be measured from an address control signal input from the outside and an element selection circuit for receiving a signal output from the generation circuit are provided. Thus, even when a large number of elements are formed, it is possible to perform measurement of the elements sequentially with a small number of control terminals and signals to identify a defective portion.
JP 2003-7785 A

  However, many of the measurements for evaluating whether or not the above-described semiconductor manufacturing process has been performed normally are electrical measurements in which a predetermined set voltage is applied to a device under test and the current flowing through the device is measured. is there. Usually, in a measuring instrument used for evaluating such a semiconductor integrated circuit, a standby time is required until the voltage becomes stable after the voltage is set in order to perform highly accurate measurement. Usually, the standby time for voltage measurement of a semiconductor element is set to a time of several tens of milliseconds to several hundreds of milliseconds per measurement.

  Therefore, in the conventional test circuit described in Patent Document 1 described above, the address of the device under test is measured by advancing one address with the external control signal, and several tens of ms to several seconds are required until the next device under test is measured. Since a time of 100 ms is required, for example, when 1000 elements are provided, it takes tens to hundreds of seconds to measure all elements under one condition. That is, it takes a lot of inspection time to measure the entire surface of the wafer while changing the measurement conditions and the like for each element. It is impractical in terms of cost to spend such a large amount of time for inspection. Moreover, the ratio of the cost required for the inspection to the total manufacturing cost in the current semiconductor manufacturing is very large.

  In view of the above, in order to solve the above-described conventional problems, the present invention makes it easier to detect a defective portion when performing electrical measurement of a plurality of elements in a large-scale contact chain or a large-scale wiring pattern. It is an object of the present invention to obtain a semiconductor device having a circuit configuration to be performed and an evaluation method thereof.

  In order to achieve the above object, according to the present invention, a semiconductor device is configured to identify a defective portion of a unit element to be measured from a potential of a node between the measurement unit elements.

  Specifically, the first semiconductor device according to the present invention is connected to a measured element circuit including a plurality of measured unit elements connected in series and each node between adjacent measured unit elements. A plurality of selection elements and a node information transmission circuit connected to the plurality of selection elements, and the potential generated at each node when a voltage is applied across the measured element circuit is input to the node information transmission circuit. The node information transmission circuit sequentially outputs the input potential of each node to the outside.

  According to the first semiconductor device, since the potential of each node input to the node information transmission circuit is sequentially output, it is possible to easily detect a defective portion by counting the number of nodes until the potential changes. Can do.

  The first semiconductor device further includes potential fixing means for fixing a potential of any one of the plurality of nodes, and is generated at each node between the node where the potential is fixed and both ends of the element circuit to be measured. The potential is preferably input to the node information transmission circuit.

  In this way, a potential can be applied from any node in the device under test circuit toward both ends of the device under test circuit, so detection is not possible even if a potential is applied from both ends of the device under test circuit. It is possible to detect a plurality of defective portions that were possible.

  A second semiconductor device according to the present invention includes a circuit to be measured, each of which includes a plurality of unit elements to be measured connected in series and having a plurality of element circuits to be measured connected in parallel to each other; A plurality of selection circuits connected to each node between adjacent unit elements to be measured in the circuit and connected in parallel to each other; and a node information transmission circuit connected to the plurality of selection circuits. Node information is transmitted by a signal that controls a plurality of selection circuits corresponding to one measured device circuit when a voltage is applied across the measured device circuit of one of the measured device circuits. The node information transmission circuit that is input to the circuit sequentially outputs the input potential of each node to the outside.

  According to the second semiconductor device, even when a plurality of device circuits to be measured connected in series are connected in parallel, the potential of the node between the device devices to be measured is input to the node information transmission circuit. Since the signals are sequentially output, it is possible to easily detect a plurality of trouble spots in the plurality of element circuits to be measured.

  A first semiconductor device evaluation method according to the present invention includes a step (a) of applying a voltage to both ends of an element circuit to be measured, and a potential generated at each node by the step (a), and controlling a plurality of selection elements. A step (b) of inputting the signal to the node information transmission circuit by a signal, a step (c) of sequentially outputting the potential of each node input to the node information transmission circuit in the step (b), and a step (c) And a step (d) of identifying a first defect location in the unit element to be measured by detecting a change point of the potential of each outputted node.

  According to the first method for evaluating a semiconductor device, it is possible to easily detect a defective portion in a measured element circuit in which a plurality of measured unit elements are connected in series.

  The first semiconductor device evaluation method includes a step (e) of applying a voltage in the opposite direction to the step (a) to both ends of the element circuit to be measured after the step (d), and a step (e). The step (f) of inputting the potential generated at each node to the node information transmission circuit by a signal for controlling a plurality of selection elements, and the potential of each node input to the node information transmission circuit by the step (f) A step (g) of sequentially outputting to a step, and a step (h) of identifying a second failure location in the terminal element to be measured by detecting a change point of the potential of each node output in the step (g). It is preferable to provide.

  In this way, even when there are a plurality of failure locations in the measured element circuit composed of a plurality of unit elements to be measured, the second failure location can be easily detected.

  The first semiconductor device evaluation method includes a step (i) of applying a potential to any one of a plurality of nodes after the step (h), and a potential generated at each node by the step (i). Are input to the node information transmission circuit by a signal for controlling a plurality of selection elements, and the steps of sequentially outputting the potential of each node input to the node information transmission circuit in step (j) (k) And a step (l) of identifying a third defect location in the terminal element to be measured by detecting a change point of the potential of each node output in step (k).

  In this way, even if there are a plurality of defect locations in the measured element circuit composed of a plurality of unit elements to be measured, the plurality of defect locations can be easily detected.

  The second semiconductor device evaluation method according to the present invention includes a step (a) of applying a voltage to both ends of the first device-under-measurement circuit among the plurality of device-under-measurement circuits, and a step (a). (B) inputting a potential generated at each node of the device under test circuit to the node information transmission circuit by a signal for controlling a plurality of selection circuits corresponding to the first device under test circuit; Step (c) for sequentially outputting the potential of each node of the first device under test circuit inputted to the node information transmission circuit by the step (c), and detecting the change point of the potential of each node outputted by the step (c) A step (d) of identifying a defective portion of the unit elements to be measured constituting the first device-under-measurement circuit, and other than the first device-under-test circuit among the plurality of device-under-measurement circuits For a plurality of device circuits to be measured, the process (a ~ Sequentially executed repeatedly (d), and identifies the measured unit elements failure in all occurs a plurality of device under test circuitry.

  According to the second method for evaluating a semiconductor device, even if a plurality of device elements to be measured in which a plurality of device elements to be measured are connected in series are connected in parallel, a problem location is detected from among the plurality of device elements to be measured. Can be easily detected.

  A third semiconductor device according to the present invention is formed so as to meander in one plane, and has a snake-shaped first wiring pattern having a plurality of concavo-convex portions and the concavo-convex portions of the first wiring pattern. A plurality of comb-shaped second wiring patterns disposed opposite to each other, a plurality of selection elements respectively connected to each node between the adjacent second wiring patterns, When a voltage is applied between a node information transmission circuit connected to a plurality of selection elements and a predetermined second wiring pattern selected from the first wiring pattern and the plurality of second wiring patterns, the first wiring pattern And a terminal for measuring an electric current value flowing between the second wiring pattern and the predetermined second wiring pattern by an external measuring device, and the node information transmission circuit sequentially deselects the selection elements, thereby And wherein the disconnecting next.

  According to the third semiconductor device, since the node information transmission circuit sequentially disconnects the second wiring pattern by sequentially deselecting the selection elements, when the short-circuit current stops flowing due to the disconnected second wiring pattern, It can be seen that the short-circuit portion is included in the second wiring pattern separated.

  A fourth semiconductor device according to the present invention is formed so as to meander in one plane, and has a snake-shaped first wiring pattern having a plurality of uneven portions, and along each uneven portion of the first wiring pattern. A device under test circuit configured by a plurality of comb-shaped second wiring patterns disposed opposite to each other, a node information transmission circuit connected to the plurality of second wiring patterns, a first wiring pattern, and a plurality of wirings When a voltage is applied between a predetermined second wiring pattern selected from the second wiring patterns, a current value flowing between the first wiring pattern and the predetermined second wiring pattern is measured by an external measuring instrument. And the node information transmission circuit is characterized in that the potential of the connected second wiring pattern is the same as the potential of the first wiring pattern.

  According to the fourth semiconductor device, the node information transmission circuit sets the potential of the connected second wiring pattern to the same potential as that of the first wiring pattern. Since it does not flow, it can be seen that there was a defect in the predetermined second wiring pattern.

  A third semiconductor device evaluation method according to the present invention includes a step (a) of applying a voltage between a first wiring pattern and a predetermined second wiring pattern selected from a plurality of second wiring patterns, and a node A step (b) of sequentially deselecting the plurality of selection elements by the information transmission circuit and sequentially separating the second wiring pattern, and a flow between the first wiring pattern and the plurality of second wiring patterns not separated by the step (b). A step (c) of sequentially monitoring the current, and a step (d) of identifying a defective portion in the plurality of second wiring patterns by detecting a change point of the current value of each node output in the step (c). It is characterized by having.

  According to the third method for evaluating a semiconductor device, a defective portion, particularly a short-circuit failure can be easily detected from a plurality of second wiring patterns even in a snake and comb-shaped element circuit to be measured.

  A fourth semiconductor device evaluation method according to the present invention includes a step (a) of applying a voltage between a first wiring pattern and a predetermined second wiring pattern selected from a plurality of second wiring patterns, and a node The step (b) of setting the potential of the second wiring pattern to the same potential as the potential of the first wiring pattern by the information transmission circuit, and the first wiring pattern and the plurality of second wiring patterns that sequentially change in the step (b) A step (c) for sequentially monitoring the current flowing between them, and a step (d) for identifying a defective portion in the plurality of second wiring patterns by detecting a change point of the current value of each node in the step (c). It is characterized by having.

  According to the fourth method for evaluating a semiconductor device, even a snake-and-comb-shaped element circuit to be measured can easily detect a defective portion, particularly a short-circuit failure, from among a plurality of second wiring patterns.

  According to the semiconductor device and the evaluation method thereof according to the present invention, it is possible to easily measure the presence / absence of a defective portion in a short time with respect to a large-scale contact chain or a large-scale wiring pattern in which it is difficult to detect the defective portion. Therefore, it is possible to cope with a decrease in yield due to defects in the semiconductor manufacturing process at an early stage.

(First embodiment)
A semiconductor device and an evaluation method thereof according to a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a circuit configuration of the semiconductor device according to the first embodiment.

  As shown in FIG. 1, the semiconductor device according to the first embodiment includes two or more measured unit elements 101 (indicated by reference numerals 101a, 101b, and 101c in FIG. 1 and M + 1 (M is a positive integer)). Are connected in series, the first test pad 102 and the second test pad 103 connected to both ends of the measured element circuit, and the unit elements to be measured The transfer switch 104, which is a selection element connected to each node, the first signal input pad 105 that opens and closes each transfer switch 104, and the node potential information between the measured elements transferred by the transfer switch 104 are sequentially propagated. A node information transmission circuit 107 having a function of functioning, a third test pad 108 for reading the node information, and one or more second signal input pads for controlling the node information transmission circuit 107. And a de-109. Here, as shown in FIG. 1, a node information transmission circuit unit (unit) 106 is configured by each measured unit element 101 and the transfer switch 104 connected to each measured unit element 101.

  The unit element to be measured 101 is, for example, a contact chain shown in FIG. 14, a wiring break check pattern shown in FIG. 16, or a stacked contact chain that connects the multilayer wiring layers shown in FIG. 17, and its scale is arbitrary. .

  Next, a method for evaluating the semiconductor device of this embodiment will be described below.

  First, the first measurement mode is performed. In the first measurement mode, the presence / absence of a defective portion of the element circuit to be measured is measured.

  The transfer switch 104 is set in a non-selected state (here, in a high (H) state) by the first signal input pad 105, the first test pad 102 which is one end of the element circuit to be measured is in the H state, and the terminal to be measured The second test pad 103 which is the other end of the circuit is set to a low (L) state, and a current flowing from the first test pad 102 to the second test pad 103 is measured. If this current value is an appropriate value in view of the resistance value of the device-under-test circuit, it can be seen that there is no disconnection in the device-under-test circuit. On the other hand, when there is a disconnection, it can be seen that a problem occurs because almost no current flows.

  Next, when there is a disconnection in the device under test, the second measurement mode is performed. The defective part is specified by the second measurement mode.

  In the second measurement mode, first, similarly to the first measurement mode, the first test pad 102 is set to the H state, the second test pad 103 is set to the L state, and the first test pad 102 to the second test pad are set. A current is passed through 103. Here, for example, when a disconnection failure occurs in the unit element 101c constituting the device circuit to be measured, the potential information of the node between the first test pad 102 and the defective part becomes the H potential, and the first part from the defective part is The potential information of the node between the two test pads 103 is L potential. That is, the potential information of the node N01 and the node N02 is the H potential, and the potential information from the node N03 to the node NM is the L potential.

  Next, when the transfer switch 104 is turned on by switching the first signal input pad 105 from the H state to the L state in this state, the potential information of the node between the node N01 and the node NM becomes the node information transmission circuit 107. It is transmitted to. By inputting an appropriate control signal to the second signal input pad 109 from the outside, the node potential information received by the node information transmission circuit 107 is transferred to the third test pad 108. Node potential information is sequentially transferred from the node NM to the node N01 and output to the third test pad 108 in that order. Since the potential information of the L potential is output from the node NM to the disconnection location, and the potential information of the H potential is output from the disconnection location to the node N01, the node of the L potential until it changes from the L potential to the H potential. By counting the number, the number of unit elements to be measured including the broken portion can be measured. As a result, it is possible to easily detect a defective portion in the element circuit to be measured.

  As described above, according to the semiconductor device evaluation method of the first embodiment, it is possible to easily detect a defective portion due to a disconnection occurring in a large-scale contact chain or the like in a short time. Can also be specified.

  Next, a specific example of the node information transmission circuit 107 will be described with reference to FIGS.

  As an example of the semiconductor device according to the first embodiment, FIG. 2 shows a flip-flop circuit (F / F) 110 connected to each unit 106 in place of the node information transmission circuit 107 which is a circuit that sequentially propagates node information. Is shown. The transfer switch 104 is connected so that the output signal of the preceding flip-flop circuit 110 becomes the input signal of the succeeding flip-flop circuit 110 when the first signal input pad 105 is in the H state. Further, the transfer switch 104 is connected so that each node such as the unit element 101a to be measured becomes an input signal of the flip-flop circuit 110 of the unit 106 at the subsequent stage when the first signal input pad 105 is in the L state.

  FIG. 3 shows an example of the configuration of the flip-flop circuit 110. Although connection is not shown in FIG. 2, the node in each flip-flop circuit 110 is reset in advance by a reset signal (RST) 111 before measurement.

  As described above, when the transfer switch 104 is turned on by switching the first signal input pad 105 from the H state to the L state in the second measurement mode, the semiconductor device evaluation method shown in FIG. The potential information of each node between N01 and node NM becomes the input signal of the corresponding flip-flop circuit 110. In this state, by applying a pulse signal to the clock signal (CLK) 112, node potential information is transmitted to each flip-flop circuit 110.

  Next, the flip-flop circuit 110 is connected in series by switching the first signal input pad 105 from the L state to the H state, and the potential information of each node received by the flip-flop circuit 110 by the clock signal 112. Are successively transmitted from NM to N01 to the third test pad 108 which is the OUT terminal. Here, by counting the number of pulses of the clock signal 112 input until the potential changes from the L potential to the H potential, the number of unit elements to be measured including the broken portion can be measured. As a result, it is possible to easily detect a defective portion in the element circuit to be measured.

  As described above, an example in which a flip-flop circuit is used as a circuit that sequentially propagates node information has been described. However, a circuit having the same effect can be configured by using a commonly used shift register circuit.

  In the first embodiment, it is assumed that a contact chain or the like is provided on a scribe line in which the number of test pads is limited. It can be easily detected.

  According to the semiconductor device and the evaluation method thereof according to the first embodiment, even in a large-scale contact chain or the like in which it is difficult to detect the failure location with the conventional semiconductor device and the evaluation method thereof, the failure location is achieved in a short time. Can be specified.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described.

  According to the semiconductor device and the evaluation method thereof according to the first embodiment of the present invention, it is possible to easily detect a defective portion due to a disconnection occurring in a large-scale contact chain or the like. However, when a plurality of failure locations occur, only the failure location close to the first test pad 102 to which the H potential is applied is detected, and the second failure location cannot be detected. The semiconductor device and the evaluation method thereof according to the second embodiment of the present invention are evaluation methods in the case where two defective portions due to disconnection occur in a large-scale contact chain or the like.

  FIG. 4 shows a circuit configuration of the semiconductor device according to the second embodiment. About the same component as 1st Embodiment, description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  As shown in FIG. 4, the circuit configuration of the semiconductor device according to the second embodiment is the same as that of the first embodiment. Here, in 2nd Embodiment, the malfunction location by disconnection has generate | occur | produced in the to-be-measured unit element 101b and the to-be-measured unit element 101c.

  In the semiconductor device evaluation method according to the second embodiment, the first test pad 102 is set to the H state and the second test pad 103 is set to the L state in the same manner as in the first measurement mode in the first embodiment. By measuring the current flowing from the first test pad 102 to the second test pad 103, the presence / absence of a defective portion of the device circuit to be measured is measured, and the first defective portion is detected. That is, the potential information of the node between the first test pad 102 and the first defect location is the H potential, and between the first defect location and the second test pad 103 including the second defect location. The node potential information is L potential. Here, the node N01 between the first test pad 102 and the first disconnection location is at the H potential, and the nodes N02 to NM are at the L potential. The node potential information is transferred to the third test pad 108 via the node information transmission circuit 107 in the same manner as in the second measurement mode of the first embodiment. By counting the number of pulses of the clock signal 112 input until the output from the pad 108 changes from the L potential to the H potential, it is possible to detect that the first defect has occurred in the unit element 101b.

  Next, by setting the first test pad 102 to the L state and the second test pad 103 to the H state, the potential information of the node between the second test pad 103 and the second defect location becomes the H potential. Thus, the potential information of the node between the second defective portion and the first test pad 102 including the first defective portion becomes the L potential. Here, the node NM to the node N03 between the second test pad 103 and the second disconnection point are set to the H potential, and the node N02 and the node N01 are set to the L potential. The node potential information is transferred to the third test pad 108 via the node information transmission circuit 107 in the same manner as described above until the output from the third test pad changes from the H potential to the L potential. By counting the number of pulses of the input clock signal, it can be detected that the second defect has occurred in the unit element to be measured 101c.

  According to the semiconductor device and the evaluation method thereof according to the second embodiment, even when two defects occur in a large-scale contact chain or the like, it is possible to identify each defective area in a short time. is there.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described.

  According to the semiconductor device and the evaluation method thereof according to the first and second embodiments of the present invention, it is possible to easily detect a defective portion due to a disconnection of two or less locations generated in a large-scale contact chain or the like. However, in the semiconductor device and the evaluation method thereof according to the first and second embodiments, it is possible to detect only a defective portion closest to the test pad among the defective portions, and it is not possible to detect defects at three or more locations. The third embodiment of the present invention is a semiconductor device capable of detecting a defective portion when a plurality of defective portions are generated in a large-scale contact chain or the like and an evaluation method thereof.

  FIG. 5 shows a circuit configuration of the semiconductor device according to the third embodiment. Also in the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 5, the semiconductor device according to the third embodiment includes a device under test circuit in which two or more unit devices under test 101 (M + 1 in FIG. 5) are connected in series. A transfer switch 104 and a PMOS transistor 113 that pulls up the potential of the unit element to be measured to the VDD potential are connected to a node between the unit elements. A first test pad 102 and a second test pad 103 are connected to both ends of the device under test circuit, and a first signal input pad 105 is connected to the transfer switch 104. The gate terminal of each PMOS transistor 113 is connected to the flip-flop circuit 110 corresponding to each unit element to be measured, the input signal of the flip-flop circuit 110 is drawn to the fourth test pad 114, and the output signal is the third test pad. It is drawn out to the pad 108. Here, it is assumed that disconnections occur at three locations of the unit elements 101a, 101b, and 101m to be measured.

  In the semiconductor device according to the third embodiment, the first signal input pad 105 is set to the H state so that the flip-flop circuits 110 are connected in series. Arbitrary H state or L state potential information corresponding to the number of stages of the flip-flop circuit 110 is input to the fourth test pad 114 in synchronization with the clock signal 112, so that the potential states of all the flip-flop circuits 110 can be arbitrarily externally input. Can be set to That is, by setting the potential state of an arbitrary flip-flop circuit 110 to the L state, the PMOS transistor 113 connected to the flip-flop circuit 110 in which the potential state is the L state and the power supply VDD are brought into conduction, and the node N01 to the node It is possible to force any node from the NM to be in the H state. After setting the potential state of the node in this manner, it is possible to detect which unit element to be measured has failed by reading out the potential information of the node from the output pad 108 as shown in the first embodiment. Can do.

  Hereinafter, a method for evaluating the occurrence of a failure due to disconnection in the unit elements 101a, 101b, and 101m to be measured will be specifically described.

  By setting the first test pad 102 and the second test pad 103 to the H state or the L state, respectively, by the same method as the semiconductor device evaluation method according to the first and second embodiments, the H potential is set. Since a defect location near the applied test pad is detected, the unit to be measured 101 a that is the failure location closest to the first test pad 102 and the measurement target that is the failure location closest to the second test pad 103 are detected. It is possible to detect that a disconnection has occurred in the unit element 101m.

  Next, for example, after the node N03 is forcibly set to the H state, the potential information of each node can be read to detect that a failure has occurred in the unit element to be measured 101b.

  As described above, in the semiconductor device evaluation method according to the first and second embodiments, the disconnection point is detected by measuring the node that switches from the L state to the H state, and thus the devices to be measured connected in series. When disconnection occurs at a plurality of locations in the unit element, only the disconnection at the position closest to the test pad set in the H state is detected. However, a node in the L state may include a plurality of disconnections, but cannot be detected by the evaluation methods according to the first and second embodiments. Since the semiconductor device evaluation method according to the third embodiment can forcibly set the node in the L state to the H state, it is possible to detect the third fault location, and a plurality of disconnections occur. Even in this case, it is possible to identify the defective part.

  FIG. 6 is a diagram showing an operation procedure for efficiently detecting a plurality of disconnection points. The expression in the figure indicates the sign of each node as position information as it is. For example, n03 = n01 + (n02−n01) / 2 in the expression indicating the node n03 is a location obtained by adding a half between the node n01 and the node n02 to the position of the node n01, and an intermediate point between the node n01 and the node n02 Indicates.

  As shown in FIG. 6, by the semiconductor device evaluation method according to the first and second embodiments, between the first test pad 102 and the node n01 and between the second test pad 103 and the node n02, If a fault location due to a disconnection is detected between the node n01 and the node n02, it is unknown whether there is a fault location between the node n01 and the node n02, and the number of fault locations is unknown. Evaluate between. First, the node n03 that is an intermediate point between the node n01 and the node n02 is forcibly set to the H state. In this manner, the third failure location is detected from the position of the node that is in the L state. Here, for example, if the node n04 is in the L state, a failure has occurred in the unit element to be measured on the node n03 side as viewed from the node n04, and there is a further failure between the node n04 and the node n01. Whether there is a place is unknown. Next, the node n05, which is an intermediate point between the node n01 and the node n04, is forcibly set to the H state, and a defective portion is detected by measuring the node in the L state. This operation is repeated until no defective part is detected.

  In addition, although the node at the midpoint of the area that may contain the defective part is forcibly set to the H state, the unit element to be measured provided in the area that may contain the defective part is Since it is an integer, it may be in the vicinity of the intermediate point instead of the exact intermediate point.

  The circuit configuration shown in FIG. 5 shows a circuit example in which a PMOS transistor is connected to each node and the node potential is pulled up to the VDD potential. Instead of this configuration, as shown in FIG. The same effect can be obtained by pulling down the potential of each node to VSS.

  According to the semiconductor device and the evaluation method thereof according to the third embodiment, even when an arbitrary number of trouble spots are generated in a large-scale contact chain, the plurality of trouble spots are identified in a short time. Is possible.

(Fourth embodiment)
The fourth embodiment of the present invention will be described below.

  In the semiconductor device and the evaluation method thereof according to the first to third embodiments, one measured element circuit in which a plurality of measured unit elements are connected in series between the first test pad 102 and the second test pad 103. With respect to the above, even if a plurality of trouble spots occur in the device circuit to be measured, the trouble spots can be easily detected. In the fourth embodiment of the present invention, it is easy to solve the problem of a semiconductor device in which a plurality of configurations in which both ends of a measured element circuit in which a plurality of measured unit elements are connected in series are connected to a test pad are provided in parallel. And a method for evaluating the semiconductor device.

  FIG. 8 shows a circuit configuration of the semiconductor device according to the fourth embodiment. Also in the present embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 8, a first test pad 102 and a second test pad 103 are connected to both ends of a measured element circuit 115 (1151,..., 115K) in which a plurality of measured unit elements 101 are connected in series. Has been. Similarly, a configuration in which both ends of the device under test circuit are connected to the test pad is provided in parallel to form a circuit under test, and the Kth configuration is the fifth test at both ends of the device under test circuit 115K. The pad 116 and the sixth test pad 117 are connected. A corresponding selection circuit 118 is connected to each node between the measured unit elements in each measured element circuit, and one selected circuit 118 has K measured unit elements of each measured element circuit. It is connected. In addition, a plurality of signal input pads (K in FIG. 8) are connected to each selection circuit 118 according to the device circuit under test, and the device under test circuit 1151 receives a selection signal input from the signal input pad. An information signal of one node in the measurement element circuit 115K is selected, transmitted to the node information transmission circuit 107, and extracted from the third test pad 108. As described above, since the semiconductor device according to the fourth embodiment shares the node information transmission circuit 107 with a plurality of element circuits to be measured, a test pattern that effectively uses a limited scribe line region is provided. ing.

  In the semiconductor device evaluation method according to the fourth embodiment, first, in the same manner as the semiconductor device evaluation method of the first embodiment, the test pads connected to both ends of each element circuit to be measured are in the H state or By setting the L state, the presence or absence of disconnection in each device under test circuit is sequentially measured, and when a malfunction due to disconnection is detected, the first disconnection location is specified by measuring the node. . Further, when a defective portion due to disconnection occurs, the defective portion can be detected and specified in the same manner as in the semiconductor device evaluation methods of the second and third embodiments. In this way, a defective portion can be easily detected even in a semiconductor device provided with a plurality of element circuits to be measured.

  FIG. 9 shows a modification of the semiconductor device according to the fourth embodiment.

  As shown in FIG. 9, both ends of each device under test circuit are connected to a pad selection circuit 119 and connected to a common test pad. For this reason, since the number of test pads can be reduced as compared with the configuration in which each test pad is connected to each device under test circuit, the limited scribe line region can be used more effectively.

  FIG. 10 shows details of the pad selection circuit 119.

  As shown in FIG. 10, the first test pad 102 is connected to each device under test circuit via CMOS transfer switches ST1 to STK in which a PMOS transistor and an NMOS transistor are connected in parallel. The CMOS transfer switches ST1 to STK are pad selection circuits. The gate electrodes of the NMOS transistors constituting the respective CMOS transfer switches are connected to a selection signal connected to the signal input pads 1051 to 105K, and the gate electrodes of the PMOS transistors are The selection signal is connected to an inverted signal through an inverter circuit.

  Note that the signal input pads 1051 to 105K are in a selected state by being in the H state, and are normally in the L state of the non-selected state. For example, when the device under test circuit 1151 is selected, if only the first signal input pad 1051 is set to the H state and the other signal input pads are set to the L state, the node information transmitting circuit 107 is connected to the device under test circuit 1151. Are connected, and the information of each node of the device under test circuit 1151 is extracted from the third test pad 108.

  In this way, it is possible to detect a defective portion occurring in each device under test circuit. By using the evaluation methods shown in the second embodiment and the third embodiment, a plurality of devices under test each device circuit. Even when a problem occurs, it is possible to easily identify the defect part.

  In the fourth embodiment, only two measured device circuits are shown in order to simplify the illustration, but the number of measured device circuits to be paralleled may be arbitrarily set. Although not shown, when a plurality of element circuits to be measured are provided, a decoding method can be used to reduce the number of test pads.

  According to the semiconductor device and the evaluation method thereof according to the fourth embodiment, even when a failure occurs in a semiconductor device having a circuit to be measured in which a plurality of large-scale contact chains and the like are provided in parallel, It is possible to specify easily in a short time.

(Fifth embodiment)
The fifth embodiment of the present invention will be described below.

  In the semiconductor device and the evaluation method thereof according to the first to fourth embodiments, even if a plurality of open defective portions are generated in the measured element circuit for one measured element circuit in which a plurality of measured unit elements are connected in series. A defective part can be easily detected.

  The fifth embodiment according to the present invention is a semiconductor device capable of easily detecting a defective portion of a measured element circuit which is a short circuit failure detection pattern, and an evaluation method thereof.

  FIG. 11 shows a semiconductor device according to the fifth embodiment. The semiconductor device shown in FIG. 11 has a configuration obtained by modifying the snake and comb pattern shown in FIG. 18 and has “O1” terminals and “O2” terminals at both ends of the first wiring pattern 1. The second wiring pattern 2 on the comb side (for short circuit inspection) for detecting a short circuit (short circuit inspection) shown in FIG. 18 is divided into predetermined wiring units 10, and in FIG. 3 wiring patterns and 4th wiring pattern 4 are shown. The divided wiring patterns 2, 3, 4 for short-circuit inspection are sequentially connected by switching transistors 5, 6 shown in FIG.

  Each gate of the switching transistors 5 and 6 is connected to each output node of the shift register circuits 7 and 8 arranged corresponding to the switching transistors 5 and 6. In the circuit example shown in FIG. 11, P-type MOS transistors are used for the switching transistors 5 and 6. Accordingly, the output nodes of the shift register circuits 7 and 8 are initially set to “L” level, the switching transistors 5 and 6 are set to be in the same state, and each wiring pattern 2 for short circuit inspection is set. 3, 4 are electrically connected to each other in the initial state and have the same potential as the terminal “S1”.

  When detecting an open defect, a voltage is applied to the “O1” and “O2” terminals at both ends of the first wiring pattern 1 to measure the value of the current flowing between the terminals, thereby detecting the presence or absence of the open defect. . In order to detect a short-circuit failure, a voltage is applied between the “O1” or “O2” terminal and the “S1” terminal of the short-circuit inspection wiring pattern to detect the presence or absence of a short-circuit failure. At this time, as described above, 2, 3 and 4 of each wiring pattern for short circuit inspection are electrically connected to the “S1” terminal and have the same potential.

  Hereinafter, a means for identifying a defective portion when a short-circuit failure occurs between the “O1” terminal and the S1 terminal or between the “O2” terminal and the S1 terminal will be described. Here, a description will be given assuming that a short-circuit defect has occurred between the third wiring pattern 3 for short-circuit inspection and the first wiring pattern 1.

  As described above, the output values of the shift register circuits 7 and 8 are fixed to the “L” level in the initial state. Therefore, when the input of the shift register circuit 7 is set to the “H” level and the clock signal is input to the “CLK” terminal, the output of the first-stage shift register circuit 7 is in the “L” state corresponding to the input of the clock signal. To “H” state. As a result, the switching transistor 5 is switched from the conductive state to the cutoff state, and the second pattern 2 for short circuit inspection is disconnected from the “S1” terminal. Since there is no short circuit failure in the pattern 2, there is no change in the short circuit current between the “O1” terminal or the “O2” terminal and the “S1” terminal.

  Next, when a clock signal is input to the “CLK” terminal, the output value of the second-stage shift register circuit 8 changes to “H” level, and the switching transistor 6 connected to the second-stage shift register circuit 8 is cut off. In this state, the third wiring pattern 3 for short-circuit inspection at the second stage is disconnected from the “S1” terminal.

  In this way, by checking whether or not a short-circuit current is flowing between the “O1” terminal or “O2” terminal and the S1 terminal, the clock signal is sequentially input to the “CLK” terminal, thereby checking the short circuit. The wiring patterns 2, 3, and 4 are sequentially cut off, and a short-circuit current flows while the wiring pattern including the portion where the short-circuit defect occurs is connected to the “S 1” terminal. When the third wiring pattern 3 for short-circuit inspection is cut off, a short-circuit current does not flow between the “O1” terminal or the “O2” terminal and the S1 terminal, so that a defective portion is included in the third wiring pattern 3. It turns out that Therefore, the defective position can be easily identified by counting the number of input clock pulses.

  As described above, according to the fifth embodiment, it is possible to easily identify the occurrence location of a short-circuit defect even in a large-scale short-circuit inspection wiring pattern.

  In the fifth embodiment, the switching transistors 5 and 6 are P-type MOS transistors, but other switching means such as an N-type MOS transistor can form a test pattern having the same effect.

(Sixth embodiment)
Hereinafter, a sixth embodiment of the present invention will be described with reference to FIG. About the same component as 5th Embodiment, description is abbreviate | omitted by attaching | subjecting the same code | symbol.

    Similar to the fifth embodiment, the wiring pattern for short circuit inspection is divided into a predetermined number such as the second wiring pattern 2, the third wiring pattern 3, and the fourth wiring pattern 4. Corresponding to the divided wiring patterns 2, 3, 4, shift register circuits 7, 8, 9 are connected in series, and each node between the shift register circuits 7, 8, 9 is divided short circuit. The wiring patterns 2, 3, and 4 for inspection are connected to the wiring patterns. The shift register circuits 7, 8, and 9 are set to the “L” level in the initial state. Here, the description will be made on the assumption that a short-circuit defect has occurred between the third wiring pattern 3 for short-circuit inspection and the first wiring pattern 1.

  When the “H” potential is applied to the “O1” terminal or the “O2” terminal, the current from the “O1” terminal or the “O2” terminal to which the “H” potential is applied due to a short circuit failure in the third wiring pattern 3 for short circuit inspection. Flows into the circuit, confirming the occurrence of a short circuit failure.

  By setting the input value of the first-stage shift register circuit 7 to the “H” level and inputting the clock signal to the “CLK” terminal, the output of the shift register circuit 7 becomes the “H” state. At this time, if a short-circuit failure occurs between the first wiring pattern 1 and the second wiring pattern 2 for short-circuit inspection, both potentials are in the “H” state, so that no current flows, and the short-circuit failure is It can be seen that this occurred between the first wiring pattern 1 and the second wiring pattern 2. However, since the short-circuit portion is between the first wiring pattern 1 and the third wiring pattern 3, no change occurs in the short-circuit current. Thereby, it can be seen that there was no short circuit failure between the first wiring pattern 1 and the second wiring pattern 2.

  Further, by sequentially inputting the clock signal to the “CLK” terminal, the output values of the shift register circuits 7, 8, 9 are sequentially switched to the “H” level, and the output terminals of the shifted shift register circuits 7, 8, 9 are switched. As long as there is no short circuit failure in the short circuit inspection wiring pattern 2 or the like connected to, the short circuit current does not change.

  When the clock signal is sequentially input and the output value of the shift register circuit 8 connected to the third wiring pattern 3 for short circuit inspection is switched to the “H” level, the same potential as that of the “O1” terminal or “O2” terminal is obtained. Therefore, the short circuit current does not flow. Thereby, it is found that the third wiring pattern 3 is defective. Therefore, the defective position can be easily identified by counting the number of input clock pulses.

  As described above, in the sixth embodiment, it is possible to easily identify the occurrence location of the short-circuit defect in the large-scale short-circuit test pattern.

  FIG. 13 shows an example of a detailed circuit of the semiconductor device according to the sixth embodiment. The configuration is equivalent to the circuit configuration according to the first embodiment shown in FIG. 2, and has a node information transmission circuit unit 106 equivalent to the node information transmission circuit unit (unit) 106 in FIG.

  In FIG. 13, a second wiring pattern 2 for short circuit inspection is added and connected to the output terminal of the flip-flop circuit 110 included in the unit 106. When detecting an open failure, as shown in the first embodiment, the “O1” terminal is set to the H state, the other end “O2” terminal is set to the L state, and the current flowing between both terminals is detected. Is measured to detect the presence of open defects. When it is determined that an open defect has occurred, the defect position can be identified by the method described in the first embodiment.

  On the other hand, in order to detect a short circuit failure, the “C1” terminal is first set to the H state, and a plurality of flip-flop circuits 110 are connected in series. Thereafter, the “O1” terminal or the “O2” terminal is fixed to the H state. Here, by applying the RST signal, the output value of each flip-flop circuit 110 is in the L state. Therefore, if there is a short circuit failure in the second wiring pattern 2 for short circuit inspection, the “O1 in the H state is displayed. Since current flows from the “terminal” or “O2” terminal, a short circuit failure is found.

  After that, similarly to the method shown in the fifth embodiment, by sequentially inputting clock pulses to the CLK terminal and sequentially setting the potential of the short-circuit inspection terminal to the H state, the “O1” terminal or the “O2” terminal A state where current does not flow from is generated, and the number of clock pulses reaching that state is counted to identify a short-circuit defective portion.

  As described above, the short circuit inspection can be realized by adding the short circuit inspection pattern to the same basic circuit configuration as the node information transmission circuit unit 106 used in the first to fourth embodiments.

  The semiconductor device and the evaluation method thereof according to the present invention can detect a defective part more easily in a short time when performing electrical measurement of an element with a large-scale contact chain or a large-scale wiring pattern. This is useful for stable management of semiconductor device manufacturing processes.

1 is a circuit diagram showing a circuit configuration of a semiconductor device according to a first embodiment of the present invention. 1 is a circuit diagram showing an example of a circuit configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing an example of a flip-flop circuit in the semiconductor device according to the first embodiment of the present invention. It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a figure which shows the procedure of the evaluation method which concerns on the 3rd Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on the modification of the 3rd Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on the modification of the 4th Embodiment of this invention. It is a circuit diagram which shows the pad selection circuit based on the 4th Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on the 5th Embodiment of this invention. It is a circuit diagram which shows the circuit structure of the semiconductor device which concerns on the 6th Embodiment of this invention. It is a circuit diagram which shows the detail of the circuit structure of the semiconductor device which concerns on the 6th Embodiment of this invention. (A) And (b) is a figure which shows the conventional contact chain, (a) is a top view, (b) is sectional drawing. (A) And (b) is a circuit diagram which shows typically the conventional test pattern. It is a top view which shows the disconnection check pattern for the conventional wiring layers. (A) And (b) shows the conventional stacked contact chain, (a) is a top view, (b) is sectional drawing. It is a top view which shows the short circuit check pattern (snake & comb) for the conventional wiring layers. It is a circuit diagram which shows the circuit structure of the semiconductor device (test circuit) which concerns on a prior art example.

Explanation of symbols

101 a unit element to be measured 101 b unit element to be measured 101 c unit element to be measured 102 first test pad 103 second test pad 104 transfer switch 105 first signal input pad 106 node information transmission circuit unit (unit)
107 node information transmission circuit 108 third test pad 109 second signal input pad 110 flip-flop circuit 111 reset signal 112 clock signal 113 PMOS transistor 114 fourth test pad 115 measured device circuit 116 fifth test pad 117 first 6 test pads 118 selection circuit 119 pad selection circuit 1 first wiring pattern 2 second wiring pattern 3 third wiring pattern 4 fourth wiring pattern 5 switching transistor 6 switching transistor 7 shift register circuit 8 shift register circuit 9 shift register circuit 10 Wiring unit

Claims (11)

A measured element circuit including a plurality of measured unit elements connected in series;
A plurality of selection elements respectively connected to each node between the adjacent unit elements to be measured;
A node information transmission circuit connected to the plurality of selection elements,
The potential generated at each node when a voltage is applied across the measured device circuit is input to the node information transmission circuit,
The node information transmission circuit sequentially outputs the inputted potential of each node to the outside. A potential fixing means for fixing the potential of any one of the plurality of nodes;
2. The semiconductor device according to claim 1, wherein a potential generated at each node between the node at which the potential is fixed and both ends of the device under test circuit is input to the node information transmission circuit. . A circuit under test having a plurality of device under test circuits each including a plurality of device under test devices connected in series and connected in parallel with each other;
A plurality of selection circuits connected to each node between adjacent unit elements to be measured in the device circuit to be measured, and connected in parallel to each other;
A node information transmission circuit connected to the plurality of selection circuits,
The potentials generated at the nodes when a voltage is applied to both ends of one of the plurality of device circuits to be measured are applied to the plurality of selection circuits corresponding to the one device circuit to be measured. Input to the node information transmission circuit by a signal to be controlled,
The node information transmission circuit sequentially outputs the inputted potential of each node to the outside. A method for evaluating a semiconductor device according to claim 1, wherein:
Applying a voltage across the measured device circuit (a);
(B) inputting the potential generated at each node by the step (a) to the node information transmission circuit by a signal for controlling the plurality of selection elements;
A step (c) of sequentially outputting the potential of each node input to the node information transmission circuit in the step (b) to the outside;
And (d) identifying a first defect location in the unit element to be measured by detecting a change point of the potential of each node output in the step (c). Semiconductor device evaluation method. After step (d)
A step (e) of applying a voltage in the opposite direction to the step (a) to both ends of the device circuit to be measured;
Inputting the potential generated at each node by the step (e) into the node information transmission circuit by a signal for controlling the plurality of selection elements;
A step (g) of sequentially outputting the potential of each node input to the node information transmission circuit in the step (f) to the outside;
And (h) identifying a second failure location in the terminal element to be measured by detecting a change point of the potential of each node output in the step (g). The method for evaluating a semiconductor device according to claim 4. (I) applying a potential to any one of the plurality of nodes after the step (h);
Inputting the potential generated at each node in the step (i) into the node information transmission circuit by a signal for controlling the plurality of selection elements;
A step (k) of sequentially outputting the potential of each node input to the node information transmission circuit in the step (j) to the outside;
And (1) identifying a third defect location in the measured terminal element by detecting a change point of the potential of each node output in the step (k). The method for evaluating a semiconductor device according to claim 5. A method for evaluating a semiconductor device according to claim 3, comprising:
Applying a voltage across the first measured device circuit of the plurality of measured device circuits (a);
The potential generated at each node of the first device under test circuit by the step (a) is input to the node information transmission circuit by a signal for controlling a plurality of selection circuits corresponding to the first device under test circuit. Step (b) to perform,
A step (c) of sequentially outputting the potential of each node of the first device under test circuit input to the node information transmission circuit in the step (b) to the outside;
A step (d) of identifying a defective portion in the unit element to be measured that constitutes the first device to be measured circuit by detecting a change point of the potential of each node output in the step (c). When,
The steps (a) to (d) are sequentially and repeatedly performed on a plurality of measured device circuits other than the first measured device circuit among the plurality of measured device circuits. A method for evaluating a semiconductor device, comprising: identifying a unit element to be measured in which a failure occurs in all of the measurement element circuits. A snake-shaped first wiring pattern formed so as to meander in one plane and having a plurality of concavo-convex portions, and a plurality of comb shapes disposed so as to face each concavo-convex portion of the first wiring pattern A device under test circuit configured by the second wiring pattern,
A plurality of selection elements respectively connected to each node between the adjacent second wiring patterns;
A node information transmission circuit connected to the plurality of selection elements;
Between the first wiring pattern and the predetermined second wiring pattern when a voltage is applied between the first wiring pattern and the predetermined second wiring pattern selected from the plurality of second wiring patterns. A terminal for measuring the current value flowing through the external measuring instrument,
The node information transmission circuit sequentially disconnects the second wiring pattern by sequentially deselecting selection elements. A snake-shaped first wiring pattern formed so as to meander in one plane and having a plurality of concavo-convex portions, and a plurality of comb shapes disposed so as to face each concavo-convex portion of the first wiring pattern A device under test circuit configured by the second wiring pattern,
A node information transmission circuit connected to the plurality of second wiring patterns;
Between the first wiring pattern and the predetermined second wiring pattern when a voltage is applied between the first wiring pattern and the predetermined second wiring pattern selected from the plurality of second wiring patterns. A terminal for measuring the current value flowing through the external measuring instrument,
The node information transmission circuit makes the potential of the connected second wiring pattern the same as the potential of the first wiring pattern. A method for evaluating a semiconductor device according to claim 8, comprising:
Applying a voltage between the first wiring pattern and the predetermined second wiring pattern selected from the plurality of second wiring patterns (a);
A step (b) of sequentially deselecting the plurality of selection elements by the node information transmission circuit and sequentially separating the second wiring pattern;
A step (c) of sequentially monitoring a current flowing between the first wiring pattern and the plurality of second wiring patterns that have not been separated by the step (b);
And (d) identifying a defect location in the plurality of second wiring patterns by detecting a change point of the current value of each node output in the step (c). For evaluating a semiconductor device. A method for evaluating a semiconductor device according to claim 9, comprising:
Applying a voltage between the first wiring pattern and a predetermined second wiring pattern selected from the plurality of second wiring patterns (a);
Setting the potential of the second wiring pattern to the same potential as the potential of the first wiring pattern by the node information transmission circuit;
A step (c) of sequentially monitoring a current flowing between the first wiring pattern and the plurality of second wiring patterns that sequentially change in the step (b);
A step (d) of identifying a defective portion in the plurality of second wiring patterns by detecting a change point of the current value of each node in the step (c). Evaluation methods.

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