JP2017045905A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2017045905A
JP2017045905A JP2015168422A JP2015168422A JP2017045905A JP 2017045905 A JP2017045905 A JP 2017045905A JP 2015168422 A JP2015168422 A JP 2015168422A JP 2015168422 A JP2015168422 A JP 2015168422A JP 2017045905 A JP2017045905 A JP 2017045905A
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semiconductor device
plate
semiconductor element
pair
conductive material
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孝 大美賀
Takashi Omika
孝 大美賀
健治 藤本
Kenji Fujimoto
健治 藤本
博之 荻野
Hiroyuki Ogino
博之 荻野
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Sanken Electric Co Ltd
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Sanken Electric Co Ltd
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Priority to JP2015168422A priority Critical patent/JP2017045905A/en
Priority to CN201520920357.1U priority patent/CN205104480U/en
Publication of JP2017045905A publication Critical patent/JP2017045905A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of securing a large current capacity to market demands of security of a large current capacity without performing wire bonding of a thick aluminium wire a plurality of times.SOLUTION: A semiconductor device comprises a semiconductor element, a lead frame, a conductive material for electrically connecting between the semiconductor element and the lead frame, and a case arranged so as to surround the semiconductor element. A region surrounded by the case is encapsulated by an encapsulation body. In the semiconductor device, the conductive material has a structure having a pair of plate-like connection parts, a pair of plate-like bridge pier parts coupled with one end of the connection parts, and formed so as to stand upward from the connection parts, and a plate-like bridge plate part that couples between upper ends of the pair of bridge pier parts.SELECTED DRAWING: Figure 1

Description

本発明は、ケース内を樹脂で封止する高温領域で動作可能な半導体装置に関する。
The present invention relates to a semiconductor device operable in a high temperature region in which a case is sealed with resin.

金型を使用したトランスファーモールドに代えて、樹脂ケースを使用した半導体装置がある。この半導体装置は、半導体素子としてＳｉＣなどの化合物半導体を用いたものがあり、従来のＳｉ半導体を用いたものに比べて、高温領域での動作が可能であり、小型化や高効率化が期待されている。
There is a semiconductor device using a resin case instead of a transfer mold using a mold. Some of these semiconductor devices use a compound semiconductor such as SiC as a semiconductor element, and can operate in a higher temperature region than those using a conventional Si semiconductor, and are expected to be smaller and more efficient. Has been.

半導体素子の電気的接続のために、従来技術の一般的な手法として、高導電性の金属線によるワイヤボンディングが広く用いられている。金属線には例えばアルミニウムが用いられるが、金線や銅線といった、金属線を用いる場合もある。また、例えば電力用半導体素子のように、制御用半導体素子に比べて相対的に多くの電流が流れる場合、太いアルミ線を複数本用いてワイヤボンディングを行うことがある。（特許文献１）
For electrical connection of semiconductor elements, wire bonding using a highly conductive metal wire is widely used as a general technique of the prior art. For example, aluminum is used as the metal wire, but a metal wire such as a gold wire or a copper wire may be used. In addition, when a relatively large amount of current flows as compared to the control semiconductor element, such as a power semiconductor element, wire bonding may be performed using a plurality of thick aluminum wires. (Patent Document 1)

中国実用新案２０３０１３７０９Ｕ号公報Chinese Utility Model No. 20301709U

従来技術によれば、さらに大電流容量の要求に応えるためには、より太いアルミ線が複数本必要となる。例えば、５００アンペアの電流を流す必要がある場合、直径５００μｍのアルミ線が６本必要である。

しかしながら、太いアルミ線のワイヤボンディングを複数行うには、多くの工数とコストがかかる。一方では、半導体装置の小型化という市場要求もあって、電力用半導体素子の電極面積を広くすることも難しい。あるいは、アルミニウムよりも電気抵抗が低い金属線の利用も考えられるが、例えば銅線では硬度が高く、ワイヤボンディングでの半導体素子へのダメージが懸念される。さらには、電力用半導体素子からの発熱といった課題がある。
According to the prior art, a plurality of thicker aluminum wires are required to meet the demand for higher current capacity. For example, when it is necessary to pass a current of 500 amperes, six aluminum wires having a diameter of 500 μm are required.

However, many man-hours and costs are required to perform a plurality of wire bondings of thick aluminum wires. On the other hand, due to the market demand for miniaturization of semiconductor devices, it is difficult to increase the electrode area of power semiconductor elements. Alternatively, use of a metal wire having an electric resistance lower than that of aluminum is conceivable. However, for example, a copper wire has high hardness, and there is a concern about damage to a semiconductor element in wire bonding. Furthermore, there is a problem of heat generation from the power semiconductor element.

本発明は、上記問題点を鑑み、大電流容量を確保できる半導体装置を提供することを目的とする。
In view of the above problems, an object of the present invention is to provide a semiconductor device that can ensure a large current capacity.


上述の課題を解決するために、本発明は以下に掲げる構成とした。
本発明の半導体装置は、半導体素子と、リードフレームと、半導体素子とリードフレームとを、電気的に接続する導電材と、半導体素子を囲むように配置されるケースと、ケースで囲まれる領域を封止体で封止する半導体装置において、導電材は、板状の一対の接続部と、接続部の一端に連結され且つ、接続部から上方に立ちあがって形成された板状の一対の橋脚部と、一対の橋脚部の上端を連結する板状の橋板部とを有することを特徴とする。
In order to solve the above-described problems, the present invention is configured as follows.
A semiconductor device of the present invention includes a semiconductor element, a lead frame, a conductive material that electrically connects the semiconductor element and the lead frame, a case disposed so as to surround the semiconductor element, and a region surrounded by the case In a semiconductor device to be sealed with a sealing body, a conductive material includes a pair of plate-like connection portions and a pair of plate-like bridge pier portions that are connected to one end of the connection portion and are raised upward from the connection portion. And a plate-like bridge plate portion connecting the upper ends of the pair of bridge pier portions.

本発明では、大電流容量を確保できる半導体装置を提供することができる効果を奏する。
The present invention has an effect of providing a semiconductor device that can ensure a large current capacity.

本発明の実施例１に係る半導体装置１００の断面概念図である。1 is a conceptual cross-sectional view of a semiconductor device 100 according to Embodiment 1 of the present invention. 本発明の実施例１に係る導電材３付近の斜視概念図である。It is a perspective conceptual diagram near the electrically conductive material 3 which concerns on Example 1 of this invention. 本発明の変形例１に係る半導体装置１００の断面概念図である。It is a cross-sectional conceptual diagram of the semiconductor device 100 which concerns on the modification 1 of this invention.

以下、本発明を実施するための形態について、図を参照して詳細に説明する。なお以下の図面の記載において、同一または類似の部分には、同一または類似の符号で表している。但し、図面は模式的なものであり、寸法関係の比率等は現実のものとは異なる。したがって、具体的な寸法等は以下の説明を照らし合わせて判断するべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。

また、以下に示す実施の形態は、この発明の技術的思想を具体化するための例示であって、この発明の実施の形態は、構成部品の材質、形状、構造、配置等を下記のものに特定するものではない。この発明の実施の形態は、要旨を逸脱しない範囲内で種々変更して実施できる。
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the dimensional relationship ratios and the like are different from the actual ones. Therefore, specific dimensions and the like should be determined in light of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

The following embodiments are exemplifications for embodying the technical idea of the present invention, and the embodiments of the present invention are described below in terms of the material, shape, structure, arrangement, etc. of the components. It is not something specific. The embodiments of the present invention can be implemented with various modifications without departing from the scope of the invention.

以下、図面を参照して本発明の実施例に係る半導体装置１００を説明する。図１は、本発明の実施例に係る半導体装置１００の平面概念図である。また図２は、本発明の実施例に係る導電材３付近の斜視概念図である。
Hereinafter, a semiconductor device 100 according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a conceptual plan view of a semiconductor device 100 according to an embodiment of the present invention. FIG. 2 is a perspective conceptual view of the vicinity of the conductive material 3 according to the embodiment of the present invention.

図１に示す半導体装置１００は、半導体素子１、リードフレーム２、導電材３、基板４、放熱板５、ケース６、封止体７から成っている。
A semiconductor device 100 shown in FIG. 1 includes a semiconductor element 1, a lead frame 2, a conductive material 3, a substrate 4, a heat sink 5, a case 6, and a sealing body 7.

半導体素子１は、リードフレーム２上に接着材を介して載置され固定されている。例えばＳｉＣ半導体やＧａＮ半導体等の化合物半導体で構成する電力用半導体素子である。Ｓｉ半導体に比べて高温状態での動作が可能であり、またスイッチング速度が速く、低損失である。
The semiconductor element 1 is placed and fixed on the lead frame 2 via an adhesive. For example, it is a power semiconductor element composed of a compound semiconductor such as a SiC semiconductor or a GaN semiconductor. Compared to Si semiconductors, it can operate at high temperatures, has a high switching speed, and low loss.

リードフレーム２は、主面に半導体素子１を載置し、接着材を介して固定している。本発明の実施例では、リードフレーム２は、例えば、１．０ｍｍ厚の平形状板材をプレス打ち抜き加工や化学的なエッチング加工が施されて形成され、材質は銅または銅合金が多く使用され、表面は銀めっき等を施すことができる。
The lead frame 2 has the semiconductor element 1 mounted on the main surface and fixed via an adhesive. In the embodiment of the present invention, the lead frame 2 is formed, for example, by subjecting a flat plate material having a thickness of 1.0 mm to press punching or chemical etching, and the material is often copper or copper alloy, The surface can be subjected to silver plating or the like.

図２で示すように、導電材３は、板状の一対の接続部と、接続部の一端に連結され且つ、接続部から上方に立ちあがって形成された板状の一対の橋脚部と、一対の橋脚部の上端を連結する板状の橋板部とを有し、接続部は、半導体素子１およびリードフレーム２とを、はんだ（図示せず）を介して電気的に接続する。

導電材３は、導電性が高い金属材が好ましく、アルミニウム材、あるいは銅材、あるいは金材で構成するのがよい。導電材の断面積は必要なアルミ線の断面積と同じくすればよい。本発明の実施例では、直径５００μｍのアルミ線６本分に相当する断面積である。
As shown in FIG. 2, the conductive material 3 includes a pair of plate-like connection portions, a pair of plate-like bridge piers that are connected to one end of the connection portion and are raised upward from the connection portion, And a plate-like bridge plate portion for connecting the upper ends of the bridge pier portions, and the connection portion electrically connects the semiconductor element 1 and the lead frame 2 via solder (not shown).

The conductive material 3 is preferably a metal material having high conductivity, and is preferably composed of an aluminum material, a copper material, or a gold material. The cross-sectional area of the conductive material may be the same as the required cross-sectional area of the aluminum wire. In the embodiment of the present invention, the cross-sectional area is equivalent to six aluminum wires having a diameter of 500 μm.

基板４は、アルミ基板と、アルミ基板の上面に形成された絶縁層（図示せず）と、絶縁層を介して、アルミ基板の上面に形成された導体層（回路配線）を有し、導体層は、半導体素子を一方の主面に導電性接着材を介して固着させている。また基板４の下面には、熱伝導性の高い接着剤を介して、放熱板５を配置する。
The substrate 4 has an aluminum substrate, an insulating layer (not shown) formed on the upper surface of the aluminum substrate, and a conductor layer (circuit wiring) formed on the upper surface of the aluminum substrate via the insulating layer. The layer fixes the semiconductor element to one main surface via a conductive adhesive. Further, a heat radiating plate 5 is disposed on the lower surface of the substrate 4 with an adhesive having high thermal conductivity.

放熱板５は、銅または銅合金を基材とし、めっきが施されている。放熱板５は、基板４の下面に配置され、放熱板５の一方の主面は、半導体装置１００の外表面に露出している。これにより基板４の放熱性を向上させる。
The heat sink 5 is made of copper or a copper alloy as a base material and plated. The heat sink 5 is disposed on the lower surface of the substrate 4, and one main surface of the heat sink 5 is exposed on the outer surface of the semiconductor device 100. Thereby, the heat dissipation of the substrate 4 is improved.

ケース６は、基板４の一方の主面に配置され、平面視において、半導体素子を囲むように設けられている。本実施例においては、ケース６を基板４の外周縁に沿って配置し、基板４の側面の延長線上にケース５の外壁が位置するようにしている。このため、ケース６は、半導体素子を保護するパッケージ（外囲体）の一部として機能するとともに、封止樹脂が注入される器として機能する。

ケース６は、例えば、加工性がよく融点も２８０℃と高い、ポリフェニレンスルファイド（ＰＰＳ）が望ましい。
The case 6 is disposed on one main surface of the substrate 4 and is provided so as to surround the semiconductor element in plan view. In the present embodiment, the case 6 is disposed along the outer peripheral edge of the substrate 4 so that the outer wall of the case 5 is positioned on the extended line of the side surface of the substrate 4. For this reason, the case 6 functions as a part of the package (enclosure) that protects the semiconductor element and also functions as a container into which the sealing resin is injected.

For example, the case 6 is preferably polyphenylene sulfide (PPS), which has good workability and a high melting point of 280 ° C.

封止体７は、基板４の上面において、ケース６で囲まれた領域に形成されている。封止体７は、熱による物性変化が少なく耐熱性が優れた樹脂から成る。例えばシリコン系樹脂が用いられる。

以上により、半導体装置１００が完成する。
The sealing body 7 is formed in a region surrounded by the case 6 on the upper surface of the substrate 4. The sealing body 7 is made of a resin that has little change in physical properties due to heat and excellent heat resistance. For example, a silicon resin is used.

Thus, the semiconductor device 100 is completed.

次に、上述の実施例に係る半導体装置１００の効果を説明する。
Next, effects of the semiconductor device 100 according to the above-described embodiment will be described.

本発明の実施例に係る半導体装置は、請求項１によれば、導電材に、板状の一対の接続部と、接続部の一端に連結され且つ、接続部から上方に立ちあがって形成された板状の一対の橋脚部と、一対の橋脚部の上端を連結する板状の橋板部とを有する構造をもつことから、金属線を用いたワイヤボンディングに比べて、導電材の熱容量を増大することができ、また放熱面積を拡大することができる。よって大電流が流れる場合の放熱性を向上することができる。
According to claim 1, the semiconductor device according to the embodiment of the present invention is formed by connecting the conductive material to the pair of plate-like connection portions and one end of the connection portion and rising upward from the connection portion. Because it has a structure with a pair of plate-like bridge piers and a plate-like bridge plate that connects the upper ends of the pair of bridge piers, the heat capacity of the conductive material is increased compared to wire bonding using metal wires In addition, the heat dissipation area can be expanded. Therefore, heat dissipation when a large current flows can be improved.

また、導電材の電気的接続の際には、はんだの使用が可能であり、チップのはんだ付けと同時に接合できる。さらに、複数のワイヤボンディング工程を必要としないなど、製造工数の削減が可能である。
In addition, when electrically connecting the conductive materials, solder can be used, and bonding can be performed simultaneously with the soldering of the chip. Furthermore, it is possible to reduce the number of manufacturing steps, such as not requiring a plurality of wire bonding steps.

上述のように、本発明を実施するための形態を記載したが、この開示から当業者には様々な代替実施の形態、実施例が可能であることは明らかである。
As described above, the mode for carrying out the present invention has been described. However, it is apparent to those skilled in the art that various alternative embodiments and examples are possible from this disclosure.

ケース６はＰＰＳ材を主材としたが、金属よりも軽くて絶縁性が保たれる材料が好ましく、塩化ビニール樹脂、ＡＢＳ樹脂などでもよい。
The case 6 is mainly made of a PPS material, but is preferably a material that is lighter than metal and can maintain insulation, and may be a vinyl chloride resin, an ABS resin, or the like.

基板４をアルミ基板としたが、ＡｌＮ基板あるいは、アルミナセラミックス基板に、銅回路をＤｉｒｅｃｔ Ｃｏｐｐｅｒ Ｂｏｎｄ法にて接合したＤＢＣ基板を用いて、放熱用絶縁基板としてもよい。
Although the substrate 4 is an aluminum substrate, a DBC substrate obtained by bonding a copper circuit to an AlN substrate or an alumina ceramic substrate by the Direct Copper Bond method may be used as an insulating substrate for heat dissipation.

変形例として、図３に示すように、半導体装置１００は、ケース６の上面に蓋８を取り付けてもよい。これにより、さらに密着性が良好に得られ、耐湿性に優れた半導体装置を実現できる。
As a modification, as shown in FIG. 3, the semiconductor device 100 may have a lid 8 attached to the upper surface of the case 6. As a result, it is possible to realize a semiconductor device that has better adhesion and is excellent in moisture resistance.

１、半導体素子
２、リードフレーム
３、導電材
３１、接続部
３２、橋脚部
３３、橋板部
４、基板
５、放熱板
６、ケース
７、封止体
１００、半導体装置 DESCRIPTION OF SYMBOLS 1, Semiconductor element 2, Lead frame 3, Conductive material 31, Connection part 32, Bridge pier part 33, Bridge board part 4, Board | substrate 5, Heat sink 6, Case 7, Sealing body 100, Semiconductor device

Claims (1)

半導体素子と、リードフレームと、前記半導体素子と前記リードフレームとを、電気的に接続する導電材と、前記半導体素子を囲むように配置されるケースと、前記ケースで囲まれる領域を封止体で封止する半導体装置において、前記導電材は、板状の一対の接続部と、前記接続部の一端に連結され且つ、接続部から上方に立ちあがって形成された板状の一対の橋脚部と、前記一対の橋脚部の上端を連結する板状の橋板部とを有することを特徴とする半導体装置。   A semiconductor element, a lead frame, a conductive material that electrically connects the semiconductor element and the lead frame, a case disposed so as to surround the semiconductor element, and an area surrounded by the case In the semiconductor device to be sealed, the conductive material includes a pair of plate-like connection portions, and a pair of plate-like bridge pier portions that are connected to one end of the connection portion and are raised upward from the connection portion. A semiconductor device comprising: a plate-like bridge plate portion that connects upper ends of the pair of bridge pier portions.
JP2015168422A 2015-08-28 2015-08-28 Semiconductor device Pending JP2017045905A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019165051A (en) * 2018-03-19 2019-09-26 京セラ株式会社 Power semiconductor module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019165051A (en) * 2018-03-19 2019-09-26 京セラ株式会社 Power semiconductor module

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