CN205104480U - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN205104480U CN205104480U CN201520920357.1U CN201520920357U CN205104480U CN 205104480 U CN205104480 U CN 205104480U CN 201520920357 U CN201520920357 U CN 201520920357U CN 205104480 U CN205104480 U CN 205104480U
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- connecting portion
- pair
- utility
- model
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/37124—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/37099—Material
- H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/37147—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
Abstract
The utility model provides a semiconductor device to the market requirements who ensures big current capacity, need not to carry out the lead bonding than the crude aluminum line many times, can ensure big current capacity. The utility model discloses a semiconductor device has: semiconductor component, lead frame, general semiconductor component with conductive parts that lead frame electricity is connected and in order to surround the casing of semiconductor component's mode configuration, this semiconductor device uses the seal to the quilt seal in the region that the casing surrounded, semiconductor device's characterized in that, conductive parts has: platelike a pair of connecting portion, platelike a pair of pier portion, its with the one end of connecting portion links mutually to form to from connecting portion to the top immediately, and platelike bridge plate portion, its binding the upper end of a pair of pier portion.
Description
Technical field
The utility model relates to and uses resin to sealing in housing and can carrying out the semiconductor device of work at high-temperature area.
Background technology
Some semiconductor devices employ resin-case to replace the transfer modling using mould.In this semiconductor device, what have employs the compound semiconductors such as SiC as semiconductor element, compared with the semiconductor device of use Si semiconductor in the past, can carry out work at high-temperature area, is expected to realize miniaturized and high efficiency.
In order to realize the electrical connection of semiconductor element, as the general means of prior art, the wire-bonded based on high-conductivity metal line is widely used.Metal wire such as uses aluminum steel, but also sometimes uses gold thread or the such metal wire of copper cash.Such as, in addition, as power semiconductor element, when flowing through electric currents much more relatively compared with control semiconductor element, much thicker aluminum steels are sometimes used to carry out wire-bonded (patent documentation 1).
[patent documentation 1]: Chinese utility model 203013709U publication
According to prior art, in order to tackle the requirement of further high current capacity, need the aluminum steel that use many is thicker.Such as, when needing the electric current flowing through 500 amperes, use 6 diameters are needed to be the aluminum steel of 500 μm.
But, want the wire-bonded of repeatedly carrying out compared with crude aluminum line, need more man-hour and cost.On the other hand, there are the market demands that the miniaturization of semiconductor device is such, be difficult to the electrode area expanding power semiconductor element.Or, also can consider the metal wire using resistance lower than aluminium, but such as copper cash, its hardness is higher, likely in wire-bonded, causes damage to semiconductor element.There is the problem of power semiconductor element heating in addition.
Utility model content
Point in view of the above problems, the purpose of this utility model is to provide a kind of semiconductor device can guaranteeing high current capacity.
In order to solve the problem, the utility model becomes structure as follows.
Semiconductor device of the present utility model has: semiconductor element, lead frame, conductive component semiconductor element and lead frame are electrically connected and the housing configured in the mode of surrounding semiconductor element, sealed by seal by the region that housing surrounds, the feature of this semiconductor device is, conductive component has: a pair connecting portion of tabular; A pair bridge pier portion of tabular, one end of itself and connecting portion is connected, and is formed as erecting upward from connecting portion; And the bridge plate portion of tabular, it links the upper end in a pair bridge pier portion.
In the utility model, achieve and a kind of effect can guaranteeing the semiconductor device of high current capacity can be provided.
Accompanying drawing explanation
Fig. 1 be the semiconductor device 100 of embodiment 1 of the present utility model analyse and observe concept map.
Fig. 2 is the three-dimensional concept map near the conductive component 3 of embodiment 1 of the present utility model.
Fig. 3 be the semiconductor device 100 of variation 1 of the present utility model analyse and observe concept map.
Label declaration
1: semiconductor element; 2: lead frame; 3: conductive component; 31: connecting portion; 32: bridge pier portion; 33: bridge plate portion; 4: substrate; 5: heating panel; 6: housing; 7: sealing; 100: semiconductor device.
Embodiment
Below, be described in detail for implementing mode of the present utility model with reference to accompanying drawing.In addition, in the record of the following drawings, for same or similar part, same or similar label is used to represent.But accompanying drawing is schematic, and the ratio of size relationship etc. are different from reality.Therefore, concrete size etc. should judge with reference to following explanation.In addition, certain accompanying drawing also comprises size relationship each other or the different part of ratio each other.
In addition, execution mode shown below is the example for making the technological thought of this utility model specialize, and the material of component parts, shape, structure, configuration etc. are not defined as following content by the execution mode of this utility model.The execution mode of this utility model can implement various change in the scope not departing from purport.
Below, be described with reference to the semiconductor device 100 of accompanying drawing to embodiment of the present utility model.Fig. 1 be the semiconductor device 100 of embodiment of the present utility model analyse and observe concept map.In addition, Fig. 2 is the three-dimensional concept map near the conductive component 3 of embodiment of the present utility model.
Semiconductor device 100 shown in Fig. 1 comprises semiconductor element 1, lead frame 2, conductive component 3, substrate 4, heating panel 5, housing 6 and seal 7.
Semiconductor element 1 is loaded by binding material and is fixed on lead frame 2.Semiconductor element 1 is such as the power semiconductor element be made up of compound semiconductors such as SiC semiconductor or GaN semiconductors.Compared with Si semiconductor, can carry out work at high operating temperatures, in addition, switching speed is very fast, and loss is low.
Lead frame 2 is placed with semiconductor element 1 on interarea, and is fixed by adhesives.In embodiment of the present utility model, lead frame 2 is such as implement Punching Technology or chemical etching processing to the flat-shaped sheet material that 1.0mm is thick and formed, material many uses copper or copper alloy, and surface can be implemented silver-plated etc.
As shown in Figure 2, conductive component 3 has: a pair connecting portion of tabular; A pair bridge pier portion of tabular, one end of itself and connecting portion is connected, and is formed as erecting upward from connecting portion; And the bridge plate portion of tabular, it links the upper end in a pair bridge pier portion.
Semiconductor element 1 and lead frame 2 are electrically connected by solder (not shown) by connecting portion.
Conductive component 3 metal material that preferably conductivity is higher, can be made up of aluminum or copper product or gold copper-base alloy.The sectional area of conductive component can be identical with the sectional area of required aluminum steel.In embodiment of the present utility model, sectional area is equivalent to the aluminum steel that 6 diameters are 500 μm.
Substrate 4 has: the conductor layer (wiring) of aluminium base, the insulating barrier (not shown) formed at the upper surface of aluminium base and the upper surface that is formed in aluminium base across insulating barrier, conductor layer is fixed wtih semiconductor element by conductivity adhesives on an interarea.In addition, at the lower surface of substrate 4, by the bonding agent configuration heating panel 5 that heat conductivity is higher.
Heating panel 5 for base material, and implements plating with copper or copper alloy.Heating panel 5 is configured at the lower surface of substrate 4, and an interarea of heating panel 5 is exposed to the outer surface of semiconductor device 100.Thus, improve the thermal diffusivity of substrate 4.
Housing 6 is configured at an interarea of substrate 4, during top view, arranges in the mode of surrounding semiconductor element.In the present embodiment, the outer peripheral edges of housing 6 along substrate 4 are configured, the outer wall of housing 6 is positioned on the extended line of the side of substrate 4.Therefore, housing 6 plays a role as a part for the encapsulation (outer containment body) of protection semiconductor element, and plays a role as the utensil being injected into sealing resin.
Housing 6 is such as preferably the good and polyphenylene sulfide (PPS) that fusing point is higher (280 DEG C) of processability.
Seal 7 is formed in the region surrounded by housing 6 on the upper surface of substrate 4.The resin that the physical property that seal 7 causes by being heated changes little excellent heat resistance is formed.Such as, silicon resinoid is used.
Thus, semiconductor device 100 is completed.
Then, the effect of the semiconductor device 100 of above-described embodiment is described.
According to first method, the semiconductor device of embodiment of the present utility model has following structure: conductive component has: a pair connecting portion of tabular; A pair bridge pier portion of tabular, one end of itself and connecting portion is connected, and is formed as erecting upward from connecting portion; And the bridge plate portion of tabular, it links the upper end in a pair bridge pier portion.Therefore, compared with the wire-bonded employing metal wire, the thermal capacitance of conductive component can be increased, and can area of dissipation be expanded.Thereby, it is possible to improve thermal diffusivity when having big current to flow through.
In addition, when the electrical connection of conductive component, can solder be used, side by side can engage with welding of chip.Further, do not need the wire-bonded operation etc. of carrying out repeatedly, can manufacturing man-hours be reduced.
As above describe for implementing mode of the present utility model, but those skilled in the art can realize multiple alternative execution mode and embodiment according to above-mentioned disclosed content obviously.
Housing 6 is with PPS material for main material, and preferably can keep the material of insulating properties than metal light, also can be vinyl chloride resin, ABS resin etc.
Although substrate 4 is set to aluminium base, DBC substrate also can be used as heat transmission insulated substrate, this DBC substrate is the substrate formed after utilizing DirectCopperBond method to engage copper circuit in AlN substrate or aluminium oxide ceramic substrate.
As variation, as shown in Figure 3, semiconductor device 100 also can be provided with lid 8 at the upper surface of housing 6.Thereby, it is possible to obtain further good close fitting, thus realize the semiconductor device of excellent moisture resistance.
Claims (1)
1. a semiconductor device, it has:
Semiconductor element;
Lead frame;
By the conductive component that described semiconductor element and described lead frame are electrically connected; And
With the housing that the mode of surrounding described semiconductor element configures,
Sealed by seal by the region that described housing surrounds,
The feature of this semiconductor device is,
Described conductive component has:
A pair connecting portion of tabular;
A pair bridge pier portion of tabular, one end of itself and described connecting portion is connected, and is formed as erecting upward from connecting portion; And
The bridge plate portion of tabular, it links the upper end in described a pair bridge pier portion.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015168422A JP2017045905A (en) | 2015-08-28 | 2015-08-28 | Semiconductor device |
| JP2015-168422 | 2015-08-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205104480U true CN205104480U (en) | 2016-03-23 |
Family
ID=55520240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520920357.1U Expired - Fee Related CN205104480U (en) | 2015-08-28 | 2015-11-18 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2017045905A (en) |
| CN (1) | CN205104480U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6924716B2 (en) * | 2018-03-19 | 2021-08-25 | 京セラ株式会社 | Power semiconductor module |
-
2015
- 2015-08-28 JP JP2015168422A patent/JP2017045905A/en active Pending
- 2015-11-18 CN CN201520920357.1U patent/CN205104480U/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017045905A (en) | 2017-03-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10559538B2 (en) | Power module | |
| CN105981274B (en) | Semiconductor module for electric power | |
| CN100444371C (en) | Power semiconductor package | |
| CN103403862B (en) | Power semiconductor modular and the method being used for manufacturing the power semiconductor modular sintered together with temperature sensor | |
| TWI608589B (en) | Semiconductor device and alternator using the same | |
| CN104078428B (en) | Power semiconductor modular and the method for manufacturing power semiconductor modular | |
| CN109075148B (en) | Semiconductor package body, the module and electrical equipment for being equipped with semiconductor package body | |
| CN106104779A (en) | Power semiconductor apparatus | |
| CN105914185A (en) | Packaging structure and packaging method for silicon carbide power device | |
| CN206116387U (en) | Big current power semiconductor device's packaging structure | |
| KR20130051498A (en) | Semiconductor module and method of manufacturing a semiconductor module | |
| CN109599384A (en) | Semiconductor devices | |
| CN108735721A (en) | Semiconductor device | |
| EP2571053A1 (en) | Power semiconductor arrangement and method of forming thereof | |
| US20170084521A1 (en) | Semiconductor package structure | |
| CN205104483U (en) | Semiconductor device | |
| JP5233853B2 (en) | Semiconductor device | |
| JP2017034152A (en) | Power semiconductor device | |
| CN205104480U (en) | Semiconductor device | |
| CN207474454U (en) | Semiconductor device | |
| JP2015115471A (en) | Power semiconductor device | |
| CN206961827U (en) | Semiconductor packages and the intermediate plate for semiconductor packages | |
| CN207800600U (en) | Conductive frame and power semiconductor cascaded structure | |
| CN203339143U (en) | Semiconductor device | |
| CN218849464U (en) | Diode packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160323 Termination date: 20181118 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |