JP2017041495A - Semiconductor inspection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor inspection circuit designed such that a voltage application test and a characteristic inspection are simultaneously performed with the same number of needles for a probe card as that for the characteristic inspection, thereby reducing time for the voltage application test by the time for the characteristic inspection of the entire wafer surface.SOLUTION: A plurality of semiconductor chips 2 are formed on a wafer 1. A power source line 4 and a grind line 5 are arranged in a scribe area, and a power source pad 6, a grind pad 7, analog switches 8, 9, first and second switch pads 10, 12 and the like are arranged for each semiconductor chip 2. A gate is connected to the analog switches 8, 9 such that it is always on. A burn-in voltage is supplied to each semiconductor chip 2 from the power source line 4 and the grind line 5. When an off signal is applied to the switch pads 10, 12, the analog switches 8, 9 turn off. Testing is conducted in such a manner that the voltage of a semiconductor chip 2 to be a target is stopped by a probe and a characteristic inspection is made and a burn-in voltage is continuously applied to each of other semiconductor chips 2.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor inspection circuit.

  There is a process of performing a voltage application test such as a wafer burn-in test in a state where a large number of semiconductor chips are formed on a semiconductor wafer, and further performing a characteristic inspection of each semiconductor chip. Normally, in this process, the characteristic inspection is sequentially performed after the wafer burn-in test is performed. Therefore, in addition to the wafer burn-in process and the characteristic inspection process being separated, the probe is brought into contact with the entire surface of the wafer in the wafer burn-in test and characteristic inspection. Therefore, there are problems that an apparatus having a large number of probes is expensive and that it is difficult to contact the probes to the entire wafer surface.

  For this reason, there is a method in which probes are set up on two semiconductor chips as a method of not setting up probes on the entire wafer surface. In this method, a characteristic inspection is performed on one semiconductor chip, and a wafer burn-in test is performed on the other semiconductor chip to be inspected later. However, in this method, it is possible to simultaneously perform the characteristic inspection process and the wafer burn-in test on two semiconductor chips, but the time of the wafer burn-in test is equal to the period during which the characteristic inspection process is performed. Because it is the same, it takes a short time.

  On the other hand, a method has been considered in which the wafer burn-in test or characteristic adjustment can be performed simultaneously on the entire wafer surface by uniformly taking out the power supply and signal terminals. The characteristics are individually adjusted, and after the wafer burn-in test, the inspection process is separately performed by probing with the wafer taken out.

  For this reason, when the probe is brought into contact with the entire surface of the wafer, there is a problem that the manufacturing cost for the configuration for probing is increased, and the adjustment and specifications for contacting the probe are severe. In the characteristic adjustment, the same high voltage as in the wafer burn-in test is applied, and therefore the characteristic adjustment condition is different from the normal usage pattern. Furthermore, the wafer burn-in test has a problem that a long application time is required with all the probes in contact with each other.

JP 2011-29512 A Japanese Patent Application Laid-Open No. 2002-71501

  The present invention has been made in consideration of the above circumstances, and its purpose is to perform the characteristic inspection on individual semiconductor chips with the same number of probes as the characteristic inspection, and to all the semiconductor chips. It is an object of the present invention to provide a semiconductor inspection circuit capable of performing a voltage application test at the same time and performing a characteristic inspection on the entire surface of the wafer while the voltage application test is being performed.

  According to a first aspect of the present invention, there is provided a semiconductor inspection circuit for inspecting a circuit of a plurality of semiconductor chips provided on a wafer, and a first inspection power supply for supplying inspection power provided in common to the plurality of semiconductor chips. A first power supply pad and a second power supply line provided corresponding to each of the plurality of semiconductor chips and a first power supply pad for supplying the inspection power to each of the first power supply line and the second power supply line Two power supply pads and a first switch that is always on from the first power supply line to the first power supply terminal of each circuit of the plurality of semiconductor chips, and the plurality of power supplies from the second power supply line. A second switch that is provided between the second power supply terminal of each circuit of the semiconductor chip and is always on, and an off-motion that is provided corresponding to each of the first switch and the second switch. The first voltage application for which and a switch pad and a second switch pad.

  By adopting the above configuration, when inspecting a plurality of semiconductor chips provided on a wafer, an inspection device such as a probe uses a first power pad and a second power pad corresponding to one semiconductor chip. A test power supply is applied between them, and a voltage is applied to the first switch pad and the second switch pad to turn off the first switch and the second switch. As a result, since inspection power is supplied between the first power supply line and the second power supply line, the remaining power from the first power supply pad and the second power supply pad to each of the remaining semiconductor chips excluding the semiconductor chip to be inspected. Inspection power is applied via the first switch and the second switch. Thus, a voltage application test can be performed by applying the inspection power supply.

  Further, in the semiconductor chip to be inspected, the inspection switch is not supplied because the first switch and the second switch are turned off. This makes it possible to independently perform necessary characteristic inspections on the inspection pads of the target semiconductor chip using other probes or the like. Hereinafter, by sequentially moving the inspection means corresponding to the other semiconductor chips provided on the wafer, it is possible to individually perform the characteristic inspection of a plurality of semiconductor chips, and for all other semiconductor chips Can continue the voltage application test.

  As a result, by using an inspection apparatus having a number of probes for performing characteristic inspection of one semiconductor chip, individual semiconductors can be tested while performing voltage application tests on a plurality of semiconductor chips formed on the entire wafer. Chip characteristic inspection can be performed. Further, by performing the characteristic inspection in a high temperature atmosphere, a wafer burn-in test that accelerates the voltage application test can be performed.

Schematic plan view of the semiconductor chip and its periphery showing the first embodiment Schematic plan view of the entire wafer Time chart showing the voltage of each part during inspection Schematic plan view of the semiconductor chip and its periphery showing the second embodiment Schematic plan view of the semiconductor chip and its periphery showing the third embodiment Schematic plan view of the semiconductor chip and its periphery showing the fourth embodiment The structure of the part which comprises a capacitor is shown, (a) The top view of a 1st example, (b) The typical sectional view of a 1st example, (c) The top view of a 2nd example, (d) 2nd Schematic cross section of example Time chart showing the voltage of each part during inspection Schematic plan view of the semiconductor chip and its periphery showing the fifth embodiment (A) Top view and (b) Schematic cross-sectional view showing the configuration of the part constituting the capacitor Schematic plan view of the semiconductor chip and its periphery showing the sixth embodiment

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In FIG. 2 showing a plan view of the entire wafer, a wafer 1 using a silicon substrate or the like has a disk shape, for example, and is generally handled in this state in the manufacturing process of semiconductor chips. The wafer 1 is formed with a plurality of semiconductor chips 2 in which semiconductor elements and wiring patterns are formed through various semiconductor manufacturing processes.

  The semiconductor chip 2 is formed as an independent semiconductor device by being separated individually in a subsequent process, and is enclosed in a resin package or the like. In FIG. 2, a plurality of semiconductor chips 2 are shown in a state where adjacent ones are arranged with a wide gap, but actually, they are adjacent to each other with a narrow gap scribe region and arranged in a matrix. Has been.

  In a scribe region around the semiconductor chip 2 of the wafer 1, a semiconductor inspection circuit 3 for performing a characteristic inspection of each semiconductor chip 2 and a voltage application test in the wafer state is provided. The semiconductor inspection circuit 3 is provided with a power supply line 4 as a first power supply line for wafer burn-in and a ground line 5 as a second power supply line arranged along all the side portions of the plurality of semiconductor chips 2. It has been. Each semiconductor chip 2 is provided with inspection pads, switches, and the like used for performing a wafer burn-in test, which is a voltage application test described later, in a scribe region on the outer periphery thereof to constitute an inspection circuit.

  FIG. 1 shows a configuration of an inspection circuit provided for each semiconductor chip 2. In FIG. 1, a power supply line 4 and a ground line 5 are arranged in the upper and lower scribe regions with the semiconductor chip 2 interposed therebetween. On the power line 4, a power pad 6 as a first power pad is formed at each position corresponding to each semiconductor chip 2. In the ground line 5, a ground pad 7 as a second power supply pad is formed for each position corresponding to each semiconductor chip 2.

  Each semiconductor chip 2 is provided with a plurality of test pads such as test pads 2a, 2b, and 2c for contacting a test probe. The inspection pads 2a and 2b are first and second power supply terminals, and are provided as pads for supplying a burn-in voltage Vbi or an inspection signal as an inspection power source. A first analog switch 8 as a first switch is connected between the power supply line 4 and the inspection pad 2a of the semiconductor chip 2 by a wiring pattern. A second analog switch 9 as a second switch is connected between the ground line 5 and the test pad 2b of the semiconductor chip 2 by a wiring pattern.

  The positive gate terminals which are the first gates of the first and second analog switches 8 and 9 are both connected to the power supply line 4 by a wiring pattern via the first switch pad 10 and the first resistor 11 in series. Further, the negative gate terminals which are the second gates of the first and second analog switches 8 and 9 are both connected to the ground line 5 by the wiring pattern via the second switch pad 12 and the second resistor 13 in series. Yes.

  In each of the first analog switch 8 and the second analog switch 9, the positive gate terminal is connected to the power supply line 4, and the negative gate terminal is connected to the ground line 5. Therefore, both the first and second analog switches 8 and 9 are always in an on state when a positive voltage is applied to the power supply line 4 and the ground line 5 is set to the ground. As a result, when the voltage for off operation is not applied to the first switch pad 10 and the second switch pad 12, the voltage of the power supply line 4 is applied to the test pad 2a of the semiconductor chip 2, and the test pad 2b is applied. The voltage of the ground line 5 is applied.

  The power supply pad 6, the ground pad 7, the first switch pad 10, the second switch pad 12, the test pad 2a, the test pad 2b, and the test pad 2c have the same positional relationship with respect to the semiconductor chip 2. It is arranged to be. Therefore, the semiconductor chips 2 are arranged so as to be repeatedly provided.

  When inspecting each semiconductor chip 2, for example, seven wafer inspection probes A to G are brought into electrical contact with the corresponding pads. In this case, the probe A is in contact with the first switch pad 10, the probe B is in the second switch pad 12, the probe C is in contact with the power supply pad 6, the probe D is in contact with the ground pad 7, and the probe E is in the inspection pad 2 a of the semiconductor chip 2. F is in electrical contact with the inspection pad 2b of the semiconductor chip 2, and the probe G is in electrical contact with the inspection pad 2c of the semiconductor chip 2.

  The probes C and D are for applying a burn-in voltage between the power supply line 4 and the ground line 5. The probes A and B are for applying an off voltage for cutting the burn-in voltage to the target semiconductor chip 2. The probes E to G are for carrying out an inspection of the target semiconductor chip 2.

  The plurality of semiconductor chips 2 formed on the wafer 1 having the above-described configuration are subjected to a wafer burn-in test and a characteristic inspection process, which will be described later, after completion of the fabrication in the wafer state, and then scribed in the scribe area in the semiconductor manufacturing process. To be separated. Therefore, elements or wiring patterns formed in the scribe region as the inspection circuit 3 are cut or lost, and their functions are invalidated.

  Next, a case where the above-described probes A to G are brought into contact with the wafer 1 having the above-described configuration to perform a wafer burn-in test and a characteristic inspection as a voltage application test will be described with reference to FIG.

  The inspection apparatus is configured to perform a wafer burn-in test. When the wafer 1 is mounted on the wafer stage, the wafer stage is controlled to be heated to a predetermined temperature. Alternatively, the atmosphere of the wafer stage is set to a high temperature atmosphere. In this state, a wafer burn-in test is performed by applying a burn-in voltage to the remaining plurality of semiconductor chips 2 while inspecting the target semiconductor chip 2 in the wafer 1.

  First, at time t1, the probes A to G are lowered (UP → DOWN), and as described above, the probes A to G are moved to the first switch pad 10, the second switch pad 12, the power supply pad 6, the ground pad 7, The test pad 2a, the test pad 2b, and the test pad 2c are brought into contact with each other. Thereby, the burn-in voltage Vbi given by the probes C and D is applied between the power supply line 4 and the ground line 5, and the first period (t1 to t6) is started.

  The power supply line 4 and the ground line 5 are provided so as to be connected to the plurality of semiconductor chips 2 in common. At this time, in each semiconductor chip 2 to which the probes A and B are not in contact, the analog switches 8 and 9 are held in the ON state by the voltage applied to the positive and negative gate terminals. A burn-in voltage Vbi is applied between the test pads 2a and 2b of the semiconductor chip 2.

  On the other hand, in the semiconductor chip 2 to be contacted with the probes A to G, the burn-in voltage Vbi is applied to the probe A and the ground voltage is applied to the probe B when all the probes are contacted at time t1. Thereafter, at time t2, the probe A is set to the ground potential, and the probe B is set to the burn-in voltage Vbi. As a result, the analog switches 8 and 9 are both turned off, and the test pads 2a and 2b that are in contact with the probes E and G are in a state where no voltage is applied, and the second period (t2 to t5) starts.

  In this state, only the semiconductor chip 2 in contact with the probes A to G is in a state where the burn-in voltage Vbi is not applied between the inspection pads 2a and 2b, that is, in a state where the characteristic inspection can be performed independently, and the other remaining semiconductors The chip 2 is in a state where the burn-in voltage Vbi is applied between the inspection pads 2a and 2b, and the wafer burn-in test is performed.

  At time t3, the third period (t3 to t4) is reached, and the characteristic inspection of the semiconductor chip 2 is performed by the probes E to G. Inspection signals are appropriately given from the probes E to G to the inspection pads 2a to 2c of the semiconductor chip 2, and response signals appearing on the inspection pads 2a to 2c at that time are detected by the probes E to G, etc. I do. Here, the case where the characteristic inspection is performed with the three probes E to G is shown. However, depending on the number of inspection pads of the semiconductor chip 2, the characteristic inspection is performed by bringing two or more probes into contact with each other. It can also be done.

  When the characteristic inspection is completed at time t4 (end of the third period), the voltage of probe A is switched from ground level to burn-in voltage Vbi at time t5, and the voltage of probe B is switched from burn-in voltage Vbi to ground level. Set. As a result, the analog switches 8 and 9 return to the conductive state after the off period ends (second period ends). Subsequently, at time t6, the probes A to G are raised to release the contact state with each pad (DOWN → UP). As a result, the burn-in voltage Vbi between the power supply line 5 and the ground line 6 disappears, and all the semiconductor chips 2 on the wafer 1 are in a state in which the burn-in voltage Vbi is released (end of the first period).

  Subsequently, in a state where the probes A to G are raised, the probes A to G are moved to corresponding positions of the pads of the adjacent semiconductor chip 2. Alternatively, the wafer stage is moved. When the movement is completed (time t7), the above-described operation from the first period is repeated.

  Thereafter, the above operation is repeated until all the semiconductor chips 2 on the wafer 1 or the semiconductor chips 2 to be inspected are similarly completed. As a result, the semiconductor chips 2 other than the semiconductor chip 2 that performs the characteristic inspection by contacting the probes A to G are in a state in which the burn-in voltage Vbi is applied during the period in which the probes A to G are lowered. Although intermittent, it is possible to perform the characteristic inspection of the semiconductor chip 2 while performing the wafer burn-in test.

  As described above, in the above embodiment, the inspection circuit 3 is provided on the wafer 1, the power supply line 4 and the ground line 5 are provided with the power supply pad 6 and the ground pad 7 corresponding to the respective semiconductor chips 2, and the first analog switch is provided. 8. The second analog switch 9 is provided so that the burn-in voltage Vbi is not applied only to the target semiconductor chip 2. In this state, the characteristic inspection of the semiconductor chip 2 is performed by the probes E to G. As a result, a wafer burn-in test can be simultaneously performed on all the other semiconductor chips 2 while using a configuration using a small number of probes for performing the characteristic inspection on one semiconductor chip 2.

  In the above embodiment, the wafer burn-in test is performed by applying a voltage by setting the wafer 1 in a high temperature atmosphere. However, it may be used as a voltage application test for applying a voltage in a normal temperature state. it can.

(Second Embodiment)
FIG. 4 shows the second embodiment. Hereinafter, parts different from the first embodiment will be described. In this embodiment, instead of the semiconductor chip 2 shown in the first embodiment, a plurality of semiconductor chips 20 are provided on the wafer 1. The components of the inspection circuit 3 are the same. The semiconductor chip 20 has a configuration in which the first analog switch 8, the second analog switch 9, the first switch pad 10, and the second switch pad 12 are also integrally provided.
Accordingly, even with such a configuration, it is possible to obtain the same operational effects as those of the first embodiment.

(Third embodiment)
FIG. 5 shows a third embodiment, and the following description will be focused on differences from the first embodiment. In this embodiment, instead of the semiconductor chip 2 shown in the first embodiment, a plurality of semiconductor chips 21 are provided on the wafer 1. The components of the inspection circuit 3 are the same. The semiconductor chip 21 includes a first resistor 11 and a second resistor 13 in addition to the first analog switch 8, the second analog switch 9, the first switch pad 10, and the second switch pad 12.
Accordingly, even with such a configuration, it is possible to obtain the same operational effects as those of the first embodiment.

(Fourth embodiment)
FIGS. 6-8 shows 4th Embodiment, and demonstrates a different part from 1st Embodiment below. In this embodiment, the power supply line 4 and the ground line 5 are arranged close to each other. For this reason, the power supply line 4 and the ground line 5 that are arranged separately above and below the semiconductor chip 2 are arranged side by side above the semiconductor chip 2 as shown in FIG. By making the power supply line 4 and the ground line 5 close to each other, the fact that the capacitance distributed between the wirings is increased is utilized. In this embodiment, the capacitance distributed between the wirings is shown as an inter-wiring capacitance Cx formed equivalently between the power supply line 4 and the ground line 5 corresponding to each semiconductor chip 2.

  By arranging the power supply line 4 and the ground line 5 as described above, when the burn-in voltage Vbi is applied between the power supply pad 6 and the ground pad 7 by the probes C and D, the burn-in voltage Vbi is applied. In this state, the inter-wiring capacitor Cx is charged. As a result, when the first period ends and the probes C and D move away from the power supply pad 6 and the ground pad 7, the potential of the power supply line 4 is held by the charge of the inter-wiring capacitance Cx, and the charge is discharged. It will gradually decline.

  FIG. 7 shows a specific configuration of the wafer 1 with respect to the electrical configuration as described above. FIG. 7 shows two examples. A first example is shown in FIGS. 7A and 7B, and a second example is shown in FIGS. 7C and 7D. 7A and 7C schematically show top views of portions where the power supply lines 4 and the ground lines 5 are arranged in the scribe region of the wafer 1. FIGS. 7B and 7D schematically show vertical sections of portions indicated by broken lines XX in FIGS. 7A and 7C, respectively.

  7A to 7D, the wafer 1 has a configuration in which a semiconductor layer 33 is provided on a semiconductor substrate 31 such as a silicon substrate via an insulating film 32, and is a so-called SOI (silicon on insulator). It is called an insulating substrate. For example, three layers of interlayer insulating films 34 to 36 are stacked on the upper surface of the semiconductor layer 33. These are for functioning as an insulating film and for forming interlayer wiring.

  For example, in the first example shown in FIGS. 7A and 7B, the power supply line 4 and the ground line 5 are arranged close to each other by patterning a conductor on the interlayer insulating film 36. As a result, an interwiring capacitance Cx is formed between the two. Further, in the second example shown in FIGS. 7C and 7D, the ground line 5 obtained by patterning the conductor is formed in the interlayer insulating film 35, and the conductor is patterned at the same position in the interlayer insulating film 36 on the upper part. The power supply line 4 is formed. As a result, an interwiring capacitance Cx is formed between the two.

  Next, the operation of the above configuration will be described with reference to FIG. The process is the same as in the first embodiment until the first characteristic inspection is performed. In the first period of the characteristic inspection, the inter-wiring capacitance Cx between the power supply line 4 and the ground line 5 is charged by charging. As a result, during the time when the probe is moved to another semiconductor chip 2 from the time t6 when the first period ends (period from t6 to t7), the voltage of the inter-wiring capacitance Cx decreases due to the discharge of the charge, The voltage of the power supply line 4 does not immediately decrease to the ground level but gradually decreases (see FIG. 8F).

  At time t7, the probes A to G are lowered again, so that the burn-in voltage Vbi is applied to the power supply pad 6 and the ground pad 7. Therefore, the voltage of the power supply line 4 is changed from a slightly lowered state to the burn-in voltage Vbi. Return. As a result, the other semiconductor chips 2 except the target semiconductor chip 2 with which the probes A to G are in contact are in a state in which the burn-in voltage Vbi or a voltage in the vicinity thereof is continuously applied between the test pads 2a and 2b. Can be held.

  According to the fourth embodiment, in addition to the operational effects of the first embodiment, the burn-in voltage Vbi is continuously reduced by reducing the voltage drop for the plurality of semiconductor chips 2 to be subjected to the wafer burn-in test. The characteristic inspection of the target semiconductor chip 2 can be performed while applying.

(Fifth embodiment)
FIG. 9 and FIG. 10 show the fifth embodiment, and the following description will be focused on differences from the fourth embodiment. In this embodiment, the structural capacity of the wafer 1 is used as a configuration for holding the voltage of the power supply line 4.

  As shown in FIG. 10, the power supply line 4 and the ground line 5 are arranged in a separated state by patterning a conductor on the interlayer insulating film 36. As shown in FIG. 10B, in the scribe region where the semiconductor chip 2 is not formed, the power supply line 4 is connected to the semiconductor layer 33 at a position close to each semiconductor chip 2, for example. , 34 is provided through the plug 4a.

As a result, the semiconductor layer 33 in the scribe region has the same voltage as that of the power supply line 4, so that a substrate capacitance Cy as a capacitive element is formed between the semiconductor substrate 31 connected to the ground (SUB) with the insulating film 32 interposed therebetween. Is done. As shown in FIG. 9, the substrate capacitance Cy formed between the semiconductor substrate 31 and the substrate line SUB can be shown as equivalently connected to the substrate line SUB.
Therefore, the fifth embodiment can provide the same effects as those of the fourth embodiment.

(Sixth embodiment)
FIG. 11 shows the sixth embodiment. Hereinafter, parts different from the first embodiment will be described. In this embodiment, the second analog switch 9 provided in the first embodiment is omitted. That is, as shown in FIG. 11, the test pad 2b of each semiconductor chip 2 is directly connected from the ground line 5 by wiring. Therefore, in this embodiment, all the semiconductor chips 2 are in a state where the test pads 2b are connected to the ground line and are held at the ground potential.

  In the above configuration, the semiconductor chip 2 in contact with the probe can be subjected to the characteristic inspection by the probes E to G in a state where the burn-in voltage Vbi is not applied. Thereby, the configuration of the inspection circuit can be reduced and the occupied area can be reduced. In this case, since the potential of the test pad 2b is fixed to the ground, there is a limitation in the characteristic test. For example, there is a restriction that the test pad 2b cannot be floated or set to another potential. In other words, when performing a characteristic inspection that does not include such inspection items, the occupied area can be saved.

(Other embodiments)
In addition, this invention is not limited only to one embodiment mentioned above, It can apply to various embodiment in the range which does not deviate from the summary, For example, it can deform | transform or expand as follows. .

  The first and second analog switches 8 and 9 are used as the first and second switches. However, the first and second analog switches 8 and 9 can always be kept on and can be switched to the off state by applying an off signal to the switch pad. It ’s fine. For example, by using a depletion type MOSFET or the like, it can be always turned on and can be turned off by applying an off signal to the gate.

  The first power supply line and the second power supply line are shown as the power supply line 4 and the ground line 5, but the potentials of the first power supply line and the second power supply line can be used as long as the inspection voltage is applied between them. Can be positive or negative or zero.

  Each semiconductor chip 2 is provided with three test pads 2a to 2c for characteristic inspection, but a semiconductor chip having two or more test pads may be used. This case can be dealt with by providing corresponding probes in accordance with the number of inspection pads.

  In the fourth to sixth embodiments, the example using the semiconductor chip 2 of the first embodiment is shown. However, the semiconductor chip 20 shown in the second embodiment or the semiconductor chip 21 shown in the third embodiment is used. You can also.

  In addition to the inter-wiring capacitance Cx and the substrate capacitance Cy as in the fourth and fifth embodiments, a capacitance is provided between the power supply line 4 and the ground line 5 using the wiring pattern or the structure of the wafer 1. The same effect can be obtained if the configuration can be achieved.

  In the drawings, 1 is a wafer, 2, 20 and 21 are semiconductor chips, 2a is a test pad (first power supply terminal), 2b is a test pad (second power supply terminal), 2c is a test pad, 3 is a test circuit, and 4 is a test circuit. Power line (first power line), 5 is a ground line (second power line), 6 is a power pad (first power pad), 7 is a ground pad (second power pad), and 8 is a first analog switch (second power line). 1 switch), 9 is a second analog switch (second switch), 10 is a first switch pad, 11 is a first resistor, 12 is a second switch pad, 13 is a second resistor, AG are probes, and Cx is Inter-wiring capacitance (capacitance element), Cy is a substrate capacitance (capacitance element).

Claims (7)

Inspecting a circuit of a plurality of semiconductor chips (2, 20, 21) provided on the wafer (1),
A first power supply line (4) and a second power supply line (5) for supplying inspection power provided in common to the plurality of semiconductor chips;
A first power supply pad (6) and a second power supply pad (7) provided corresponding to each of the plurality of semiconductor chips and for supplying the inspection power to each of the first power supply line and the second power supply line. When,
A first switch (8) that is provided between the first power supply line and the first power supply terminal (2a) of each circuit of the plurality of semiconductor chips, and is always on;
A second switch (9) that is provided between the second power supply line and the second power supply terminal (2b) of each circuit of the plurality of semiconductor chips, and is always on;
And a first switch pad (10) for voltage application and a second switch pad (12) for performing an off operation provided corresponding to each of the first switch and the second switch. Semiconductor inspection circuit. The semiconductor inspection circuit according to claim 1,
The first switch includes a first analog switch (8) provided between the first power supply line and the first power supply terminal (2a) of the semiconductor chip,
The second switch comprises a second analog switch (9) provided between the second power supply line and the second power supply terminal (2b) of the semiconductor chip,
The first and second analog switches have a first gate connected to the first power supply line via a first resistor (11), and a second gate connected to the second power supply via a second resistor (13). A semiconductor inspection circuit characterized by being connected to a wire. In the semiconductor inspection circuit according to claim 1 or 2,
The semiconductor inspection circuit, wherein each of the plurality of semiconductor chips (20) includes the first switch, the second switch, the first switch pad, and the second switch pad. The semiconductor inspection circuit according to claim 2,
Each of the plurality of semiconductor chips (21) includes the first analog switch, the second analog switch, the first switch pad and the second switch pad, the first resistor, and the second resistor. A characteristic semiconductor inspection circuit. In the semiconductor inspection circuit according to any one of claims 1 to 4,
A semiconductor inspection circuit, wherein capacitive elements (Cx, Cy) are provided between the first power supply line (4) and the second power supply line (5). The semiconductor inspection circuit according to claim 5,
The semiconductor inspection circuit, wherein the capacitive element is an inter-wiring capacitance (Cx) generated by arranging the first power supply line and the second power supply line close to each other. The semiconductor inspection circuit according to claim 5,
The wafer (1) is formed of an insulating substrate in which a supporting substrate (31) and a semiconductor layer (33) are separated by an insulating film (32),
The semiconductor inspection circuit, wherein the capacitive element (Cy) is a capacitive element composed of the support substrate and a semiconductor layer.

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