CN112147487A - Analog quantity test pad arrangement structure for parallel test of wafer chip - Google Patents
Analog quantity test pad arrangement structure for parallel test of wafer chip Download PDFInfo
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- CN112147487A CN112147487A CN202011021160.6A CN202011021160A CN112147487A CN 112147487 A CN112147487 A CN 112147487A CN 202011021160 A CN202011021160 A CN 202011021160A CN 112147487 A CN112147487 A CN 112147487A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
Abstract
The application relates to the field of wafer testing, in particular to a simulation quantity testing pad arrangement structure for parallel testing of wafer chips. The wafer comprises a plurality of chips distributed in an array form, and scribing grooves are formed between adjacent chips; a longitudinal scribing groove is formed between two adjacent rows of chips, and a transverse scribing groove is formed between two adjacent rows of chips; and the scribing grooves positioned around the chips are provided with analog quantity testing bonding pads which are electrically coupled with the corresponding chips. This application is through locating the simulation volume test pad and corresponding the chip around the scribing groove, when saving the pad and taking up chip area, through guaranteeing when carrying out wafer test the simulation volume test pad with correspond chip electrical coupling, can guarantee promptly that the process of parallel test is gone on at wafer chip simulation parameter.
Description
Technical Field
The application relates to the field of wafer testing, in particular to a simulation quantity testing pad arrangement structure for parallel testing of wafer chips.
Background
Before the wafer leaves the factory, the chip on the wafer needs to be tested to judge the performance of the chip. In wafer chip testing, a target wafer is mounted on a testing machine, a testing pad (pad) of the target wafer is electrically coupled to the testing machine through a probe card, and the testing machine executes a testing instruction to complete a testing process for the target wafer. After testing one chip, the probe card is electrically coupled with the test pad of the next target chip to continue the test.
In order to improve the testing efficiency and reduce the testing cost, when a wafer chip is tested, the chip on the wafer is usually required to be tested in parallel, that is, a plurality of target chips of a target wafer are tested at the same time, or a plurality of testing tasks are synchronously or asynchronously operated on a single target chip, so as to simultaneously complete the testing of a plurality of parameters of the target chip.
When parallel testing of wafer chips is performed, it is usually necessary to measure a specific test pad to obtain an analog electrical parameter value of a target chip and adjust the analog electrical parameter of the target chip. With the increasing integration of chips on wafers, the number of types of electrical parameters to be adjusted in a target chip increases, and thus the number of required specific test pads also increases.
However, in the related art, the test pads for obtaining the analog electrical parameter values of the target chip cannot be reused with the functional pads on the target chip, and need to be manufactured separately, so that too many test pads occupy a larger area of the chip, and adversely affect the performance of the chip.
Disclosure of Invention
The application provides a simulation test pad arrangement structure for parallel test of wafer chips, which can solve the problem that a test pad for acquiring a simulation electrical parameter value of a target chip in the related art can occupy a larger area of the chip.
The application provides a simulated quantity test pad arrangement structure for parallel test of wafer chips, wherein the wafer comprises a plurality of chips which are distributed in an array manner, and scribing grooves are formed between adjacent chips; a longitudinal scribing groove is formed between two adjacent rows of chips, and a transverse scribing groove is formed between two adjacent rows of chips;
and the scribing grooves positioned around the chips are provided with analog quantity testing bonding pads which are electrically coupled with the corresponding chips.
Optionally, the wafer chip is subjected to parallel testing through a probe card, and an analog signal transmission probe capable of being in corresponding contact with the analog quantity testing pad is arranged on the probe card;
through the analog signal transmission probe, the probe card can send an analog quantity test instruction to the corresponding analog quantity test bonding pad and can acquire an analog parameter signal fed back by the analog quantity test bonding pad.
Optionally, the chip has reserved bits for analog quantity testing pads; (ii) a
The analog quantity test bonding pad is arranged in a scribing groove closest to the reserved position of the analog quantity test bonding pad along the needle outlet direction of the analog signal transmission probe.
Optionally, the analog quantity test pads are multiple, and the reserved positions of the analog quantity test pads on the chip correspond to the analog quantity test pads one to one.
Optionally, when the analog signal transmission probe contacts the analog quantity test pad in the scribe line, the extending direction of the analog signal transmission probe in the probe-out direction passes through the analog quantity test pad reserved position corresponding to the analog quantity test pad.
Optionally, a longitudinal scribing groove is formed between two adjacent rows of chips, and a transverse scribing groove is formed between two adjacent rows of chips.
Optionally, the chip is provided with at least one functional pad, and the probe card is further provided with a functional signal transmission probe capable of correspondingly contacting the functional pad.
Optionally, the needle withdrawing direction of the functional signal transmission probe is the same as the needle withdrawing direction of the analog signal transmission probe.
The technical scheme at least comprises the following advantages: the simulation quantity test pad is arranged in the scribing groove around the corresponding chip, so that the area of the chip occupied by the pad is saved, and the process of parallel testing of simulation parameters of the wafer chip can be ensured to be normally carried out by ensuring that the simulation quantity test pad is electrically coupled with the corresponding chip when the wafer test is carried out.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic diagram of a pad arrangement of a wafer in a partial area according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a pad arrangement of a wafer partial area according to another embodiment of the present disclosure;
fig. 3 is a schematic view of the signal transmission probe in contact with the corresponding pad in the embodiment shown in fig. 2.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a schematic diagram illustrating a pad arrangement structure of a partial region of a wafer according to an embodiment of the present disclosure, referring to fig. 1, the wafer includes a plurality of chips 100 distributed in an array, a longitudinal scribe line 210 is formed between two adjacent rows of chips 100, and a transverse scribe line 220 is formed between two adjacent rows of chips 100; an analog quantity test pad is disposed in the scribe line around each chip 100, and the analog quantity test pad is electrically coupled to the corresponding chip 100.
Taking the chip C1 in fig. 1 as an example, scribe grooves are isolated between the chip C1 and other chips, and include a transverse scribe groove 220 and a longitudinal scribe groove 210. An analog quantity test pad1 is arranged in a scribing groove around the chip C1, the analog quantity test pad1 is electrically coupled with the chip C1, namely electrically coupled with a device layer of the chip C1, and by applying an analog quantity test command to the analog quantity test pad1, the analog quantity test pad1 can transmit the analog quantity test command to the device layer of the chip C1, so that charge movement in the device layer of the chip C1 is triggered, and an analog parameter signal of the chip C1 is fed back through the analog quantity test pad 1.
It can be understood that the analog quantity test pad is arranged in the scribing groove around the corresponding chip, the area of the chip occupied by the pad is saved, and the process of parallel testing of the analog quantity test pad and the corresponding chip can be ensured to be normally carried out by ensuring that the analog quantity test pad is electrically coupled with the corresponding chip when the wafer test is carried out.
While the chip C1 shown in fig. 1 has only one analog quantity test pad1, in other embodiments, there may be more than one analog quantity test pad of the chip, and each analog quantity test pad is used for measuring and debugging different analog parameters of the corresponding chip. Fig. 2 is a schematic diagram of a pad arrangement structure of a wafer partial area according to another embodiment of the present application, based on fig. 1, where the chip in fig. 2 has two analog quantity test pads. Taking the chip C2 in fig. 2 as an example, for the chip shown in fig. 2, the chip C2 has two analog quantity test pads, namely a first analog quantity test pad padA and a second analog quantity test pad padB, the padA and the padB are both disposed in the scribe line around the chip C2, and the two analog quantity test pads padA and padB are both electrically coupled to the chip C2.
On the chip including the embodiments shown in fig. 1 and fig. 2, there are reserved analog quantity test pads, and the reserved analog quantity test pads correspond to the analog quantity test pads one to one. The reserved positions of the analog quantity test bonding pads are original planned positions of the analog quantity test bonding pads on the chip, and the actual analog quantity test bonding pads are located in scribing grooves around the reserved positions of the analog quantity test bonding pads, so that the reserved positions of the analog quantity test bonding pads are reserved, and the occupation of the area of the chip is saved. Taking chip C1 in fig. 1 as an example, chip C1 has a first reserved site1 of the analog test pad corresponding to analog test pad 1.
Taking chip C2 in fig. 2 as an example, chip C2 has a first reserved site siteA and a second reserved site siteB of the analog testing pad corresponding to padA and padB, respectively.
The chip including the embodiments shown in fig. 1 and 2 is further provided with at least one functional pad, and the functional pad is electrically coupled with the corresponding chip.
The wafer chip is subjected to parallel test through a probe card, and an analog signal transmission probe capable of being in corresponding contact with the analog quantity test bonding pad is arranged on the probe card; through the analog signal transmission probe, the probe card can send an analog quantity test instruction to the corresponding analog quantity test bonding pad and can acquire an analog parameter signal fed back by the analog quantity test bonding pad.
Illustratively, the probe card includes several test blocks capable of simultaneously testing several chips on a wafer. Each test block is provided with a signal transmission probe capable of contacting with a corresponding chip bonding pad, and the test blocks can send test instructions to the corresponding bonding pads and can acquire signals fed back by the bonding pads through the signal transmission probes.
The signal transmission probe includes: an analog signal transmission probe and a functional signal transmission probe.
When the test block is in corresponding contact with the chip of the wafer, the analog signal transmission probe can be in corresponding contact with the analog quantity test pad of the corresponding chip, and through the analog signal transmission probe, the test block can send an analog quantity test instruction to the corresponding analog quantity test pad and can acquire an analog parameter signal fed back by the analog quantity test pad.
When the test block is in corresponding contact with the chip of the wafer, the functional signal transmission probe can be in corresponding contact with the functional bonding pad, and through the functional signal transmission probe, the test block can send a functional test instruction to the corresponding functional bonding pad and can acquire a functional parameter signal fed back by the functional bonding pad.
The needle outlet direction of the analog signal transmission probe is consistent with the needle outlet direction of the functional signal transmission probe.
The analog signal transmission probe is contacted with the analog quantity test bonding pad in the scribing groove, and the extending direction of the needle-out direction of the analog signal transmission probe penetrates through the analog quantity test bonding pad reserved position corresponding to the analog quantity test bonding pad.
Fig. 3 is a schematic view illustrating the corresponding contact of signal transmission probes with pads when the wafer of fig. 2 is inspected using a probe card. The needle-out direction of the analog signal transmission probe shown in fig. 3 is the same as the needle-out direction of the functional signal transmission probe. Taking the chip C2 in fig. 3 as an example, the chip C2 has two analog quantity test pads, namely a first analog quantity test pad padA and a second analog quantity test pad padB, and both the padA and the padB are disposed in the scribe groove around the chip C2; the chip C2 has a first reserved site siteA and a second reserved site siteB corresponding to padA and padB, respectively. For the probe card test block for testing the chip C2, the analog signal transmission probes thereon include two first analog signal transmission probes probe a and second analog signal transmission probes probe b, and the probe-out directions of the first analog signal transmission probes probe a and the second analog signal transmission probes probe b are both horizontal. The extending direction of the probe A needle outlet direction of the first analog signal transmission probe penetrates through the reserved site siteA of the first analog quantity test pad, and the padA of the first analog quantity test pad is located in a longitudinal scribing groove which is closest to the reserved site siteA of the first analog quantity test pad in the needle outlet direction of the probe A of the first analog signal transmission probe. Similarly, the extending direction of the probe pin-out direction of the second analog signal transmission probe passes through the reserved site siteB of the second analog quantity test pad, and the second analog quantity test pad padB is located in the longitudinal scribe groove which is closest to the reserved site siteB of the second analog quantity test pad in the probe pin-out direction of the second analog signal transmission probe.
In other embodiments, the probe outgoing direction of the analog signal transmission probe may also be a longitudinal direction, for example, for the chip C2 in fig. 2, if the probe outgoing direction of the analog signal transmission probe is the longitudinal direction, the first analog quantity test pad padA is located in the transverse scribe groove closest to the first analog quantity test pad reserved location siteA in the probe outgoing direction of the first analog signal transmission probe; the second analog quantity test pad padB is located in the transverse scribe groove closest to the second analog quantity test pad reserved location siteB in the probe outgoing direction of the second analog signal transmission probe b.
This embodiment, through inciting somebody to action analog quantity test pad, along analog signal transmission probe's play needle direction locates the distance in the nearest scribing groove of analog quantity test pad reservation position, the play needle direction of functional signal transmission probe, with analog signal transmission probe's play needle direction is the same, can vacate analog quantity test pad reservation position, saves the occupation to chip area, simultaneously, avoids the test process to influencing other functional pads.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A simulated quantity test pad arrangement structure for wafer chip parallel test is characterized in that a wafer comprises a plurality of chips distributed in an array manner, and scribing grooves are formed between adjacent chips; a longitudinal scribing groove is formed between two adjacent rows of chips, and a transverse scribing groove is formed between two adjacent rows of chips;
and the scribing grooves positioned around the chips are provided with analog quantity testing bonding pads which are electrically coupled with the corresponding chips.
2. The arrangement structure of the analog testing pads for the parallel testing of the wafer chips as claimed in claim 1, wherein the wafer chips are tested in parallel by a probe card, on which analog signal transmission probes capable of contacting the analog testing pads correspondingly are disposed;
through the analog signal transmission probe, the probe card can send an analog quantity test instruction to the corresponding analog quantity test bonding pad and can acquire an analog parameter signal fed back by the analog quantity test bonding pad.
3. The arrangement structure of analog testing pads for wafer chip parallel testing as claimed in claim 2, wherein there are reserved analog testing pads on the chip; (ii) a
The analog quantity test bonding pad is arranged in a scribing groove closest to the reserved position of the analog quantity test bonding pad along the needle outlet direction of the analog signal transmission probe.
4. The layout structure of the analog testing pads for the parallel testing of the wafer chip as claimed in claim 3, wherein there are a plurality of the analog testing pads, and the reserved locations of the analog testing pads on the chip are in one-to-one correspondence with the analog testing pads.
5. The layout structure of the analog testing pads for the parallel testing of the wafer chip as claimed in claim 3, wherein when the analog signal transmission probe contacts the analog testing pad in the scribe line, the extension direction of the probe-out direction of the analog signal transmission probe passes through the reserved position of the analog testing pad corresponding to the analog testing pad.
6. The structure of claim 1, wherein a longitudinal scribe line is formed between two adjacent rows of chips, and a transverse scribe line is formed between two adjacent rows of chips.
7. The pad layout structure for analog quantity test of wafer chip parallel test as claimed in claim 2, wherein said chip is provided with at least one functional pad, and said probe card is further provided with a functional signal transmission probe capable of corresponding contact with said functional pad.
8. The layout structure of the analog testing pads for the parallel testing of the wafer chips as claimed in claim 7, wherein the probe-out direction of the functional signal transmission probe is the same as the probe-out direction of the analog signal transmission probe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011021160.6A CN112147487A (en) | 2020-09-25 | 2020-09-25 | Analog quantity test pad arrangement structure for parallel test of wafer chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011021160.6A CN112147487A (en) | 2020-09-25 | 2020-09-25 | Analog quantity test pad arrangement structure for parallel test of wafer chip |
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| CN112147487A true CN112147487A (en) | 2020-12-29 |
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Citations (8)
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| CN1790047A (en) * | 2004-12-16 | 2006-06-21 | 安捷伦科技有限公司 | Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment |
| JP2007150130A (en) * | 2005-11-30 | 2007-06-14 | Matsushita Electric Ind Co Ltd | Inspection circuit and inspection method for semiconductor device |
| JP2007266078A (en) * | 2006-03-27 | 2007-10-11 | Fujitsu Ltd | Semiconductor device, semiconductor device of chip-on-chip structure, and process for manufacturing the semiconductor device |
| CN204834614U (en) * | 2015-07-30 | 2015-12-02 | 北京卓锐微技术有限公司 | Wafer test structure |
| JP2017041495A (en) * | 2015-08-18 | 2017-02-23 | 株式会社デンソー | Semiconductor inspection circuit |
| CN107516655A (en) * | 2017-07-21 | 2017-12-26 | 上海华虹宏力半导体制造有限公司 | Scribe line test structure and method of testing |
| CN109904119A (en) * | 2019-01-24 | 2019-06-18 | 上海南麟电子股份有限公司 | A kind of preparation method of chip |
| CN111435145A (en) * | 2019-01-11 | 2020-07-21 | 北京确安科技股份有限公司 | Test system for smart card chip |
-
2020
- 2020-09-25 CN CN202011021160.6A patent/CN112147487A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1790047A (en) * | 2004-12-16 | 2006-06-21 | 安捷伦科技有限公司 | Mock wafer, system calibrated using mock wafer, and method for calibrating automated test equipment |
| JP2007150130A (en) * | 2005-11-30 | 2007-06-14 | Matsushita Electric Ind Co Ltd | Inspection circuit and inspection method for semiconductor device |
| JP2007266078A (en) * | 2006-03-27 | 2007-10-11 | Fujitsu Ltd | Semiconductor device, semiconductor device of chip-on-chip structure, and process for manufacturing the semiconductor device |
| CN204834614U (en) * | 2015-07-30 | 2015-12-02 | 北京卓锐微技术有限公司 | Wafer test structure |
| JP2017041495A (en) * | 2015-08-18 | 2017-02-23 | 株式会社デンソー | Semiconductor inspection circuit |
| CN107516655A (en) * | 2017-07-21 | 2017-12-26 | 上海华虹宏力半导体制造有限公司 | Scribe line test structure and method of testing |
| CN111435145A (en) * | 2019-01-11 | 2020-07-21 | 北京确安科技股份有限公司 | Test system for smart card chip |
| CN109904119A (en) * | 2019-01-24 | 2019-06-18 | 上海南麟电子股份有限公司 | A kind of preparation method of chip |
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