CN204834614U - Wafer test structure - Google Patents
Wafer test structure Download PDFInfo
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- CN204834614U CN204834614U CN201520567017.5U CN201520567017U CN204834614U CN 204834614 U CN204834614 U CN 204834614U CN 201520567017 U CN201520567017 U CN 201520567017U CN 204834614 U CN204834614 U CN 204834614U
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Abstract
The utility model discloses a wafer test structure, the tube core that includes array arrangement on the wafer, separate through the scribing groove between the tube core, wafer test structure is still including setting up the conductive path in the scribing groove, the conductive path connects into two at least tube core electricity into a test group. Wafer test structure has improved the efficiency of wafer test.
Description
Technical field
The utility model relates to semiconductor test field, is specifically related to a kind of wafer sort structure.
Background technology
The manufacture process of semiconductor integrated circuit, can be divided into wafer manufacture, wafer sort, encapsulation and last test haply.Wafer refers to the wafer that Si semiconductor production of integrated circuits is used, and because its shape is circular, therefore be called wafer (wafer), its size is such as 6 inches, 8 inches or 12 inches.Wafer manufacture is the process making integrated circuit on wafer, after completing, wafer is formed the tube core (die) of arrayed.Then On-Wafer Measurement step is to make testing electrical property to tube core, is eliminated by underproof tube core, and qualified tube core is cut into individual independently tube core from wafer.Afterwards, encapsulation is carried out packing and routing by qualified tube core, forms the chip after encapsulation, finally need to carry out testing electrical property again to guarantee the quality of integrated circuit.
As shown in Figure 1, wafer 10 is comprised between some tube cores 20 of array arrangement, tube core and being separated by scribe line, and wafer sort equipment carries out testing electrical property to tube core in sequence successively one by one, to find out underproof tube core in the wafer sort of prior art.The wafer sort efficiency of prior art is too low, too much time-consuming.
Utility model content
In view of this, the utility model provides a kind of wafer sort structure improving testing efficiency.Described wafer comprises the tube core of array arrangement, separated by scribe line between described tube core, described wafer sort structure also comprises the conductive path be arranged in scribe line, at least two tube core electrical connections are become a test group by described conductive path, wherein, whether the tube core judged in this group according to the test result of a tube core in described test group is qualified.
Preferably, the number of die in described test group is less than or equal to 10.
Preferably, the number of die in described test group is 4.
Preferably, the tube core in described test group is 2x2 array arrangement.
Preferably, the number of die in described test group is 9.
Preferably, the tube core in described test group is 3x3 array arrangement.
Preferably, described conductive path is the silicon of doping.
Preferably, the die series in described test group or parallel connection.
Preferably, the tube core in described test group is MEMS sensor.
Preferably, described conductive path is as test and application state electric connection line one of at least.
Wafer sort structure of the present utility model by tube core grouping test, underproof test group all eliminate or group in by die testing with determine lost efficacy tube core, improve the efficiency of test.
Accompanying drawing explanation
By referring to the description of accompanying drawing to the utility model embodiment, above-mentioned and other objects, features and advantages of the present utility model will be more clear, in the accompanying drawings:
Fig. 1 is the wafer sort structural representation of prior art;
Fig. 2 is the schematic diagram of the wafer sort structure according to the utility model first embodiment;
Fig. 3 is the schematic diagram of the wafer sort structure according to the utility model second embodiment;
Fig. 4 is the first dicing methods schematic diagram of the wafer sort structure according to the utility model second embodiment; And
Fig. 5 is the second dicing methods schematic diagram of the wafer sort structure according to the utility model second embodiment.
Embodiment
Based on embodiment, the utility model is described below, but the utility model is not restricted to these embodiments.In hereafter details of the present utility model being described, detailedly describe some specific detail sections.Do not have the description of these detail sections can understand the utility model completely for a person skilled in the art yet.In order to avoid obscuring essence of the present utility model, known method, process, flow process, element and circuit do not describe in detail.In addition, it should be understood by one skilled in the art that the accompanying drawing provided at this is all for illustrative purposes, and accompanying drawing is not necessarily drawn in proportion.
Meanwhile, should be appreciated that in the following description, " circuit " refers to the galvanic circle connected and composed by electrical connection or electromagnetism by least one element or electronic circuit.When " being connected to " another element when claiming element or circuit or claiming element/circuit " to be connected to " between two nodes, it can be directly couple or be connected to another element or can there is intermediary element, the connection between element can be physically, in logic or its combine.Unless the context clearly requires otherwise, similar words such as " comprising ", " comprising " otherwise in whole specification and claims should be interpreted as the implication that comprises instead of exclusive or exhaustive implication; That is, be the implication of " including but not limited to ".
In description of the present utility model, it is to be appreciated that term " first ", " second " etc. are only for describing object, and instruction or hint relative importance can not be interpreted as.In addition, in description of the present utility model, except as otherwise noted, the implication of " multiple " is two or more.
MEMS sensor chip is using electric capacity, inductance or resistance as main sensitive fashion.Wafer sort structure of the present utility model will be positioned at some tube core electrical connections of the same area by conductive channel, carry out integrated testability as a test group, and wherein, in test group, the electrical connection of tube core is series connection or parallel connection.When testing, test a tube core in this race, if the resistance value of test or capacitance or inductance value are in preset range, this group tube core is all qualified; If the resistance value of test or capacitance or inductance value be not in preset range, then this test group comprises the tube core of inefficacy.When this test group comprises the tube core of inefficacy, can whole tube core in this test group be cast out superseded, also can die testing one by one further, to determine the tube core lost efficacy.Preferably, in a test group quantity of tube core between 2 to 10.Such as, test group comprises four tube cores of the arrangement in 2x2, or test group comprises nine tube cores of the arrangement in 3x3 or six tube cores of 2x3 arrangement.Preferably, between each test group, the quantity of chip can be different.
The wafer sort structure of the first embodiment as shown in Figure 2, wafer 10 is comprised the tube core 20 of array arrangement, is separated between tube core by scribe line.Two adjacent tube cores are as a test group, and two tube cores realize electrical connection by the conductive channel be arranged in scribe line, and wherein, the annexation of two tube cores is in parallel or series connection.
Conductive channel can be metal wire, such as, be gold thread, copper cash or aluminum steel etc.Preferably, this conductive channel is the silicon of doping.For metal wire, because it is comparatively large to sharp light reflectance, in follow-up scribing process, comparatively large to the infringement of equipment, and the reflectivity of silicon is less, also less to the infringement of equipment.
In parallel for the tube core of two in test group, wherein, two tube cores are sensitive fashion with electric capacity, and reading when good die normally works is C.To the integrated testability of test group, test a tube core in this race, if testing capacitor value is in preset range, two tube cores in this group are all qualified; If the resistance value of test or capacitance or inductance value be not in preset range, then this test group comprises the tube core of inefficacy, is all cast out by this test group tube core after scribing, and wherein, preset range is such as 1.5C to 2.5C.Test by group according to identical mode, to determine all groups comprising inefficacy tube core.
Preferably, the tube core appearance design in test group is obtained mutually slightly difference, be convenient to observe identifying.If find product failure in the later stage like this, also can trace back to a certain problem tube core, instead of trace back to all tube cores in group.
Compared to prior art, the testing efficiency according to the wafer sort structure of the present embodiment is doubled.
The wafer sort structure of the second embodiment as shown in Figure 3, wafer 10 is comprised the tube core 20 of array arrangement, is separated between tube core by scribe line.Four adjacent tube cores realize electrical connection as a group by the conductive channel be arranged in scribe line.Wherein, four tube core arrangements in " field " type, the annexation of tube core is in parallel or series connection.
Conductive channel can be metal wire, such as, be gold thread, copper cash or aluminum steel etc.Preferably, this conductive channel is the silicon of doping.For metal wire, because it is comparatively large to sharp light reflectance, in follow-up scribing process, comparatively large to the infringement of equipment, and the reflectivity of silicon is less, also less to the infringement of equipment.
Connect for the tube core cc of four in test group, wherein, four tube cores are sensitive fashion with resistance, and reading when good die normally works is R.Carry out integrated testability to test group, test a tube core in this race, if the resistance value of test is in preset range, four tube cores in this group are all qualified; If the resistance value of test is not in preset range, then this group comprises the chip of inefficacy, this group tube core all can be cast out after scribing, or test dies one by one in this set further, to determine the tube core lost efficacy.Wherein, preset range is such as 3.5R to 4.5R.
Test by group according to identical mode, to determine all groups comprising inefficacy tube core.
Need die separation after wafer sort, carry out packaging and testing.According to the purposes of product, packing forms comprises a die package, two or four tube core as various ways such as module package.Such as, four tube cores comprise again as a module package and are electrically connected to each other and are not electrically connected two kinds of situations.
As shown in Figure 4, cut according to the test group of the wafer sort structure of the second embodiment, each test group is as a module package, and the tube core in group is electrically connected by conductive channel for the first cutting mode.The module cut out comprises the tube core of four electrical connections.
The second cutting mode as shown in Figure 5, each module cut out comprises four unconnected tube cores, and four tube cores come from the adjacent test group of four of the wafer sort structure of the second embodiment respectively.
The wafer sort structure of the present embodiment not only increases the efficiency of wafer sort, and improves the efficiency of follow-up scribing.
The utility model provides a kind of crystal round test approach, and this wafer comprises some tube cores of array arrangement, separated between tube core by scribe line, this crystal round test approach comprises:
First, tube core is divided into multiple test group, in each test group, the number of tube core is 2 to 10.Preferably, the tube core in test group is 4 tube cores of 2x2 array arrangement, or 9 of 3x3 array arrangement tube cores.
Further, arrange conductive channel with the electrical connection of tube core in realization group in test group, the tube core in test can in parallel or series connection.
Further, to the die testing of in test group, if the resistance value of test or capacitance or inductance value are in preset range, the tube core in this group is all qualified; If the resistance value of test or capacitance or inductance value be not in preset range, then this group comprises the chip of inefficacy.
The foregoing is only preferred embodiment of the present utility model, be not limited to the utility model, to those skilled in the art, the utility model can have various change and change.All do within spirit of the present utility model and principle any amendment, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.
Claims (10)
1. a wafer sort structure, described wafer comprises the tube core of array arrangement, separated by scribe line between described tube core, it is characterized in that, described wafer sort structure also comprises the conductive path be arranged in scribe line, whether at least two tube core electrical connections are become a test group by described conductive path, wherein, qualified according to the tube core that the test result of a tube core in described test group judges in this group.
2. structure according to claim 1, is characterized in that, the number of die in described test group is less than or equal to 10.
3. structure according to claim 2, is characterized in that, the number of die in described test group is 4.
4. structure according to claim 3, is characterized in that, the tube core in described test group is 2x2 array arrangement.
5. structure according to claim 2, is characterized in that, the number of die in described test group is 9.
6. structure according to claim 5, is characterized in that, the tube core in described test group is 3x3 array arrangement.
7. structure according to claim 1, is characterized in that, described conductive path is the silicon of doping.
8. structure according to claim 1, is characterized in that, the die series in described test group or parallel connection.
9. structure according to claim 1, is characterized in that, the tube core in described test group is MEMS sensor.
10. structure according to claim 1, is characterized in that, described conductive path is as test and application state electric connection line one of at least.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520567017.5U CN204834614U (en) | 2015-07-30 | 2015-07-30 | Wafer test structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520567017.5U CN204834614U (en) | 2015-07-30 | 2015-07-30 | Wafer test structure |
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| CN204834614U true CN204834614U (en) | 2015-12-02 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107329077A (en) * | 2017-08-16 | 2017-11-07 | 苏州易美新思新能源科技有限公司 | A kind of PCB soft boards drain current test method and device |
| CN112147487A (en) * | 2020-09-25 | 2020-12-29 | 上海华虹宏力半导体制造有限公司 | Analog quantity test pad arrangement structure for parallel test of wafer chip |
-
2015
- 2015-07-30 CN CN201520567017.5U patent/CN204834614U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107329077A (en) * | 2017-08-16 | 2017-11-07 | 苏州易美新思新能源科技有限公司 | A kind of PCB soft boards drain current test method and device |
| CN112147487A (en) * | 2020-09-25 | 2020-12-29 | 上海华虹宏力半导体制造有限公司 | Analog quantity test pad arrangement structure for parallel test of wafer chip |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180718 Address after: 261000 Fengshan Road, Fangzi District, Weifang, Shandong Province, No. 68 Patentee after: Shandong Gettop Acoustic Co.,Ltd. Address before: 100191 Beijing Haidian District Zhichun Road 23 quantum Ginza 1002 room Patentee before: Beijing Acuti Microsystems Co., Ltd. |
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| TR01 | Transfer of patent right |