CN111753477B - Multi-die FPGA for realizing system monitoring by utilizing active silicon connection layer - Google Patents

Multi-die FPGA for realizing system monitoring by utilizing active silicon connection layer Download PDF

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CN111753477B
CN111753477B CN202010620195.5A CN202010620195A CN111753477B CN 111753477 B CN111753477 B CN 111753477B CN 202010620195 A CN202010620195 A CN 202010620195A CN 111753477 B CN111753477 B CN 111753477B
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CN111753477A (en
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单悦尔
范继聪
徐彦峰
张艳飞
闫华
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Wuxi Zhongwei Yixin Co Ltd
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    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other

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Abstract

The application discloses a multi-die FPGA for realizing system monitoring by utilizing an active silicon connecting layer, and relates to the technical field of FPGAs (field programmable gate arrays). the multi-die FPGA integrates a plurality of FPGA dies by utilizing the silicon connecting layer, so that a plurality of small-scale and small-area FPGA dies can be cascaded to realize large-scale and large-area FPGA products, the processing difficulty is reduced, the production yield of chips is improved, and the design speed is accelerated; meanwhile, the active silicon connection layer is internally provided with a system monitoring circuit which can be connected with any one FPGA bare chip and/or silicon connection layer to carry out real-time monitoring on various signals inside the multi-bare-chip FPGA, can also monitor various signals outside the multi-bare-chip FPGA, can timely carry out corresponding operation when monitoring abnormity, can ensure the reliability and stability of the operation of the multi-bare-chip FPGA, and prevents the system from being damaged due to the conditions of high temperature, high pressure and the like.

Description

Multi-die FPGA for realizing system monitoring by utilizing active silicon connection layer
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to a multi-die FPGA for realizing system monitoring by utilizing an active silicon connection layer.
Background
An FPGA (Field Programmable Gate Array) is a Programmable logic device, and is widely applied to the fields of mobile communication, data centers, navigation guidance, automatic driving, and the like. With the increasing demands of new applications on bandwidth, storage and data processing capabilities, the requirements on the scale, functionality and stability of the FPGA are increasing, and new requirements on the design and production of the FPGA are provided.
Disclosure of Invention
The present invention provides a multi-die FPGA for implementing system monitoring by using an active silicon connection layer, in order to solve the above problems and technical requirements, and the technical scheme of the present invention is as follows:
a multi-die FPGA for realizing system monitoring by utilizing an active silicon connection layer is characterized in that the multi-die FPGA comprises a substrate, a silicon connection layer stacked on the substrate and a plurality of FPGA dies stacked on the silicon connection layer, wherein the silicon connection layer covers all the FPGA dies;
each FPGA bare chip comprises a plurality of configurable function modules, interconnection resource modules distributed around each configurable function module and a connection point leading-out end, each configurable function module in the FPGA bare chip at least comprises a programmable logic unit, a silicon stacking connection module and an input/output port, each silicon stacking connection module comprises a plurality of silicon stacking connection points, the programmable logic units in the FPGA bare chip are respectively connected with the silicon stacking connection points and the input/output ports through the interconnection resource modules, and the silicon stacking connection points are connected with the corresponding connection point leading-out ends through top metal wires in a rewiring layer; the connection point leading-out end in each FPGA bare chip is connected with the corresponding connection point leading-out end in other FPGA bare chips through a cross bare chip connection wire in the silicon connection layer, and each FPGA bare chip is connected with any other FPGA bare chip through the cross bare chip connection wire in the silicon connection layer; the input/output port in the FPGA bare chip is connected to the substrate through the silicon through hole on the silicon connecting layer;
a system monitoring circuit is distributed on the silicon connection layer, the input end of the system monitoring circuit is connected with monitoring points in at least one FPGA (field programmable gate array) die and/or monitoring points on the silicon connection layer and acquires a plurality of groups of internal working signals to be monitored, and the system monitoring circuit monitors the working process of the system according to the acquired internal working signals to be monitored; the monitoring point in the FPGA die is connected to the corresponding connection point leading-out end through the silicon stacking connection point, and the input end of the system monitoring circuit is connected to the corresponding connection point leading-out end to realize connection with the monitoring point in the FPGA die.
The input end of the system monitoring circuit is also connected with an external port of the multi-bare-chip FPGA and acquires an external working signal to be monitored, and the system monitoring circuit monitors the working process of the system according to all the acquired working signals to be monitored.
The system monitoring circuit comprises a multiplexer, a high-precision ADC and a measuring register group, wherein the multiplexer comprises N input ends and N input ends, N groups of working signals to be monitored are acquired by the N input ends respectively, the output end of the multiplexer is connected with the input end of the high-precision ADC, the output end of the high-precision ADC is connected with the measuring register group, the measuring register group comprises N channels, the high-precision ADC sequentially performs analog-to-digital conversion on the acquired N groups of working signals to be monitored into measuring results and then stores the measuring results into the measuring registers of the N channels respectively, and the system monitoring circuit stores each measuring result in the working process of the system through the measuring register group.
The system monitoring circuit also comprises a monitoring alarm circuit, the monitoring alarm circuit is connected with the measuring register group and detects whether the system works abnormally according to the measuring result in the measuring register group, and when at least one measuring result exceeds a preset range, the system is determined to work abnormally and preset emergency operation is executed.
The method further comprises the following technical scheme that the monitoring alarm circuit executes preset emergency operation corresponding to the current abnormal grade when the system is detected to work abnormally, and the preset emergency operation corresponding to different abnormal grades has different reaction time and/or operation types.
The further technical scheme is that the operation type of the preset emergency operation executed by the monitoring alarm circuit when the system work abnormity is detected comprises sending an alarm signal and/or controlling to close the power supply of each FPGA bare chip and the power supply of the silicon connection layer.
The system monitoring circuit further comprises a reference register group, the reference register group comprises reference registers of N channels, and a reference value is stored in the reference register of each channel, so that the monitoring alarm circuit is also connected with the reference register group; the monitoring alarm circuit comprises N comparators and an OR gate, a measuring register of one channel, a reference register of one channel and a comparator are respectively corresponding to each other, each comparator respectively obtains a measuring result in the corresponding measuring register and a reference value in the corresponding reference register to compare to obtain a comparison result, the output ends of the N comparators are connected with the OR gate, the N comparators are used for comparing the measuring results in the measuring register group in parallel, the monitoring alarm circuit detects whether the system works abnormally according to the result of the OR logic generation of the internal OR gate on the N comparison results, and the system works abnormally when the deviation of at least one measuring result and the corresponding reference value exceeds a preset error range.
The system monitoring circuit further comprises a reference register of one channel, a reference value is stored in the reference register, the monitoring alarm circuit is further connected with the reference register, the monitoring alarm circuit internally comprises a comparator, the comparator sequentially obtains measurement results from the measurement registers of the N channels and obtains the reference value from the reference register to compare the measurement results to obtain a comparison result, the comparator serially compares the measurement results in the measurement register group, the monitoring alarm circuit detects whether the system works abnormally according to the comparison result of the comparator, and if the deviation of the current comparison measurement result and the reference value exceeds a preset error range, the system works abnormally.
The technical scheme is that when FPGA bare chips in the multi-bare-chip FPGA are the same, one or a plurality of comparators are arranged in the monitoring alarm circuit, and the comparators compare the measurement results of the same FPGA bare chips in the measurement register group in pairs in sequence, or the comparators compare the measurement results of the same FPGA bare chips in the measurement register group in pairs.
The system monitoring circuit further comprises a read-write control circuit and a configuration register, the read-write control circuit is connected with a JTAG port of the multi-die FPGA and/or any one FPGA die, the read-write control circuit is connected with each register in the system monitoring circuit, the JTAG port reads the value of each register in the system monitoring circuit through the read-write control circuit, and/or a dynamic reconfiguration circuit in the JTAG port and/or the FPGA die utilizes the configuration register to configure each register in the system monitoring circuit through the read-write control circuit.
The further technical scheme is that the internal working signal to be monitored acquired by the system monitoring circuit comprises at least one of a voltage signal, a temperature signal, a pressure signal and other sensor signals, and the working signal to be monitored is input in a single-pole mode or in a double-pole differential mode.
The further technical scheme is that the input end of the system monitoring circuit is connected with monitoring points in at least one FPGA bare chip and/or monitoring points on a silicon connecting layer and acquires voltage signals, and the method comprises the following steps:
the system monitoring circuit is connected with a voltage monitoring point in the FPGA bare chip to acquire a bare chip voltage signal and/or a voltage monitoring point on a silicon connection layer and a power supply voltage signal of the silicon connection layer, wherein the bare chip voltage signal comprises at least one of core voltage, IO voltage, configuration voltage, BRAM voltage and high-speed interface voltage.
The input end of the system monitoring circuit is connected with at least one FPGA bare chip and/or a temperature sensor on a silicon connection layer and acquires a temperature signal;
and/or the input end of the system monitoring circuit is connected with at least one FPGA bare chip and/or a pressure sensor on a silicon connection layer and acquires a pressure signal;
and/or the input end of the system monitoring circuit is connected with at least one FPGA bare chip and/or other sensors on the silicon connection layer and acquires corresponding other sensor signals, wherein the other sensor signals comprise humidity, sound, speed, concentration, light, radioactive rays, particles, radar waves, electric waves, magnetic waves and gravity.
The beneficial technical effects of the invention are as follows:
according to the multi-die FPGA, the silicon connection layer is used for integrating the plurality of FPGA dies, so that a large-scale large-area FPGA product can be realized by cascading the plurality of small-scale small-area FPGA dies, the processing difficulty is reduced, the production yield of chips is improved, and the design speed is accelerated; meanwhile, the active silicon connection layer is internally provided with a system monitoring circuit which can be connected with any one FPGA bare chip and/or silicon connection layer to carry out real-time monitoring on various signals inside the multi-bare-chip FPGA, can also monitor various signals outside the multi-bare-chip FPGA, can timely carry out corresponding operation when monitoring abnormity, can ensure the reliability and stability of the operation of the multi-bare-chip FPGA, and prevents the system from being damaged due to the conditions of high temperature, high pressure and the like.
Drawings
FIG. 1 is a cross-sectional view of the structure of a multi-die FPGA of the present application.
FIG. 2 is a schematic diagram of the internal circuit structure of a multi-die FPGA.
Fig. 3 is a schematic circuit diagram of a part of the circuit in the system monitoring circuit according to the present application.
Fig. 4 is a schematic diagram of another circuit configuration of a portion of the circuit in the system monitoring circuit of the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses utilize active silicon connecting layer to realize many bare chips FPGA of system monitoring, please refer to fig. 1 and 2, this many bare chips FPGA includes from the base plate 1, silicon connecting layer 2 and a plurality of FPGA bare chip that from supreme range upon range of setting gradually down, represents with bare chip 1, bare chip 2 etc. respectively, analogizes in proper order. In practical implementation, the FPGA further comprises a package housing for protecting the various components, packaged outside the substrate 1, the silicon connection layer 2 and the FPGA die, and further comprises pins for signal extraction, etc. connected to the substrate, which conventional structures are not shown in detail in fig. 1.
The FPGA of the application does not adopt a single FPGA bare chip structure, but comprises a plurality of FPGA bare chips, and the plurality of FPGA bare chips are all stacked and arranged on the same silicon connection layer 2. The plurality of FPGA bare chips can be arranged on the silicon connection layer 2 along a one-dimensional direction, and also can be arranged on the silicon connection layer 2 according to a two-dimensional stacking mode, namely, arranged on a horizontal plane along a transverse direction and a longitudinal direction, and can be reasonably arranged on the silicon connection layer 2, so that the whole area of the whole FPGA is smaller and the interconnection performance between the bare chips is better according to the shape and the area of each FPGA bare chip which are compactly arranged on the silicon connection layer 2.
The FPGA bare chip in the present application is different from a conventional FPGA bare chip, the conventional FPGA bare chip is composed of configurable functional modules with multiple functions, and the conventional configurable functional modules mainly include programmable logic units (CLBs or PLBs) and input/output ports (IOBs), and sometimes include some other functional modules, such as BRAMs, DSPs, PCs, and the like. Each configurable functional module has an interconnection resource module (INT) with the same structure distributed around the configurable functional module, and horizontal or vertical connecting lines among the configurable functional modules are connected through the INT module. On the basis of the conventional structure, the FPGA bare chip in the application also comprises a silicon stacking connection module which is specially designed inside the bare chip according to the signal interconnection requirement among the bare chips, besides the conventional configurable function modules comprising the CLB, the IOB and other function modules, each silicon stacking connection module comprises a plurality of silicon stacking connection points 3, the silicon stacking connection module is a newly-added configurable function module which is specially used for leading out bare chip signals, and the FPGA bare chip in the application replaces some conventional configurable function modules in the conventional FPGA bare chip into the silicon stacking connection module. And the conventional configurable functional module at any position can be replaced according to the signal interconnection requirement, for example, for the conventional Column-Based FPGA architecture, the silicon stacking connection module may be disposed in the row-Column structure where the programmable logic unit is located, or the silicon stacking connection module may be disposed in the row-Column structure where other functional modules are located to obtain the FPGA die in the present application.
Each silicon stacking connection module in the FPGA bare chip in the application also has an interconnection resource module distributed around the silicon stacking connection module, so that the winding structure of the FPGA bare chip in the application can be consistent with that of a conventional FPGA bare chip without changing. The horizontal or vertical connecting lines between the silicon stacking connection module and each other configurable function module are all connected through an INT module, and the silicon stacking connection module LNK is directly connected with an interconnection switch in the INT corresponding to the silicon stacking connection module and is a part of an interconnection line. The silicon stacking connection module LNK and the interconnection switch can be fully interconnected or partially interconnected according to the requirement of connectivity.
The FPGA bare chip in the application further comprises a connection point leading-out end 4 corresponding to the internal silicon stacking connection point 3, the silicon stacking connection point 3 in the FPGA bare chip is connected with the corresponding connection point leading-out end 4 through a top layer metal wire 5 in a rewiring layer (RDL layer), and the silicon stacking connection point 3 and the connection point leading-out end 4 are located on different planes. The connection point terminals 4 are generally arranged in a row-column configuration along the first direction and the second direction according to the stack interconnection needs. In addition, in order to achieve higher communication bandwidth, multiple rows/multiple columns of connection point leading-out terminals 4 can be arranged, that is, multiple rows of connection point leading-out terminals 4 are arranged in each FPGA die along the first direction, and/or multiple columns of connection point leading-out terminals 4 are arranged along the second direction, so that efficient two-dimensional cascade of multiple rows and multiple columns is achieved. When the plurality of rows/columns of the connection point leading-out terminals 4 are arranged along each direction, they may be arranged at regular intervals or at random.
As shown in fig. 1, the silicon connection layer 2 is internally provided with the cross-die connection lines 6, the cross-die connection lines 6 are distributed in the whole area or a partial area of the silicon connection layer 2, and the silicon connection layer 2 covers all the FPGA dies, so that each FPGA die can be connected to any other FPGA die through the cross-die connection lines 6 according to circuit requirements, and the circuit interconnection between the FPGA dies is almost not limited in space. In addition, a silicon through hole 7 is further formed in the silicon connecting layer 2, and the IOB in the FPGA die is connected to the substrate 1 through the silicon through hole 7 in the silicon connecting layer 2 so as to finally lead out a signal.
The manufacturing process of the silicon connection layer 2 can be different from that of the FPGA bare chip, the silicon connection layer 2 in the application is an active silicon connection layer, a plurality of layers of cross-bare-chip connecting wires 6 are arranged in the active silicon connection layer, and silicon connection layer circuits are also arranged in the active silicon connection layer, and can comprise a configuration circuit for configuring a multi-bare-chip FPGA, a clock tree circuit for providing clock signals, a signal delay adjusting circuit connected between the FPGA bare chips and the like.
In addition, a system monitoring circuit is further arranged in the silicon connection layer 2, the input end of the system monitoring circuit is connected with a monitoring point in at least one FPGA (field programmable gate array) die and/or a monitoring point on the silicon connection layer 2, and the monitoring point can be a certain node or a certain device in a circuit structure. When the monitoring circuit is connected with the monitoring point on the silicon connection layer 2, the system monitoring circuit is directly connected with the monitoring point on the silicon connection layer 2 through the connecting line in the silicon connection layer 2. When the monitoring point in the FPGA die is connected, the monitoring point in the FPGA die is connected to the corresponding connection point leading-out end through the silicon stacking connection point, and then the input end of the system monitoring circuit is connected to the corresponding connection point leading-out end to realize the connection with the monitoring point in the FPGA die. The input end of the system monitoring circuit acquires the internal working signals to be monitored at each monitoring point, and acquires a plurality of groups of internal working signals to be monitored, and the system monitoring circuit monitors the working process of the system according to the acquired internal working signals to be monitored.
In addition, the system monitoring circuit also supports external analog input monitoring, that is, as shown in fig. 2, the input end of the system monitoring circuit is further connected to the external port of the multi-die FPGA and acquires a plurality of sets of external working signals to be monitored, and then the system monitoring circuit monitors the working process of the system according to all the acquired working signals to be monitored, including internal working signals to be monitored and external working signals to be monitored.
Referring to fig. 2, the system monitoring circuit in the present application includes a multiplexer MUX, a high-precision ADC, and a measurement register set, where the multiplexer includes N input terminals, and the N input terminals respectively obtain N sets of working signals to be monitored. The working signal to be monitored adopts unipolar input or bipolar differential input, when the bipolar differential input is carried out, a corresponding input end comprises two differential input lines, and the wiring of the two differential input ends is balanced. The output end of the multiplexer MUX is connected with the input end of the high-precision ADC, the output end of the high-precision ADC is connected with the measurement register group, the measurement register group comprises N channels of measurement registers, and the high-precision ADC sequentially performs analog-to-digital conversion on N groups of working signals to be monitored into measurement results and then stores the measurement results into the measurement registers of the N channels respectively. The high-precision ADC and each measurement register are b-bit precision. The system monitoring circuit stores various measurement results in the working process of the system through the measurement register group, so that data recording of the working process of the system is realized.
The system monitoring circuit can record various measurement results in the working process of the system and can also alarm the working abnormity of the system in the monitoring process. That is, as shown in fig. 2, the system monitoring circuit further includes a monitoring alarm circuit, the monitoring alarm circuit is connected to the measurement register set and detects whether the system is working abnormally according to the measurement result in the measurement register set, and determines that the system is working abnormally and executes a predetermined emergency operation when at least one measurement result is detected to be out of a preset range.
When the predetermined emergency operation is executed, the system monitoring circuit can execute the same predetermined emergency operation aiming at all the abnormal working conditions, wherein the operation type of the predetermined emergency operation comprises sending out an alarm signal, and/or controlling to close the power supply of each FPGA bare chip and the power supply of the silicon connection layer so that the system is closed.
When the predetermined emergency operation is executed, different predetermined emergency operations may also be executed for different abnormal working conditions, for example, the corresponding predetermined emergency operation may be executed according to the current abnormal level. When the current abnormal level is determined, it is usually determined that the abnormal level corresponding to the type of the measurement result which currently exceeds the preset range is the current abnormal level, for example, if the voltage signal currently exceeds the range, the abnormal level corresponding to the voltage signal is determined, and if the temperature signal currently exceeds the range, the abnormal level corresponding to the temperature signal is determined. The classification of the abnormal grade is predetermined, the abnormal grade can be classified equally for all the monitored objects, or the abnormal grade can be classified respectively for different monitored objects, where the monitored objects include a silicon connection layer, an FPGA bare chip and external signals, for example, the abnormal grade can be classified for all the signals to be detected on the silicon connection layer, the abnormal grade is classified for all the signals to be detected in the FPGA bare chip, and the abnormal grade of the signals on the silicon connection layer and the abnormal grade of the signals in the FPGA bare chip are independent and not related to each other. When different preset emergency operations are executed according to different work abnormal conditions, the reaction time and/or the operation type of the preset emergency operations corresponding to different abnormal levels are different, and the meaning of the operation type is as described above. A higher anomaly level indicates more impairment of the system operation, generally shorter reaction times and more urgent operation types, for example, a high anomaly level may directly shut down the system and a low anomaly level may only send out an alarm signal.
The following three ways of detecting whether the system has abnormal operation by the system monitoring circuit are available:
1. the system monitoring circuit comprises a plurality of reference registers and a plurality of comparators, and the plurality of comparators perform multi-channel parallel comparison on values in the measurement register and the reference registers. Namely: the system monitoring circuit further comprises a reference register group, the reference register group comprises N channels of reference registers, reference values are stored in the reference registers of each channel, and each reference register has b-bit precision. The monitoring alarm circuit is further connected to the reference register set, and the monitoring alarm circuit internally includes N comparators and an or gate. The measuring register of one channel, the reference register of one channel and the comparator are respectively corresponding, the reference value in the reference register of each channel is corresponding to the measuring result in the corresponding measuring register, therefore, the reference values stored in the reference registers of different channels can be the same or different, each comparator respectively obtains the measuring result in the corresponding measuring register and the reference value in the corresponding reference register to compare to obtain a comparison result, when the error between the measuring result and the corresponding reference value exceeds a preset error range, the comparator outputs a high level, otherwise, the comparator outputs a low level. The N comparators compare the measurement results in the measurement register group in parallel to generate N comparison results, the output ends of the N comparators are connected with the OR gate, the OR gate outputs corresponding results in an OR logic mode on the N comparison results, when at least one comparator outputs high level, namely when the at least one measurement result exceeds a corresponding reference value, the output end of the OR gate outputs high level, the monitoring alarm circuit detects whether the system works abnormally according to the results generated by the OR logic of the internal OR gate on the N comparison results, when the OR gate outputs high level, the system works abnormally, otherwise, the system works normally.
2. The system monitoring circuit includes a reference register and a comparator that serially compares the values in the respective measurement and reference registers. The method can save the number of registers and comparators and save area.
Namely: the system monitoring circuit also comprises a reference register of one channel, and a reference value is stored in the reference register. The monitoring alarm circuit is also connected with a reference register, the monitoring alarm circuit internally comprises a comparator, and the comparator sequentially obtains the measurement results from the measurement registers of the N channels and obtains the reference values from the reference register for comparison to obtain the comparison result. The comparator serially compares the N measurement results, and when the error between the measurement result and the corresponding reference value exceeds a preset error range, the comparator outputs a high level, otherwise, the comparator outputs a low level. The monitoring alarm circuit detects whether the system works abnormally according to the comparison result of the comparator, determines that the system works abnormally when the comparator outputs high level, and otherwise determines that the system works normally and continues to compare the next measurement result.
3. The two methods are relatively general methods, and any one implementation can be selected for various scenes, but in some special cases, a third method exists. When each FPGA die in the multi-die FPGA is the same, the reference register can be directly omitted in the system monitoring circuit, and because the same FPGA dies are arranged, signals of the same monitoring point can be adopted to be mutually referenced. At the moment, the monitoring alarm circuit internally comprises one or a plurality of comparators, one comparator compares the measurement results of the same FPGA bare chips in the measurement register group in pairs in sequence, or the comparators compare the measurement results of the same FPGA bare chips in the measurement register group in pairs at the same time.
In addition, the system monitoring circuit also comprises a read-write control circuit and a configuration register, wherein the read-write control circuit is connected with a JTAG port of the multi-die FPGA and/or any one FPGA die. The read-write control circuit is connected with each register in the system monitoring circuit, comprises a measurement register and a reference register, and can be connected with a high-precision ADC. The JTAG port reads the value of each register in the system monitoring circuit through the read-write control circuit, and the read-write control circuit reads the measurement result in the measurement register so as to export each item of data in the working process of the system, thereby not only obtaining each item of data in the working process of the system, but also reading the measurement result one by one when the system works abnormally to judge the abnormality caused by which measurement result. In addition, the dynamic reconfiguration circuit in the JTAG port and/or the FPGA bare chip carries out write operation on each register in the system monitoring circuit by utilizing the configuration register through the read-write control circuit so as to realize configuration adjustment.
In this application, the type of the working signal of waiting to monitor of the acquisition of system monitoring circuit has a plurality ofly, and the inside working signal of waiting to monitor mainly includes at least one in voltage signal, temperature signal, pressure signal and other sensor signals to can in time react when above-mentioned signal is unusual, prevent the system damage:
the system monitoring circuit is connected with a voltage monitoring point in the FPGA bare chip to acquire a bare chip voltage signal and/or connected with a voltage monitoring point on the silicon connection layer and acquire a power supply voltage signal of the silicon connection layer, wherein the bare chip voltage signal comprises at least one of core voltage, IO voltage, configuration voltage, BRAM voltage and high-speed interface voltage.
And/or the system monitoring circuit is connected with a temperature sensor in the FPGA bare chip to acquire a temperature signal of the bare chip and/or is connected with a temperature sensor on the silicon connecting layer to acquire a temperature signal of the silicon connecting layer.
And/or the system monitoring circuit is connected with a pressure sensor in the FPGA bare chip to acquire a pressure signal of the bare chip and/or connected with a pressure sensor on the silicon connecting layer to acquire a pressure signal of the silicon connecting layer.
And/or the system monitoring circuit is connected with other sensors in the FPGA bare chip to obtain corresponding other sensor signals and/or connected with other sensors on the silicon connecting layer to obtain corresponding other sensor signals, wherein the other sensor signals comprise humidity, sound, speed, concentration, light, radioactive rays, particles, radar waves, electric waves, magnetic waves and gravity.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (12)

1. A multi-die FPGA for realizing system monitoring by utilizing an active silicon connection layer is characterized by comprising a substrate, a silicon connection layer arranged on the substrate in a stacked mode and a plurality of FPGA dies arranged on the silicon connection layer in a stacked mode, wherein the silicon connection layer covers all the FPGA dies;
each FPGA bare chip comprises a plurality of configurable function modules, interconnection resource modules distributed around each configurable function module and a connection point leading-out terminal, each configurable function module in the FPGA bare chip at least comprises a programmable logic unit, a silicon stacking connection module and an input/output port, each silicon stacking connection module comprises a plurality of silicon stacking connection points, each programmable logic unit in the FPGA bare chip is respectively connected with the silicon stacking connection point and the input/output port through the interconnection resource modules, and the silicon stacking connection points are connected with the corresponding connection point leading-out terminals through top metal wires in a rewiring layer; the connection point leading-out terminal in each FPGA bare chip is connected with the corresponding connection point leading-out terminal in other FPGA bare chips through a cross bare chip connection wire in the silicon connection layer, and each FPGA bare chip is connected with any other FPGA bare chip through the cross bare chip connection wire in the silicon connection layer; an input/output port in the FPGA bare chip is connected to the substrate through a silicon through hole on the silicon connecting layer;
the system monitoring circuit is distributed on the silicon connection layer, the input end of the system monitoring circuit is connected with monitoring points in at least one FPGA (field programmable gate array) die and/or monitoring points on the silicon connection layer and acquires a plurality of groups of internal working signals to be monitored, and the system monitoring circuit monitors the working process of the system according to the acquired internal working signals to be monitored; the input end of the system monitoring circuit is connected to the corresponding connection point leading-out end to realize the connection with the monitoring point in the FPGA die; wherein, system monitoring circuit includes multiplexer, high accuracy ADC and measures register group, the multiplexer includes that N input and N input acquire N group respectively and wait to monitor the working signal, the output of multiplexer is connected high accuracy ADC's input, high accuracy ADC's output is connected measure register group, measure register group and include the measurement register of N passageway, high accuracy ADC carries out analog-to-digital conversion to the N group that acquires in proper order and waits to monitor the working signal and stores in the measurement register of N passageway respectively after the measuring result, system monitoring circuit passes through each item measuring result in the measurement register group memory system working process.
2. The multi-die FPGA of claim 1, wherein the input terminal of the system monitoring circuit is further connected to an external port of the multi-die FPGA and obtains an external working signal to be monitored, and the system monitoring circuit monitors the working process of the system according to all the obtained working signals to be monitored.
3. The multi-die FPGA of claim 1 wherein said system monitoring circuitry further comprises a monitoring alarm circuit, said monitoring alarm circuit being connected to said set of measurement registers and detecting whether said system is operating abnormally based on measurements in said set of measurement registers, and determining that said system is operating abnormally and performing a predetermined emergency operation when at least one of said measurements is detected to be outside a predetermined range.
4. The multi-die FPGA of claim 3, wherein the monitoring alarm circuit executes a predetermined emergency operation corresponding to a current abnormality level when a system operation abnormality is detected, and the predetermined emergency operation corresponding to different abnormality levels has different reaction times and/or different operation types.
5. The multi-die FPGA of claim 3 wherein the type of operation of said predetermined contingency operations performed by said monitoring alarm circuitry upon detection of a system operational anomaly comprises issuing an alarm signal and/or controlling the shutting down of power to individual FPGA dies and to said silicon connectivity layer.
6. The multi-die FPGA of claim 3, wherein the system monitoring circuit further comprises a reference register set comprising N channels of reference registers, each channel of reference registers having a reference value stored therein, the monitoring alarm circuit further connected to the reference register set; the monitoring alarm circuit comprises N comparators and an OR gate, a measuring register of one channel, a reference register of one channel and a comparator are respectively corresponding to each other, each comparator respectively obtains a measuring result in the corresponding measuring register and a reference value in the corresponding reference register to compare to obtain a comparison result, the output ends of the N comparators are connected with the OR gate, the N comparators are used for parallelly comparing the measuring results in the measuring register group, the monitoring alarm circuit detects whether the system works abnormally according to the result of the OR gate in the monitoring alarm circuit on the N comparison results or the result generated by logic, and the system works abnormally when the deviation of at least one measuring result and the corresponding reference value exceeds a preset error range.
7. The multi-die FPGA of claim 3, wherein the system monitoring circuit further comprises a reference register of one channel, and a reference value is stored in the reference register, the monitoring alarm circuit is further connected to the reference register, the monitoring alarm circuit internally comprises a comparator, the comparator sequentially obtains the measurement results from the measurement registers of the N channels and obtains the reference value from the reference register for comparison to obtain a comparison result, the comparator serially compares the measurement results in the measurement register set, the monitoring alarm circuit detects whether the system is abnormal according to the comparison result of the comparator, and if the deviation between the currently compared measurement result and the reference value exceeds a predetermined error range, the system is determined to be abnormal.
8. The multi-die FPGA of claim 3, wherein when the FPGA dies inside the multi-die FPGA are the same, the monitoring alarm circuit includes one or more comparators inside, and the comparators compare the measurement results of the corresponding same FPGA die in the measurement register set in pairs in sequence, or the comparators compare the measurement results of the corresponding same FPGA die in the measurement register set in pairs at the same time.
9. The multi-die FPGA of claim 3, wherein the system monitoring circuit further comprises a read-write control circuit and a configuration register, the read-write control circuit is connected to a JTAG port of the multi-die FPGA and/or any one of the FPGA dies, the read-write control circuit is connected to each register inside the system monitoring circuit, the JTAG port reads a value of each register inside the system monitoring circuit through the read-write control circuit, and/or the JTAG port and/or a dynamic reconfiguration circuit inside the FPGA dies configures each register inside the system monitoring circuit through the read-write control circuit by using the configuration register.
10. The multi-die FPGA of claim 1 or 2 wherein the acquired internal operating signals to be monitored of the system monitoring circuitry comprise at least one of voltage signals, temperature signals, pressure signals, and other sensor signals, the operating signals to be monitored being either unipolar inputs or bipolar differential inputs.
11. The multi-die FPGA of claim 10, wherein an input of a system monitor circuit is connected to a monitor point within at least one FPGA die and/or a monitor point on said silicon connection layer and obtains a voltage signal, comprising:
the system monitoring circuit is connected with a voltage monitoring point in an FPGA bare chip to acquire a bare chip voltage signal and/or a voltage monitoring point on a silicon connection layer and a power supply voltage signal of the silicon connection layer, wherein the bare chip voltage signal comprises at least one of core voltage, IO voltage, configuration voltage, BRAM voltage and high-speed interface voltage.
12. The multi-die FPGA of claim 10,
the input end of the system monitoring circuit is connected with at least one FPGA bare chip and/or a temperature sensor on the silicon connection layer and acquires a temperature signal;
and/or the input end of the system monitoring circuit is connected with at least one FPGA bare chip and/or a pressure sensor on the silicon connection layer and acquires a pressure signal;
and/or the input end of the system monitoring circuit is connected with at least one FPGA bare chip and/or other sensors on the silicon connection layer and acquires corresponding other sensor signals, wherein the other sensor signals comprise humidity, sound, speed, concentration, light, radioactive rays, particles, radar waves, electric waves, magnetic waves and gravity.
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