JP2017034095A - Semiconductor element mounting substrate, semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element mounting substrate which allows for further compaction, thinning and higher density mounting, in a semiconductor device where a die pad and a lead are separated by etching from the back, after mounting the semiconductor element on the semiconductor element mounting substrate, and resin sealing, and to provide a semiconductor device and their manufacturing method.SOLUTION: A semiconductor element mounting substrate includes a plurality of leads consisting of a lead metal formed of a semiconductor element mounting region on the conductive substrate surface and the conductive substrate, a lead front plating layer bonded oppositely to the front and back thereof and connectable with the electrode of a mounted semiconductor element, and a lead back plating layer for connection with an external apparatus. The semiconductor element mounting region and the plurality of leads are coupled by a surface coupling metal connecting the lead metals, and the surface coupling metal is provided on the lead surface plating layer side of te lead metal, in seamless structure with the lead metal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor element mounting substrate, a semiconductor device, and manufacturing methods thereof.

In recent years, as represented by mobile phones and the like, downsizing and thinning of electronic devices have been promoted. For this reason, high density, small size, light weight, and high density mounting on a circuit board are also achieved for semiconductor devices used in such electronic devices.
Conventionally, in a semiconductor device, a conductive substrate is etched or pressed to produce a lead frame, a semiconductor element is mounted on the lead frame, connection is made by wire bonding or the like, and then the whole is covered with a sealing resin. A semiconductor device was manufactured. However, a semiconductor device of the type that finally removes the conductive substrate has been proposed for the purpose of reducing the size and weight.

  In such a semiconductor device, a resist mask subjected to predetermined patterning is formed on both sides of a conductive base material, and a conductive metal is provided as a plating layer on the base material exposed from the resist mask by plating. Using the provided plating layer on the surface side as a mask, half-etching from the surface side forms a die pad part for mounting a semiconductor element and a lead part for external connection, and removes the resist mask to remove the semiconductor element mounting board. First form. Then, the semiconductor element is mounted on the formed semiconductor element mounting substrate, and after wire bonding, resin sealing is performed, and the conductive substrate at a predetermined location is removed using the plating layer on the back side as a mask, and the die pad portion and the lead portion Semiconductor devices that have been separated have been developed. For example, Patent Document 1 and Patent Document 2 disclose a semiconductor device of a type that removes such a conductive substrate.

  However, in the semiconductor device of Patent Document 1, after mounting a semiconductor element and sealing with resin, etching is performed using the plating layer on the back side of the lead portion as a mask. At this time, since the conductive substrate in the vicinity of the outer peripheral portion of the back plating layer of the lead portion is also etched, the outer peripheral portion has a bowl shape, and a plating burr defect may occur. In particular, after the resin was sealed, it was likely to occur when the etching amount was large.

In the semiconductor device of Patent Document 2, after mounting a semiconductor element and sealing with resin, a resist mask is formed on the back side of the lead portion, and etching is performed using this resist mask. After the etching process, exterior plating is applied to the exposed portions of the individually separated terminals. For this reason, since the plating layer is not used as an etching mask as in Patent Document 1, the problem of plating burr does not occur.
However, since the outer plating is after terminal separation, the plating method is limited to electroless plating, batch plating, etc., and there are quality problems such as low plating productivity and easily varying plating thickness for each terminal. is there.

JP 2007-150372 A JP 2014-49718 A

  Accordingly, the present invention has been made in view of the above problems, and a semiconductor device in which a semiconductor element is mounted on a substrate for mounting a semiconductor element, and after sealing with a resin, a die pad portion and a lead portion are separated by etching from the back surface. In this case, after the resin sealing, the influence on the plating layer is reduced by minimizing the amount of etching of the conductive substrate, and at the same time, the plating burr failure at the outer peripheral portion of the back plating layer of the lead portion is prevented. Provided are a semiconductor element mounting substrate, a semiconductor device, and a manufacturing method thereof that can be miniaturized, thinned, and mounted with high density.

  A first aspect of the present invention is a semiconductor element mounting substrate on which a semiconductor element can be mounted in a semiconductor element mounting area, and is formed from a semiconductor element mounting area provided on the surface of a conductive substrate and the conductive substrate. A lead metal part, a lead surface plating layer connectable to an electrode of a semiconductor element mounted on a semiconductor element mounting region bonded opposite to the front and back surfaces of the lead metal part, and a lead back plating layer connected to an external device The semiconductor element mounting region and the plurality of lead portions are connected by a surface connection metal portion that connects the lead metal portions constituting the lead portion, and the surface connection metal portion is a lead of the lead metal portion. A semiconductor element mounting substrate, wherein the lead metal portion and the seamless structure are provided on the surface plating layer side.

  According to a second aspect of the present invention, the surface of the lead metal portion on the bonding side with the lead back plating layer in the first invention has a size including the surface of the lead back plating layer on the lead metal portion bonding side. This is a substrate for mounting a semiconductor element.

  According to a third aspect of the present invention, there is provided a semiconductor element mounting substrate, wherein the semiconductor element mounting region in the first and second aspects is formed in a die pad portion having the same configuration as the lead portion.

  According to a fourth aspect of the present invention, there is provided a substrate for mounting a semiconductor element, wherein the semiconductor element mounting region in the first and second inventions is a recessed recess region provided on the surface side of the conductive substrate. is there.

  According to a fifth aspect of the present invention, a semiconductor element, a semiconductor element mounting region, a lead surface plating layer disposed around and electrically connected to the semiconductor element, and an external electrical connection are possible. A lead portion having a lead back plating layer, a bonding wire for electrically connecting the electrode of the semiconductor element and the lead surface plating layer, and the lead surface plating layer, the bonding wire, the semiconductor element, and the semiconductor element mounting region are sealed. A semiconductor device comprising: a first sealing resin; and a second sealing resin that seals at least a side surface of the lead portion and a side surface of the back plating layer.

  A sixth invention of the present invention is the semiconductor device according to the fifth invention, wherein at least the surface of the lead back plating layer is exposed from the second sealing resin.

  According to a seventh aspect of the present invention, there is provided the semiconductor device according to the fifth and sixth aspects, wherein the longitudinal cross-sectional shape of the lead portion is a gentle curve or a taper shape extending from the back surface of the lead portion toward the surface. .

  The eighth invention of the present invention is a semiconductor device characterized in that the first sealing resin and the second sealing resin in the fifth to seventh inventions are the same resin.

  A ninth aspect of the present invention is a semiconductor device characterized in that the semiconductor element mounting region in the fifth to eighth aspects is a die pad portion having the same configuration as the lead portion.

  A tenth invention of the present invention is a semiconductor device characterized in that the bottom surface of the semiconductor element in the fifth to eighth inventions is arranged at a position closer to the bottom surface side of the semiconductor device than the bottom surface of the lead surface plating layer.

The eleventh invention of the present invention is the method for manufacturing a substrate for mounting a semiconductor element according to any one of claims 1 to 3, comprising the following steps (1) to (8) in order. .
(Record)
(1) A conductive substrate preparation step of preparing a conductive substrate.
(2) A first resist coating step of covering both surfaces of the conductive substrate with a first resist.
(3) A first exposure / development step for forming a plating mask having an opening by exposing / developing a predetermined pattern.
(4) Plating / first resist removing step of plating the openings using the plating mask having the openings to form respective front and back plating layers and then removing the plating mask.
(5) A second resist coating step of covering both surfaces of the conductive substrate with the second resist after the plating / first resist removing step.
(6) A second exposure / development step in which a predetermined pattern is exposed / developed to form an etching mask having an opening.
(7) An etching step of forming a recessed region on the back surface of the conductive substrate by etching using the etching mask.
(8) A second resist removing step for removing the etching mask.

  A twelfth aspect of the present invention is the method for manufacturing a substrate for mounting a semiconductor element according to the fourth aspect, comprising the steps (1) to (8) in order, The predetermined pattern in the first exposure / development process is a pattern in which the semiconductor element mounting region on the surface of the conductive substrate is covered with the first resist and the die pad portion surface plating layer is not formed, and the second of (6) The method for manufacturing a substrate for mounting semiconductor elements is characterized in that the predetermined pattern in the exposure / development process is a pattern for forming an opening in a semiconductor element mounting region on the surface of the conductive substrate.

A thirteenth aspect of the present invention is a method for manufacturing a semiconductor device, comprising the following steps (A) to (E) in the fifth to ninth aspects in order.
(Record)
(A) A semiconductor element mounting step of mounting a semiconductor element in a semiconductor element region of a semiconductor element mounting substrate.
(B) A wire bonding step of electrically connecting the electrode portion of the semiconductor element and the lead surface plating layer using a bonding wire.
(C) A first resin sealing step in which a surface of a semiconductor element mounting substrate including a semiconductor element, a bonding wire, and each surface plating layer is resin-sealed with a first sealing resin.
(D) Etching is performed from the back side of the substrate for mounting the semiconductor, and the side surfaces of the metal parts and the surface connection metal parts are simultaneously etched, and the metal parts and the surface connection metal parts are individually divided and electrically Etching process after resin sealing that is in an independent state except for connection.
(E) A second resin sealing step in which the lead portion and the die pad portion are resin-sealed with a second sealing resin so that each back plating layer is exposed on the surface of the second sealing resin.

The present invention creates a recess from the back surface of the conductive substrate, and at the time of etching processing after the first resin sealing, by setting the etching amount of the surface connection metal part and the lead metal part to be substantially the same, It is possible to perform etching at the same time, and by minimizing the amount of etching, the influence on the back plating layer can be reduced.
Further, although the lead back plating layer is used as an etching mask, since etching is started from the side surface of the lead metal part, it is difficult for plating burr to occur in this part, and a plating burr defect can be prevented.

  As a result, in a semiconductor device in which a semiconductor element is mounted on a semiconductor element mounting substrate and the die pad portion and the lead portion are separated by etching from the back surface after resin sealing, the amount of etching of the conductive substrate after resin sealing Minimize the impact on the plating layer and prevent plating burr defects on the outer periphery of the back plating layer of the lead part, while at the same time mounting a semiconductor element that can be downsized, thinned, and mounted at high density And a semiconductor device using the substrate can be provided.

It is sectional drawing which shows an example of 1st Embodiment of the board | substrate for semiconductor element mounting which concerns on this invention. It is sectional drawing which shows an example of 1st Embodiment of the semiconductor device using the board | substrate for semiconductor element mounting of 1st Embodiment concerning this invention. It is sectional drawing which shows an example of 2nd Embodiment of the board | substrate for semiconductor element mounting which concerns on this invention. It is sectional drawing which shows an example of 1st Embodiment of the semiconductor device using the board | substrate for semiconductor element mounting of 2nd Embodiment concerning this invention. It is a figure which shows a series of processes of the manufacturing method of the board | substrate for semiconductor element mounting concerning this invention, (a) is a figure which shows an example of an electroconductive board | substrate preparation process, (b) is an example of a 1st resist coating process. (C) is a figure which shows an example of a 1st exposure and image development process, (d) is a figure which shows an example of a plating and 1st resist removal process. FIG. 5E is a view subsequent to FIG. 5A showing a series of steps of the method for manufacturing a semiconductor element mounting substrate according to the present invention, FIG. 5E is a view showing an example of a second resist coating step, and FIG. 2A and 2B are diagrams showing an example of the exposure / development process 2, FIG. 3G is a diagram showing an example of an etching process, and FIG. 4H is a diagram showing an example of a second resist removal process. It is a figure which shows an example of the manufacturing method of the semiconductor device which concerns on this invention, (a) is a figure which shows an example of a semiconductor element mounting process, (b) is a figure which shows an example of a wire bonding process, (c) is It is a figure which shows an example of a 1st resin sealing process. FIG. 6D is a diagram subsequent to FIG. 6A illustrating an example of a method for manufacturing a semiconductor device according to the present invention, in which FIG. 6D is a diagram illustrating an example of an etching process after resin sealing, and FIG. It is a figure which shows an example of a stop process.

  Hereinafter, a semiconductor element mounting substrate and a semiconductor device according to the present invention will be described with reference to the drawings.

[First Embodiment]
1. FIG. 1 is a diagram showing an example of a semiconductor element mounting substrate (hereinafter also referred to as a lead frame) according to the first embodiment of the present invention. In FIG. 1, 1 is a surface plating layer, 2 is a metal part, 3 is a back surface plating layer, 4 is a recessed part, 10 is a conductive substrate, 11 is a surface connection metal part, 20 is a lead part, and 21 is a lead surface plating layer. , 22 is a lead metal part, 23 is a lead back plating layer, 50 is a die pad part, 51 is a die pad surface plating layer, 52 is a die pad metal part, 53 is a die pad back plating layer, and 100a is the semiconductor element mounting of the first embodiment. A substrate 110 is a semiconductor element mounting region.
As shown in FIG. 1, a semiconductor element mounting substrate 100a according to the first embodiment is connected to a conductive substrate 10, a die pad portion 50 as a semiconductor element mounting region 110, an electrode of a semiconductor element, and externally. It consists of a plurality of lead portions 20 connected to a device (not shown).

  The material of the conductive substrate 10 is not particularly limited as long as conductivity is obtained. For example, copper or a copper alloy is used. After resin sealing with a sealing resin, in order to dissolve and remove a predetermined portion of the conductive substrate 10, copper or a copper alloy that can be selectively dissolved and removed is often used.

  The die pad portion 50 and the lead portion 20 in the semiconductor element mounting substrate 100a are formed by placing the surface plating layer 1 formed by electroplating on the conductive substrate 10 and the surface plating layer 1 on the back side of the conductive substrate 10. The metal portion 2 is formed by etching from the back surface, and the back surface plating layer 3 is formed on the back surface side of the conductive substrate 10 by electroplating.

The type of plating metal used for the lead surface plating layer 21 constituting the lead part 20 is not particularly limited, but is selected in consideration of the following points.
Since the uppermost surface of the lead surface plating layer 21 includes an internal electrode portion connected by wire bonding to the electrode of the semiconductor element, a plating metal suitable for the bonding wire connection is selected. For example, in the case of an Au wire, Ag plating, Au plating, Pd plating, or the like is preferable.

  Since the lead back plating layer 23 includes an external electrode portion connected to an external device, a plating metal suitable for connection to the external device is selected. Since there are generally many solder-based alloys such as solder balls for connection to external devices, Au (gold) plating, Pd plating, etc., which have good solder wettability and good bondability with solder, are preferable.

Furthermore, since the surface plating layer 1 and the back surface plating layer 3 are generally formed by performing electroplating simultaneously, the same plating configuration is desirable. For example, multilayer plating in which Ni, Pd, and Au are laminated in this order outside the contact surface of the conductive substrate may be used.
Further, the types of plating of the front plating layer 1 and the back plating layer 3 may be different. For example, the surface may be Ag plating with good bonding properties, and the back surface may be laminated plating in which Ni, Pd, and Au are laminated in order of good solder wettability.

  Furthermore, in the etching process after the first resin sealing in the manufacturing process of the semiconductor device, in order to prevent the lead portion from being disconnected, the vertical cross-sectional shape of the surface plating layer is changed from a normal rectangular shape to an inverted trapezoidal shape. Adhesiveness with the sealing resin may be improved. In this case, in the exposure step shown in FIG. 5-1 (c) described later, the ultraviolet light used for exposure is changed from parallel light to scattered light, and irradiation can be performed for exposure. Moreover, the same effect can be obtained even if the plating surface is roughened.

A lead back plating layer 23 is formed on the opposite side of the lead surface plating layer 21 to the conductive substrate. Further, a plurality of lead metal portions 22 are formed by providing the recessed portions 4 by etching from the back side.
On the other hand, since the surface side of the conductive substrate 10 is not etched and no depression is formed, the surface connection metal portion 11 that is seamlessly connected to the die pad metal portion 52 and the lead metal portion 22 is formed over the entire material surface.
The lead metal portion 22 is mounted with a semiconductor element and sealed with resin, and then etching the side surface of the lead metal portion and the corresponding portion of the surface connection metal portion (range located at the tip of the recess portion 4) by etching. , Make each independent.

  The depth of the recess 4 to be provided is from 1/2 the plate thickness to -0.03 mm plate thickness. If the depth of the dent is less than 1/2 of the plate thickness, the amount of etching processing after resin sealing increases, the etching time becomes longer, and the etching solution dissolves part of the plating layer. It becomes easy to do. If the plate thickness exceeds -0.03 mm, the strength of the surface connection metal part is weak, and deformation defects may occur during transportation. The plate thickness is preferably -0.05 mm to plate thickness -0.03 mm.

In addition, the size of the lead metal part 22 is a size including the lead back plating layer from the outer periphery of the lead back plating layer 23 to the outer periphery increased from 1/2 of the plate thickness to the plate thickness −0.03 mm. Is desirable.
Similarly to the surface connection metal part 11, the side surface of the lead metal part 22 is etched after the resin sealing, so that it is increased by the amount etched in the same manner.

2. Semiconductor Device Next, a semiconductor device using the semiconductor element mounting substrate as a lead frame will be described with reference to FIG. In FIG. 2, 5 is a bonding wire, I is the semiconductor device of the first embodiment, 101 is a semiconductor element, 102 is a first sealing resin, and 103 is a second sealing resin.

The semiconductor device I according to the first embodiment of the present invention mounts the semiconductor element 101 in the semiconductor element mounting region 110 using the semiconductor element mounting substrate.
In FIG. 2, a case where a die pad portion is formed and a semiconductor element is mounted thereon will be described. In addition, a type in which a semiconductor element mounting area is secured and a die pad part is not formed, for example, in the flip chip method, instead of wire bonding, the lead part and the electrode part of the semiconductor element are directly connected, and the semiconductor element is placed on the lead part. May be installed.

2, the semiconductor element 101 is mounted on the die pad surface plating layer 51, and the electrode portion (not shown) of the semiconductor element and the lead surface plating layer 21 are electrically connected by a bonding wire 5 or the like. A lead back plating layer 23 is formed on the opposite side of the lead surface plating layer 21.
Further, the semiconductor element, the bonding wire, and the lead surface plating layer are sealed with the first sealing resin 102.

Thereafter, the sealed lead frame is etched from the back surface side to form a lead metal portion 22 to make the lead portion 20 independent.
In this etching process, each lead part is separated and independent by etching the surface connection metal part 11 and the side surfaces of the lead metal part 22 in the lead frame of FIG.
The die pad portion 50 is similar to the lead portion when the back plating layer is formed, and becomes a thin portion by etching from the back surface when the back plating layer is not formed. In other words, since there is no exposure from the second sealing resin 103, it is effective for a semiconductor device or the like that places importance on the moisture resistance of the semiconductor element. Furthermore, since the die pad part 50 is not exposed from the second sealing resin 103, there is no risk of contact with an external device. FIG. 2 shows a case where the die pad back surface plating layer 53 is provided.

As described in Patent Document 1, when the surface is etched and recessed, and after the resin is sealed with the back surface being flat, the etching is performed only from the back surface side of the conductive substrate when the back surface plating layer is used as a mask. For this reason, the etching time becomes long, and there may be a problem that the etching solution dissolves a part of the plating layer.
Also, the lead back plating layer is used as an etching mask. Etching is started from the back surface, and the conductive substrate around the back plating layer is etched faster and the dissolution time becomes longer than the back plating layer. Is etched, and the back surface plating layer has a bowl shape, which causes a problem that it becomes a plating burr.

In the present invention, the etching process after the resin sealing is indented from the back side as shown in FIG.
The lead back plating layer 23 is used as an etching mask. However, since the lead back plating layer 23 is mainly etched from the side surface of the lead, generation of burrs on the lead back plating layer 23 can be prevented. In addition, the amount of etching after sealing can be minimized by adjusting the amount of depression at the lead frame manufacturing stage.
Further, even in the first resin sealing, in the case of the present invention, since the surface of the conductive substrate is flat except for the surface plating layer and there is no depression on the surface as in Patent Document 1, there is no void or resin leakage. There are few malfunctions.

In addition, the vertical cross section, which is the vertical cross section of the lead part, has the same curve as the etching direction at the lead frame and the etching direction after resin sealing. It has become. This shape prevents the lead part from coming off from the sealing resin after the second resin sealing.
Further, at least the side surface of the lead back plating layer 23 and the lead metal part 22 are covered with the second sealing resin 103, and the lead back plating layer 23 is exposed from the second sealing resin 103. In the semiconductor device disclosed in Patent Document 1, a part of the side surface of the lead metal part is exposed from the sealing resin part and is not plated, so that troubles such as discoloration are likely to occur. Then, since it exists in the 2nd sealing resin part, generation | occurrence | production of the same malfunction does not occur.
The first sealing resin 102 and the second sealing resin 103 may be of the same type or different.
In general, for example, in the case of an optical semiconductor device, the first sealing resin 102 is sealed with a transparent resin, and the second sealing resin 103 is sealed with a resin that reflects light. For example, different resins may be used.

[Second Embodiment]
1. Next, a second embodiment will be described with reference to FIGS. 3 and 4. FIG. 3 and 4, reference numeral 100b denotes a semiconductor element mounting substrate according to the second embodiment, II denotes a semiconductor device according to the second embodiment, 5 denotes a bonding wire, 6 denotes a recess provided in the semiconductor mounting area, and 60 denotes insulation. The other reference numerals are the same as in FIGS.
FIG. 3 is a diagram showing a second embodiment of a semiconductor element mounting substrate according to the present invention. The semiconductor element mounting substrate 100b is a die pad portion surface plating layer in the semiconductor mounting substrate 100a of the first embodiment. The recess 6 is formed from the surface side of the conductive substrate 10 without being formed, and the bottom of the recess is used as a semiconductor element mounting region.

2. Semiconductor Device FIG. 4 is a diagram showing a second embodiment of the semiconductor device according to the present invention. In the semiconductor device II, as shown in FIG. 4, the semiconductor element 101 is insulatively bonded to the semiconductor element mounting region 110 of the recess 6. It is fixed with agent 60 or the like.
Compared to the first embodiment (see FIG. 2, reference numeral I), the semiconductor element mounting region 110 is a recess 6, so that the mounting position of the semiconductor element can be further lowered, and the thickness of the entire semiconductor device is reduced. Making it possible.

[Manufacturing method of semiconductor element mounting substrate]
Next, a method for manufacturing a semiconductor element mounting substrate according to the present invention will be described using the substrate 100a of the first embodiment. Here, a case where a die pad portion is formed and a semiconductor element is mounted thereon will be described. However, a case where a semiconductor region is secured and a die pad portion is not formed will be described each time.

  (A) to (h) shown in FIGS. 5-1 and 5-2 are views showing the first half steps in an example of the method for manufacturing the semiconductor element mounting substrate 100a according to the present invention. In the following description, the same constituent elements as those described above are denoted by the same reference numerals as those described above, and the description thereof is omitted. In FIGS. 5A and 5B, 160 and 161 are first resists provided on both surfaces of the conductive substrate 10, 163 is an opening of the first resist, 165 and 166 are second resists, and 168. Is the opening of the second resist, and the other symbols are the same as in FIGS.

[Conductive substrate preparation process]
FIG. 5A is a diagram illustrating a conductive substrate preparation process.
In the conductive substrate preparation step, the conductive substrate 10 is prepared.
The material of the conductive substrate 10 is not particularly limited as long as conductivity is obtained, but a Cu alloy is generally used.

[First resist coating step]
FIG. 5B is a diagram illustrating a first resist coating process.
In the first resist coating step, both surfaces of the conductive substrate 10 are covered with the first resists 160 and 161. As the resists 160 and 161 to be used, a conventional method such as laminating a dry film resist or applying a liquid resist to both surfaces of the conductive substrate 10 can be used.

[First exposure / development process]
FIG. 5C is a diagram showing a first exposure / development process.
In the first exposure step, exposure masks having a predetermined pattern are placed above and below the first resists 160 and 161 in an exposure apparatus (not shown), and exposure is performed by irradiating ultraviolet light. In addition, the pattern of the exposure mask is prepared so that the lead surface plating layer and the die pad surface plating layer are formed on the front surface, and the lead back surface plating layer and the die pad back surface plating layer are formed on the back surface. As a result, unexposed portions (FIG. 5-1 (c), positions of openings indicated by reference numeral 163) are formed in the first resists 160 and 161.
Next, in the first development step, the unexposed portions of the resists 160 and 161 are removed, and the opening 163 is formed. Thereby, a part of the conductive substrate 10 is exposed from the opening 163. As described above, the resist 160 having the opening 163 and the resist 161 are configured as a plating mask.
Moreover, when forming a recessed part in a semiconductor element mounting area, it is set as the pattern which does not form a die pad surface plating layer.

[Plating / first resist removal process]
FIG. 5A is a diagram illustrating a plating / first resist removing step.
Using the resist 160 and the resist 161 formed in the first development step shown in FIG. 5-1 (c) as plating masks, plating is performed on the openings not covered with the mask, and the lead surface plating layer 21 and the die pad surface A lead back plating layer 23 and a die pad back plating layer 53 are formed on the plating layer 51 and the back surface.
Thereafter, the resist formed as the plating mask is peeled off. Note that the first resist stripping may be performed using, for example, a liquid resist stripper.
By this first resist peeling, the resists 160 and 161 (see FIG. 5A (d)) are removed, and the surface plating layers 21 and 51 and the back surface plating layers 23 and 53 are formed on the conductive substrate 10. It will be in the formed state.

[Second resist coating step]
FIG. 5E is a diagram illustrating an example of a second resist coating process.
In the second resist coating step, the front surface plating layers 21 and 51 and the back surface plating layers 23 and 53 are provided in the previous step, and both surfaces of the conductive substrate 10 are covered with the second resists 165 and 166.
As the second resists 165 and 166 to be used, a conventional method such as laminating a dry film resist or applying a liquid resist is used as in the first resist coating step described in FIG. Can do.

[Second exposure / development process]
FIG. 5B is a diagram illustrating an example of the second exposure / development process.
In the second exposure step, exposure masks (not shown) are respectively provided above and below the second resists 165 and 166 in an exposure apparatus (not shown), and exposure is performed with ultraviolet light.
The exposure mask used in the second exposure step covers the entire surface of the conductive substrate on which the surface plating layers 21 and 51 are formed, and the back surface includes the lead back surface plating layer 23 and the die pad portion back surface plating layer 53. Then, a pattern is formed so as to be covered with a mask.

Note that the size of the mask is set to be approximately equal to the thickness of the surface coupling metal portion on one side from the lead back plating layer and the die pad back plating layer. Preferably, it is 0.03 m to 0.05 mm. This is because the etching process is completed almost simultaneously with the etching process after resin sealing.
Further, when the die pad portion is not exposed from the second sealing resin, a pattern is formed so as not to form the die pad back surface plating layer.

  In the second developing step to be performed next, the unexposed portion is removed, and second resists 166 and 165 having openings 168 are formed as etching masks.

[Etching process]
FIG. 5-2 (g) is a diagram illustrating an example of an etching process in which etching is performed from the back surface.
In the etching step, the recess 4 is formed by etching the back surface of the conductive substrate 10 with an etching solution using the etching mask formed from the second resists 165 and 166 in FIG. The formed depressions form parts that become lead metal parts, die pad metal parts, and surface connection metal parts.

[Second resist removal step]
FIG. 5-2 (h) is a step of removing the second resist. The second resist removal may be performed using, for example, a liquid resist remover. Thereafter, if necessary, the sheet may be cut into a predetermined size.
The semiconductor element mounting substrate 100a according to the present invention is completed by the steps (a) to (h) described above.

[Method for Manufacturing Semiconductor Device]
Next, a method for manufacturing a semiconductor device using the semiconductor element mounting substrate of the present invention will be described with reference to FIG. 6A and 6B are schematic diagrams illustrating an example of a method for manufacturing a semiconductor device according to the embodiment of the present invention. The reference numerals in FIG. 6 are the same as those in FIGS.

[Semiconductor element mounting process]
FIG. 6A is a diagram illustrating an example of a semiconductor element mounting process.
In the semiconductor element mounting step, the semiconductor element 101 is mounted on the semiconductor element mounting region 110 of the semiconductor element mounting substrate 100a. When there is a die pad portion, the semiconductor element 101 is mounted using Ag paste or the like (not shown). When the concave portion is formed in the die pad portion, the semiconductor element 101 is mounted via an insulating adhesive layer (not shown) such as an insulating paste or a die attach film.

[Wire bonding process]
FIG. 6B is a diagram illustrating an example of a wire bonding process.
In the wire bonding step, an electrode portion (not shown) of the semiconductor element 101 and the lead surface plating layer 21 are electrically connected using the bonding wire 5 or the like.

[First resin sealing step]
FIG. 6C is a diagram illustrating an example of the first resin sealing step.
In the first resin sealing step, the surface of the conductive substrate 10 including the semiconductor element 101, the bonding wire 5, the lead surface plating layer 21, and the die pad surface plating layer 51 is resin sealed with the first sealing resin 102. Is done.

[Etching process after resin sealing]
FIG. 6D is a diagram illustrating an example of an etching process after the first resin sealing.
In the etching process after resin sealing, etching is performed from the back side of the conductive substrate, the side surface of the lead metal part 22, the surface connection metal part (refer to FIG. 6-1 (c), reference numeral 11), the die pad metal part. The side surfaces of 52 are etched simultaneously. At this time, the vertical cross-sectional shape of the lead portion 20 (actually, the lead metal portion 22) is set to a gentle curve or a taper shape extending from the back surface of the lead portion toward the surface.

  By this etching, each part is individually divided, and each part becomes an independent form except for connection by wire bonding or the like. It is desirable that the etching amount is set so that the etching amount to each part becomes the same in the “etching step” shown in FIG. 5-2 (g), and the etching is completed simultaneously in a minimum time. .

  Further, when the die pad portion 50 does not have the back surface plating layer and includes the die pad metal portion 52, the back surface side is etched simultaneously with each side surface to form a thin portion.

[Second resin sealing step]
FIG. 6E is a diagram illustrating an example of the second resin sealing step.
In the second resin sealing step, the lead part 20, the die pad part 50, and the like are resin-sealed with the second sealing resin 103, and the lead back plating layer 23 and the die pad back face are formed on the surface of the second sealing resin 103. The plating layer 53 is exposed. Further, when the die pad portion does not have a back plating layer and has a die pad metal portion, the thin portion is formed by etching in the “etching step after resin sealing” in FIG. There is no exposure from the stop resin part and it is in the resin, so there is no risk of contact with external equipment.

  Next, individual semiconductor devices are obtained by cutting into a predetermined shape. In addition, the cutting does not have a metal part in a cutting location, but is all resin parts, and the cutting load is reduced.

  Regarding the second embodiment of the semiconductor element mounting substrate (see FIG. 3, reference numeral 100b), as described above, the mask pattern in the steps shown in FIGS. 5-1 (c) and 5-2 (f). It is possible to produce by changing.

Moreover, it is also possible to change the kind of plating of a surface plating layer and a back surface plating layer.
In this case, it can manufacture by performing the process of FIGS. 5-1 (b) to 5-1 (d) twice on the surface plating side and the back surface plating side.

  In addition, in order to prevent the lead portion from being disconnected in the etching process after sealing shown in FIGS. 6A and 6B in manufacturing the semiconductor device, the cross-sectional shape of the surface plating layer is changed from a normal rectangular shape to an inverted trapezoidal shape. In addition, the adhesion with the first sealing resin may be enhanced. In this case, in the exposure step of FIG. 5-1 (c), the ultraviolet light used for the exposure can be changed to the scattered light, and irradiation and exposure can be performed. Furthermore, the same effect can be obtained even if the plating surface is roughened.

  Hereinafter, the present invention will be described in detail using examples.

As a conductive substrate, a Cu plate having a thickness of 0.2 mm (Furukawa Electric Co., Ltd .: EFTEC64-T) is processed into a long plate shape having a width of 140 mm, and then a photosensitive dry film resist having a thickness of 0.025 mm. Was attached to both surfaces of the conductive substrate.
In a pattern-aligned state, a glass mask with a desired pattern to be a lead surface plating layer and die pad surface plating layer on the surface of the conductive substrate with the resist applied and a lead back surface plating layer and die pad back surface plating layer on the back surface is aligned. Covered on the front and back surfaces, both surfaces were exposed to ultraviolet light through the glass mask.

After the exposure, the dry film resist was developed with a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed due to the irradiation of ultraviolet light.
After the development, plating was performed on the portion where the dry film was dissolved and the metal surface of the conductive substrate was exposed. Plating was carried out in order from the exposed surface of the substrate with a Ni plating thickness of 3.0 μm, a Pd plating thickness of 0.1 μm, and an Au plating thickness of about 0.04 μm.

Next, the dry film resist was peeled off with a sodium hydroxide solution. Thereby, it forms in the state provided with the plating layer on the front and back of a conductive substrate.
Thereafter, a photosensitive dry film resist having a thickness of 0.025 mm was attached to both surfaces of the conductive substrate on which the plating layer was formed.

Next, a glass film on which a desired pattern is formed so that the front side of the substrate covers the entire surface including the surface plating layer and the back side covers 0.05 mm larger than the lead back plating layer and the die pad back plating layer on a dry film is dry film. It was covered with a resist and exposed to ultraviolet light.
Thereafter, the dry film resist was developed with a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed to ultraviolet light irradiation.

  After the development process, the resist remaining after development was used as a mask, and selective etching was performed from the back side with a ferric chloride solution to produce a recessed region 4 having a depth of 0.15 mm on the conductive substrate. By this etching process, a lead metal part, a die pad metal part, and a portion to be a surface connection metal layer were formed. Then, the semiconductor element mounting substrate which concerns on Example 1 of 1st Embodiment was produced by cut | disconnecting to a predetermined dimension.

Next, using the produced semiconductor element mounting substrate, a semiconductor element is mounted on the die pad surface plating layer of the semiconductor element mounting substrate using Ag paste, and the electrode portion of the semiconductor element and the lead surface plating layer are wired. After being connected by bonding, the surface on which the semiconductor element is mounted was resin-sealed and molded using a first sealing resin. Thereafter, the lead back plating layer and the die pad back plating layer were used as a mask, and the surface connecting metal portion, the side surface of the lead metal portion, and the side surface of the die pad metal portion were simultaneously etched to make each portion independent. Then, each part of the independent state was resin-sealed and molded with a second sealing resin.
The first sealing resin and the second sealing resin were the same type.

  Finally, the semiconductor device according to Example 1 of the first embodiment was completed by cutting to a predetermined semiconductor device size.

The substrate for mounting a semiconductor element according to Example 2 is shown in FIG. 3 in which the die pad portion surface plating layer described in the second embodiment is not formed, and the concave portion is formed on the die pad portion from the surface side.
The concave portion is formed by forming a pattern so that the die pad portion is covered with the resist when the first resist pattern is formed, and when the second resist pattern is formed, the die pad portion region becomes an opening portion on the surface side. A pattern was prepared.
In the next etching step, since the die pad area was an opening, a recess was formed at a depth of 0.15 mm from the surface side.

  A semiconductor device according to Example 2 of the second embodiment was manufactured by using the manufactured semiconductor element mounting substrate in the same manner as in the example. In the semiconductor element mounting step, the semiconductor element was mounted in the recess using an insulating adhesive.

Using the semiconductor devices produced in Example 1 and Example 2, the occurrence of plating peeling and plating burrs on the lead back plating layer was observed with an optical microscope.
In the semiconductor devices of Example 1 and Example 2, it was confirmed that the lead back plating layer was good without any plating peeling or plating burr.

DESCRIPTION OF SYMBOLS 1 Surface plating layer 2 Metal part 3 Back surface plating layer 4 Indentation part 5 Bonding wire 6 Recess 10 provided in the semiconductor mounting area Conductive substrate 11 Surface connection metal part 20 Lead part 21 Lead surface plating layer 22 Lead metal part 23 Lead back surface Plating layer 50 Die pad portion 51 Die pad surface plating layer 52 Die pad metal portion 53 Die pad back surface plating layer 60 Insulating adhesive 100a Semiconductor device mounting substrate 100b of the first embodiment Semiconductor device mounting substrate 101 of the second embodiment Semiconductor Element 102 First sealing resin 103 Second sealing resin 110 Semiconductor element mounting region 160, 161 First resist 163 provided on both surfaces of conductive substrate 10 First resist openings 165, 166 Second Resist 168 Second resist opening I Semiconductor device of first embodiment
II Semiconductor device of the second embodiment

Claims (13)

A semiconductor element mounting substrate capable of mounting a semiconductor element in a semiconductor element mounting area,
A semiconductor element mounting region provided on the surface of the conductive substrate;
A lead metal part formed from the conductive substrate, a lead surface plating layer connectable to an electrode of a semiconductor element mounted in the semiconductor element mounting region bonded to the front and back surfaces of the lead metal part, and an external device With multiple lead parts consisting of a lead back plating layer connected to
The semiconductor element mounting region and the plurality of lead parts are connected by a surface connecting metal part that connects the lead metal parts constituting the lead part,
The substrate for mounting a semiconductor element, wherein the surface connection metal part is provided on the lead surface plating layer side of the lead metal part in a seamless structure with the lead metal part.   2. The semiconductor element according to claim 1, wherein a surface of the lead metal portion on the side of joining with the lead back plating layer includes a size including the surface of the lead back surface plating layer on the lead metal portion joining side. Mounting board.   3. The semiconductor element mounting substrate according to claim 1, wherein the semiconductor element mounting region is formed in a die pad part having the same configuration as the lead part. 4.   3. The semiconductor element mounting substrate according to claim 1, wherein the semiconductor element mounting region is a concave-shaped depression region provided on a surface side of the conductive substrate. A semiconductor element, and the semiconductor element mounting region;
A lead portion having a lead surface plating layer disposed around and electrically connected to the semiconductor element; and a lead back plating layer capable of being electrically connected from the outside;
A bonding wire for electrically connecting the electrode of the semiconductor element and the lead surface plating layer;
A first sealing resin for sealing the lead surface plating layer, the bonding wire, the semiconductor element, and the semiconductor element mounting region;
A semiconductor device comprising: a second sealing resin that seals at least a side surface of the lead portion and a side surface of the back plating layer.   6. The semiconductor device according to claim 5, wherein at least a surface of the lead back plating layer is exposed from the second sealing resin.   7. The semiconductor device according to claim 5, wherein the vertical cross-sectional shape of the lead portion is a gentle curve extending from the back surface of the lead portion toward the front surface or a tapered shape.   The semiconductor device according to claim 5, wherein the first sealing resin and the second sealing resin are the same resin.   The semiconductor device according to claim 5, wherein the semiconductor element mounting region is a die pad portion having the same configuration as the lead portion.   9. The semiconductor device according to claim 5, wherein a bottom surface of the semiconductor element is disposed at a position closer to a bottom surface side of the semiconductor device than a bottom surface of the lead surface plating layer. 4. The method for manufacturing a semiconductor element mounting substrate according to claim 1, comprising the following steps (1) to (8) in order: 5.
(Record)
(1) A conductive substrate preparation step of preparing a conductive substrate.
(2) A first resist coating step of covering both surfaces of the conductive substrate with a first resist.
(3) A first exposure / development step for forming a plating mask having an opening by exposing / developing a predetermined pattern.
(4) Plating / first resist removing step of plating the openings using the plating mask having the openings to form respective front and back plating layers and then removing the plating mask.
(5) A second resist coating step of covering both surfaces of the conductive substrate with the second resist after the plating / first resist removing step.
(6) A second exposure / development step in which a predetermined pattern is exposed / developed to form an etching mask having an opening.
(7) An etching step of forming a recessed region on the back surface of the conductive substrate by etching using the etching mask.
(8) A second resist removing step for removing the etching mask. The method for manufacturing a semiconductor element mounting substrate according to claim 4, comprising the steps (1) to (8) in order.
The predetermined pattern in the first exposure / development step of (3) is a pattern in which the semiconductor element mounting region on the surface of the conductive substrate is covered with the first resist and the die pad surface plating layer is not formed.
The predetermined pattern in the second exposure / development step (6) is a pattern for forming an opening in a semiconductor element mounting region on the surface of the conductive substrate. Method. 10. The method for manufacturing a semiconductor device according to claim 5, further comprising the following steps (A) to (E) in order.
(Record)
(A) A semiconductor element mounting step of mounting a semiconductor element in a semiconductor element region of a semiconductor element mounting substrate.
(B) A wire bonding step of electrically connecting the electrode portion of the semiconductor element and the lead surface plating layer using a bonding wire.
(C) A first resin sealing step in which a surface of a semiconductor element mounting substrate including a semiconductor element, a bonding wire, and each surface plating layer is resin-sealed with a first sealing resin.
(D) Etching is performed from the back side of the substrate for mounting the semiconductor, and the side surfaces of the respective metal parts and the surface connection metal part are simultaneously etched to divide each of the metal parts and the surface connection metal part individually for electrical connection. Etching process after resin sealing to make independent except.
(E) A second resin sealing step in which the lead portion and the die pad portion are resin-sealed with a second sealing resin so that each back plating layer is exposed on the surface of the second sealing resin.

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