JP2017034094A - Semiconductor element mounting substrate, semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor element mounting substrate capable of compaction, thinning and high density mounting, while reducing the impact on a plating layer by minimizing the amount of a conductive substrate to be dissolved and removed, and preventing the plating burrs on the outer periphery of an external terminal back plating layer, and to provide a semiconductor device and a manufacturing method therefor.SOLUTION: A semiconductor element mounting substrate 100a has, on the front of a conductive substrate 10, an element mounting region 110, an internal terminal front plating layer 21 on the periphery thereof, an external terminal front plating layer 41 placed farther from the element mounting region than the internal terminal, and a wiring front plating layer 31 placed between opposite surface plating layers, and connecting them electrically. On the back, an external terminal back plating layer 43 is provided at a position facing the external terminal front plating layer, and at least from the back toward the front, a non-penetration depression region forming the metal parts 22, 32, 42, 52 of the conductive substrate is provided along the cross section shape of the front plating layers 21, 31, 41 and external terminal back plating layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor element mounting substrate, a semiconductor device, and manufacturing methods thereof.

In recent years, as represented by mobile phones and the like, downsizing and thinning of electronic devices have been promoted. For this reason, high density, small size, light weight, and high density mounting on a circuit board are also achieved for semiconductor devices used in such electronic devices.
Conventionally, in a semiconductor device, a conductive substrate is etched or pressed to produce a lead frame, a semiconductor element is mounted on the lead frame, connection is made by wire bonding or the like, and then the whole is covered with a sealing resin. A semiconductor device was manufactured.
However, a semiconductor device of the type that finally removes the conductive substrate has been proposed for the purpose of reducing the size and weight.

In such a semiconductor device, a resist mask subjected to predetermined patterning is formed on both sides of a conductive base material, and a conductive metal is provided as a plating layer on the base material exposed from the resist mask by plating. Using the provided plating layer on the surface side as a mask, half-etching from the surface side forms a die pad part for mounting a semiconductor element and a lead part for external connection, and removes the resist mask to remove the semiconductor element mounting board. First form.
Then, the semiconductor element is mounted on the formed semiconductor element mounting substrate, and after wire bonding, resin sealing is performed, and the conductive substrate at a predetermined location is removed using the plating layer on the back side as a mask, and the die pad portion and the lead portion Semiconductor devices that have been separated have been developed.

For example, Patent Document 1 discloses a semiconductor device that removes such a conductive substrate.
Further, in Patent Document 2 in which these semiconductor devices have been miniaturized, thinned, and simultaneously mounted with high density, using a method such as removing the substrate after sealing the above wiring layer with a sealing resin, A Fan-In type semiconductor device in which an external terminal is also arranged below the die pad portion is disclosed.

  However, in the semiconductor devices of Patent Document 1 and Patent Document 2, after the semiconductor element is mounted and resin-sealed, etching is performed using the plating layer on the back surface side of the external terminal portion as a mask. Since the conductive substrate in the vicinity of the outer peripheral portion of the back surface plating layer of the external terminal portion is also etched, the outer peripheral portion has a bowl shape, which may cause a plating burr defect. In particular, when the amount of etching is large after resin sealing, it is likely to occur.

  Furthermore, in Patent Document 2, through holes are formed by etching from the side of the wiring layer between the external terminal and the internal terminal for the purpose of improving the adhesion between the terminal portion and the sealing resin, but etching from the side is performed. Controlling the amount is difficult and requires advanced management.

JP 2007-150372 A JP 2014-86486 A

  Accordingly, the present invention has been made in view of the above problems, and a semiconductor device in which a semiconductor element is mounted on a substrate for mounting a semiconductor element, and after sealing with a resin, a die pad portion and a lead portion are separated by etching from the back surface. In this case, after the resin sealing, the influence on the plating layer is reduced by minimizing the amount of etching of the conductive substrate, and at the same time, the plating burr failure at the outer peripheral portion of the external terminal back surface plating layer is prevented. Provided are a semiconductor element mounting substrate, a semiconductor device, and a manufacturing method thereof that can be miniaturized, thinned, and mounted with high density.

  According to a first aspect of the present invention, there is provided a semiconductor element mounting substrate on which a semiconductor element can be mounted in a predetermined semiconductor element mounting area, the semiconductor element mounting area and the semiconductor element mounting area on the surface of the conductive substrate. Internal terminal surface plating layer that is arranged around and electrically connected to the electrode of the semiconductor element mounted in the semiconductor element mounting area, and the external terminal surface that is disposed around the semiconductor element from the semiconductor element mounting area A conductive layer having a plating layer and a wiring surface plating layer disposed between the internal terminal surface plating layer and the external terminal surface plating layer to electrically connect the internal terminal surface plating layer and the external terminal surface plating layer; An external terminal back plating layer that is electrically connected to an external device at a position facing the external terminal surface plating layer with the conductive substrate interposed therebetween, and at least the back surface of the conductive substrate From the surface toward the surface, the internal terminal metal part, the wiring metal part, and the external terminal metal part of the conductive substrate along the substantially planar shape of the internal terminal surface plating layer, the wiring surface plating layer, and the external terminal front and back plating layers A semiconductor element mounting substrate comprising a non-penetrating recess region forming a portion.

  According to a second aspect of the present invention, a part of the non-penetrating recessed area in the first aspect includes a semiconductor element mounting area, an internal terminal surface plating layer, and an area on the back side of the conductive substrate of the wiring surface plating layer. This is a substrate for mounting a semiconductor element.

  According to a third aspect of the present invention, the semiconductor element mounting region provided on the surface of the conductive substrate in the first and second aspects is a recessed region directed from the front surface side to the back surface side of the conductive substrate. The semiconductor element mounting substrate.

  In the fourth invention of the present invention, the shape of the cross section of the external terminal metal part on the external terminal back plating layer side of the external terminal metal part in the first to third inventions is a size including the shape of the external terminal back plating layer. This is a substrate for mounting a semiconductor element.

  According to a fifth aspect of the present invention, there is provided an internal terminal having a semiconductor element, an internal terminal surface plating layer disposed around the semiconductor element and electrically connectable to an electrode portion of the semiconductor element, and the internal terminal. An external terminal having an external terminal back plating layer that is arranged away from the periphery of the semiconductor element and electrically connected to an external device, a wiring part that electrically connects the internal terminal and the external terminal, and an electrode of the semiconductor element A bonding wire for electrically connecting the internal terminal surface plating layer of the internal terminal and the internal terminal surface plating layer, each surface of the internal terminal surface plating layer, the external terminal surface plating layer and the wiring surface plating layer, and the bonding wire and the semiconductor element are sealed. A semiconductor device comprising: a first sealing resin that seals; and a second sealing resin that seals at least the side surface of the external terminal metal part and the side surface of the external terminal back surface plating layer.

  The sixth invention of the present invention is characterized in that the internal terminal, the external terminal, and the wiring portion in the fifth invention are connected by at least an internal terminal surface plating layer, an external terminal surface plating layer, and a wiring surface plating layer. This is a semiconductor device.

  A seventh invention of the present invention is a semiconductor device characterized in that at least the external terminal back plating layer in the fifth and sixth inventions is exposed from the second sealing resin.

  An eighth invention of the present invention is a semiconductor device characterized in that the shape of the longitudinal section of the external terminal metal part in the fifth to seventh inventions is a gentle curve or a taper shape extending from the back surface to the surface direction. is there.

  A ninth invention of the present invention is a semiconductor device characterized in that the first sealing resin and the second sealing resin in the fifth to eighth inventions are the same resin.

  According to a tenth aspect of the present invention, there is provided a semiconductor device characterized in that a plurality of external terminals are arranged immediately below the semiconductor element mounting region in the fifth to ninth aspects.

  An eleventh invention of the present invention is a semiconductor device characterized in that the bottom surface of the semiconductor element in the fifth to ninth inventions is disposed at a position lower than the bottom surface of the internal terminal surface plating layer.

A twelfth aspect of the present invention is the method for manufacturing a substrate for mounting a semiconductor element according to the first, second, and fourth aspects of the invention, comprising the following steps (1) to (8) in order. is there.
(Record)
(1) A conductive substrate preparation step of preparing a conductive substrate.
(2) A first resist coating step of covering both surfaces of the conductive substrate with a first resist.
(3) A first exposure / development step for forming a plating mask having an opening by exposing / developing a predetermined pattern.
(4) Plating and first resist for removing the plating mask after plating the opening using the plating mask having the opening to form a predetermined surface plating layer and a predetermined back surface plating layer Removal process.
(5) A second resist coating step of covering both surfaces of the conductive substrate with the second resist after the plating / first resist removing step.
(6) A second exposure / development step in which a predetermined pattern is exposed / developed to form an etching mask having an opening.
(7) An etching step of forming a recessed region on the back surface of the conductive substrate by etching using the etching mask.
(8) A second resist removing step for removing the etching mask.

  A thirteenth aspect of the present invention is the method for manufacturing a substrate for mounting a semiconductor element according to the third aspect, which includes the steps (1) to (8) in order. The predetermined pattern of the exposure mask in the first exposure / development step is a pattern in which the semiconductor element mounting region on the surface of the conductive substrate is covered with the first resist and the die pad surface plating layer is not formed, and (6) The semiconductor element mounting substrate manufacturing method is characterized in that the predetermined pattern in the second exposure / development step is a pattern for forming an opening in a semiconductor element mounting region on the surface of the conductive substrate.

A fourteenth invention of the present invention is the method for manufacturing a semiconductor device according to the fifth to ninth inventions, comprising the following steps (A) to (E) in order.
(Record)
(A) A semiconductor element mounting step of mounting a semiconductor element in a semiconductor element region of a semiconductor element mounting substrate.
(B) A wire bonding step of electrically connecting the electrode portion of the semiconductor element and the internal terminal surface plating layer using a bonding wire.
(C) A first resin sealing step in which a surface of a semiconductor element mounting substrate including a semiconductor element, a bonding wire, and a predetermined surface plating layer is resin-sealed with a first sealing resin.
(D) An etching process after resin sealing, in which etching is performed from the back side of the semiconductor mounting substrate, and predetermined metal parts are individually divided to be in an independent state except for electrical connection.
(E) Second resin sealing in which the predetermined metal portion is resin-sealed with a second sealing resin so that at least the external terminal back plating layer is exposed on the surface of the second sealing resin. Process.

The present invention creates a recess from the back surface of the conductive substrate so that the etching amount of the surface connecting metal portion and the external terminal metal portion is set to be substantially the same during the etching process after the first resin sealing. It is possible to perform etching at the same time, and it is possible to minimize the amount of etching of the conductive substrate after resin sealing with a sealing resin, and to reduce the influence on the plating layer.
Moreover, although the external terminal back surface plating layer is used as an etching mask, since etching is started from the side surface of the external terminal metal part, plating burr hardly occurs in this part, and a plating burr defect can be prevented.
In addition, since the internal terminal part and the external terminal part are connected by the wiring surface plating layer, the wiring pitch by plating can be made smaller than the wiring pitch by etching, and the arrangement of external terminals can be made in multiple rows. Accordingly, it is necessary to form a corresponding wiring portion between the external terminals, and it becomes possible to increase the number of pins or the number of external terminals.
Furthermore, the semiconductor device in which the die pad portion, the internal terminal portion, the external terminal portion, and the wiring portion are separated by the etching process from the rear surface after mounting the semiconductor element on the semiconductor element mounting substrate and sealing the resin by having the above effect. In the apparatus, a semiconductor element mounting substrate and a semiconductor device that can be miniaturized, thinned, and mounted at high density can be provided.

It is sectional drawing which shows an example of the board | substrate 100a for semiconductor element mounting concerning the 1st Embodiment of this invention. 1 is a cross-sectional view showing an example of a semiconductor device I according to a first embodiment of the present invention. It is sectional drawing which shows an example of the board | substrate 100b for semiconductor element mounting which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the example of the semiconductor device II concerning the 2nd Embodiment of this invention. It is sectional drawing which shows an example of the board | substrate 100c for semiconductor element mounting which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows the example of the semiconductor device III which concerns on the 3rd Embodiment of this invention. It is sectional drawing which shows an example of the board | substrate 100d for semiconductor element mounting which concerns on the 4th Embodiment of this invention. It is sectional drawing which shows an example of the semiconductor device IV concerning the 4th Embodiment of this invention. It is a top view which shows an example of the board | substrate for a semiconductor element mounting concerning the 4th Embodiment of this invention, (a) is a top view of a Fan-In type semiconductor device, (b) was enclosed with the broken line of (a). It is the elements on larger scale of A section. It is a figure which shows a series of processes of the manufacturing method of the semiconductor element mounting board | substrate 100b which concerns on this invention, (a) is a figure which shows a conductive substrate preparatory process, (b) is a figure which shows a 1st resist coating | coated process, (c) is a view showing a first exposure / development step, and (d) is a view showing a plating / first resist removal step. FIGS. 10A and 10B show a series of steps of the method for manufacturing the semiconductor element mounting substrate 100b according to the present invention, FIG. 10E shows a second resist coating step, and FIG. 10F shows a second exposure. The figure which shows a image development process, (g) is a figure which shows an etching process, (h) is a figure which shows an example of a 2nd resist removal process. It is a figure which shows a series of processes of the manufacturing method of the other semiconductor element mounting board | substrate 100a based on this invention, (a) is a figure which shows a 2nd exposure and image development process, (b) is a figure which shows an etching process, (c) is a diagram showing a second resist removal step. 2A and 2B are diagrams showing a series of steps of a method for manufacturing a semiconductor device II according to the present invention, in which FIG. 1A shows an example of a semiconductor element mounting process, FIG. 2B shows an example of a wire bonding process, and FIG. It is a figure which shows an example of a 1st resin sealing process. It is a figure following FIG. 12-1 which shows a series of processes of the manufacturing method of the semiconductor device II which concerns on this invention, (d) is a figure which shows an example of the etching process after resin sealing, (e) is 2nd resin. It is a figure which shows an example of a sealing process. It is a figure which shows a series of processes of the manufacturing method of the other semiconductor device I which concerns on this invention, (a) is a figure which shows an example of a 1st resin sealing process, (b) is an etching process after resin sealing. The figure which shows an example, (c) is a figure which shows an example of a 2nd resin sealing process.

[First Embodiment]
1. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing an example of a semiconductor element mounting substrate (hereinafter also referred to as a lead frame) according to the first embodiment of the present invention. FIG. 1 is a cross-sectional view showing a cross section cut along a line intersecting the wiring portion 30, not a cross section along the wiring portion 30.
As shown in FIG. 1, a semiconductor element mounting substrate 100a according to the first embodiment includes a conductive substrate 10, a die pad portion 50 as a semiconductor element mounting region 110, and an internal terminal for connecting to an electrode of the semiconductor element. 20, an external terminal 40 for connecting to an external device (not shown), and a wiring portion 30 for electrically connecting the internal terminal 20 and the external terminal 40.

  The material of the conductive substrate 10 to be used is not particularly limited as long as conductivity is obtained. For example, copper or a copper alloy is used. In order to dissolve and remove a predetermined portion of the conductive substrate 10 after sealing the sealing resin, copper or a copper alloy capable of selective dissolution and removal is often used.

  In the semiconductor element mounting substrate 100a of the first embodiment, the component parts of the die pad portion 50, the internal terminal 20, the wiring portion 30, and the external terminal 40 are surface plating formed on the conductive substrate 10 by electroplating. It is composed of a layer 1, a metal part 2 formed by etching the conductive substrate 10 from the back side so as to place the surface plating layer 1, and a surface connecting metal part 11. In the external terminal 40, The back surface plating layer 3 is formed on the back surface side of the conductive substrate 10 by electroplating.

  Specifically, each of the surface plating layer 21 constituting the internal terminal 20 (hereinafter referred to as an internal terminal surface plating layer) and the surface plating layer 41 constituting the external terminal 40 (hereinafter referred to as an external terminal surface plating layer) Are connected by a surface plating layer 31 (hereinafter referred to as a wiring surface plating layer) constituting the wiring portion 30.

  In addition, the metal part 22 constituting the internal terminal 20 (hereinafter referred to as an internal terminal metal part) and the metal part 42 constituting the external terminal 40 (hereinafter referred to as an external terminal metal part) are a surface plating layer. Similarly, they are connected by a metal part 32 (hereinafter referred to as a wiring metal part) constituting the wiring part 30, and are also connected by a surface connection metal part 11 formed by etching the conductive substrate. Further, a metal part (hereinafter referred to as a die pad metal part 52) constituting the die pad part 50 is connected to each internal / external terminal and wiring part by the surface connection metal part 11.

The type of plating metal used for the internal terminal surface plating layer 21, the external terminal surface plating layer 41, and the wiring surface plating layer 31 is not particularly limited, but is selected in consideration of the following points.
Since the uppermost surface of the internal terminal surface plating layer 21 includes an internal electrode portion connected by wire bonding to the electrode of the semiconductor element, a plating metal suitable for connection of the bonding wire is selected. For example, in the case of an Au wire, Ag plating, Au plating, Pd plating, or the like is preferable.

The external terminal surface plating layer 41 and the wiring surface plating layer 31 have a function of electrical connection, and since the wiring is formed by electroplating, the thickness thereof is thin, so that the plated metal having a certain strength such as Ni plating Is good.
Since this external terminal back surface plating layer 43 includes an external electrode portion connected to an external device, a plating metal suitable for connection to the external device is selected. Since there are generally many solder-based alloys such as solder balls for connection to external devices, Au (gold) plating, Pd plating, etc., which have good solder wettability and good bondability with solder, are preferable.

Furthermore, since the surface plating layer 1 and the back surface plating layer 3 are generally formed by electroplating at the same time, the same plating configuration is desirable. For example, multilayer plating in which Ni, Pd, and Au are laminated in this order outside the contact surface of the conductive substrate may be used.
Further, the types of plating of the front plating layer 1 and the back plating layer 3 may be different. For example, the surface may be Ag plating with good bonding properties, and the back surface may be laminated plating in which Ni, Pd, and Au are laminated in order of good solder wettability.
A plating layer such as the external terminal back plating layer 43 is not formed on the back side of the internal terminal surface plating layer 21 and the wiring surface plating layer 31.

  Further, in the etching process after the first resin sealing in the manufacturing process of the semiconductor device, the vertical cross-sectional shape of the external terminal surface plating layer 41 is changed from a normal rectangular shape to an inverted trapezoidal shape in order to prevent external terminal disconnection defects. The adhesion with the first sealing resin may be improved. In this case, in the exposure process in FIGS. 10-2 (e), 10-2 (f), and 10-2 (g) described later, the ultraviolet light used for exposure is changed from parallel light to scattered light. It can be manufactured by irradiating and exposing. Moreover, the same effect can be obtained even if the plating surface is roughened.

On the opposite surface side of the conductive substrate other than the internal terminal surface plating layer 21, the external terminal surface plating layer 41, and the wiring surface plating layer 31, a recess portion 4 is provided in the recess region by etching from the back surface side.
By forming the recess 4, the internal terminal metal part 22, the external terminal metal part 42, the wiring metal part 32, and the die pad metal part 52 are formed. In addition, since the surface side of the conductive substrate is not etched and no depression is formed, the surface connection metal portion 11 connected to the entire material surface is formed.
In addition, the internal terminal metal part 22, the external terminal metal part 42, the wiring metal part 32, and the surface connection part metal part 11 are mounted with a semiconductor element, sealed with resin, and then etched to process the internal terminal metal part, the external terminal metal part, The wiring metal part, the side surface of the die pad metal part, and the corresponding part of the surface connecting metal part (the range located at the tip of the recess 4) are etched to make them independent.

Here, the depth of the recessed portion 4 to be provided is from 1/2 of the plate thickness to −0.03 mm.
If the depth of the dent is less than ½ of the plate thickness, the amount of etching processing after resin sealing increases, the etching time becomes longer, and the etching solution etches part of the plating layer. It becomes easy. When the plate thickness exceeds ½ to the plate thickness of −0.03 mm, the formed surface connecting metal portion becomes thin, and there is a possibility that a deformation defect may occur during conveyance.
The plate thickness is preferably -0.05 mm to plate thickness -0.03 mm.

Further, the joint surface of the external terminal metal part 42 with the back surface plating layer is a size including the back surface plating layer 43, and is spaced from the back surface plating layer outer peripheral part by 1/2 to the plate thickness −0.03 mm. A large outer periphery.
Moreover, since the side surface of the external terminal metal part 42 is etched after the resin sealing as in the case of the surface connection metal part 11, it is increased by the same amount to be etched.
Further, the bonding surfaces of the internal terminal metal part 22 and the wiring metal part 32 with each plating layer are not particularly limited, but the size includes the bonding surface with the metal part of each surface plating layer, and the outer periphery of each plating layer. It is good also as a large outer peripheral part at intervals of about 0.03 mm to 0.05 mm from the part.

  In the following description, the same components as those described so far are denoted by the same reference numerals as those described above, and the description thereof is omitted.

2. Next, a semiconductor device using the semiconductor element mounting substrate as a lead frame will be described with reference to FIG.
In FIG. 2, not a cross section along the wiring part 30 but a cross-sectional view cut along a line intersecting with the wiring part 30 is shown.

The semiconductor device I according to the first embodiment of the present invention mounts the semiconductor element 101 in the semiconductor element mounting region using the semiconductor element mounting substrate.
In FIG. 2, a case where a die pad portion is formed and a semiconductor element is mounted thereon will be described. In addition, there is a semiconductor device such as a Fan-In type in which a semiconductor mounting area is secured and an external terminal is disposed on the lower surface of a semiconductor element.

A semiconductor element 101 is mounted on the surface plating layer 51 of the die pad portion, and an electrode portion (not shown) of the semiconductor element and the internal terminal surface plating layer 21 are electrically connected by a bonding wire 5 or the like. The internal terminal surface plating layer 21 and the external terminal surface plating layer 41 are connected via a wiring surface plating layer 31. On the opposite side of the external terminal surface plating layer 41, an external terminal back surface plating layer 43 is formed.
Further, the semiconductor element, the bonding wire, the internal terminal surface plating layer, the external terminal surface plating layer, and the wiring surface plating layer are sealed with the first sealing resin 102.

Thereafter, the sealed lead frame is etched from the back side to form the external terminal metal part 42, the internal terminal metal part 22, and the wiring metal part 32, and the external terminal, the internal terminal, and the wiring part are made independent.
In this etching process, each terminal is formed by etching the surface connection metal part 11, the side surface of the external terminal metal part 42, the side surface of the internal terminal metal part 22, the side surface of the wiring metal part 32, etc. in the lead frame of FIG. Separated independently. Further, since this etching process is performed using the back plating layer as a mask, the external terminal 40 having the external terminal back plating layer 43 is not etched from the back side, but the internal terminal 20 and the wiring part 30 are formed by the back plating layer. Therefore, it is etched from the back surface to form a thin portion. When the back plating layer is formed, the die pad portion 50 is the same as the external terminal, and when the back plating layer is not formed, the die pad portion 50 is a thin portion like the internal terminal. FIG. 2 shows a case where a back plating layer is provided.

Moreover, as described in Patent Document 2, when the surface is etched to form a dent, the resin is sealed with the back surface being flat, and then etched using the back plating layer as a mask, only from the back side of the conductive substrate. Since the etching is performed, the etching time becomes long, and there may be a problem that the etching solution dissolves a part of the plating layer.
Furthermore, the external terminal back plating layer is used as an etching mask. Etching is started from the back, and the conductive substrate is etched faster and the etching time is longer than the back plating layer. Has been etched, and the back plating layer has a bowl shape, which causes a problem of burr.

In the present invention, the etching process after the resin sealing is indented from the back side as shown in FIG.
Although the external terminal back plating layer 43 is used as a mask for etching, since the etching is mainly performed from the side of the external terminal, generation of burrs on the external terminal back plating layer 43 can be prevented. In addition, the amount of etching after sealing can be minimized by adjusting the amount of depression at the lead frame manufacturing stage.
In addition, the vertical cross-section of the external terminal in the vertical direction is the same as the etching direction at the time of the lead frame and the etching direction after resin sealing. It has become. For this reason, after the second resin sealing is performed, the external terminals are prevented from coming off from the sealing resin.

The side surface of the external terminal back surface plating layer 43, the external terminal metal part 42, the internal terminal metal part 22, and the wiring metal part 32 are covered with the second sealing resin 103, and the external terminal back surface plating layer 43 is covered with the second seal. It is exposed from the stop resin 103. This exposed surface is for connection with an external device.
The internal terminal metal portion 22 and the wiring metal portion 32 are thin portions as described above, and are not easily exposed from the second sealing resin portion 103, and there is no risk of contact with an external device. Furthermore, in the semiconductor device disclosed in Patent Document 2, a part of the side surface of the external terminal metal part is exposed from the sealing resin part and is not plated, so that troubles such as discoloration are likely to occur. In the present invention, since it is in the second sealing resin portion, there is no similar problem.
The first sealing resin 102 and the second sealing resin 103 may be of the same type or different. In general, for example, in the case of an optical semiconductor device, the first sealing resin 102 is sealed with a transparent resin, and the second sealing resin 103 is sealed with a resin that reflects light. For example, different resins may be used.

[Second Embodiment]
1. Next, a second embodiment will be described with reference to FIGS. 3 and 4. In FIGS. 3 and 4, reference numerals 20a and 30a denote internal terminals and wiring portions each having no metal portion.
The semiconductor mounting substrate 100b according to the second embodiment is a form that does not include the internal terminal metal portion 22 and the wiring metal portion 32 in the semiconductor mounting substrate 100a according to the first embodiment. And the wiring surface plating layer 31 is formed on the surface connection metal part 11, and the internal terminal 20a which does not have a metal part, and the wiring part 30a which does not have a metal part are comprised.

Further, the semiconductor device II of the second embodiment does not have the internal terminal metal part 22 and the wiring metal part 32 in the semiconductor device I of the first embodiment, and the external terminal 40 is the internal terminal surface plating layer 21 and the wiring surface. The structure is connected only by the plating layer 31, and the wiring pitch by plating can be processed smaller than the wiring pitch by etching.
That is, as in the semiconductor device IV of the fourth embodiment according to the present invention shown in FIG. 8, as the arrangement of the external terminals becomes a plurality of columns, it is necessary to form a corresponding wiring portion between the external terminals. For a multi-pin product or a multi-row product in which the external terminals are arranged, it is advantageous to produce only the wiring surface plating layer of the second embodiment. Note that the semiconductor device I according to the first embodiment is advantageous for a device having a specification in which a large current flows because the internal terminal, the external terminal, and the wiring portion are connected by a metal portion. Further, it is advantageous for preventing deformation or the like in the semiconductor device manufacturing process or in the transportation.

  Further, in the semiconductor device II, since the internal terminal 20a does not have the internal terminal metal part, there is a possibility that the strength is insufficient at the time of wire bonding, and the heater plate or the like is adapted to the pattern instead of the internal terminal metal part. Take measures such as processing into a frame shape or the like.

[Third Embodiment]
1. Next, a third embodiment will be described with reference to FIGS. 5 and 6. In FIGS. 5 and 6, 6 is a recess serving as a semiconductor element mounting region, 100c is a third embodiment of a semiconductor element mounting substrate, and III is a third embodiment of a semiconductor device.
FIG. 5 is a diagram showing a third embodiment of a semiconductor element mounting substrate according to the present invention. In the semiconductor mounting substrate 100b of the second embodiment, the die pad surface plating layer 51 is not formed, and the third embodiment is performed. In the semiconductor element mounting substrate 100c of the embodiment, the semiconductor element mounting region 110 is formed with the recess 6 from the surface side.

2. FIG. 6 is a diagram showing a third embodiment of the semiconductor device according to the present invention. As shown in FIG. 6, the semiconductor element 101 is a semiconductor element mounting region of the recess 6 shown in the semiconductor element mounting substrate of FIG. 110 is fixed by an insulating method such as an insulating adhesive 60.
Compared to the second embodiment, the semiconductor element mounting region is a recess, so that the mounting position of the semiconductor element can be further lowered, and the thickness of the entire semiconductor device can be reduced. The third embodiment can also be applied to the first embodiment.

[Fourth Embodiment]
Next, a fourth embodiment will be described with reference to FIG. 7, FIG. 8, and FIG.
The embodiments described so far are examples of a fan-out type in which a semiconductor element is mounted in a semiconductor element mounting region provided in a die pad portion or a recess, and an external terminal is disposed outside the semiconductor element mounting region.
In contrast to this Fan-Out type, the fourth embodiment is an example of a Fan-In type as shown in FIG. 9 in which the semiconductor element mounting region 110 is secured and an external terminal is also arranged on the lower surface of the semiconductor element. is there. 9A is a plan view of the Fan-In type semiconductor device, FIG. 9B is a partial enlarged view of a portion A surrounded by a broken line in FIG. 9A, 110 is a semiconductor element mounting region, and 71 is an outside of the FI. It is a terminal (external terminal arranged under the semiconductor element) surface plating layer.

1. FIG. 7 is a cross-sectional view showing an example of a Fan-In type semiconductor element mounting substrate, where 100d is a Fan-In type semiconductor element mounting substrate, and 70 is disposed below the semiconductor element. FI external terminal portion, 71 is an FI external terminal surface plating layer, 72 is an FI external terminal metal portion, and 73 is an FI external terminal back surface plating layer.
The semiconductor element mounting substrate 100d according to the fourth embodiment of the present invention uses a plurality of FI external terminal portions 70 having front and back plating layers without having a dedicated semiconductor element mounting region such as a die pad portion or a recess. The semiconductor element 101 is mounted on the plurality of FI external terminal surface plating layers 71, and the FI external terminal back surface plating layer 73 is used for connection to an external device as in the case of the external terminals 40. The form adopts the same structure as the semiconductor element mounting substrate 100a according to the first embodiment.

2. Semiconductor Device FIG. 8 is a cross-sectional view showing an example of a Fan-In type semiconductor device, where IV is a Fan-In type semiconductor device of the fourth embodiment, and 60 is an insulating adhesive.
A semiconductor device IV according to the fourth embodiment shown in FIG. 8 includes a plurality of FI external terminal portions 70 including front and back plating layers in a semiconductor element mounting region (see FIG. 7, reference numeral 110), and the plurality of FI external portions. A structure in which the semiconductor element 101 is mounted and fixed using an insulating adhesive 60 or the like in a form straddling the FI external terminal surface plating layer 71 of the terminal portion is adopted, and a semiconductor element electrode (not shown) is connected to the internal terminal 20. A portion connected to the internal terminal surface plating layer 21 and sealed with the first sealing resin and the second sealing resin (external terminal back surface plating layer) is connected to the external device. Since it is also provided directly underneath, the structure is suitable for miniaturization and high-density mounting of semiconductor devices.
The structure of the semiconductor element mounting substrate 100d according to the fourth embodiment can also be applied to the semiconductor element mounting substrate 100b of the second embodiment.

<Manufacturing method of semiconductor element mounting substrate>
Next, as a method for manufacturing a semiconductor element mounting substrate according to the present invention, (a) to (h) following FIGS. 10-1 to 10-2 are performed on the semiconductor element mounting substrate 100b of the second embodiment. It explains using.
The semiconductor device 100b according to the present embodiment is a Fan-Out type semiconductor device, in which a die pad portion on which a semiconductor element is mounted is formed and the back plating layer of the die pad portion is exposed from the second sealing resin. As will be described, without being limited thereto, if a semiconductor element mounting region can be secured, an external terminal can be disposed on the lower surface of the semiconductor element as in the Fan-In type.

A method for manufacturing the semiconductor element mounting substrate 100a according to the first embodiment of the present invention will also be described with reference to FIGS. Note that the first half of the manufacturing method, the steps shown in FIGS. 10A to 10D, are the same as the manufacturing steps of the semiconductor element mounting substrate 100b.
In the following description, the same constituent elements as those described above are denoted by the same reference numerals as those described above, and the description thereof is omitted.

1. Manufacturing method of semiconductor element mounting substrate 100b [conductive substrate preparation step]
FIG. 10A is a diagram illustrating an example of a preparation process for preparing a conductive substrate.
In the step of preparing the conductive substrate, the conductive substrate 10 is prepared.
The material of the conductive substrate 10 is not particularly limited as long as conductivity is obtained, but a Cu alloy is generally used.

[First resist coating step]
FIG. 10B is a diagram illustrating an example of the first resist coating process.
In the first resist coating step, both surfaces of the conductive substrate 10 are coated with resists 160 and 161. As the resists 160 and 161 to be used, a conventional method such as laminating a dry film resist or applying a liquid resist to both surfaces of the conductive substrate 10 can be used.

[First exposure / development process]
FIG. 10C is a diagram illustrating an example of the first exposure / development process.
In the first exposure step, exposure masks (not shown) are placed above and below the first resist in an exposure apparatus (not shown), and exposure is performed by irradiating ultraviolet light (not shown). Do. The exposure mask pattern has an internal terminal surface plating layer, an external terminal surface plating layer, a wiring surface plating layer, a die pad surface plating layer on the surface, and an external terminal back surface plating layer and a die pad back surface plating layer on the back surface. A pattern is prepared. Thereby, an unexposed portion is formed in the resist 160.

After the exposure, in the first development, the unexposed portions of the resists 160 and 161 are removed, and an opening 163 is formed. Thereby, a part of the conductive substrate 10 is exposed from the opening 163. As described above, the resist 160 having the opening 163 and the resist 161 are configured as a plating mask.
Note that when an external terminal or the like is disposed under the semiconductor element mounting region without forming a die pad, a mask pattern in which an external terminal surface plating layer or the like is disposed is produced. Moreover, when forming a recessed part in a semiconductor element mounting area, it is set as the pattern which does not form the surface plating layer of a die pad part.

[Plating / first resist removal process]
FIG. 10D is a diagram illustrating an example of the plating / first resist removing step.
Using the resist 160 and the resist 161 formed in the first development step shown in FIG. 10-1 (c) as plating masks, plating is performed on the openings not covered with the mask, and the internal terminal surface plating layer 21 is formed. The external terminal surface plating layer 41, the wiring surface plating layer 31, the die pad surface plating layer 51, and the external terminal back surface plating layer 43 and the die pad back surface plating layer 53 are formed on the back surface.

  Thereafter, the resist 160 and the resist 161 formed as a plating mask are peeled and removed. The first resist stripping may be performed using, for example, a liquid resist stripper. By the first resist peeling, the resists 160 and 161 are removed, and the surface plating layer and the back plating layer are formed on the conductive substrate 10.

[Second resist coating step]
FIG. 10-2 (e) is a diagram illustrating an example of a second resist coating process.
In the second resist coating step, both surfaces of the conductive substrate 10 are covered with resists 165 and 166 in a state where the surface plating layer and the back surface plating layer are formed on the conductive substrate 10. As the resists 165 and 166, a conventional method such as laminating a dry film resist or applying a liquid resist can be used as in the first resist coating process described with reference to FIG.

[Second exposure / development process]
FIG. 10-2 (f) is a diagram illustrating an example of the second exposure / development process.
In the second exposure step, exposure masks (not shown) are placed above and below the resists 165 and 166 in an exposure apparatus (not shown), and exposure is performed with ultraviolet light (not shown). The exposure mask used in the second exposure step covers the entire surface of the conductive substrate 10 on which the surface plating layer is formed, and the back surface is covered with the external terminal back surface plating layer 43 and the die pad back surface plating layer 53 with the mask. A pattern is formed.

Note that the size of the mask is such that the outer peripheral portion is larger than the outer peripheral portions of the external terminal back surface plating layer and the die pad back surface plating layer at intervals similar to the thickness of the surface connection metal portion. Preferably, it is enlarged at intervals of 0.03 mm to 0.05 mm.
This is because the etching process is completed almost simultaneously with the etching process after resin sealing. When the internal terminal metal part and the wiring metal part are formed, they are arranged so that the mask covers the back surface side corresponding to the position of the internal terminal surface plating layer and the wiring surface plating layer in the same manner as the external terminal. There is no particular limitation on the size of the mask, but it is desirable that it be within the setting of the external terminal.

  Next, in the second development step, the unexposed portion is removed, and a resist 165 having an opening 168 and a resist 166 are formed as an etching mask.

[Etching process]
FIG. 10-2 (g) is a diagram illustrating an example of an etching process in which etching is performed from the back surface.
In the etching step, the recess 4 is formed by etching the back surface of the conductive substrate 10 with an etching solution using the resist formed in FIG. 10-2 (f) as an etching mask. Thereby, the external terminal metal part 42, the die pad metal part 52, and the surface connection metal part 11 are formed.

[Second resist removal step]
FIG. 10-2 (h) is a step of removing the second resist. The second resist removal may be performed using, for example, a liquid resist remover. Thereafter, if necessary, the sheet may be cut into a predetermined size.
With the above manufacturing method, the semiconductor element mounting substrate 100b according to the second embodiment of the present invention is completed.

2. Manufacturing Method of Semiconductor Element Mounting Board 100a Next, a manufacturing method of the semiconductor element mounting board 100a (first embodiment) having a different form will be described.
The manufacturing method of the semiconductor element mounting substrate 100a (first embodiment) is the “second resist coating step: FIG. 10-2 (e)” of the manufacturing method of the “semiconductor element mounting substrate 100b” described above. The same process is performed until. Here, the manufacturing process after that process will be described with reference to FIG.

[Second exposure / development process]
FIG. 11A shows an example of the second exposure / development process.
In the second exposure step, exposure masks (not shown) are placed above and below the resists 165 and 166 in an exposure apparatus (not shown), and exposure is performed with ultraviolet light (not shown).
The exposure mask used in the second exposure step covers the entire surface of each surface plating layer 21, 31, 41, 51 of the conductive substrate 10, and the back surface is the external terminal back surface plating layer 43, The die pad back surface plating layer 53 is covered with a mask, and the portions corresponding to the positions of the internal terminal surface plating layer and the wiring surface plating layer are also covered with the mask, so that a recess can be formed from the back surface in a subsequent etching process. A pattern is formed so that the position of the portion 168 is unexposed.

The size of the mask is a mask which is larger than the outer peripheral portion of the external terminal back surface plating layer and the die pad back surface plating layer at an interval similar to the thickness of the surface connection metal portion, and preferably the interval is 0.03 mm to 0. It is a large one of about .05mm.
This is because the etching process is completed almost simultaneously with the etching process after resin sealing. Further, the size of the mask in the case of forming the internal terminal metal part and the wiring metal part is not particularly limited, but is preferably within the setting of the external terminal.

  Next, in the second development step, the unexposed portion is removed, and a resist 165 having an opening 168 and a resist 166 are formed as an etching mask.

[Etching process]
FIG.11 (b) is a figure which shows an example of the process of forming a hollow area | region from a back surface by an etching process.
In the etching step, the back surface of the conductive substrate 10 is etched with an etching solution using the resist mask made in FIG. Thereby, the external terminal metal part 42, the internal terminal metal part 22, the die pad metal part 52, the wiring metal part 32, and the surface connection metal part 11 are formed.

[Second resist removal step]
FIG. 11C shows a step of removing the second resist. The second resist removal may be performed using, for example, a liquid resist remover. Thereafter, if necessary, the sheet may be cut into a predetermined size.
With the above manufacturing method, the semiconductor element mounting substrate 100a according to the second embodiment of the present invention is completed.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing a semiconductor device using the semiconductor element mounting substrate of the present invention will be described with reference to FIGS. 12-1, 12-2, and 13. FIG.
12A and 12B are diagrams illustrating a series of steps of the method of manufacturing the semiconductor device according to the embodiment of the present invention, and are the method of manufacturing the semiconductor device II shown in FIG.
FIG. 13 is a view showing a series of steps of another method for manufacturing a semiconductor device according to the embodiment of the present invention, and is a method for manufacturing the semiconductor device I described above with reference to FIG.

1. Manufacturing method of semiconductor device II [semiconductor element mounting process]
FIG. 12A is a diagram illustrating an example of a semiconductor element mounting process.
In this semiconductor element mounting step, the semiconductor element 101 is mounted on the semiconductor element region 110 of the semiconductor element mounting substrate 100b. Here, when there is a die pad portion, a semiconductor element is mounted using Ag paste or the like.
On the other hand, when an external terminal is disposed under the semiconductor element, or when a recess is formed in the die pad portion, the semiconductor element is mounted via an insulating adhesive layer, for example, an insulating paste or a die attach film.
When the external terminal 40 and the wiring part 30 are disposed in the semiconductor element region 110, the semiconductor element 101 is mounted thereon. Reference numeral 11 denotes a surface connecting metal part.

[Wire bonding process]
FIG. 12B is a diagram illustrating an example of a wire bonding process. In the wire bonding step, an electrode portion (not shown) of the semiconductor element 101 and the internal terminal surface plating layer 21 of the internal terminal 20 are electrically connected using a bonding wire 5 or the like.

[First resin sealing step]
FIG. 12C is a diagram illustrating an example of the first resin sealing step.
In the first resin sealing step, the surface connection metal part including the semiconductor element 101, the bonding wire 5, the internal terminal surface plating layer 21, the external terminal surface plating layer 41, the wiring surface plating layer 31, and the die pad surface plating layer 51 is included. 11 is sealed with the first sealing resin 102.

[Etching step after first resin sealing]
FIG. 12D is a diagram illustrating an example of an etching process after resin sealing.
In the etching process after resin sealing, etching is performed from the direction of the metal part that is not resin-sealed, and the side surface of the external terminal metal part 42, the surface connection metal part (see FIG. 12 (c), reference numeral 11), die pad The side surface of the metal part 52 is etched at the same time. At this time, the vertical cross-sectional shape of the external terminal metal portion 52 is set to a gentle curve or a taper shape extending from the back surface of the external terminal portion toward the surface.
Thereby, it divides | segments separately for every terminal and will be in an independent state, respectively.
The etching amounts are set so as to be the same in FIG. 10-2 (g), and it is desirable that the etching is simultaneously completed in a minimum time.

[Second resin sealing step]
FIG. 12E is a diagram illustrating an example of the second resin sealing step.
In the second resin sealing step, the external terminals 40, the die pad portion 50, and the like are resin-sealed with the second sealing resin 103, and the external terminal back plating layer 43 and the die pad back plating are formed from the second sealing resin 103. Layer 53 is exposed.

2. 2. Manufacturing Method of Semiconductor Device I Similar to the case of semiconductor device II, the following process is performed on the intermediate product of semiconductor device II that has undergone the “semiconductor element mounting process” and the “wire bonding process” to thereby obtain the semiconductor shown in FIG. Device I was made.

[First resin sealing step]
FIG. 13A is a diagram illustrating an example of the first resin sealing step.
In the first resin sealing step, the conductive element including the semiconductor element 101, the bonding wire 5, the internal terminal surface plating layer 21, the external terminal surface plating layer 41, the wiring surface plating layer 31, and the die pad surface plating layer 51 is formed. A part of the surface of the surface connection metal part 11 is resin-sealed with the first sealing resin 102.

[Etching step after first resin sealing]
FIG. 13B is a diagram illustrating an example of an etching process after resin sealing.
In the etching process after the resin sealing, etching is performed from the recess 4 on the back surface side of the semiconductor element mounting substrate, the side surface of the internal terminal metal portion 22, the side surface of the external terminal metal portion 42, and the side surface of the wiring metal portion 32. The side surfaces of the surface connecting metal part 11 and the die pad metal part 52 are simultaneously etched. Thereby, it divides | segments separately for every terminal and will be in an independent state, respectively.
The etching amounts are set to be the same at the time of manufacturing the semiconductor element mounting substrate, and it is desirable that the etching is completed simultaneously in a minimum time.
Further, when the internal terminal metal part, the wiring metal part, or the die pad part has no back plating layer and there is a die pad metal part, the surface on the back side is etched simultaneously with each side surface to become a thin part.

[Second resin sealing step]
FIG. 13C is a diagram illustrating an example of the second resin sealing step.
In the second resin sealing step, the external terminals 40, the die pad portion 50, and the like are resin-sealed with the second sealing resin 103, and the external terminal back plating layer 43 and the die pad back plating are formed from the second sealing resin 103. Layer 53 is exposed.
If the inner terminal metal part, the wiring metal part, or the die pad part has no back plating layer and has a die pad metal part, the thin sealing part is obtained by etching in FIG. There is no exposure from the part, it is in the resin, there is no risk of contact with external equipment.

Finally, individual semiconductor devices are formed by cutting or the like so as to have a predetermined shape.
In the cutting, there is no metal part at the cutting location, and all is resin, and the cutting load is reduced.

  The manufacturing method has been described for the semiconductor element mounting substrates 100a and 100b and the semiconductor devices I and II. However, the semiconductor element mounting substrates 100c and 100d and the semiconductor devices III and IV, which are other embodiments, are also described above. As described above, when manufacturing the semiconductor element mounting substrate, the exposure mask in the first exposure / development process of FIG. 10-1 (c) and the second exposure / development process of FIG. 10-2 (f) is used. Manufacture is possible by changing the mask pattern.

Moreover, it is also possible to change the kind of plating of a surface plating layer and a back surface plating layer.
In this case, it can manufacture by performing the process of Drawing 10-1 (b) to Drawing 10-1 (d) twice on the surface plating layer side and the back plating layer side.

  Furthermore, in order to prevent the failure of the external terminal portion in the “etching step after first resin sealing” in FIG. 11, the cross-sectional shape of the surface plating layer is changed from a normal rectangular shape to an inverted trapezoidal shape. The adhesion with the sealing resin may be improved. In this case, in the exposure process of the first exposure / development process shown in FIG. 10-1 (c), the ultraviolet light used for the exposure is changed to the scattered light and irradiated to perform the exposure. Moreover, the same effect can be obtained even if the plating surface is roughened.

  Hereinafter, the present invention will be described in detail using examples.

As Example 1, a “semiconductor element mounting substrate 100b” shown in FIG. 3 was manufactured according to the following procedure.
[Conductive substrate preparation process]
A Cu plate (Furukawa Electric Co., Ltd .: EFTEC64-T) having a plate thickness of 0.2 mm was processed as a conductive substrate into a long plate shape having a width of 140 mm.
[First resist coating step]
Next, a photosensitive dry film resist having a thickness of 0.025 mm was attached to both surfaces of the conductive substrate.
[First exposure / development process]
Next, a glass mask having a desired pattern of an internal terminal surface plating layer, an external terminal surface plating layer, a wiring surface plating layer, and a die pad surface plating layer on the surface, and an external terminal back surface plating layer and a die pad back surface plating layer on the back surface ( The exposure mask was placed on the front and back surfaces in a pattern-aligned state, and both surfaces were exposed to ultraviolet light through a glass mask.
Thereafter, the dry film resist was developed with a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed due to the irradiation of ultraviolet light, thereby forming an opening.

[Plating / first resist removal process]
Next, plating was performed on the opening where the dry film was dissolved and the metal surface of the conductive substrate was exposed. The plating was formed by stacking Ni plating of 3.0 μm, Pd plating of 0.1 μm, and Au plating of about 0.04 μm in this order.
Thereafter, the dry film resist was peeled off with a sodium hydroxide solution. Thereby, the plating layer was formed on the front and back surfaces of the conductive substrate.

[Second resist coating step]
Next, a photosensitive dry film resist having a thickness of 0.025 mm was attached to both surfaces of the conductive substrate having a plating layer formed on the front and back surfaces.

[Second exposure / development process]
After covering the resist, the surface covers the entire surface including the surface plating layer, and the back surface is larger than the outer peripheries of the external terminal back surface plating layer and the die pad back surface plating layer over the entire circumference at an interval of 0.05 mm. The glass mask on which the above pattern was formed was used as an exposure mask, placed on a dry film resist, and exposed to ultraviolet light.
Thereafter, the dry film resist was developed with a sodium carbonate solution to dissolve the uncured dry film resist that was not exposed to ultraviolet light irradiation.

[Etching process]
Next, it was masked with the prepared resist, and selective etching was performed from the back side with a ferric chloride solution, so that a recess having a depth of 0.15 mm was formed on the conductive substrate. By this etching process, an external terminal metal part, a die pad metal part, and a surface connection metal part were formed.
Then, the board | substrate for semiconductor element mounting which concerns on this invention was obtained by cut | disconnecting to a predetermined dimension.

  As Example 2, the semiconductor device II shown in FIG. 4 was manufactured according to the following procedure using the semiconductor element mounting substrate manufactured in Example 1.

[Semiconductor element mounting and wire bonding process]
The semiconductor element mounting substrate according to Example 1 is used, the semiconductor element is mounted on the die pad surface plating layer of the semiconductor element mounting substrate using Ag paste, and the electrode portion of the semiconductor element and the internal terminal surface plating layer are wired. Connected by bonding.

[First resin sealing step and etching step after resin sealing]
Thereafter, the surface on which the semiconductor element is mounted is resin-sealed with the first sealing resin, and the surface connection metal part, the side of the external terminal metal part, the die pad metal using the external terminal back plating layer and the die pad back plating layer as a mask The side surfaces of the part were simultaneously etched to make the external terminal metal parts independent of each other.

[Second resin sealing step]
Thereafter, the external terminal metal part was resin-sealed with a second sealing resin. The same kind of resin was used for the first sealing resin and the second sealing resin. Finally, the semiconductor device was completed by cutting to a predetermined semiconductor device size.

<Semiconductor element mounting substrate>
In the semiconductor element mounting substrate according to Example 3, the internal terminal metal part and the wiring metal part are formed in the “first exposure / development process” and the “second exposure / development process” in Example 1. The semiconductor device mounting substrate 100a shown in FIG. 1 is manufactured using an exposure mask having a simple pattern.

<Semiconductor device>
A semiconductor device I shown in FIG. 2 was manufactured according to the manufacturing method of the present invention using the manufactured semiconductor element mounting substrate 100a.

Specifically, in the production of the substrate for mounting a semiconductor element, when the pattern is formed on the second resist, the internal terminal surface plating layer and the wiring surface plating are formed in the area corresponding to the back surface of the internal terminal surface plating layer and the wiring surface plating layer. A pattern was prepared so as to cover the resist so as to be 0.05 mm larger on one side than the layer, and in the next etching process, an internal terminal metal part and a wiring metal part were formed.
Furthermore, in the manufacture of the semiconductor device, in the etching after the first sealing resin is sealed with the resin, the side surfaces and the back surface of the internal terminal metal portion and the wiring metal portion are etched to divide each part independently. Then, it was sealed with a second sealing resin. Other manufacturing conditions are the same as those in Examples 1 and 2.

<Semiconductor element mounting substrate>
In the semiconductor element mounting substrate according to Example 4, the die pad surface plating layer was not formed in the “first exposure / development process” and “second exposure / development process” in Example 1, and the die pad portion was electrically conductive. The semiconductor element mounting substrate 100c shown in FIG. 5 is manufactured using an exposure mask having a pattern that forms a recess to be a semiconductor element mounting region from the surface side of the conductive substrate.

<Semiconductor device>
Using the manufactured semiconductor element mounting substrate 100c, a semiconductor device III shown in FIG. 6 was manufactured in accordance with the manufacturing method of the present invention.

Specifically, in the production of the semiconductor element mounting substrate, when the pattern is formed on the first resist, the die pad portion is formed so as to be covered with the resist, and when the second resist pattern is produced, the surface side In the next etching step, since the die pad area is an opening, a recess that becomes a semiconductor element mounting area at a depth of 0.15 mm from the surface side is formed. Was made.
Further, in manufacturing a semiconductor device, a semiconductor element is mounted and fixed with an insulating adhesive in a semiconductor element mounting process.
Other manufacturing conditions are the same as those in Examples 1 and 2.

<Semiconductor element mounting substrate>
The substrate for mounting a semiconductor element according to the fifth embodiment forms a semiconductor element mounting region without forming a die pad portion in the “first exposure / development process” and the “second exposure / development process” in the third embodiment. A semiconductor element mounting substrate 100d shown in FIG. 7 is manufactured using an exposure mask having a pattern in which external terminals having front and back plating layers are arranged immediately below the position.

<Semiconductor device>
A semiconductor device IV shown in FIG. 8 was manufactured in accordance with the manufacturing method of the present invention using the manufactured semiconductor element mounting substrate 100d.

Specifically, in the production of the semiconductor element mounting substrate, when the first resist pattern is formed in Example 3, the die pad portion is not arranged, but the pattern in which the external terminal portion and the wiring portion are arranged is formed. When producing the second resist pattern, the die pad part was not arranged on the back surface side, and a pattern in which the external terminal part and the wiring part were arranged was produced.
Furthermore, in the manufacture of the semiconductor device, in the semiconductor element mounting step, the semiconductor element is mounted and fixed on the external terminal surface plating layer of the plurality of external terminals directly under the semiconductor element mounting region using an insulating adhesive.
Other manufacturing conditions are the same as those in Examples 1 and 2.

<Evaluation>
With respect to the semiconductor devices fabricated in Examples 2 to 5, it was observed with a microscope whether “plating peeling” or “plating burr” or the like occurred in the external terminal back surface plating layer.
It was confirmed that the semiconductor devices fabricated in Examples 2 to 5 were good without the occurrence of “plating peeling” or “plating burr” in the external terminal back surface plating layer.

DESCRIPTION OF SYMBOLS 1 Surface plating layer 2 Metal part 3 Back surface plating layer 4 Indentation part 5 Bonding wire 6 Recess 10 provided in semiconductor mounting area Conductive substrate 11 Surface connection metal part 20 Internal terminal part 20a Internal terminal 21 having no metal part Internal terminal 21 Surface plating layer 22 Internal terminal metal portion 30 Wiring portion 30a Wiring portion 31 having no metal portion Wiring surface plating layer 32 Wiring metal portion 40 External terminal portion 41 External terminal surface plating layer 42 External terminal metal portion 43 External terminal back surface plating layer 50 Die pad portion 51 Die pad surface plating layer 52 Die pad metal portion 53 Die pad back surface plating layer 60 Insulating adhesive 70 FI external terminal portion 71 FI external terminal surface plating layer 72 FI external terminal metal portion 73 FI external terminal back surface plating layer 100a First Semiconductor device mounting substrate 100b of the second embodiment Semiconductor element of the second embodiment Mounting substrate 100c Semiconductor device mounting substrate 100d of the third embodiment Semiconductor device mounting substrate 101 of the fourth embodiment Semiconductor device 102 First sealing resin 103 Second sealing resin 110 Semiconductor device mounting region 160 161 First resist 163 provided on both surfaces of conductive substrate 10 First resist opening 165, 166 Second resist 168 Second resist opening I Semiconductor device of first embodiment
II Semiconductor device of the second embodiment
III Semiconductor Device of Third Embodiment
IV Semiconductor Device of Fourth Embodiment

Claims (14)

A semiconductor element mounting substrate capable of mounting a semiconductor element in a predetermined semiconductor element mounting region,
On the surface of the conductive substrate,
A semiconductor element mounting area;
An inner terminal surface plating layer disposed around the semiconductor element mounting region and electrically connected to an electrode of the semiconductor element mounted in the semiconductor element mounting region;
External terminal surface plating layer disposed around the semiconductor element mounting region away from the internal terminal,
Arranged between the internal terminal surface plating layer and the external terminal surface plating layer, and having a wiring surface plating layer for electrically connecting the internal terminal surface plating layer and the external terminal surface plating layer,
On the back surface of the conductive substrate, provided with an external terminal back plating layer electrically connected to an external device at a position facing the external terminal surface plating layer and the conductive substrate,
And at least from the back surface side of the conductive substrate to the surface, the internal terminal surface plating layer, the wiring surface plating layer, the external terminal front and back plating layer along the substantially planar shape of the internal terminal from a part of the conductive substrate A substrate for mounting a semiconductor element, comprising a non-penetrating recess region for forming a metal part, a wiring metal part, and an external terminal metal part.   2. The part of the non-penetrating depression region includes a region on the back side of the conductive substrate of the semiconductor element mounting region, the internal terminal surface plating layer, and the wiring surface plating layer. A substrate for mounting semiconductor elements.   3. The semiconductor element mounting area according to claim 1, wherein the semiconductor element mounting area provided on the surface of the conductive substrate is a recessed area extending from the front surface side to the back surface side of the conductive substrate. substrate.   The shape of the cross section by the side of the external terminal back surface plating layer of the said external terminal metal part is a magnitude | size including the shape of the said external terminal back surface plating layer, The any one of Claim 1 to 3 characterized by the above-mentioned. The semiconductor element mounting substrate as described. A semiconductor element;
An internal terminal having an internal terminal surface plating layer disposed around the semiconductor element and electrically connectable to the electrode portion of the semiconductor element;
An external terminal that is disposed farther from the periphery of the semiconductor element than the internal terminal and has an external terminal back plating layer that is electrically connected to an external device,
A wiring portion for electrically connecting the internal terminal and the external terminal;
A bonding wire that electrically connects the electrode of the semiconductor element and the internal terminal surface plating layer of the internal terminal;
Each surface of the internal terminal surface plating layer, the external terminal surface plating layer, and the wiring surface plating layer, a first sealing resin that seals the bonding wire and the semiconductor element, and at least the external terminal metal portion A semiconductor device comprising: a second sealing resin for sealing the side surface and the side surface of the external terminal back surface plating layer.   6. The semiconductor device according to claim 5, wherein the internal terminal, the external terminal, and the wiring portion are connected by at least an internal terminal surface plating layer, an external terminal surface plating layer, and a wiring surface plating layer.   The semiconductor device according to claim 5, wherein at least the external terminal back plating layer is exposed from the second sealing resin.   8. The semiconductor device according to claim 5, wherein a shape of a longitudinal section of the external terminal metal part is a gentle curve or a taper shape extending from the back surface to the surface direction. 9.   The semiconductor device according to claim 5, wherein the first sealing resin and the second sealing resin are the same resin.   The semiconductor device according to claim 5, wherein a plurality of external terminals are arranged immediately below the semiconductor element region.   10. The semiconductor device according to claim 5, wherein a bottom surface of the semiconductor element is disposed at a position lower than a bottom surface of the internal terminal plating layer. 11. 5. The method for manufacturing a semiconductor element mounting substrate according to claim 1, comprising the following steps (1) to (8) in order:
(Record)
(1) A conductive substrate preparation step of preparing a conductive substrate.
(2) A first resist coating step of covering both surfaces of the conductive substrate with a first resist.
(3) A first exposure / development step for forming a plating mask having an opening by exposing / developing a predetermined pattern.
(4) Plating and first resist for removing the plating mask after plating the opening using the plating mask having the opening to form a predetermined surface plating layer and a predetermined back surface plating layer Removal process.
(5) A second resist coating step of covering both surfaces of the conductive substrate with the second resist after the plating / first resist removing step.
(6) A second exposure / development step in which a predetermined pattern is exposed / developed to form an etching mask having an opening.
(7) An etching step of forming a recessed region on the back surface of the conductive substrate by etching using the etching mask.
(8) A second resist removing step for removing the etching mask. The method for manufacturing a substrate for mounting a semiconductor element according to claim 3, comprising the steps (1) to (8) in order.
The predetermined pattern of the exposure mask in the first exposure / development step of (3) is a pattern in which the semiconductor element mounting region on the surface of the conductive substrate is covered with the first resist and the die pad surface plating layer is not formed.
The predetermined pattern in the second exposure / development step (6) is a pattern for forming an opening in a semiconductor element mounting region on the surface of the conductive substrate. Method. 10. The method for manufacturing a semiconductor device according to claim 5, further comprising the following steps (A) to (E) in order.
(Record)
(A) A semiconductor element mounting step of mounting a semiconductor element in a semiconductor element region of a semiconductor element mounting substrate.
(B) A wire bonding step of electrically connecting the electrode portion of the semiconductor element and the internal terminal surface plating layer using a bonding wire.
(C) A first resin sealing step in which a surface of a semiconductor element mounting substrate including a semiconductor element, a bonding wire, and a predetermined surface plating layer is resin-sealed with a first sealing resin.
(D) An etching process after resin sealing, in which etching is performed from the back side of the semiconductor mounting substrate, and predetermined metal parts are individually divided to be in an independent state except for electrical connection.
(E) A second resin sealing step in which a predetermined metal portion is resin-sealed with a second sealing resin so that at least the external terminal back plating layer is exposed on the surface of the second sealing resin. .

Images