JP2017033998A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of achieving a low-profile device while ensuring reliability of the device.SOLUTION: A semiconductor device comprises: a substrate 1 which has a principal surface 11 and a rear face 12 which face directions opposite to each other, and has a recess 14 having a bottom face 141 formed so as to dent from the principal surface 11, and which is made of synthetic resin; a semiconductor element 31 mounted on the bottom face 141; a conductive layer 20 which is conducted to the semiconductor element 31 and formed on the substrate 1; and encapsulation resin 4 for covering the semiconductor element 31. The substrate 1 has a plurality of through holes 15 formed to pierce the bottom face 141 and the rear face 12; and the conductive layer 20 includes a bottom face conductive part 21 formed on the bottom face 141, a rear face conductive part 22 formed on the rear face 12 and a connection conductive part 23 connected to the bottom face conductive part 21 and the rear face conductive part 22; in which all of the plurality of through holes 15 are blocked by the connection conductive part 23.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device in which a light emitting diode is particularly mounted as a semiconductor element on a synthetic resin substrate molded by injection molding, and a method for manufacturing the same.

  In recent years, molded circuit devices (MID: Molded Interconnect Device) have been developed, in which a circuit (conductive layer) patterned by the combination of electroless plating and electrolytic plating is formed on a substrate made of a thermoplastic resin molded by injection molding. It has reached practical use.

  For example, Patent Document 1 discloses a light emitting diode (LED) package made of the molded circuit component. In the package, a conductive layer exposed to the outside is formed on a side surface of the substrate and a main surface (top surface) that faces in the same direction as the emission direction of light emitted from the package.

  Among light emitting diode packages, a package that emits infrared light is used as a light emitting unit of a proximity sensor that is applied to touch panel electronic devices such as a mobile phone and a tablet terminal. Since such a touch panel type electronic device is strongly demanded to be thin, a light-emitting diode package mounted on a circuit board of the electronic device is required to be further reduced in height. Here, when trying to reduce the height of the light emitting diode package of the type disclosed in Patent Document 1, a conductive layer is formed on the side surface and main surface of the substrate so as to be exposed to the outside. When mounted on a circuit board, the solder melted by reflow may crawl up to the main surface via the side surface. At this time, a lump of solder is formed on the main surface of the substrate of the package, and when the electronic device is made thin, the lump of solder comes into contact with the casing of the electronic device and a defect occurs in the electronic device. There is a concern to do. Therefore, when the height of the package is reduced to reduce the thickness of the electronic device, there is a problem that the reliability of the package is lowered.

JP 2013-219090 A

  In view of the above circumstances, an object of the present invention is to provide a semiconductor device capable of reducing the height of the device while ensuring the reliability of the device.

  A semiconductor device provided by the first aspect of the present invention includes a main surface and a back surface facing opposite to each other, and a recess having a bottom surface formed to be recessed from the main surface, and is made of a synthetic resin. A substrate, a semiconductor element mounted on the bottom surface, a conductive layer that is electrically connected to the semiconductor element and formed on the substrate, and a sealing resin that covers the semiconductor element. A plurality of through holes penetrating the bottom surface and the back surface are formed, and the conductive layer includes a bottom surface conductive portion formed on the bottom surface, a back surface conductive portion formed on the back surface, the bottom surface conductive portion and the back surface conductivity. Each of the plurality of through holes is closed by the connecting conductive portion.

  In a preferred embodiment of the present invention, the connecting conductive portion is formed along each hole wall of the plurality of through holes.

  In a preferred embodiment of the present invention, each of the plurality of through holes is closed at the end near the bottom by the connecting conductive portion.

  In a preferred embodiment of the present invention, the concave portion further includes an inner side surface connected to the bottom surface and the main surface, and the inner side surface surrounds the bottom surface conductive portion in a plan view.

  In a preferred embodiment of the present invention, the bottom surface includes a first bottom surface located near the back surface and a second bottom surface located between the first bottom surface and the main surface in the thickness direction of the substrate. And a rising surface connected to the first bottom surface and the second bottom surface, and the semiconductor element is mounted on the bottom surface conductive portion formed on the first bottom surface.

  In a preferred embodiment of the present invention, the plurality of through holes penetrate the second bottom surface and the back surface.

  In a preferred embodiment of the present invention, the substrate further includes an outer surface that is sandwiched between the main surface and the back surface in the thickness direction of the substrate and faces outward, and the back surface conductive portion is , Spaced apart from the boundary between the back surface and the outer surface.

  In a preferred embodiment of the present invention, the synthetic resin is a thermoplastic resin.

  In a preferred embodiment of the present invention, the conductive layer includes an electroless plating layer and an electroplating layer laminated so as to cover the electroless plating layer, and the electroless plating layer includes the substrate. And the electrolytic plating layer.

  In a preferred embodiment of the present invention, the electroless plating layer is made of Cu.

  In a preferred embodiment of the present invention, the electrolytic plating layer has a Cu layer and an Au layer laminated on each other, and the Cu layer is interposed between the electroless plating layer and the Au layer. Yes.

  In a preferred embodiment of the present invention, the electrolytic plating layer further includes a Ni layer interposed between the Cu layer and the Au layer.

  In a preferred embodiment of the present invention, the semiconductor element is a light emitting diode.

  In a preferred embodiment of the present invention, the sealing resin is made of a synthetic resin having translucency.

  In a preferred embodiment of the present invention, the semiconductor device further includes a Zener diode mounted on the bottom surface conductive portion and connected in parallel with the light emitting diode.

  In a preferred embodiment of the present invention, a bonding wire for connecting the semiconductor element and the conductive layer is further provided.

  The method for manufacturing a semiconductor device provided by the second aspect of the present invention comprises a synthetic resin having a main surface and a back surface facing opposite to each other, and a recess having a bottom surface and recessed from the main surface. Forming a substrate, forming a plurality of through holes penetrating the bottom surface and the back surface, forming a conductive layer on the substrate including the recess, and being accommodated in the recess. Mounting the semiconductor element on the bottom surface, and forming a sealing resin covering the semiconductor element on the substrate, wherein the conductive layer includes a bottom surface conductive portion formed on the bottom surface, In the step of forming the conductive layer, the back surface conductive portion formed on the back surface and the bottom surface conductive portion and the back surface conductive portion connected to the back surface conductive portion. All holes blocked It is characterized in that.

  In a preferred embodiment of the present invention, in the step of forming the plurality of through holes, the plurality of through holes are formed in the substrate by laser irradiation.

  In a preferred embodiment of the present invention, in the step of forming the conductive layer, a step of forming an electroless plating layer, a step of patterning the electroless plating layer, and a step of forming an electroplating layer. In the step of forming the electrolytic plating layer, all of the plurality of through holes are closed by the connecting conductive portion.

  In a preferred embodiment of the present invention, a laser is used in the patterning step.

  In a preferred embodiment of the present invention, the step of forming the electrolytic plating layer includes a step of depositing a Cu layer and a step of depositing an Au layer by electrolytic plating.

  In a preferred embodiment of the present invention, the step of forming the electrolytic plating layer further includes a step of depositing a Ni layer interposed between the Cu layer and the Au layer by electrolytic plating.

  In a preferred embodiment of the present invention, in the step of forming the electrolytic plating layer, the step of removing the electroless plating layer not covered by the Cu layer by etching after the step of depositing the Cu layer. In addition.

  In a preferred embodiment of the present invention, in the step of forming the substrate, the substrate is formed by injection molding a thermoplastic resin.

  In a preferred embodiment of the present invention, the method further includes a step of forming a bonding wire for connecting the semiconductor element and the conductive layer by wire bonding after the step of mounting the semiconductor element.

  According to the present invention, the conductive layer formed on the substrate of the semiconductor device includes the bottom surface conductive portion formed on the bottom surface of the recess, the back surface conductive portion formed on the back surface, and the bottom surface. A conductive portion connected to the conductive portion and the back surface conductive portion. Further, the plurality of through holes penetrating the bottom surface and the back surface are formed in the substrate, and the plurality of through holes are closed by the connecting conductive portion. By adopting such a configuration, the bottom surface conductive portion and the back surface conductive portion are electrically connected to each other through the plurality of through holes. Therefore, the conductive layer is formed on the main surface and the outer surface of the substrate. Not formed. Therefore, since the solder melted by reflow does not crawl up to the main surface when the semiconductor device is mounted, it is possible to prevent the semiconductor device from interfering with the casings of various electronic devices due to the solder. Further, since the gas generated from the solder due to reflow does not enter the inside of the semiconductor device, it is possible to prevent the semiconductor device from being troubled by the gas. Therefore, it is possible to reduce the height of the semiconductor device while ensuring the reliability of the semiconductor device.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a principal part top view which shows the semiconductor device concerning 1st Embodiment of this invention (a sealing resin is abbreviate | omitted). It is a principal part bottom view which shows the semiconductor device of FIG. It is sectional drawing which follows the III-III line of FIG. It is sectional drawing which follows the IV-IV line of FIG. FIG. 5 is a cross-sectional view in which a semiconductor element, a bonding layer, and a sealing resin are omitted from FIG. FIG. 4 is a partially enlarged view of FIG. 3. FIG. 4 is a cross-sectional view showing a process according to the method for manufacturing the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view showing a process according to the method for manufacturing the semiconductor device of FIG. 1. It is a perspective view which shows the state of a board | substrate when passing through the process shown in FIG. FIG. 4 is a cross-sectional view showing a process according to the method for manufacturing the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view showing a process according to the method for manufacturing the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view showing a process according to the method for manufacturing the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view showing a process according to the method for manufacturing the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view showing a process according to the method for manufacturing the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view showing a process according to the method for manufacturing the semiconductor device of FIG. 1. FIG. 4 is a cross-sectional view showing a process according to the method for manufacturing the semiconductor device of FIG. 1. It is a principal part top view which shows the semiconductor device concerning 2nd Embodiment of this invention (a sealing resin is abbreviate | omitted). It is sectional drawing which follows the XVIII-XVIII line of FIG. FIG. 18 is a cross-sectional view taken along line XIX-XIX in FIG. 17 (a semiconductor element, a bonding layer, a sealing resin, and a Zener diode are omitted).

  An embodiment of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

[First Embodiment]
A semiconductor device A10 according to an embodiment of the present invention will be described with reference to FIGS. For convenience of explanation, the horizontal direction of the plan view is defined as a first direction X, and the vertical direction of the plan view perpendicular to the first direction X is defined as a second direction Y. Both the first direction X and the second direction Y are perpendicular to the thickness direction Z of the semiconductor device A10 (or a substrate 1 described later).

  FIG. 1 is a principal plan view showing the semiconductor device A10. FIG. 2 is a bottom view of an essential part showing the semiconductor device A10. 3 is a cross-sectional view taken along line III-III (dashed line) in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a cross-sectional view in which a semiconductor element 31, a bonding layer 32, and a sealing resin 4 described later with respect to FIG. FIG. 6 is a partially enlarged view of FIG. In FIG. 1, sealing resin 4 described later is omitted for the sake of understanding. FIG. 4 shows the omitted semiconductor element 31, bonding layer 32, and sealing resin 4 with imaginary lines (two-dot chain lines).

  The semiconductor device A10 shown in these drawings is a molded circuit component (MID) of a type that is surface-mounted on circuit boards of various electronic devices. The semiconductor device A10 according to this embodiment includes a substrate 1, a conductive layer 20, a semiconductor element 31, a bonding layer 32, a sealing resin 4, and a bonding wire 5. In the present embodiment, the semiconductor device A10 has a rectangular shape in plan view (viewed in the thickness direction Z of the substrate 1).

  The board | substrate 1 is a member used as the foundation of semiconductor device A10 by mounting the semiconductor element 31. FIG. The substrate 1 is an electrical insulator. In the present embodiment, the substrate 1 is made of a synthetic resin, and more specifically is a thermoplastic resin such as an aromatic polyamide or a liquid crystal polymer (LCP). Moreover, in this embodiment, the thickness of the board | substrate 1 is 400-700 micrometers. As shown in FIG. 1, the substrate 1 has a rectangular shape with the first direction X as a long side in plan view. The substrate 1 has a main surface 11, a back surface 12, an outer surface 13, a recess 14, and a plurality of through holes 15.

  The main surface 11 is the upper surface of the substrate 1 shown in FIGS. In the present embodiment, as shown in FIGS. 1, 3, and 4, a recess 14 is formed so as to be recessed from the main surface 11. Since the concave portion 14 is formed, the main surface 11 has a frame shape surrounding the concave portion 14 in plan view as shown in FIG. The back surface 12 is the bottom surface of the substrate 1 shown in FIGS. As shown in FIG. 2, since the back surface conductive portion 22 described later is formed on the back surface 12, the back surface 12 is a surface used when the semiconductor device A10 is mounted on circuit boards of various electronic devices. As shown in FIGS. 3 and 4, the main surface 11 and the back surface 12 are both orthogonal to the thickness direction Z of the substrate 1. The main surface 11 and the back surface 12 face opposite sides in the thickness direction Z of the substrate 1. Both the main surface 11 and the back surface 12 are flat.

  As shown in FIGS. 1, 3, and 4, the outer side surface 13 is sandwiched between the main surface 11 and the back surface 12 in the thickness direction Z of the substrate 1, and the first direction X or the second direction Y These are the four surfaces facing the outside. In the present embodiment, the outer side surface 13 is orthogonal to the main surface 11 and the back surface 12. Further, the outer side surfaces 13 are all flat.

  As shown in FIGS. 1, 3, and 4, the recess 14 is a part formed so as to be recessed from the main surface 11. The recess 14 does not penetrate the substrate 1 in the thickness direction Z of the substrate 1. The shape of the recess 14 in plan view is rectangular. The recess 14 has a bottom surface 141 and an inner surface 142.

  The bottom surface 141 is a surface on which the semiconductor element 31 is mounted. The bottom surface 141 includes a first bottom surface 141a, a second bottom surface 141b, and a standing surface 141c.

  As shown in FIGS. 3 and 4, the first bottom surface 141 a is a surface located closer to the back surface 12 in the thickness direction Z of the substrate 1. The first bottom surface 141 a is orthogonal to the thickness direction Z of the substrate 1 and is flat. In the present embodiment, the semiconductor element 31 is mounted on the first bottom surface 141a.

  As shown in FIGS. 3 and 5, the second bottom surface 141 b is a pair of surfaces located between the first bottom surface 141 a and the main surface 11 in the thickness direction Z of the substrate 1. As shown in FIGS. 1 and 3, the pair of second bottom surfaces 141b are separated in the first direction X with the first bottom surface 141a interposed therebetween. The pair of second bottom surfaces 141b are both orthogonal to the thickness direction Z of the substrate 1 and flat. In the present embodiment, a plurality of through holes 15 are formed in the second bottom surface 141b.

  As shown in FIGS. 3 and 5, the standing surface 141 c is a pair of surfaces that are connected to the first bottom surface 141 a and the second bottom surface 141 b and are formed along the thickness direction Z of the substrate 1. As shown in FIGS. 1 and 3, the pair of upstanding surfaces 141c are separated in the first direction X with the first bottom surface 141a interposed therebetween. The pair of rising surfaces 141c are both flat.

  As shown in FIGS. 1, 3 and 4, the inner side surface 142 is a surface connected to the bottom surface 141 and the main surface 11. The inner side surface 142 includes a pair of inner side surfaces 142 spaced in the first direction X and a pair of inner side surfaces 142 spaced in the second direction Y. The inner side surfaces 142 are all formed along the thickness direction Z of the substrate 1 and face the bottom surface 141. The pair of inner side surfaces 142 spaced apart in the first direction X has a lower end connected to the second bottom surface 141 b and an upper end connected to the main surface 11. The pair of inner side surfaces 142 spaced apart in the second direction Y have lower ends connected to the first bottom surface 141a, the second bottom surface 141b, and the standing surface 141c, and upper ends connected to the main surface 11, respectively.

  As shown in FIGS. 1 to 3, the plurality of through holes 15 are holes that penetrate the second bottom surface 141 b and the back surface 12 of the bottom surface 141 formed in the substrate 1. In the present embodiment, four through holes 15 are formed in the substrate 1. The shape of the through hole 15 in the thickness direction Z of the substrate 1 is substantially circular. Further, as shown in FIG. 6, the transverse shape of the through hole 15 with respect to the thickness direction Z of the substrate 1 is gradually reduced from the back surface 12 toward the second bottom surface 141b. Therefore, the shape of the through hole 15 is a substantially truncated cone. The through hole 15 has a hole wall 151.

  The conductive layer 20 is a member formed on the substrate 1 that constitutes a conductive path between the semiconductor device A10 and circuit boards of various electronic devices. In the present embodiment, the conductive layer 20 is electrically connected to the semiconductor element 31 through the bonding layer 32 and the bonding wire 5. The conductive layer 20 includes a bottom conductive part 21, a back conductive part 22, and a connecting conductive part 23.

  As shown in FIGS. 1 and 3 to 5, the bottom conductive portion 21 is a portion formed on the bottom 141. In the present embodiment, four bottom surface conductive portions 21 are formed on the second bottom surface 141b, and the through holes 15 are located in regions surrounded by the bottom surface conductive portions 21 in plan view. Among these, the two bottom surface conductive portions 21 are formed to extend to the first bottom surface 141a through the upright surface 141c. A semiconductor element 31 is mounted on the bottom surface conductive portion 21 formed on the first bottom surface 141a. In the present embodiment, the inner side surface 142 surrounds the bottom surface conductive portion 21 in plan view.

  As shown in FIGS. 2 to 5, the back surface conductive portion 22 is a part formed on the back surface 12. In the present embodiment, the back surface conductive portion 22 is formed at four locations on the back surface 12. The shape of each back surface conductive portion 22 is a shape in which a rectangle and a semicircle are combined. A through hole 15 is located at the center of the semicircular shape. In the present embodiment, the back surface conductive portion 22 is formed away from the boundary between the back surface 12 and the outer surface 13.

  As shown in FIGS. 3 and 6, the connecting conductive portion 23 is a portion connected to the bottom conductive portion 21 and the back conductive portion 22. Therefore, the bottom surface conductive portion 21 and the back surface conductive portion 22 are electrically connected to each other via the connection conductive portion 23. In the present embodiment, four connecting conductive portions 23 are formed on the substrate 1, and all are formed along the respective hole walls 151 of the plurality of through holes 15. Further, the plurality of through holes 15 are all closed by the connecting conductive portion 23. In the present embodiment, as shown in FIG. 6, the plurality of through holes 15 are all closed by the closing region 231 of the connecting conductive portion 23 at the end portion of the bottom surface 141 near the second bottom surface 141b.

  As shown in FIGS. 3 to 6, the conductive layer 20 includes an electroless plating layer 201 and an electrolytic plating layer 202. The electroless plating layer 201 is formed in contact with the substrate 1, and the electrolytic plating layer 202 is formed so as to cover the electroless plating layer 201. Therefore, the electroless plating layer 201 is interposed between the substrate 1 and the electrolytic plating layer 202. In the present embodiment, the electroless plating layer 201 is made of Cu and has a thickness of 400 to 800 nm. The electroplating layer 202 is various metal layers laminated on each other, and in this embodiment, has a Cu layer, a Ni layer, and an Au layer. Arrangement forms of various metal layers are the Cu layer, the Ni layer, and the Au layer in order from the electroless plating layer 201 side, and the surface of the electrolytic plating layer 202 is the Au layer. Therefore, the Cu layer is interposed between the electroless plating layer 201 and the Au layer, and the Ni layer is interposed between the Cu layer and the Au layer. In this embodiment, the Cu layer has a thickness of 5 to 25 μm, the Ni layer has a thickness of 2 to 13 μm, and the Au layer has a thickness of 0.02 to 1.4 μm. The Ni layer may be omitted from the arrangement.

  1 to 5 is an example, and the actual arrangement of the semiconductor device A10 is not limited to this.

  As shown in FIGS. 1 and 3 to 5, the semiconductor element 31 is mounted on the bottom surface conductive portion 21 formed on the first bottom surface 141 a via the bonding layer 32. In the present embodiment, the semiconductor element 31 is two light emitting diodes (LEDs), and the light emitting diodes emit infrared light. The semiconductor element 31 is an element in which a plurality of semiconductor layers are stacked on each other by, for example, a pn junction, and the semiconductor element 31 emits light when a current flows through the semiconductor device A10. In this embodiment, a p-side electrode (anode) is formed on the upper surface of the semiconductor element 31 shown in FIG. 3, and an n-side electrode (cathode) is formed on the lower surface of the semiconductor element 31 shown in FIG. ). By connecting the bonding wire 5 to the p-side electrode, the semiconductor element 31 is electrically connected to the bottom surface conductive portion 21 formed on the second bottom surface 141 b via the bonding wire 5. Further, since the n-side electrode is in contact with the bonding layer 32, the semiconductor element 31 is electrically connected to the bottom surface conductive portion 21 formed on the first bottom surface 141 a through the bonding layer 32. In the present embodiment, the number of semiconductor elements 31 is two, but the number of semiconductor elements 31 in the actual semiconductor device A10 is not limited to this.

  As shown in FIGS. 1 and 3 to 5, the bonding layer 32 is a conductive member that is interposed between the semiconductor element 31 and the bottom surface conductive portion 21 formed on the first bottom surface 141 a. By the bonding layer 32, the semiconductor element 31 is mounted on the bottom surface conductive portion 21 formed on the first bottom surface 141a by being fixed, and conduction between the semiconductor element 31 and the bottom surface conductive portion 21 is ensured. The bonding layer 32 is made of, for example, an Ag paste.

  As shown in FIGS. 3 and 4, the sealing resin 4 is a synthetic resin that covers the semiconductor element 31 filled in the recess 14. In the present embodiment, the sealing resin 4 is made of a synthetic resin having translucency and electrical insulation, for example, a silicone resin. In addition to the semiconductor element 31, the sealing resin 4 covers the bottom surface conductive portion 21, a part of the connecting conductive portion 23, the bonding layer 32, and the bonding wire 5. The sealing resin 4 has a resin main surface 41. The resin main surface 41 is a surface exposed in the semiconductor device A10. The resin main surface 41 is a surface facing the same direction as the main surface 11 and is flat. The resin main surface 41 is flush with the main surface 11.

  The bonding wire 5 is a wiring that connects the semiconductor element 31 and the bottom surface conductive portion 21 of the conductive layer 20 formed on the second bottom surface 141b. As shown in FIG. 1, in this embodiment, two bonding wires 5 are formed. The bonding wire 5 is made of, for example, Au.

  Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to FIGS. 7 to 16, the drawings excluding FIG. 9 are cross-sectional views illustrating steps in the method for manufacturing the semiconductor device A <b> 10. The cross section is the same as that shown in FIG. FIG. 9 is a perspective view showing a state of a substrate 81 to be described later when the process shown in FIG. 8 is performed.

  First, as shown in FIG. 7, a substrate 81 made of a synthetic resin having a main surface 811 and a back surface 812 and a plurality of recesses 814 recessed from the main surface 811 is formed. The substrate 81 is an aggregate of the substrates 1 of the semiconductor device A10. The substrate 81 is formed, for example, by injection molding a thermoplastic resin such as aromatic polyamide or liquid crystal polymer (LCP). The main surface 811 is a surface facing upward in FIG. The back surface 812 is a surface facing downward in FIG. The main surface 811 and the back surface 812 face each other in the thickness direction Z of the substrate 81. Both the main surface 811 and the back surface 812 are flat. The recess 814 has a bottom surface 814a and an inner surface 814b. The bottom surface 814 a has a step in the thickness direction Z of the substrate 81. The inner side surface 814b is a surface connected to the bottom surface 814a and the main surface 811, is formed along the bottom surface 814a, and stands up from the bottom surface 814a.

  Next, as shown in FIG. 8, a plurality of through holes 815 that penetrate the bottom surface 814 a and the back surface 812 are formed in the substrate 81. The through hole 815 corresponds to the through hole 815 of the semiconductor device A10. In the present embodiment, a plurality of through holes 815 are formed in the substrate 81 by laser irradiation. At this time, the laser irradiates the back surface 812. FIG. 9 is a perspective view showing a state where a plurality of through holes 815 are formed in a substrate 81 having a plurality of recesses 814. As shown in FIG. 9, a plurality of recesses 814 that are spaced apart in each of the first direction X and the second direction Y are formed so that the main surface 811 of the substrate 81 is recessed. For reference, a range corresponding to the substrate 1 of the semiconductor device A10 in the substrate 81 is indicated by a two-dot chain line in FIG.

  Next, the conductive layer 82 is formed on the substrate 81 including the recess 814. The conductive layer 82 corresponds to the conductive layer 20 of the semiconductor device A10. In the present embodiment, the step of forming the conductive layer 82 includes a step of forming the electroless plating layer 824, a step of patterning the electroless plating layer 824, and a step of forming the electroplating layer 825. The conductive layer 82 includes a bottom surface conductive portion 821 formed on the bottom surface 814a, a back surface conductive portion 822 formed on the back surface 812, and a connecting conductive portion 823 connected to the bottom surface conductive portion 821 and the back surface conductive portion 822. Bottom conductive portion 821, back conductive portion 822, and connecting conductive portion 823 correspond to bottom conductive portion 21, back conductive portion 22, and connecting conductive portion 23 of semiconductor device A10, respectively.

First, as shown in FIG. 10, an electroless plating layer 824 is formed on the entire main surface 811, back surface 812, and recess 814 of the substrate 81. In forming the electroless plating layer 824, the surface of the substrate 81 is first modified and roughened by, for example, ultraviolet rays. Next, the substrate 81 is immersed in the Pd ion catalyst solution, and the Pd ion catalyst is adsorbed on the roughened portion of the substrate 81. Next, the substrate 81 is immersed in, for example, an aqueous solution of sodium borohydride (NaBH ₄ ) to reduce the Pd ion catalyst adsorbed on the substrate 81 to Pd metal. Next, the substrate 81 on which the Pd metal is adsorbed is immersed in an electroless Cu plating solution, whereby an electroless plating layer 824 made of Cu with the Pd metal as a core is formed. At this time, the electroless plating layer 824 is also formed on each hole wall 815a of the plurality of through holes 815.

  Next, as shown in FIG. 11, the electroless plating layer 824 formed on the back surface 812 and the recess 814 is patterned. In this embodiment, patterning is performed using a laser. By patterning, the electroless plating layer 824 is divided into a conductive region 824a that becomes a part of the conductive layer 82 and a non-conductive region 824b that is not formed in the conductive layer 82 but is removed in a later step. Among these, the conductive region 824a corresponds to the electroless plating layer 201 of the semiconductor device A10. The substrate 81 is exposed from the boundary portion between the divided conductive region 824a and non-conductive region 824b.

  Next, an electrolytic plating layer 825 is formed in the conductive region 824a of the electroless plating layer 824. The electrolytic plating layer 825 corresponds to the electrolytic plating layer 202 of the semiconductor device A10. In the present embodiment, in the step of forming the electrolytic plating layer 825, the step of depositing the Cu layer 825a, the step of removing the non-conductive region 824b of the electroless plating layer 824 not covered with the Cu layer 825a by etching, The step of depositing the Ni layer 825b and the step of depositing the Au layer 825c are included.

  First, as shown in FIG. 12, a Cu layer 825a is deposited on the conductive region 824a by electrolytic plating. At this time, the Cu layer 825a is deposited also in the conductive region 824a formed in the hole wall 815a of the through hole 815, and the plurality of through holes 815 are closed by the deposited Cu layer 825a. Note that the Cu layer 825a is not deposited in the non-conductive region 824b.

Next, as shown in FIG. 13, all the non-conductive regions 824b not covered with the Cu layer 825a are removed by etching. The etching is, for example, wet etching using a mixed solution of sulfuric acid (H ₂ SO ₄ ) and hydrogen peroxide (H ₂ O ₂ ). The substrate 81 is exposed from the portion where the non-conductive region 824b is removed. At this time, the Cu layer 825a is also removed by the etching by a thickness corresponding to the layer thickness of the non-conductive region 824b. Even after the etching, the plurality of through holes 815 are all blocked by the Cu layer 825a.

  Next, as shown in FIG. 14, an Ni layer 825b and an Au layer 825c are deposited on the Cu layer 825a in this order by electrolytic plating. Therefore, the Ni layer 825b is interposed between the Cu layer 825a and the Au layer 825c. Through this step, the conductive layer 82 including the bottom conductive portion 821, the back conductive portion 822, and the connecting conductive portion 823 is formed. At this time, all of the plurality of through holes 815 are closed by the closed region 823a of the connecting conductive portion 823. Since the blocking region 823a includes the Cu layer 825a, the Ni layer 825b, and the Au layer 825c, the plurality of through holes 815 are blocked by the connecting conductive portion 823 in the step of forming the electrolytic plating layer 825. . The formation of the Ni layer 825b may be omitted.

  Next, as illustrated in FIG. 15, the semiconductor element 831 is mounted on the bottom surface 814 a so as to be accommodated in the recess 814. The semiconductor element 831 corresponds to the semiconductor element 31 of the semiconductor device A10. In the present embodiment, the semiconductor element 831 is a light emitting diode (LED) that emits infrared light. In mounting the semiconductor element 831, Ag paste is applied to the bottom surface conductive portion 821 formed on each bottom surface 814 a of the plurality of recesses 814, and the semiconductor element 831 is fixed to the bottom surface conductive portion 821 by die bonding. At this time, the Ag paste becomes the bonding layer 832. Thereafter, a bonding wire 85 for connecting the semiconductor element 831 and the bottom surface conductive portion 821 of the conductive layer 82 is formed by wire bonding. The bonding wire 85 corresponds to the bonding wire 5 of the semiconductor device A10.

  Next, as illustrated in FIG. 16, a sealing resin 84 that covers the semiconductor element 831 is formed on the substrate 81. The sealing resin 84 corresponds to the sealing resin 4 of the semiconductor device A10. The sealing resin 84 is formed so as to fill the concave portion 814 formed in the substrate 81 and completely cover the bottom surface conductive portion 821, a part of the connecting conductive portion 823, the semiconductor element 31, the bonding layer 32, and the bonding wire 5. To do. The sealing resin 84 is made of, for example, a synthetic resin having translucency and electrical insulation, for example, a silicone resin. The sealing resin 84 is formed by pouring the molten synthetic resin into each of the plurality of recesses 814 and solidifying it.

  Finally, the substrate 81 is cut (diced) to be divided into individual pieces for each recess 814. For cutting, for example, a dicing blade (not shown) is used. The piece becomes the semiconductor device A10. The semiconductor device A10 is manufactured through the above steps.

  Next, functions and effects of the semiconductor device A10 will be described.

  According to the present embodiment, the conductive layer 20 formed on the substrate 1 of the semiconductor device A10 includes the bottom surface conductive portion 21 formed on the bottom surface 141 of the recess 14, the back surface conductive portion 22 formed on the back surface 12, and the bottom surface. It includes a conductive portion 21 connected to the conductive portion 21 and the back surface conductive portion 22. In addition, a plurality of through holes 15 penetrating the bottom surface 141 and the back surface 12 are formed in the substrate 1, and all of the plurality of through holes 15 are closed by the connecting conductive portion 23. By adopting such a configuration, the bottom surface conductive portion 21 and the back surface conductive portion 22 are electrically connected to each other through the plurality of through holes 15, so that the conductive layer 20 is formed on the main surface 11 and the outer surface 13 of the substrate 1. Not formed. Therefore, when the semiconductor device A10 is mounted, the solder melted by the reflow does not crawl up to the main surface 11. Therefore, it is possible to prevent the semiconductor device A10 and the casings of various electronic devices from interfering with the solder. In addition, since the gas generated from the solder due to reflow does not enter the inside of the semiconductor device A10, it is possible to prevent the semiconductor device A10 from being defective due to the gas. Therefore, it is possible to reduce the height of the semiconductor device A10 while ensuring the reliability of the semiconductor device A10.

  The semiconductor element 31 is mounted on the bottom surface 141 of the recess 14 formed so as to be recessed from the main surface 11 in the substrate 1. Such a structure of the substrate 1 is suitable for reducing the height of the semiconductor device A10 because the inside of the substrate 1 is used as a housing space for the semiconductor element 31 and the sealing resin 4 does not protrude from the main surface 11. is there.

  The back surface conductive portion 22 is formed away from the boundary between the back surface 12 and the outer surface 13 of the substrate 1. Here, in manufacturing the semiconductor device A10, as shown in FIGS. 7 to 16, a process of forming the conductive layer 82 on the substrate 81, which is an assembly of the substrates 1, and mounting the semiconductor element 831 is performed. After that, the substrate 81 is cut to be divided into individual pieces for each recess 814. Therefore, by taking such a form of the back surface conductive portion 22, it is possible to prevent the occurrence of metal burrs caused by the conductive layer 82 at the boundary between the back surface 12 and the outer surface 13 of the semiconductor device A 10 due to the cutting of the substrate 81. be able to. In addition, when the metal burr | flash which generate | occur | produced in semiconductor device A10 becomes a fragment and falls on the circuit board of various electronic devices, there exists a possibility that malfunction may generate | occur | produce in this electronic device itself.

  An inner side surface 142 of the recess 14 surrounds the bottom surface conductive portion 21. In the present embodiment, since the semiconductor element 31 is mounted on the bottom conductive portion 21, the semiconductor element 31 is surrounded by the inner side surface 142. By adopting such a configuration, when the semiconductor element 31 is a light emitting diode, it is possible to prevent light from leaking from the side surface of the semiconductor device A10 and generating noise in various electronic devices.

  17 to 19 show other embodiments of the present invention. In these drawings, the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant description is omitted.

[Second Embodiment]
A semiconductor device A20 according to the second embodiment of the present invention will be described with reference to FIGS.

  FIG. 17 is a plan view of a principal part showing the semiconductor device A20. 18 is a cross-sectional view taken along the line XVIII-XVIII (dashed line) in FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. For convenience of understanding, FIG. 17 omits the sealing resin 4, and FIG. 19 omits the semiconductor element 31, the bonding layer 32, the sealing resin 4, and a Zener diode 33 described later. Further, FIG. 19 shows the omitted semiconductor element 31, bonding layer 32, sealing resin 4, and Zener diode 33 described later by imaginary lines (two-dot chain lines). In the present embodiment, the semiconductor device A20 has a rectangular shape in plan view.

  The semiconductor device A20 of this embodiment is different from the semiconductor device A10 described above in that it includes a configuration of the semiconductor element 31, the bonding layer 32, and the bonding wire 5, and further includes a Zener diode (constant voltage diode) 33.

  In the present embodiment, as shown in FIGS. 17 to 19, the bottom surface on which one of the two semiconductor elements 31 (light emitting diode) (the semiconductor element 31 shown on the left side in FIG. 17) is mounted. A Zener diode 33 is mounted on the conductive portion 21. Further, in this embodiment, the structure of the one semiconductor element 31 is different from that of the semiconductor device A10, and a p-side electrode (anode) and an n-side electrode (cathode) are formed on the upper surface of the one semiconductor element 31 shown in FIG. Are formed (not shown). When the bonding wire 5 is connected to the p-side electrode and the n-side electrode, the one semiconductor element 31 is electrically connected to the bottom surface conductive portion 21 formed on the second bottom surface 141b via the bonding wire 5. ing. Here, the bottom surface conductive part 21 on which the one semiconductor element 31 and the Zener diode 33 are mounted is an anode, and the bottom surface conductive part electrically connected to the one semiconductor element 31 and the Zener diode 33 through the bonding wire 5. 21 is a cathode. Therefore, the one semiconductor element 31 is not electrically connected to the bottom surface conductive portion 21 formed on the first bottom surface 141a. The structure of the other semiconductor element 31 is the same as that of the semiconductor device A10.

  In the present embodiment, since the one semiconductor element 31 is not electrically connected to the bottom surface conductive portion 21 formed on the first bottom surface 141 a, the junction interposed between the one semiconductor element 31 and the bottom surface conductive portion 21. Layer 32 is an electrical insulator. In this case, the bonding layer 32 is made of, for example, a synthetic resin mainly composed of a polyimide resin.

  As shown in FIGS. 17 to 19, the Zener diode 33 is mounted on the bottom surface conductive portion 21 formed on the second bottom surface 141 b and is connected in parallel with the one semiconductor element 31 (light emitting diode). When a reverse voltage is applied to the Zener diode 33, a sudden current flows through the Zener diode 33 when the voltage reaches a certain value. The Zener diode 33 has a characteristic that the voltage applied to the Zener diode 33 is substantially constant even when the magnitude of the current changes. In this embodiment, an n-side electrode (cathode) is formed on the upper surface of the Zener diode 33 shown in FIG. 18, and a p-side electrode (anode) is formed on the lower surface of the Zener diode 33 shown in FIG. By connecting the bonding wire 5 to the n-side electrode, the Zener diode 33 is electrically connected to the bottom surface conductive portion 21 formed on the second bottom surface 141b via the bonding wire 5. The p-side electrode is electrically connected to the bottom surface conductive portion 21 formed on the second bottom surface 141b through the bonding layer 32. Accordingly, the bonding layer 32 interposed between the Zener diode 33 and the bottom conductive portion 21 has conductivity, and is made of, for example, Ag paste.

  Also in the present embodiment, it is possible to reduce the height of the semiconductor device A20 while ensuring the reliability of the semiconductor device A20. In addition, according to the present embodiment, the Zener diode 33 further connected in parallel with the one semiconductor element 31 is further provided. By forming such a circuit in the semiconductor device A20, for example, when static electricity in the reverse direction is discharged with respect to the one semiconductor element 31, the static electricity flows through the Zener diode 33, Not flowing. In addition, when a forward voltage is applied to the semiconductor device A20, the voltage applied to the one semiconductor element 31 is always below a certain arbitrary value. Even when the forward static electricity is discharged to the semiconductor device A20, the voltage applied to the one semiconductor element 31 is always equal to or less than an arbitrary value as described above. Therefore, even if the static electricity in the forward direction and the reverse direction is discharged with respect to the semiconductor device A20, the one semiconductor element 31 can be prevented from being destroyed by the static electricity. In addition, it is possible to prevent a forward overvoltage from being applied to the one semiconductor element 31.

  The semiconductor device according to the present invention is not limited to the embodiment described above. The specific configuration of each part of the semiconductor device according to the present invention can be modified in various ways.

A10, A20: Semiconductor device 1: Substrate 11: Main surface 12: Back surface 13: Outer surface 14: Recessed surface 141: Bottom surface 141a: First bottom surface 141b: Second bottom surface 141c: Standing surface 142: Inner surface 15: Through hole 151: Hole wall 20: Conductive layer 201: Electroless plated layer 202: Electroplated layer 21: Bottom conductive portion 22: Back conductive portion 23: Connection conductive portion 231: Blocking region 31: Semiconductor element 32: Junction layer 33: Zener diode 4: Sealing resin 41: Resin main surface 5: Bonding wire 81: Substrate 811: Main surface 812: Back surface 814: Recess 814a: Bottom surface 814b: Inner surface 815: Through hole 815a: Hole wall 82: Conductive layer 821: Bottom conductive portion 822 : Back surface conductive portion 823: Connection conductive portion 823 a: Blocking region 824: Electroless plating layer 824 a: Conductive region 824 b: Non-conductive Region 825: electroplating layer 825a: Cu layer 825b: Ni layer 825c: Au layer 831: semiconductor device 832: bonding layer 84: sealing resin 85: bonding wire X: the first direction Y: the second direction Z: thickness direction

Claims (25)

A main surface and a back surface facing opposite sides, and a recess having a bottom surface formed so as to be recessed from the main surface, and a substrate made of a synthetic resin,
A semiconductor element mounted on the bottom surface;
A conductive layer electrically connected to the semiconductor element and formed on the substrate;
Sealing resin covering the semiconductor element,
A plurality of through holes penetrating the bottom surface and the back surface are formed in the substrate,
The conductive layer includes a bottom surface conductive portion formed on the bottom surface, a back surface conductive portion formed on the back surface, and a communication conductive portion connected to the bottom surface conductive portion and the back surface conductive portion,
The semiconductor device, wherein the plurality of through holes are all closed by the connecting conductive portion.   The semiconductor device according to claim 1, wherein the communication conductive portion is formed along each hole wall of the plurality of through holes.   3. The semiconductor device according to claim 2, wherein each of the plurality of through holes is closed by the connecting conductive portion at an end near the bottom surface.   4. The semiconductor device according to claim 1, wherein the recess further includes an inner side surface connected to the bottom surface and the main surface, and the inner side surface surrounds the bottom surface conductive portion in a plan view.   The bottom surface includes, in the thickness direction of the substrate, a first bottom surface located closer to the back surface, a second bottom surface located between the first bottom surface and the main surface, the first bottom surface, and the second bottom surface. 5. The semiconductor device according to claim 1, further comprising: an upstanding surface connected to a bottom surface, wherein the semiconductor element is mounted on the bottom surface conductive portion formed on the first bottom surface.   The semiconductor device according to claim 5, wherein the plurality of through holes penetrate the second bottom surface and the back surface.   The substrate further includes an outer surface that is sandwiched between the main surface and the back surface in the thickness direction of the substrate and faces the outside, and the back surface conductive portion is a boundary between the back surface and the outside surface. The semiconductor device according to claim 1, wherein the semiconductor device is formed apart from the semiconductor device.   The semiconductor device according to claim 1, wherein the synthetic resin is a thermoplastic resin.   The conductive layer includes an electroless plating layer and an electroplating layer laminated to cover the electroless plating layer, and the electroless plating layer is interposed between the substrate and the electroplating layer. The semiconductor device according to claim 1, wherein   The semiconductor device according to claim 9, wherein the electroless plating layer is made of Cu.   The said electroplating layer has Cu layer and Au layer which were mutually laminated | stacked, The said Cu layer is interposed between the said electroless-plating layer and the said Au layer, The Claim 9 or 10 Semiconductor device.   The semiconductor device according to claim 11, wherein the electrolytic plating layer further includes a Ni layer interposed between the Cu layer and the Au layer.   The semiconductor device according to claim 1, wherein the semiconductor element is a light emitting diode.   The semiconductor device according to claim 13, wherein the sealing resin is made of a synthetic resin having translucency.   The semiconductor device according to claim 13, further comprising a Zener diode mounted on the bottom surface conductive portion and connected in parallel with the light emitting diode.   The semiconductor device according to claim 1, further comprising a bonding wire that connects the semiconductor element and the conductive layer. Molding a substrate made of a synthetic resin having a main surface and a back surface facing opposite sides, and a recess having a bottom surface and recessed from the main surface;
Forming a plurality of through holes penetrating the bottom surface and the back surface of the substrate;
Forming a conductive layer on the substrate including the recess;
Mounting a semiconductor element on the bottom surface so as to be received in the recess;
Forming a sealing resin covering the semiconductor element on the substrate,
The conductive layer includes a bottom surface conductive portion formed on the bottom surface, a back surface conductive portion formed on the back surface, and a communication conductive portion connected to the bottom surface conductive portion and the back surface conductive portion,
In the step of forming the conductive layer, the plurality of through holes are closed by the formation of the connecting conductive portion.   The method of manufacturing a semiconductor device according to claim 17, wherein in the step of forming the plurality of through holes, the plurality of through holes are formed in the substrate by laser irradiation.   The step of forming the conductive layer includes a step of forming an electroless plating layer, a step of patterning the electroless plating layer, and a step of forming an electrolytic plating layer, and forming the electrolytic plating layer The method of manufacturing a semiconductor device according to claim 17, wherein all of the plurality of through holes are closed by the connecting conductive portion.   The method of manufacturing a semiconductor device according to claim 19, wherein a laser is used in the patterning step.   21. The method of manufacturing a semiconductor device according to claim 19, wherein the step of forming the electrolytic plating layer includes a step of depositing a Cu layer and a step of depositing an Au layer by electrolytic plating.   The method for manufacturing a semiconductor device according to claim 21, wherein the step of forming the electrolytic plating layer further includes a step of depositing a Ni layer interposed between the Cu layer and the Au layer by electrolytic plating.   The step of forming the electrolytic plating layer further includes a step of removing the electroless plating layer not covered with the Cu layer by etching after the step of depositing the Cu layer. Semiconductor device manufacturing method.   24. The method of manufacturing a semiconductor device according to claim 17, wherein in the step of forming the substrate, the substrate is formed by injection molding of a thermoplastic resin.   25. The method for manufacturing a semiconductor device according to claim 17, further comprising a step of forming a bonding wire for connecting the semiconductor element and the conductive layer by wire bonding after the step of mounting the semiconductor element. .

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