JP2017022279A - Heterojunction bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a heterojunction bipolar transistor (HBT) capable of improving a maximum oscillation frequency without reducing uniformity or reproducibility in manufacture and without reducing a current gain.SOLUTION: The heterojunction bipolar transistor comprises: a first base layer 105 formed on a collector layer 104; a base contact layer 106 formed on the first base layer 105 in contact therewith; a second base layer 107 formed on the base contact layer 106 in contact therewith; and an emitter layer 108 formed on the second base layer 107. A hole concentration (average concentration) of the base contact layer 106 is higher than those of the first base layer 105 and the second base layer 107, the hole concentration of the base contact layer 106 is 1×10cmor lower and the hole concentrations of the first base layer 105 and the second base layer 107 are 1×10cmor higher.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a heterojunction bipolar transistor having an element portion composed of a collector, a base, and an emitter.

  There is an increasing demand for high-speed communication and large capacity, and there is a demand for improved performance of high-frequency semiconductor transistors such as heterojunction bipolar transistors (HBTs). In recent years, research using an InP-based HBT having particularly excellent high-frequency characteristics has been actively conducted in an IC that operates in a band of about 1 THz, which is called a millimeter wave or a terahertz band.

As an index for evaluating the high-frequency characteristics of the transistor, there are a current gain cut-off frequency f _T and a maximum oscillation frequency f _max . f _T is expressed by the following equation.

In the above equation, τ _E is the emitter charging time, τ _B is the base traveling time, τ _C is the collector traveling time, and τ _CC is the collector charging time. τ _E and τ _CC are expressed by the contact resistance and capacitance of the emitter and collector. Therefore, in order to improve f _T , it is important to reduce the capacitance by reducing the element area, or to reduce the contact resistance by a highly doped contact. Further, τ _B and τ _C represent the time required for electrons to pass through the base and collector, and it is necessary to shorten these travel times in order to further improve f _T.

Further, f _max can be expressed by the following equation.

In the above formula, R _B is the base resistance, and C _BC is the capacitance between the base and the collector. It is necessary to further reduce f _max to reduce these. In particular, the base resistance is represented by the sum of the intrinsic resistance of the base immediately under the emitter, the access resistance from the base electrode to the region where carriers flow, and the contact resistance with the base electrode. In order to improve f _max , reducing the intrinsic resistance with a heavily doped base is one means, but since the current gain decreases with increasing doping concentration, the doping concentration is increased unnecessarily. I don't want it. Accordingly, there is a need for means for improving f _max by reducing other components such as contact resistance.

  By the way, in the compound semiconductor device as described above, a predetermined layer is first laminated on a substrate such as InP by an epitaxial growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). I am making it. For example, in an InP-based HBT, a layer structure of a desired compound semiconductor such as a subcollector formation layer, a collector formation layer, a base formation layer, an emitter formation layer, and an emitter contact formation layer is generally stacked on an InP substrate.

  Such a laminated structure is patterned by using a resist pattern formed by a known lithography technique and using the resist pattern as a mask by an etching technique to produce a mesa structure such as an emitter mesa or a base mesa. By using an etchant with high etching selectivity and etching only a desired semiconductor layer to leave a necessary layer, the above-described mesa structure can be manufactured relatively easily. Thus, the mesa structure is manufactured, and the emitter contact electrode, the base contact electrode, and the collector contact electrode are formed by a high vacuum deposition method or the like to manufacture the HBT.

As a structure for increasing the HBT of f _T, the so-called gradient composition base structure and the like. In this structure, the band gap of the base layer is continuously changed in the base layer, thereby inducing a pseudo electric field and accelerating electrons traveling from the emitter side in the base layer, and traveling in the base layer. The time, that is, τ _B + τ _C is shortened.

For example, when InGaAs is applied to the base layer, the solid phase In composition is increased from the emitter layer side to the collector layer side of the base layer by utilizing the fact that the band gap of this material tends to decrease as the In composition increases. Is changed from a small state to a large state. By doing so, the band gap of the base layer changes from a large band gap to a small band from the emitter side to the collector side. Along with such a change in the band gap, a pseudo electric field is applied to the base layer, and electrons injected from the emitter are accelerated. Due to the effect of this pseudo electric field, τ _B + τ _C is shortened, and a higher f _T can be obtained than when the base layer does not have a composition gradient (see Non-Patent Document 1).

  Such a composition gradient structure is not limited to InGaAs as a base layer material, and can be formed by adjusting the mixing ratio of Sb and As in the base layer, for example, even with GaAsSb (see Non-Patent Document 2).

  Further, the technique for generating the pseudo electric field is not limited to the composition gradient, and for example, it can be formed by changing the doping concentration in the base layer. When the doping concentration of the base layer increases, Fermi energy enters the valence band in the degenerate semiconductor, and the conduction band energy in the thermal equilibrium state increases accordingly. Therefore, a pseudo electric field can be induced by reducing the doping concentration of the base layer from the emitter side to the collector side without changing the band gap of the material (see Non-Patent Document 3).

Graded layer as described above, a structural contrivance order to mainly improve f _T. On the other hand, for improving f _max , as described above, it is effective to reduce the contact resistance between the base electrode and the base layer. As one of the techniques, a technique for forming an external base layer by epitaxial regrowth has been reported. This technique will be described with reference to FIG.

  The HBT shown in FIG. 6 includes a substrate 601, a buffer layer 602 formed on the substrate 601, a subcollector layer 603 formed on the buffer layer 602, and a collector formed on the subcollector layer 603. A layer 604; a base layer 605 formed on the collector layer 604; an emitter layer 607 formed on the base layer 605; and an emitter contact layer 608 formed on the emitter layer 607.

  An emitter electrode 611 is formed on the emitter contact layer 608. Further, a base electrode 612 is formed on the base layer 605 around the emitter mesa by the emitter layer 607 and the emitter contact layer 608 via a regrown external base layer 606. A collector electrode 613 is formed on the subcollector layer 603 around the collector mesa formed by the collector layer 604 and the base layer 605.

  In a general HBT, after forming an emitter mesa, the base layer surface is exposed by selective wet etching or the like, and a base electrode is formed so as to be in contact with the base layer surface. In contrast, the above-described HBT has a base electrode 612 formed on a regrowth external base layer 606 formed by regrowth. In this structure, an emitter mesa is formed to expose the surface of the base layer 605, and then a regrowth outer base layer 606 doped to a higher hole concentration is formed by selective regrowth.

In the regrowth of the regrowth external base layer 606, a mask 621 is formed in advance with SiN _x or the like for the purpose of preventing crystal growth in the emitter electrode 611, emitter mesa structure, and the region where the base electrode 612 is not formed. Keep it.

By forming the base electrode 612 on the regrowth external base layer 606 doped to this higher hole concentration, the contact resistance between the base electrode 612 and the regrowth external base layer 606 can be reduced, The f _max of HBT can be improved.

In a normal HBT, the current gain and the intrinsic resistance of the base layer are in a trade-off relationship, and the current gain decreases as the intrinsic resistance decreases. On the other hand, to improve f _max , it is necessary to reduce base resistance. Therefore, in general, f _max and current gain have a trade-off relationship. In the structure of the HBT described with reference to FIG. 6, the device structure immediately below the emitter layer is the same as the conventional structure. For this reason, the current gain of this HBT is almost equivalent to the structure in which the regrowth external base layer 606 is not regrown. Therefore, the external base regrowth structure is an effective method that can improve f _max without impairing the current gain (see Non-Patent Document 4).

  Next, another configuration will be described with reference to FIG. 7 includes a substrate 701, a buffer layer 702 formed on the substrate 701, a subcollector layer 703 formed on the buffer layer 702, and a collector formed on the subcollector layer 703. Layer 704, first base layer 705 formed on collector layer 704, second base layer 706 formed on first base layer 705, and emitter formed on second base layer 706 A layer 707 and an emitter contact layer 708 formed on the emitter layer 707 are provided.

  An emitter electrode 711 is formed on the emitter contact layer 708. A base electrode 712 is formed on the second base layer 706 around the emitter mesa by the emitter layer 707 and the emitter contact layer 708. A collector electrode 713 is formed on the sub-collector layer 703 around the collector mesa by the collector layer 704, the first base layer 705, and the second base layer 706.

In this HBT, the impurity concentration of the second base layer 706 having a thickness of several nanometers close to the emitter layer 707 is set to a p-doped state higher than that of the normal (first base layer 705). There are various uses for this structure, one is to achieve a low base contact resistance without significantly degrading the current gain, thereby achieving a high f _max . By doping only the second base layer 706 close to the emitter layer at a high concentration, the contact resistance with the base electrode 712 can be reduced without significantly reducing the average sheet resistance of the entire base layer. It is possible to improve f _max (see Non-Patent Document 5).

  Although the above report uses InGaAs for the base layer, a similar structure has also been reported for HBTs having GaAsSb for the base layer. In particular, in this report, a region having a thickness of about 4 nm close to the emitter layer in the base layer is a layer having a high As composition and a high concentration, in combination with the above base contact resistance reduction effect. It is also used for pseudo electric field control in the base layer (see Non-Patent Document 6).

W. Snodgrass, W. Hafez, N. Harff, and M. Feng, "Pseudomorphic InP / InGaAs Heterojunction Bipolar Transistors (PHBTs) Experimentally Demonstrating fT = 765 GHz at 25 ℃ Increasing to fT = 845 GHz at -55 ℃", IEEE Proceedings of IEDM, pp.1-4, 2006. HG Liu, O. Ostinelli, Y. Zeng, and CR Bolognesi, "600 GHz InP / GaAsSb / InP DHBTs Grown by MOCVD with a Ga (As, Sb) Graded-Base and fT x BVCEO> 2.5 THz-V at Room Temperature ", IEEE Proceedings of IEDM, pp.667-670, 2007. H. Xu, B. Wu, EW Iverson, TS Low, and M. Feng, "0.5 THz Performance of a Type-II DHBT With a Doping-Graded and Constant-Composition GaAsSb Base", IEEE Electron Device Letter, vol.35 , no.1, pp.24-26,2014. M. Ida, S. Yamahata, K. Kurishima, H. Ito, T. Kobayashi, and Y. Matsuoka, "Enhancement of fmax in InP / InGaAs HBT's by Selective MOCVD Growth of Heavily-Doped Extrinsic Base Regions", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.43, no.11, pp.1812-1818, 1996. MJW Rodwell, J. Rode, HW Chiang, P. Choudhary, T. Reed, E. Bloch, S. Danesgar, HC Park, AC Gossard, BJ Thibeault, W. Mitchell, M. Urteaga, Z. Griffith, J. Hacker , M. Seo, B. Brar, "THz INDIUM PHOSPHIDE BIPOLAR TRANSISTOR TECHNOLOGY", IEEE Proceedings of CSICS 2012, pp.1-4. R. Lovblom, R. Fluckiger, O. Ostinelli, M. Alexandrova, C. Bolognesi, "Base Design for High-Speed InP / GaAsSb DHBTs", The 26th International Conferance on Indium Phosphide and Related Materials, 2014, Th-D2- 3. H. -W. Chiang, J. C. Rode, P. Choudhary, and M. J. W. Rodwell, "Optimization of direct current performance in terahertz InGaAs / InP doubleheterojunction bipolar transistors", Journal of Applied Physics, vol.116, 164509, 2014. T. Hoshi, N. Kashio, H. Sugiyama, H. Yokoyama, K. Kurishima, M. Ida, H. Matsuzaki, and H. Gotoh, "A simple method for forming compositionally graded InxGa1-xAs1-ySby base of double- heterojunction bipolar transistors modulating CBr4-doping-precursor flow in metalorganic chemical vapor deposition ", Applied Physics Express, vol.7, 114102, 2014. T. Hoshi, N. Kashio, H. Sugiyama, H. Yokoyama, K. Kurishima, M. Ida, H. Matsuzaki, and M. Kohtoku, "Impact of strained GaAs spacer between InP emitter and GaAs1-ySby base on structural properties and electrical characteristics of MOCVD-grown InP / GaAs1-ySby / InP DHBTs ", Journal of Crystal Growth, vol.395, pp.31-37, 2014.

As described above, conventionally, in order to improve the f _max of HBT, a technique for selectively re-growing an external base layer having a high hole concentration in the external base region, or a hole concentration in a region close to the emitter layer in advance. Techniques have been proposed for introducing a second base layer with an increased height. However, both techniques have the following problems from the viewpoint of reduction in current gain and reproducibility.

In an HBT structure using a regrowth external base layer, it is possible to reduce the base contact resistance without compromising the current gain and to achieve both high f _max and current gain, but in order to use the regrowth technique, Problems arise in the uniformity and reproducibility of the solid phase composition and doping concentration of the regrown external base layer.

In the structure in which the second base layer having a high hole concentration is formed in a region close to the emitter layer of the base layer, regrowth is not used, so reproducibility and uniformity are problems compared to the case of using regrowth. Don't be. However, in order to form a region having a high hole concentration in a region close to the emitter layer, a decrease in current gain is caused by an increase in recombination current at the emitter-base interface. For this reason, although this technique can be expected to improve f _max by reducing the contact resistance, the current gain is reduced as compared with the technique using regrowth (see Non-Patent Document 7).

  As described above, the conventional techniques have a problem that the manufacturing uniformity and reproducibility are reduced, while the current gain is reduced.

  The present invention has been made in order to solve the above-described problems, and the maximum oscillation frequency is reduced without causing deterioration in manufacturing uniformity and reproducibility and without causing reduction in current gain. The purpose is to be able to improve.

A heterojunction bipolar transistor according to the present invention includes a substrate made of InP, a collector layer made of a III-V group compound semiconductor formed on the substrate, and a p doped with carbon containing Ga, As, and Sb. A first base layer made of a type III-V compound semiconductor and formed on a collector layer, and a p-type group III-V compound semiconductor doped with carbon containing Ga, As, Sb A base contact layer formed on and in contact with the first base layer, and a p-type III-V group compound semiconductor containing In, Ga, As, and Sb and doped with carbon. A second base layer formed in contact with the first base layer, an emitter layer made of a III-V group compound semiconductor formed on the second base layer, an emitter electrode connected to the emitter layer, an emitter A base electrode connected to the base contact layer around the contact layer and a collector electrode connected to the collector layer, wherein the base contact layer has a higher hole concentration than the first base layer and the second base layer; The contact layer has a hole concentration of 1 × 10 ²¹ cm ⁻³ or less, and the first base layer and the second base layer have a hole concentration of 1 × 10 ¹⁹ cm ⁻³ or more.

  The heterojunction bipolar transistor may include a second base layer disposed between the base electrode and the emitter layer.

  In the heterojunction bipolar transistor, the base contact layer may have a thickness of 1 nm to 5 nm.

  In the heterojunction bipolar transistor, the first base layer and the second base layer may be made of InGaAsSb, and the base contact layer may be made of GaAsSb.

  As described above, according to the present invention, it is possible to obtain an excellent effect that the maximum oscillation frequency can be improved without causing deterioration in manufacturing uniformity and reproducibility and without causing reduction in current gain. .

FIG. 1 is a cross-sectional view showing a configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2A is a cross-sectional view showing a state in an intermediate step for explaining a method of manufacturing a heterojunction bipolar transistor in an embodiment of the present invention. FIG. 2B is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 2C is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 2D is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 2E is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3A is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3B is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3C is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 3D is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 4A is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 4B is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 4C is a cross-sectional view showing a state in an intermediate step for explaining the method of manufacturing the heterojunction bipolar transistor in the embodiment of the present invention. FIG. 5 is a characteristic diagram in which the base contact resistance of the actually fabricated HBT is plotted against the base doping concentration. FIG. 6 is a cross-sectional view showing the configuration of the heterojunction bipolar transistor. FIG. 7 is a cross-sectional view showing the configuration of the heterojunction bipolar transistor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a configuration of a heterojunction bipolar transistor (HBT) in an embodiment of the present invention.

  The HBT includes a substrate 101, a buffer 102 formed on the substrate 101, a subcollector layer 103 formed on the buffer layer 102, a collector layer 104 formed on the subcollector layer 103, First base layer 105 formed on collector layer 104, base contact layer 106 formed on and in contact with first base layer 105, and second base formed on and in contact with base contact layer 106 A layer 107; an emitter layer 108 formed on the second base layer 107; and an emitter contact layer 109 formed on the emitter layer 108.

  An emitter electrode 111 is formed on the emitter contact layer 109. In the embodiment, the emitter electrode 111 is connected to the emitter layer 108 via the emitter contact layer 109. Further, a base electrode 112 is formed in connection with the base contact layer 106 around the emitter mesa (emitter layer 108) by the second base layer 107, the emitter layer 108, and the emitter contact layer 109. A collector electrode 113 is formed on the subcollector layer 103 around the collector mesa by the collector layer 104, the first base layer 105, and the base contact layer 106. The buffer layer 102 and the subcollector layer 103 have a predetermined mesa shape and are isolated from each other. The collector mesa has a smaller area than this mesa, and the emitter mesa has a smaller area than the collector mesa.

The substrate 101 is made of, for example, InP made semi-insulating by doping iron, and the buffer layer 102 is made of InP. Further, the sub-collector layer 103, InP n-type impurity is added at high concentration (1 × 10 ¹⁹ cm ^-3 or higher) or n-type impurity, is added at a high concentration (1 × 10 ¹⁹ cm ^-3 or higher) InGaAs.

The collector layer 104 is made of n-type InP, and the emitter layer 108 is made of InP to which an n-type impurity is added in the range of 1 × 10 ¹⁶ to 10 ¹⁸ cm ⁻³ and has a layer thickness of 10 to 100 nm. It is said to be about. The emitter contact layer 109 is made of InGaAs to which an n-type impurity is added at a high concentration (1 × 10 ¹⁹ cm ⁻³ or more).

  The emitter electrode 111, the base electrode 112, and the collector electrode 113 are made of a metal material such as Ti, Pt, Au, or W.

  The first base layer 105 is made of p-type InGaAsSb doped with carbon, the base contact layer 106 is made of p-type GaAsSb doped with carbon, and the second base layer 107 is made of carbon. It is made of doped p-type InGaAsSb. In the present invention, as described later, it is important that the second base layer 107 is made of InGaAsSb. The first base layer 105 and the base contact layer 106 may be made of GaAsSb. In particular, the base contact layer 106 is preferably made of GaAsSb. On the other hand, the first base layer 105 is preferably composed of InGaAsSb and has a composition gradient structure described later.

Here, the base contact layer 106 has a higher hole concentration (average concentration) than the first base layer 105 and the second base layer 107, and the base contact layer 106 has a hole concentration of 1 × 10 ²¹ cm ^−3. It is important that the first base layer 105 and the second base layer 107 have a hole concentration of 1 × 10 ¹⁹ cm ⁻³ or more. When the hole concentration of the first base layer 105 is p1, the hole concentration of the second base layer 107 is p2, and the hole concentration of the base contact layer 106 is pc, “1 × 10 ¹⁹ cm ⁻³ <p1, p2 < pc <1 × 10 ²¹ cm ⁻³ ”.

  In the embodiment, the first base layer 105 has a larger band gap (composition gradient) as the region closer to the base contact layer 106 in the stacking direction has a lower In composition and Sb composition. In addition, the first base layer 105 has a higher carbon doping concentration in a region closer to the base contact layer 106 in the stacking direction (doping gradient). These inclined structures can be formed by the method shown in Non-Patent Document 8.

  On the other hand, the second base layer 107 has a constant In composition and Sb composition in the stacking direction. The second base layer 107 only needs to have a layer thickness of about 2 nm. Here, in order to improve the current gain by separating the base contact layer 106 having a high hole concentration from the emitter layer 108, the thickness of the second base layer 107 may be 1 nm or more.

  If the thickness of the base contact layer 106 is about 2 to 4 nm, the contact resistance reduction effect can be sufficiently obtained. For the purpose of reducing the electrical contact resistance between the base electrode 112 and the base contact layer 106, the thickness of the base contact layer 106 may be 1 nm.

  In the HBT in the above-described embodiment, the base electrode 112 is formed in contact with (in contact with) the base contact layer 106. Since the base contact layer 106 has a higher hole concentration than the first base layer 105 and the second base layer 107, the contact resistance between the base electrode 112 and the base contact layer 106 can be reduced.

  In addition, according to the embodiment, the second base layer 107 is in contact with the emitter layer 108. Since the second base layer 107 is set to have a doping concentration lower than that of the base contact layer 106, compared to a structure without the second base layer 107 as shown in Non-Patent Document 5 and Non-Patent Document 6, The hole concentration in the vicinity of the interface with the emitter layer 108 is set low.

  The recombination current of the HBT is greatly influenced by the emitter-base junction interface and the exposed region of the base layer surface. Therefore, in the structure in which the region is doped with a high hole concentration as in Non-Patent Documents 5 and 6, an increase in recombination current, that is, a decrease in current gain is likely to be caused.

  On the other hand, according to the embodiment, the base contact layer 106 having a high hole concentration is sandwiched between the second base layer 107 and the first base layer 105 and embedded therein. For this reason, the above-described decrease in current gain is unlikely to occur. In addition, according to the embodiment, since the second base layer 107 disposed in contact with the emitter layer 108 is made of InGaAsSb, the base layer in contact with the emitter layer is made of GaAsSb as will be described later. Compared to the case, a high current gain is easily obtained.

For these reasons, according to the embodiment, it is possible to achieve an increase in f _max by reducing the contact resistance without causing a decrease in current gain.

  Next, the manufacturing method of HBT mentioned above is demonstrated. First, as shown in FIG. 2A, a collector formation layer 204 made of a III-V group compound semiconductor, an emitter formation layer 208 made of a group III-V compound semiconductor, and between the collector formation layer 204 and the emitter formation layer 208 A first base formation layer 205 disposed; a base contact formation layer 206 disposed in contact with the first base formation layer 205 between the first base formation layer 205 and the emitter formation layer 208; and a first base formation layer. A stacked structure including the second base formation layer 207 disposed in contact with the base contact formation layer 206 between the 205 and the emitter formation layer 208 is formed on the substrate 101. In the embodiment, the collector formation layer 204, the first base formation layer 205, the base contact formation layer 206, the second base formation layer 207, and the emitter formation layer 208 are formed in this order from the substrate 101 side. The layer thickness of each layer is set appropriately.

The first base formation layer 205 is composed of p-type InGaAsSb doped with carbon, the base contact formation layer 206 is composed of p-type GaAsSb doped with carbon, and the second base formation layer 207 is composed of carbon. P-type InGaAsSb doped with The base contact formation layer 206 has a higher hole concentration than the first base formation layer 205 and the second base formation layer 207. The base contact formation layer 206 has a hole concentration of 1 × 10 ²¹ cm ⁻³ or less. The first base formation layer 205 and the second base formation layer 207 have a hole concentration of 1 × 10 ¹⁹ cm ⁻³ or more.

Added in the embodiment, on the substrate 101, a buffer layer 202 made of InP, InP n-type impurity is added 1 × 10 ¹⁹ cm ^-3 or more, or n-type impurity, is 1 × 10 ¹⁹ cm ^-3 or more On the subcollector formation layer 203 made of InGaAs, the above-described stacked structure is formed. On the emitter forming layer 208 made of InP to which n-type impurities are added in the range of 1 × 10 ¹⁶ to 10 ¹⁸ cm ⁻³ , InGaAs to which n-type impurities are added at 1 × 10 ¹⁹ cm ⁻³ or more. An emitter contact formation layer 209 is formed.

  Each semiconductor layer described above may be grown sequentially by, for example, metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

  After forming the above laminated structure, as shown in FIG. 2B, an emitter electrode material is deposited on the emitter contact formation layer 209 to form a metal film, and this metal film is patterned by a known lithography technique or the like. An emitter electrode 111 is formed.

  Next, using the emitter electrode 111 as a mask, the emitter contact formation layer 209 and the emitter formation layer 208 are patterned by a known etching technique to form an emitter mesa by the emitter layer 108 and the emitter contact layer 109 as shown in FIG. 2C. . In this stage, the upper surface of the second base formation layer 207 is exposed around the emitter mesa.

  For example, if the emitter contact formation layer 209 is patterned to form the emitter contact layer 109 by wet etching using a highly selective etchant such that InGaAs such as citric acid is well etched and InP is not etched much. good. Further, the emitter layer 108 may be formed by patterning the emitter formation layer 208 by wet etching using a highly selective etchant that does not etch InGaAsSb very much.

  Subsequently, the second base formation layer 207 is patterned to form the second base layer 107 as shown in FIG. 2D, and the upper surface of the base contact formation layer 206 is exposed around this. In this process, the second base formation layer 207 (second base layer 107) and the base contact formation layer 206 (base contact layer 106) are made of InGaAsSb or GaAsSb. It is difficult to realize wet etching having high selectivity with the formation layer 206.

  However, since the second base formation layer 207 is as thin as about 1 to 2 nm, as described above, by using a dry / wet etching technique under an etching condition with a low etching rate and controlling the etching time and the like, 2 A structure in which the upper surface of the base contact formation layer 206 is exposed around the base layer 107 can be formed.

  Next, as shown in FIG. 2E, a base electrode 112 is formed at a predetermined position of the base contact formation layer 206 exposed around the emitter mesa by a well-known lift-off method. At this time, the emitter mesa that has already been formed may be covered with a protective film made of an insulating material.

  Next, a mask pattern that protects a predetermined region including the formation region of the base electrode 112 centering on the emitter mesa formation portion is formed by a lithography technique. Next, the base contact formation layer 206, the first base formation layer 205, and the collector formation layer 204 are sequentially patterned by selective etching using the formed mask pattern, and the collector layer 104, the first base layer 105, and the base contact are patterned. A collector mesa by layer 106 is formed. The upper surface of the subcollector formation layer 203 is exposed around the collector mesa. The mask pattern is removed after the collector mesa is formed.

  Next, a collector electrode 113 is formed by a lift-off method at a predetermined location of the subcollector formation layer 203 exposed around the collector mesa. Thereafter, the sub-collector formation layer 203 and the buffer formation layer 202 are sequentially patterned to form the buffer layer 102 and the sub-collector layer 103 as shown in FIG. For example, each electrode may be formed by depositing a laminated structure containing Au, Ti, Pt, W, Mo, or the like by an evaporation method. As a result, the HBT in the embodiment is formed.

The emitter electrode 111, the base electrode 112, and the collector electrode 113 may be formed after mesa formation. In addition, from the viewpoint of improving long-term reliability and yield, passivating around mesa with oxide film material and protective film material such as SiO ₂ , SiN, Al ₂ O ₃ , and benzocyclobutene (BCB). Also good.

  Next, another manufacturing method will be described. The manufacturing method is the same as that described above until an emitter mesa is formed by the emitter layer 108 and the emitter contact layer 109 and the upper surface of the second base forming layer 207 is exposed around the emitter mesa. Next, as shown in FIG. 3A, the second base formation layer 207 is etched and patterned using the mask pattern 301. The mask pattern 301 includes an opening 302 in a region corresponding to the base electrode formation region. As a result, an opening 303 is formed in the second base formation layer 207 in a region corresponding to the base electrode formation region by the etching. By this etching, the upper surface of the base contact formation layer 206 is exposed at the bottom of the opening 303.

  Next, a base electrode material is deposited, and then the mask pattern 301 is removed (lifted off), thereby forming an upper surface of the base contact formation layer 206 exposed at the bottom of the opening 303 as shown in FIG. 3B. A base electrode 112 is formed.

  Thereafter, a mask pattern that protects a predetermined region including a region where the base electrode 112 is formed around the emitter mesa forming portion is formed by a lithography technique. Next, the second base formation layer 207, the base contact formation layer 206, the first base formation layer 205, and the collector formation layer 204 are sequentially patterned by selective etching using the formed mask pattern, and the mask pattern is removed. Thus, as shown in FIG. 3C, the second base layer 107a is formed, and a collector mesa is formed by the collector layer 104, the first base layer 105, and the base contact layer 106. As described above, the upper surface of the subcollector formation layer 203 is exposed around the collector mesa.

  Next, as shown in FIG. 3D, a collector electrode 113 is formed by a lift-off method at a predetermined location of the subcollector formation layer 203 exposed around the collector mesa. Thereafter, the subcollector formation layer 203 and the buffer formation layer 202 are sequentially patterned to form the buffer layer 102 and the subcollector layer 103.

  According to this manufacturing, the upper surface of the base contact layer 106 on the emitter mesa side of the base electrode 112 is covered with the second base layer 107a, and the region exposed as the base surface becomes the second base layer 107a. Between the base electrode 112 and the emitter layer 108, the second base layer 107a is provided. With this configuration, the hole concentration on the exposed surface is lower than when the base contact layer 106 is exposed.

  In addition to the recombination current at the emitter-base interface, the current gain is also reduced by an increase in the recombination current in a region where the emitter and the base between the emitter and the base electrode are exposed. As described above, when the region exposed as the base surface is the second base layer 107a and the hole concentration is in a low state, an increase in recombination current can be suppressed and higher current gain can be realized.

  The configuration in which the region exposed as the base surface described above is in a state where the hole concentration is low may be manufactured as follows. The manufacturing method is the same as that described above until an emitter mesa is formed by the emitter layer 108 and the emitter contact layer 109 and the upper surface of the second base forming layer 207 is exposed around the emitter mesa. Next, as shown in FIG. 4A, a base electrode 112 is formed by a well-known lift-off method at a predetermined position of the second base forming layer 207 exposed around the emitter mesa by the emitter layer 108 and the emitter contact layer 109.

  Next, as shown in FIG. 4B, an alloy layer 112a is formed by diffusing the base electrode metal into the second base formation layer 207 immediately below the base electrode 112 to form an alloy by heat treatment in a nitrogen atmosphere. To do. The alloy layer 112a is formed so as to reach the base contact formation layer 206, and the alloy layer 112a is in contact with the base contact formation layer 206.

  Next, a mask pattern that protects a predetermined region including the formation region of the base electrode 112 centering on the emitter mesa formation portion is formed by a lithography technique. Next, the second base formation layer 207, the base contact formation layer 206, the first base formation layer 205, and the collector formation layer 204 are sequentially patterned by selective etching using the formed mask pattern, and the mask pattern is removed. Thus, as shown in FIG. 4C, the second base layer 107b is formed, and a collector mesa is formed by the collector layer 104, the first base layer 105, and the base contact layer 106.

  Next, a collector electrode 113 is formed by a lift-off method at a predetermined position of the subcollector formation layer 203 exposed around the collector mesa. Thereafter, the subcollector formation layer 203 and the buffer formation layer 202 are sequentially patterned to form the buffer layer 102 and the subcollector layer 103. Also in this manufacture, the upper surface of the base contact layer 106 on the emitter mesa side of the base electrode 112 is covered with the second base layer 107b, and the region exposed as the base surface becomes the second base layer 107b. As a result, the same effect as described above can be obtained.

  Hereinafter, the results of actually creating and evaluating the element will be described. A large-area HBT having a size in plan view of the emitter electrode of 25-100 μm square was produced. The prepared sample element includes an n-type InGaAs and n-type InP sub-collector layer, an n-type InP collector layer, a p-type InGaAsSb or GaAsSb base layer, an n-type InP emitter layer, And an emitter contact cap layer made of n-type InGaAs. A base electrode was made of Ti / Pt / Au. A sample element having a base layer made of GaAsSb and a sample element having a base layer made of InGaAsSb were produced.

  When the current gain of the fabricated HBT was evaluated, it was found that the HBT having the base layer made of InGaAsSb can easily obtain a higher current gain than the HBT made of GaAsSb. In an HBT in which the base layer is made of GaAsSb, a high current gain can be obtained unless an interface quality improvement technique such as inserting a GaAs spacer layer as shown in Non-Patent Document 9 is inserted between the emitter layer and the base layer. It has been shown experimentally that it cannot be obtained. This is a result suggesting that better interface quality is easily obtained and the recombination center density is reduced in the case of the InP emitter and InGaAsSb base.

  The above experimental results show that the present invention in which the second base layer in contact with the emitter layer is made of InGaAsSb can obtain a higher current gain than the case where the region in contact with the emitter layer of the base layer is made of GaAsSb. Is shown.

  For example, for the purpose of simply reducing the contact resistance, the first base layer, the base contact layer, and the second base layer are made of GaAsSb, and the contact with only a configuration in which a simple doping profile change is provided between the layers. The effect of reducing resistance can be obtained. However, with this structure, the current gain improvement effect according to the present invention in which the second base layer is made of InGaAsSb cannot be obtained, and it is difficult to increase the current gain. In the present invention, since the second base layer is composed of InGaAsSb, it is possible to obtain a special effect from the viewpoint of achieving both high current gain and low contact resistance.

Further, since the base contact layer is made of GaAsSb instead of InGaAsSb, a special effect can be obtained in reducing contact resistance. This point will be described with reference to FIG. FIG. 5 is a plot of the base contact resistance of the fabricated HBT versus the base doping concentration. Base contact resistance was estimated by the TLM method. The white square in the figure is the value of the GaAsSb base HBT, and the black square in the figure is the value of the InGaAsSb base HBT. As shown by this experimental fact, it can be seen that InGaAsSb tends to have a contact resistance that is likely to be about one digit higher than that of GaAsSb. These experimental results show that if InGaAsSb is simply applied to the base and a structure is formed in contact with the base electrode, the contact resistance is high and high f _max is difficult to achieve.

In contrast, in the present invention, the contact with the base electrode is the base contact layer made of GaAsSb located under the second base layer, and the contact resistance can be lowered by about an order of magnitude compared with InGaAsSb. , High f _max can be realized.

  As described above, according to the present invention, since the base is constituted by the first base layer, the base contact layer, and the second base layer, there is no reduction in manufacturing uniformity and reproducibility. In addition, the maximum oscillation frequency can be improved without causing a decrease in current gain.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious.

For example, in the above description, the first base layer is made of InGaAsSb and has a composition gradient and a doping gradient structure. However, the present invention is not limited to this. The f _max improvement effect can be exhibited. However, since f _max can be improved at the same time by increasing f _T , it is preferable that the first base layer has an InGaAsSb composition gradient structure having a large band gap variation.

  In the above description, the base contact layer is made of GaAsSb. However, the base contact layer may be made of InGaAsSb as long as a high hole concentration can be realized. The base contact layer may be made of InGaAsSb as long as contact resistance that is low enough not to impair high-frequency characteristics can be realized. However, as described above, in general, GaAsSb can have a higher hole concentration than InGaAsSb, and the base contact layer is preferably composed of GaAsSb from the viewpoint of lowering contact resistance.

  The thickness of the base contact layer is 2 to 4 nm. However, for the purpose of obtaining the effect of reducing the contact resistance, the effect can be exhibited if the thickness is at least 1 nm. On the other hand, considering the relationship between the resistance of the entire base and the current gain due to this resistance, the thickness of the base contact layer is preferably set to 5 nm or less.

Incidentally, although the base contact layer is made of GaAsSb, the conduction band energy of GaAsSb generally tends to be higher than that of InGaAsSb. Therefore, the base contact layer made of GaAsSb tends to have higher conduction band energy than the second base layer made of InGaAsSb, and the base contact layer becomes a barrier for electrons injected from the emitter side. Therefore, if the thickness of the base contact layer is too large, decrease the electron electron velocity traveling the base layer, it could be caused a decrease in f _T.

On the other hand, if the thickness of the base contact layer is set to 5 nm at the maximum, electrons can pass through the base contact layer by tunneling from the second base layer toward the first base layer. The decrease in f _T due to the barrier between the layer and the base contact layer can be minimized.

  DESCRIPTION OF SYMBOLS 101 ... Substrate, 102 ... Buffer, 103 ... Subcollector layer, 104 ... Collector layer, 105 ... First base layer, 106 ... Base contact layer, 107 ... Second base layer, 108 ... Emitter layer, 109 ... Emitter contact layer, 111... Emitter electrode, 112... Base electrode, 113.

Claims (4)

A substrate composed of InP;
A collector layer made of a III-V compound semiconductor formed on the substrate;
A first base layer formed of a p-type III-V group compound semiconductor containing Ga, As, Sb and doped with carbon, and formed on the collector layer;
A base contact layer formed of a p-type III-V group compound semiconductor containing Ga, As, Sb and doped with carbon and formed on and in contact with the first base layer;
A second base layer made of a p-type III-V group compound semiconductor containing In, Ga, As, Sb and doped with carbon and formed on and in contact with the base contact layer;
An emitter layer made of a III-V compound semiconductor formed on the second base layer;
An emitter electrode connected to the emitter layer;
A base electrode connected to the base contact layer around the emitter layer;
A collector electrode connected to the collector layer,
The base contact layer has a higher hole concentration than the first base layer and the second base layer;
The base contact layer has a hole concentration of 1 × 10 ²¹ cm ⁻³ or less,
The heterojunction bipolar transistor, wherein the first base layer and the second base layer have a hole concentration of 1 × 10 ¹⁹ cm ⁻³ or more. The heterojunction bipolar transistor of claim 1,
A heterojunction bipolar transistor comprising: the second base layer disposed between the base electrode and the emitter layer. The heterojunction bipolar transistor according to claim 1 or 2,
The heterojunction bipolar transistor, wherein the base contact layer has a thickness of 1 nm to 5 nm. The heterojunction bipolar transistor according to any one of claims 1 to 3,
The first base layer and the second base layer are made of InGaAsSb,
The base contact layer is made of GaAsSb. A heterojunction bipolar transistor, wherein:

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