JP6096503B2 - Heterojunction bipolar transistor - Google Patents

Description

  The present invention relates to an npn heterojunction bipolar transistor made of a compound semiconductor.

  In order to improve the operating speed of a heterojunction bipolar transistor (HBT), it is important to increase the speed of electrons traveling in the device. In particular, the increase in the electron velocity in the collector can reduce the space charge in the collector and increase the current density that can be injected into the device. An increase in injection current density leads to a reduction in charge / discharge time in the device, and the switching speed of the device can be improved.

  The electron velocity in the collector is determined by the electric field strength applied to the collector, the effective mass of the electrons, and various scattering mechanisms acting on the electrons from the outside. In a collector composed of a group III-V compound semiconductor such as InP, InGaAs, or InGaAsP, inter-valley scattering is particularly important as an electron scattering mechanism. Inter-valley scattering is a phenomenon in which electrons gaining energy by a collector electric field transition from an Γ valley, which exists in an equilibrium state or a state close to an equilibrium state, to an upper valley such as an L valley.

  Electrons that have transitioned to the upper valley have a large effective mass, and even when energy is obtained from the collector electric field, it is difficult to accelerate and stall. In order to run the electrons at a high speed, it is necessary to devise a method that allows a moderate amount of energy to be received from the collector electric field and keeps the electrons in a Γ valley with a small effective electron mass that can be run at a high speed.

  Hereinafter, techniques for reducing inter-valley scattering currently being implemented will be described.

  FIG. 5 shows a normal double-heterojunction bipolar transistor (DHBT) that has not been devised to reduce inter-valley scattering. Here, the DHBT has a structure in which the semiconductor material of the collector and the semiconductor material of the base are different from each other, and a semiconductor material having a large band gap is usually used for the collector in order to improve the breakdown voltage performance of the element.

  In the DHBT, as shown in FIG. 5, a first subcollector layer 311 made of n-type InP doped with impurities at a high concentration is formed on a substrate 301 made of semi-insulating InP, and the first subcollector layer 311 is formed. A second sub-collector layer 312 made of n-type InGaAs doped with a high concentration of impurities is formed thereon, and a first sub-collector made of n-type InP doped with a high concentration of impurities is formed on the second sub-collector layer 312. A collector layer 321 is formed, and a second collector layer 322 having a stacked structure of InP, InGaAsP, and InGaAs is formed on the first collector layer 321.

  A base layer 331 made of p-type InGaAs doped with impurities at a high concentration is formed on the second collector layer 322, and an emitter layer 341 made of n-type InP is formed on the base layer 331. The emitter layer An emitter cap (emitter contact) layer 351 made of n-type InGaAs doped with impurities at a high concentration is formed on 341. A collector electrode 391 is formed on the second subcollector layer 312, a base electrode 392 is formed on the base layer 331, and an emitter electrode 393 is formed on the emitter cap layer 351.

  The first subcollector layer 311 is made of a material having good heat dissipation characteristics, and the second subcollector layer 312 is made of a material having a low contact resistance with the collector electrode 391. The first collector layer 321 is used to reduce the contact resistance between the collector layer and the subcollector layer, and most of the collector depletion layer (or collector electron transit layer) is in the second collector layer 322. Will be formed. Therefore, the collector travel time of electrons injected from the base layer 331 into the second collector layer 322 and the first collector layer 321 is determined by the electron transport characteristics (or electron velocity) in the second collector layer 322. .

  The second collector layer 322 has a structure including a composition gradient layer made of InGaAs and InGaAsP. This is because the band edge energy of InGaAs, which is the base layer material, and InP, which is the main material of the collector layer, are different, so that electrons are not smoothly injected from the base to the collector by simply connecting them directly. In order to alleviate the band edge energy discontinuity between the two, such a composition gradient layer is provided between the InGaAs base layer and the InP collector layer.

  FIG. 6 is an energy band diagram showing a band state in the stacking direction of the DHBT described with reference to FIG. The conduction band edge shows in detail the Γ valley edge that bears electron transport when the momentum or energy of electrons is relatively small. FIG. 6 also shows an upper valley (eg, L valley) edge located at a higher energy in order to describe collector electron transport in detail. The electrons injected from the base layer 331 to the second collector 322 are accelerated by the electric field applied to the second collector 322, and obtain high energy. As a result, electrons can transition from a Γ valley having a small effective mass to an upper valley having a large effective mass.

  This is inter-valley scattering. In the upper valley where the effective mass is large, the electrons are less likely to be accelerated, and the electron momentum (or electron velocity) decreases despite obtaining high energy. The “ballistic electron transport region” shown in FIG. 6 indicates a region where electrons can travel without collision while staying in the Γ valley. In order to shorten the electron travel time in the collector, it is necessary to keep the electrons in the Γ valley where high speed travel is possible over a long distance. In other words, it is important to expand the ballistic electron transport region shown in FIG.

  In order to expand the ballistic electron transport region, there is a proposal to provide a thin semiconductor layer to which a p-type impurity is added at the rear end of the collector depletion layer (see Non-Patent Document 1). FIG. 7 incorporates the above-described proposal for the DHBT of FIG. As shown in FIG. 7, a thin third collector layer 423 made of p-type InP is inserted between the first collector layer 421 and the second collector layer 422. Here, the layer structure other than the third collector layer 423 is the same as that of the DHBT having the band structure shown in FIG.

  FIG. 8 is an energy band diagram showing a band state in the stacking direction of the DHBT described with reference to FIG. As a result of the energy band being lifted by the third collector layer 423 provided at the rear end of the second collector layer 422, a so-called “potential cliff” structure is formed. Thereby, the collector applied electric field is concentrated in the vicinity of the third collector layer 423 (that is, the rear end of the collector depletion layer), and the electric field in the collector electron travel region is alleviated.

  As a result, as shown in FIG. 8, the ballistic electron transport region is greatly expanded, and the collector electron velocity is increased. When collector electrons travel through the potential cliff structure, there is a possibility of significant inter-valley scattering. However, it should be noted that since the potential cliff (or the p-type third collector layer 423) is thin, the influence of the electron velocity deterioration in this region is small.

T. Ishibashi, "Nonequilibrium Electron Transport in HBTs", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.48, no.11, pp.2595-2605, 2001.

  The above-mentioned proposal of providing a p-type layer at the rear end of the collector depletion layer to relax the electric field of the collector electron transit layer and expand the ballistic electron transport region is very promising. However, for example, when InP or the like is used as the collector semiconductor material, Be (beryllium) or Zn (zinc) must be used as the p-type impurity.

  These impurities are known to have a large diffusion coefficient, and it is difficult to produce a thin p-type layer (third collector layer) as intended. In GaAs, C (carbon) having a very small diffusion coefficient can be used as a p-type impurity. However, in InP or the like, C functions as an n-type impurity rather than a p-type, and thus cannot be used. For this reason, it is practically difficult to improve the collector electron velocity by adding a thin p-type layer for the HBT using InP or the like as the collector semiconductor material. Thus, at present, there has been a problem that it is difficult to suppress inter-valley scattering that causes performance degradation of the heterojunction bipolar transistor in a state where it can be practically manufactured.

  The present invention has been made to solve the above-described problems, and it is an object of the present invention to suppress inter-valley scattering that causes performance degradation of a heterojunction bipolar transistor in a state where it can be practically manufactured. And

A heterojunction bipolar transistor according to the present invention includes a substrate made of a III-V compound semiconductor, a subcollector layer formed on the substrate, and an n-type III-V compound formed on the subcollector layer . A first collector layer made of a semiconductor, a second collector layer made of a group III-V compound semiconductor formed on the first collector layer, and a p-type group III-V formed on the second collector layer A base layer made of a compound semiconductor, an emitter layer made of an n-type III-V group compound semiconductor formed on the base layer, and III-V formed between the first collector layer and the second collector layer a third collector layer made of group compound semiconductor, a first collector layer, a second collector layer, third collector layer, and a collector mesa constructed from the base layer, is composed of the emitter layer Colle An emitter mesa having a smaller area than the Tamesa, a collector electrode formed on the subcollector layer around the collector mesa, a base electrode formed on the base layer around the emitter mesa, and an emitter formed on the emitter layer And the third collector layer has a conduction band edge energy smaller than that of the first collector layer at the junction interface between the first collector layer and the third collector layer, and the third collector layer. The conduction band edge energy is made smaller than the conduction band edge energy of the second collector layer at the junction interface between the second collector layer and the third collector layer.

  In the heterojunction bipolar transistor, the third collector layer may be made of an undoped group III-V compound semiconductor. The third collector layer only needs to be composed of an n-type III-V group compound semiconductor. In this case, it is only necessary that an n-type impurity is introduced into the semiconductor layer that is in contact with the second collector layer among the semiconductor layers constituting the third collector layer in a range that does not degenerate. Note that the first collector layer and the second collector layer may be made of InP, and the third collector layer may be made of InGaAs.

  As described above, according to the present invention, it is possible to obtain an excellent effect that inter-valley scattering that causes a decrease in performance of the heterojunction bipolar transistor can be suppressed in a state where it can be practically manufactured.

FIG. 1 is a cross-sectional view showing a configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2 is an energy band diagram showing a band state in the stacking direction of the heterojunction bipolar transistor according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing the configuration of the heterojunction bipolar transistor according to the second embodiment of the present invention. FIG. 4 is an energy band diagram showing a band state in the stacking direction of the heterojunction bipolar transistor according to the second embodiment of the present invention. FIG. 5 is a configuration diagram showing the configuration of a conventional double heterojunction bipolar transistor. FIG. 6 is an energy band diagram showing a band state in the stacking direction of a conventional double heterojunction bipolar transistor. FIG. 7 is a configuration diagram showing a configuration of a double heterojunction bipolar transistor having a configuration proposed in Non-Patent Document 1. FIG. 8 is an energy band diagram showing the band state in the stacking direction of the double heterojunction bipolar transistor having the configuration proposed in Non-Patent Document 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
First, Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view showing a configuration of a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 2 is an energy band diagram showing a band state in the stacking direction of the heterojunction bipolar transistor according to the first embodiment of the present invention.

  The heterojunction bipolar transistor includes a substrate 101 made of a group III-V compound semiconductor, a first collector layer 121 made of an n-type group III-V compound semiconductor formed on the substrate 101, and a first collector layer 121. A second collector layer 122 made of a group III-V compound semiconductor formed on the substrate, a base layer 131 made of a p-type group III-V compound semiconductor formed on the second collector layer 122, and a base layer And an emitter layer 141 made of an n-type III-V compound semiconductor formed on 131.

  In addition, the heterojunction bipolar transistor according to the first embodiment includes a third collector layer 123 made of a III-V compound semiconductor formed between the first collector layer 121 and the second collector layer 122. Here, the conduction band edge energy of the third collector layer 123 is smaller than the conduction band edge energy of the first collector layer 121 at the junction interface between the first collector layer 121 and the third collector layer 123, and the third collector layer It is important that the conduction band edge energy of the layer 123 is smaller than the conduction band edge energy of the second collector layer 122 at the junction interface between the second collector layer 122 and the third collector layer 123.

  For example, the substrate 101 may be made of InP that has been made highly resistant by doping Fe, and the (001) plane of InP may be the main surface. On the substrate 101, a subcollector layer 111 made of InP into which n-type impurities are introduced at a high concentration and a second subcollector layer 112 made of InGaAs into which n-type impurities are introduced at a high concentration are stacked. Has been. A first collector layer 121 is formed on these layers.

The first collector layer 121 is made of, for example, InP into which silicon is introduced as an n-type impurity at a concentration of about 5 × 10 ¹⁸ cm ^{−3 and} has a layer thickness of about 50 nm. Further, the second collector layer 122 is, for example, a stacked structure in which an InP layer having a layer thickness of 70 nm, an InGaAsP layer having a layer thickness of 10 nm, and an InGaAs layer having a layer thickness of 10 nm are stacked from the substrate 101 side. The third collector layer 123 is made of undoped InGaAs and has a thickness of about 10 nm.

  The base layer 131 is made of, for example, InGaAs into which p-type impurities are introduced at a high concentration, and the emitter layer 141 is made of n-type InP.

  The first collector layer 121, the third collector layer 123, the second collector layer 122, and the base layer 131 are formed, for example, in a rectangular mesa shape (collector mesa) in plan view, and the emitter layer 141 is formed of the mesa described above. The mesa shape has a smaller area (emitter mesa). A collector electrode 191 is formed on the second subcollector layer 112 around the collector mesa, and a base electrode 192 is formed on the base layer 131 around the emitter mesa. An emitter electrode 193 is formed on the emitter layer 141 via an emitter cap layer 151 made of InGaAs into which an impurity (n-type) is introduced at a high concentration.

  Each of the above-described compound semiconductor layers can be formed by epitaxial growth using a well-known deposition method such as metal organic chemical vapor deposition (MOVPE) or molecular beam epitaxy (MBE). Further, the collector mesa and the emitter mesa may be formed by patterning using a known lithography technique and etching technique. Each electrode can be formed by, for example, a known vapor deposition method or lift-off method. The details of the heterojunction bipolar transistor in the first embodiment described above are omitted as long as there is no problem with the description.

  Next, the heterojunction bipolar transistor in the first embodiment will be described with reference to the energy band diagram of FIG. As shown in FIG. 2, by providing a third collector layer 123 having a low conduction band edge energy (at the junction interface) between the first collector layer 121 and the second collector layer 122, the rear end of the second collector layer 122 is provided. It can be seen that the energy of is raised by the conduction band edge discontinuity.

  By incorporating such a heterostructure, a potential cliff structure can be realized without using p-type impurities having a large diffusion coefficient. As a result, according to the first embodiment, the ballistic electron transport region in the collector electron transit layer is expanded and the electron velocity is improved. As described above, according to the first embodiment, the inter-valley scattering that causes the performance degradation of the heterojunction bipolar transistor is suppressed, and the electron velocity can be improved. Further, according to the first embodiment, the third collector layer 123 is used without using a p-type impurity which is easily diffused, and the above can be realized in a state where it can be practically manufactured.

  By the way, in the heterojunction bipolar transistor according to the first exemplary embodiment, undoped (undoped) InGaAs is used as the third collector layer 123. In this configuration, it is important that the thickness of the third collector layer 123 is appropriately reduced as will be described below.

  The third collector layer 123 is also depleted to have an electron travel region, and an electron travel time is generated. For this reason, if the third collector layer 123 made of InGaAs is too thick, a long electron traveling time is generated. In such a state, strong inter-valley scattering occurs in the formed electron travel region, and there is a risk that the electron velocity is rapidly deteriorated and the entire collector travel time is greatly increased.

  For this reason, the layer thickness of the third collector layer 123 is preferably a thin layer in a range in which no inter-valley scattering occurs. However, if the thickness is too thin, the state where the energy at the rear end of the second collector layer 122 is raised by the discontinuity of the conduction band edge due to the provision of the third collector layer 123 cannot be obtained. Therefore, the layer thickness of the third collector layer 123 may be appropriately set within a range where this state is obtained and inter-valley scattering does not occur.

[Embodiment 2]
Next, a second embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a cross-sectional view showing the configuration of the heterojunction bipolar transistor according to the second embodiment of the present invention. FIG. 4 is an energy band diagram showing a band state in the stacking direction of the heterojunction bipolar transistor according to the second embodiment of the present invention.

  This heterojunction bipolar transistor includes a substrate 201 made of a group III-V compound semiconductor, a first collector layer 221 made of an n-type group III-V compound semiconductor formed on the substrate 201, and a first collector layer 221. A second collector layer 222 made of a group III-V compound semiconductor formed on the substrate, a base layer 231 made of a p-type group III-V compound semiconductor formed on the second collector layer 222, and a base layer And an emitter layer 241 made of an n-type III-V compound semiconductor formed on the H.231.

  In addition, the heterojunction bipolar transistor according to the second embodiment includes a third collector layer 223 made of a III-V compound semiconductor formed between the first collector layer 221 and the second collector layer 222. Here, the conduction band edge energy of the third collector layer 223 is smaller than the conduction band edge energy of the first collector layer 221 at the junction interface between the first collector layer 221 and the third collector layer 223, and It is important that the conduction band edge energy of the layer 223 is smaller than the conduction band edge energy of the second collector layer 222 at the junction interface between the second collector layer 222 and the third collector layer 223. In the second embodiment, the third collector layer 223 is composed of an n-type III-V group compound semiconductor.

  Note that, for example, the substrate 201 may be made of InP that has been made highly resistant by doping Fe, and the (001) plane of InP may be the main surface. On the substrate 201, a subcollector layer 211 made of InP into which n-type impurities are introduced at a high concentration and a second subcollector layer 212 made of InGaAs into which n-type impurities are introduced at a high concentration are stacked. Has been. A first collector layer 221 is formed on these layers.

The first collector layer 221 is made of, for example, InP into which silicon is introduced as an n-type impurity at a concentration of about 5 × 10 ¹⁸ cm ^{−3 and} has a layer thickness of about 50 nm. In addition, the second collector layer 222 is, for example, a stacked structure in which an InP layer with a layer thickness of 70 nm, an InGaAsP layer with a layer thickness of 10 nm, and an InGaAs layer with a layer thickness of 10 nm are stacked from the substrate 201 side. In the second embodiment, the third collector layer 223 is made of InGaAs into which silicon is introduced at a concentration of about 2 × 10 ¹⁷ cm ⁻³ as an n-type impurity, and has a layer thickness of about 100 nm. .

  The base layer 231 is made of, for example, InGaAs into which a p-type impurity is introduced at a high concentration, and the emitter layer 241 is made of n-type InP.

  The first collector layer 221, the third collector layer 223, the second collector layer 222, and the base layer 231 are formed in a rectangular mesa shape (collector mesa), for example, in plan view, and the emitter layer 241 is formed of the mesa described above. The mesa shape has a smaller area (emitter mesa). A collector electrode 291 is formed on the second subcollector layer 212 around the collector mesa, and a base electrode 292 is formed on the base layer 231 around the emitter mesa. An emitter electrode 293 is formed on the emitter layer 241 via an emitter cap layer 251 made of InGaAs into which an n-type impurity is introduced.

  Each layer made of the compound semiconductor described above can be formed by epitaxial growth by a deposition method such as a well-known metal organic chemical vapor deposition method or molecular beam epitaxial growth method. Further, the collector mesa and the emitter mesa may be formed by patterning using a known lithography technique and etching technique. Each electrode can be formed by, for example, a known vapor deposition method or lift-off method. The details of the heterojunction bipolar transistor in the second embodiment described above are omitted as long as there is no problem with the description.

  Next, the heterojunction bipolar transistor according to the second embodiment will be described with reference to the energy band diagram of FIG. As shown in FIG. 4, by providing a third collector layer 223 having a low conduction band edge energy (at the junction interface) between the first collector layer 221 and the second collector layer 222, the rear end of the second collector layer 222 is provided. Is raised by the discontinuity of the conduction band edge.

  By incorporating such a heterostructure, a potential cliff structure can be realized without using p-type impurities having a large diffusion coefficient. As a result, also in the second embodiment, the ballistic electron transport region in the collector electron transit layer is expanded and the electron velocity is improved. As described above, also in the second embodiment, the inter-valley scattering that causes the performance degradation of the heterojunction bipolar transistor is suppressed, and the electron velocity can be improved. Also in the second embodiment, the third collector layer 223 is used without using a p-type impurity that is easily diffused, and the above can be realized in a state where it can be practically manufactured.

  In the second embodiment, since the third collector layer 223 is made of n-type InGaAs, the depleted region that causes a problem in the third collector layer 223 is the same as in the first embodiment. Will not occur. For this reason, in the second embodiment, it is not necessary to limit the layer thickness of the third collector layer 223 in particular.

  However, in Embodiment 2, attention must be paid to the impurity concentration in the third collector layer 223. When impurities are added so that the Fermi level of the third collector layer 223 made of InGaAs exceeds the conduction band edge, the energy rise at the rear end of the second collector layer 222 is reduced, and as a result, the ballistic Expansion of the electron transport region is suppressed. Therefore, it is desirable to suppress the concentration of the n-type impurity in the third collector layer 223 so that at least the region in contact with the second collector layer 222 does not degenerate. In other words, it is desirable that a semiconductor layer in contact with the second collector layer 222 among the semiconductor layers constituting the third collector layer 223 is doped with an n-type impurity within a range that does not degenerate.

  As described above, in the present invention, the conduction band edge energy is smaller than the conduction band edge energy of the first collector layer at the junction interface between the first collector layer and the third collector layer, and the third collector layer The conduction band edge energy of the first collector layer and the second collector is changed to a third collector layer in which the conduction band edge energy of the second collector layer is lower than the conduction band edge energy of the second collector layer at the junction interface between the second collector layer and the third collector layer. It was made to provide between the layers. Here, it is important that the third collector layer is composed of an undoped or n-type III-V group compound semiconductor, in other words, not in a p-type state.

  As a result, according to the present invention, it is not necessary to use a p-type impurity having a large diffusion coefficient for the third collector layer, and the inter-valley scattering that causes the performance degradation of the heterojunction bipolar transistor in a state where it can be practically manufactured. Can be suppressed.

  The present invention is not limited to the embodiment described above, and many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention. It is obvious. For example, in the above-described embodiment, the configuration in which the collector uses a stacked structure made of a type I heterojunction has been described as an example. However, the present invention is not limited to this, and a stacked structure made of a type II heterojunction is used. A structure may be used. In the above-described embodiment, the case where the base layer is made of InGaAs has been described as an example. However, the present invention is not limited to this, and the base layer may be made of, for example, GaAsSb. The dopant (impurity), the constituent material of each layer, and the composition of each layer are not limited to the above description, and other materials may be used as long as the device operation in the present invention can be realized.

  DESCRIPTION OF SYMBOLS 101 ... Substrate, 111 ... First subcollector layer, 112 ... Second subcollector layer (collector contact layer), 121 ... First collector layer, 122 ... Second collector layer, 123 ... Third collector 131, base layer, 141 ... emitter layer, 151 ... emitter contact layer, 191 ... collector electrode, 192 ... base electrode, 193 ... emitter electrode.

Claims (5)

A substrate made of a III-V compound semiconductor;
A subcollector layer formed on the substrate;
A first collector layer made of an n-type group III-V compound semiconductor formed on the subcollector layer;
A second collector layer made of a III-V compound semiconductor formed on the first collector layer;
A base layer made of a p-type III-V compound semiconductor formed on the second collector layer;
An emitter layer made of an n-type III-V compound semiconductor formed on the base layer;
A third collector layer made of a III-V compound semiconductor formed between the first collector layer and the second collector layer ;
A collector mesa composed of the first collector layer, the second collector layer, the third collector layer, and the base layer;
An emitter mesa composed of the emitter layer and having a smaller area than the collector mesa;
A collector electrode formed on the sub-collector layer around the collector mesa;
A base electrode formed on the base layer around the emitter mesa;
At least an emitter electrode formed on the emitter layer ;
The conduction band edge energy of the third collector layer is smaller than the conduction band edge energy of the first collector layer at the junction interface between the first collector layer and the third collector layer, and The heterojunction bipolar transistor, wherein the conduction band edge energy is made smaller than the conduction band edge energy of the second collector layer at the junction interface between the second collector layer and the third collector layer. The heterojunction bipolar transistor according to claim 1, wherein
The heterojunction bipolar transistor, wherein the third collector layer is made of an undoped group III-V compound semiconductor. The heterojunction bipolar transistor according to claim 1, wherein
The heterojunction bipolar transistor, wherein the third collector layer is made of an n-type III-V group compound semiconductor. The heterojunction bipolar transistor according to claim 3,
A heterojunction bipolar transistor, wherein at least a semiconductor layer in contact with the second collector layer among the semiconductor layers constituting the third collector layer is doped with an n-type impurity within a range not degenerate. The heterojunction bipolar transistor according to any one of claims 1 to 4,
The first collector layer and the second collector layer are composed of InP,
The heterojunction bipolar transistor, wherein the third collector layer is made of InGaAs.

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