JP2017017839A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise and loss occurring in a bypass passage which bypasses a conversion circuit.SOLUTION: A semiconductor device 1 includes a switching element Q 1 and a bypass switch 4. A switching element Q1 is a part of a conversion circuit 3 that converts a DC voltage input between a pair of first terminals T11 and T12 and outputs the converted DC voltage between a pair of second terminals T21 and T22, and is subjected to switching control. The bypass switch 4 opens and closes a bypass path S1 for bypassing the conversion circuit 3 between the pair of first terminals T11, T12 and the pair of second terminals T21, T22. The semiconductor device 1 further includes a package incorporated with the switching element Q1 and the bypass switch 4.SELECTED DRAWING: Figure 1

Description

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device used in a power conversion device that converts power from a DC power supply.

  2. Description of the Related Art Conventionally, a power conversion device that converts power from a DC power source is known and disclosed in, for example, Patent Document 1. The power conversion device described in Patent Literature 1 includes a booster circuit that boosts the voltage of a DC power supply using sunlight, and a bypass circuit that bypasses the booster circuit. The bypass circuit includes a relay.

  In this power conversion device, when the voltage of the DC power supply exceeds a predetermined voltage, the switch on / off operation of the booster circuit is stopped to stop the booster operation, and the booster circuit is bypassed by the bypass circuit. As described above, this power conversion device reduces the conduction loss of the components constituting the booster circuit when the boosting is stopped, thereby improving the conversion efficiency.

JP 2006-238629 A

  In the above conventional example, it is conceivable to configure the booster circuit (conversion circuit) as a semiconductor device. Here, in the above conventional example, when the bypass circuit composed of the relay and the booster circuit composed of the semiconductor device are individually configured, the wiring length of the path bypassing the booster circuit (bypass path) is increased, and the wiring impedance is increased. There is a possibility. In this case, there is a problem that loss and noise that may occur in the bypass path increase due to the large wiring impedance.

  The present invention has been made in view of the above points, and an object thereof is to reduce noise and loss that may occur in a bypass path that bypasses a conversion circuit.

  The semiconductor device of the present invention is a part of a conversion circuit that converts a DC voltage input between a pair of first terminals and outputs the converted voltage between a pair of second terminals, the switching element being controlled for switching, A bypass switch that opens and closes a bypass path that bypasses the conversion circuit between the pair of first terminals and the pair of second terminals, and a package that includes the switching element and the bypass switch. And

  The present invention can reduce noise and loss that may occur in a bypass path that bypasses the conversion circuit.

It is a schematic circuit diagram which shows the semiconductor device and power converter device which concern on embodiment. It is the schematic which shows the internal structure of the semiconductor device which concerns on embodiment. It is the schematic which shows the internal structure of the semiconductor device which concerns on a comparative example. 1 is a schematic circuit diagram illustrating a configuration further including a capacitor in a semiconductor device and a power conversion device according to an embodiment. It is the schematic which shows the structure which incorporated the capacitor in the semiconductor device which concerns on embodiment. It is the schematic which shows the structure which incorporated the connection terminal in the semiconductor device which concerns on embodiment. 1 is a schematic circuit diagram showing a configuration further including a diode in a semiconductor device and a power conversion device according to an embodiment. FIG. 8A is a schematic circuit diagram illustrating a configuration further including a current sensor in the semiconductor device and the power conversion device according to the embodiment. FIG. 8B is a schematic diagram illustrating another configuration of the current sensor in the semiconductor device according to the embodiment. It is explanatory drawing of an example of the conversion circuit in the semiconductor device which concerns on embodiment, and a power converter device. It is explanatory drawing of another example of the conversion circuit in the semiconductor device which concerns on embodiment, and a power converter device. It is explanatory drawing of another example of the conversion circuit in the semiconductor device which concerns on embodiment, and a power converter device.

  A semiconductor device 1 according to an embodiment of the present invention is used in a power conversion device 10 as shown in FIG. The power conversion device 10 includes a pair of first terminals T11 and T12, a pair of second terminals T21 and T22, a conversion circuit 3 having a switching element Q1, a bypass switch 4, and a control circuit 5.

  The conversion circuit 3 converts a DC voltage input between the pair of first terminals T11 and T12 and outputs the DC voltage between the pair of second terminals T21 and T22. Here, “DC voltage conversion” is “voltage level conversion” (step-up and step-down). That is, the conversion circuit 3 converts the DC voltage input between the pair of first terminals T11 and T12, and outputs the converted DC voltage between the pair of second terminals T21 and T22.

  The switching element Q1 is a part of the conversion circuit 3 and is switching-controlled. The bypass switch 4 opens and closes a bypass path S1 that bypasses the conversion circuit 3 between the pair of first terminals T11 and T12 and the pair of second terminals T21 and T22. The control circuit 5 controls the conversion circuit 3 and the bypass switch 4.

  As shown in FIGS. 1 and 2, the semiconductor device 1 of this embodiment includes the switching element Q1 of the conversion circuit 3, the bypass switch 4, and a package 1A. The package 1A incorporates a switching element Q1 and a bypass switch 4.

<Configuration of power converter>
First, the power conversion device 10 in which the semiconductor device 1 of the present embodiment is used will be described in more detail. In the following description, the DC voltage input between the pair of first terminals T11 and T12 is referred to as “input voltage V1”, and the current flowing through the pair of first terminals T11 and T12 is referred to as “input current”. In the following description, a voltage output from between the pair of second terminals T21 and T22 is referred to as “output voltage V2.” Furthermore, the “terminal” does not necessarily have a substance as a component for connecting the electric wire, and may be, for example, a lead of an electronic component or a part of a conductor included in a circuit board.

  As shown in FIG. 1, a DC power supply 6 is connected to the pair of first terminals T11 and T12. Note that “connection” for terminals, electronic components, electric wires, and the like includes electrical connection. For this reason, a DC voltage is input from the DC power supply 6 between the pair of first terminals T11 and T12. Here, a solar cell is assumed as the DC power source 6, but a storage battery, a fuel cell, or the like may be used. That is, the DC power source 6 may be a power source that generates a DC voltage.

  The inverter circuit 7 is connected to the pair of second terminals T21 and T22. For this reason, the DC voltage output from the pair of second terminals T <b> 21 and T <b> 22 is input to the inverter circuit 7. The inverter circuit 7 is a full bridge inverter composed of, for example, four switching elements, and converts the output voltage V2 into an AC voltage. The AC voltage output from the inverter circuit 7 is supplied to the load 8.

  The load 8 is a device that operates by receiving an AC voltage or a power system. Of course, the load 8 may be a device that operates by receiving a DC voltage. In this case, the inverter circuit 7 is unnecessary. When the load 8 is a power system, the inverter circuit 7 is controlled so that a current synchronized with the phase of the system voltage of the power system flows.

  An input capacitor C1 is connected between the pair of first terminals T11 and T12. An output capacitor C2 is connected between the pair of second terminals T21 and T22. The input capacitor C1 has a function of stabilizing the input voltage V1. The output capacitor C2 has a function of stabilizing the output voltage V2. Further, the input capacitor C1 and the output capacitor C2 absorb noise generated by switching control of the bypass switch 4.

  The conversion circuit 3 is a step-up DC / DC converter, and includes a reactor L1, a diode D1, and a switching element Q1. Of the two ends of the reactor L1, the first end is connected to the first terminal T11 on the high potential side, and the second end is connected to the anode of the diode D1. The cathode of the diode D1 is connected to the second terminal T21 on the high potential side.

  The switching element Q1 is composed of an enhancement type n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The source of the switching element Q1 is connected to the first terminal T12 and the second terminal T22 on the low potential side. The drain of the switching element Q1 is connected to the second end of the reactor L1 and the anode of the diode D1. The switching element Q1 is turned on / off by a control signal supplied from the control circuit 5. Switching element Q1 is not limited to a MOSFET, and may be another semiconductor switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor.

  The conversion circuit 3 boosts and outputs the input voltage V1 so that the output voltage V2 is stable. Here, “the output voltage V2 is stable” means a state in which the fluctuation of the voltage value of the output voltage V2 is suppressed so that the voltage value of the output voltage V2 does not fluctuate significantly. This includes not only a state where the voltage is maintained but also a state where the output voltage V2 falls within a certain range. For example, if the load 8 is a power system, the conversion circuit 3 boosts the input voltage V1 so that the output voltage V2 is equal to or higher than the reference voltage (that is, the output voltage V2 is higher than the system voltage). The reference voltage is, for example, 330 [V].

  The bypass switch 4 is composed of an enhancement type n-channel MOSFET. The source of the bypass switch 4 is connected to the first terminal T11 on the high potential side and the first end of the reactor L1. The drain of the bypass switch 4 is connected to the second terminal T21 on the high potential side and the cathode of the diode D1. A diode 41 is connected between the drain and source of the bypass switch 4. The diode 41 has an anode connected to the source of the bypass switch 4 and a cathode connected to the drain of the bypass switch 4. Here, the diode 41 is a parasitic diode of the bypass switch 4.

  The bypass switch 4 is connected in parallel with the series circuit of the reactor L1 and the diode D1 of the conversion circuit 3. In other words, the bypass switch 4 is provided in the bypass path S1 that bypasses the conversion circuit 3 between the pair of first terminals T11 and T12 and the pair of second terminals T21 and T22. The bypass switch 4 opens and closes the bypass path S <b> 1 by being turned on / off by a drive signal supplied from the control circuit 5.

  The bypass switch 4 is not limited to a MOSFET, and may be another semiconductor switch element such as an IGBT, an RB-IGBT (Reverse Blocking IGBT), a bipolar transistor, or a triac. In addition, the bypass switch 4 may be a GaN (gallium nitride) based semiconductor switching element.

  The control circuit 5 is mainly composed of, for example, a microcomputer (DSP) or a DSP (Digital Signal Processor), and executes various processes by executing a program stored in the memory. The program may be provided through a telecommunication line or may be provided by being stored in a storage medium. The control circuit 5 gives a control signal to the switching element Q1 of the conversion circuit 3, and controls the conversion circuit 3 by switching on / off. This control signal is a PWM (Pulse Width Modulation) signal. The control signal is not limited to a PWM signal, and may be, for example, a PFM (Pulse Frequency Modulation) signal or a PAM (Pulse Amplitude Modulation) signal.

  The control circuit 5 gives a drive signal to the bypass switch 4 and controls the bypass switch 4 by switching on / off. Specifically, the control circuit 5 executes control to turn on the bypass switch 4 when the voltage (input voltage V1) input between the pair of first terminals T11 and T12 is within the target range. . Here, the upper limit of the target range is not limited and may be infinite. For example, when the “input voltage V1 is equal to or higher than the target voltage”, the control circuit 5 determines that “the input voltage V1 is within the target range” and turns on the bypass switch 4. The target voltage is set according to the output voltage V2. If the load 8 is a power system, the output voltage V2 only needs to be, for example, 330 [V] or higher, so the target voltage may be set to 330V.

  The power converter 10 forms a power conditioner including the inverter circuit 7. This power conditioner performs grid connection operation in a steady state, converts DC power input from the DC power source 6 into AC power, and outputs the AC power to the power system as the load 8. Further, the power conditioner is configured to perform a self-sustained operation in which the disconnector is opened and AC power is output in a state disconnected from the power system when an abnormality such as a power failure occurs in the power system. In addition, the use of the power converter device 10 is not necessarily limited to a power conditioner.

<Operation of power converter>
Hereinafter, the operation of the power conversion apparatus 10 will be described. In the following description, it is assumed that the DC power source 6 is a solar cell and the load 8 is a power system. In the following description, it is assumed that the control circuit 5 is monitoring the input voltage V1.

  When the input voltage V1 is lower than the target voltage, the control circuit 5 controls the switching element Q1 of the conversion circuit 3 to boost the input voltage V1. That is, when the power supply voltage of the DC power supply 6 is lower than the target voltage, such as when the amount of solar radiation is small, the conversion circuit 3 operates. At this time, the control circuit 5 performs control so that the bypass switch 4 is turned off. Therefore, when the input voltage V1 is lower than the target voltage, the bypass path S1 is opened, so that no current flows through the bypass path S1. At this time, since the input voltage V1 is smaller than the output voltage V2, no current flows through the diode 41.

  When the input voltage V1 becomes equal to or higher than the target voltage, the control circuit 5 stops controlling the switching element Q1 of the conversion circuit 3 because there is no need to boost the input voltage V1. That is, when there is a sufficient amount of solar radiation and the power supply voltage of the DC power supply 6 becomes equal to or higher than the target voltage, the operation of the conversion circuit 3 is stopped. At this time, the control circuit 5 performs control so that the bypass switch 4 is turned on. Therefore, when the input voltage V1 becomes equal to or higher than the target voltage, the bypass path S1 is closed and a current flows through the bypass path S1. Then, the input current flows separately to the series circuit of the reactor L1 and the diode D1 of the conversion circuit 3 and the bypass path S1.

  Here, when the operation of the conversion circuit 3 is stopped, if a current flows through the conversion circuit 3 (reactor L1 and diode D1), conduction loss occurs and the conversion efficiency of the power conversion device 10 decreases. Therefore, in the power conversion device 10, when the operation of the conversion circuit 3 is stopped, the conversion efficiency of the power conversion device 10 is reduced by closing the bypass path S1 and flowing a current through the bypass path S1 to reduce conduction loss. Has improved. Note that the on-resistance of the bypass switch 4 is preferably smaller than the resistance of the series circuit of the reactor L1 of the conversion circuit 3 and the diode D1. In this case, since most of the input current flows through the bypass path S1, the conduction loss can be further reduced.

<Configuration of semiconductor device>
Hereinafter, the semiconductor device 1 of the present embodiment will be described in more detail. As shown in FIGS. 1 and 2, the semiconductor device 1 of the present embodiment includes a switching element Q1 of the conversion circuit 3, a diode D1 of the conversion circuit 3, a bypass switch 4, and a package 1A in which these are built. It is a so-called power module. Note that the internal structure of the package 1A shown in FIG. 2 is an example, and the present invention is not limited to this structure.

  The package 1A has a recess, and has a plurality of wiring conductors P1 to P5 at the bottom of the recess. The package 1A is configured by filling a recess with an insulating material such as silicone resin. Of the wiring conductors P1 to P5 of the package 1A, the switching elements Q1, the diode D1, and the bypass switch 4 are bare-chip mounted on the wiring conductors P2, P3, and P5, respectively. In other words, the switching element Q1, the diode D1, and the bypass switch 4 are built in the package 1A.

  The wiring conductors P1 to P5 are made of a material having a low thermal resistance such as ceramic, aluminum, or copper. The switching element Q1 mounted on the wiring conductor P2 and the wiring conductors P1 and P3 are respectively connected by bonding wires W1. The diode D1 and the bypass switch 4 are connected to the wiring conductor P4 by bonding wires W1.

  The package 1A includes three input terminals 11, 12, 13 and two output terminals 21, 22. The input terminal 11 is connected to the first terminal T11 on the high potential side. The input terminal 12 is connected to the second end of the reactor L1. The input terminal 13 is connected to the first terminal T12 on the low potential side. The output terminal 21 is connected to the second terminal T21 on the high potential side. The output terminal 22 is connected to the second terminal T22 on the low potential side.

  A bypass switch 4 is connected between the input terminal 11 and the output terminal 21 via wiring conductors P4 and P5 and a bonding wire W1. That is, a portion between the input terminal 11 and the output terminal 21 is a part of the bypass path S1. A series circuit of a switching element Q1 and a diode D1 is connected between the input terminal 12 and the output terminal 21 via wiring conductors P1, P3, P4 and a bonding wire W1. Further, the input terminal 13 and the output terminal 22 are connected by a wiring conductor P2.

<Comparative example>
Hereinafter, the semiconductor device 100 of the comparative example will be described. However, in the following description, description of the configuration common to the semiconductor device 1 of the embodiment is omitted as appropriate. The semiconductor device 100 of the comparative example is different from the semiconductor device 1 of the present embodiment in that the bypass switch 4 is not built in the package 1A as shown in FIG.

  The package 1A includes two input terminals 101 and 102 and two output terminals 111 and 112. The input terminal 101 is connected to the second end of the reactor L1. The input terminal 102 is connected to the first terminal T12 on the low potential side. The output terminal 111 is connected to the second terminal T21 on the high potential side. The output terminal 112 is connected to the second terminal T22 on the low potential side.

  A series circuit of a switching element Q1 and a diode D1 is connected between the input terminal 101 and the output terminal 111 via wiring conductors P1, P3, P4 and a bonding wire W1. Further, the input terminal 102 and the output terminal 112 are connected by a wiring conductor P2.

  The bypass switch 4 includes a discrete component 120. A first terminal of the discrete component 120 is connected to a connection point between the input capacitor C1 and the reactor L1 outside the package 1A. The second terminal of the discrete component 120 is connected to the connection point between the output capacitor C2 and the output terminal 111.

  Here, the power conversion device 10 is configured by mounting, for example, an input capacitor C1, an output capacitor C2, a conversion circuit 3, a bypass switch 4 and the like on a printed board. When the semiconductor device 100 of the comparative example is used for the power conversion device 10, in order to configure the bypass path S1 including the bypass switch 4, it is necessary to form a wiring on the printed circuit board by bypassing the semiconductor device 100 of the comparative example. There is.

  For this reason, in the power converter device 10 using the semiconductor device 100 of the comparative example, the wiring length of the bypass path S1 is increased and the wiring impedance is increased. In this case, the loss and noise that can occur in the bypass path S1 increase due to the large wiring impedance.

<Effect>
In the semiconductor device 1 of this embodiment, the switching element Q1 and the bypass switch 4 of the conversion circuit 3 are built in one package 1A. For this reason, in the semiconductor device 1 of the present embodiment, the bypass path S1 can be configured without bypassing the semiconductor device 1, so that the wiring length of the bypass path S1 is made shorter than that of the semiconductor device 100 of the comparative example. be able to. As a result, in the semiconductor device 1 of the present embodiment, the wiring impedance of the bypass path S1 can be reduced as compared with the semiconductor device 100 of the comparative example. Therefore, in the semiconductor device 1 of the present embodiment, loss and noise that can occur in the bypass path S1 that bypasses the conversion circuit 3 can be reduced as compared with the semiconductor device 100 of the comparative example.

  Further, in the semiconductor device 1 of the present embodiment, since the thermal resistance is low, heat is easily dispersed, and only a part of the elements (for example, the switching element Q1) can be prevented from becoming high temperature. Furthermore, since the semiconductor device 1 of the present embodiment has a configuration in which heat is easily dispersed as described above, the temperature of a plurality of elements (for example, the switching element Q1 and the like) incorporated in the package 1A is unlikely to vary. . Therefore, in the semiconductor device 1 of the present embodiment, for example, if a thermistor is incorporated in the package 1A, the temperatures of a plurality of elements incorporated in the package 1A can be monitored collectively.

  Further, in the semiconductor device 1 of the present embodiment, the package 1A has a built-in connection point between the output capacitor C2 and the bypass switch 4. Therefore, in the semiconductor device 1 of the present embodiment, the wiring of the bypass path S1 is easier than in the case where the output capacitor C2 and the bypass switch 4 are connected outside the package 1A. Note that whether or not to adopt the configuration is arbitrary.

  Further, in the semiconductor device 1 of the present embodiment, the wiring conductors P1 to P4 are arranged at the input terminal 12, the switching element Q1, the diode D1, the output at the center in the short direction (the center in the vertical direction in FIG. 2) in the package 1A. It arrange | positions along the direction where the terminal 21 is located in a line. Further, the wiring conductor P2 is arranged along the direction in which the input terminal 13 and the output terminal 22 are arranged on the input terminal 13 side (lower side in FIG. 2) in the short direction in the package 1A. Furthermore, the wiring conductors P4 and P5 are arranged along the direction in which the input terminal 11 and the bypass switch 4 are arranged on the input terminal 11 side (upper side in FIG. 2) in the short direction in the package 1A. The wiring conductor P4 is connected to the portion on the input terminal 11 side in the short direction of the package 1A and the central portion in the short direction of the package 1A, and the connection point between the output capacitor C2 and the bypass switch 4 described above. It has become.

  For this reason, in the semiconductor device 1 of the present embodiment, the wiring length of the bypass path S1 in the package 1A can be shortened. As a result, the wiring length of the entire bypass path S1 can be shortened.

  Incidentally, in the conversion circuit 3, a switching loss occurs when the switching element Q1 is switched on / off. In the conversion circuit 3, conduction loss occurs when a current flows through the switching element Q1. And in the conversion circuit 3, since the frequency which switches on / off of the switching element Q1 is high, the ratio which occupies for the whole loss has a larger switching loss than a conduction loss.

  On the other hand, also in the bypass switch 4, switching loss occurs when switching on / off, and conduction loss occurs when current flows. Since the bypass path S1 is rarely frequently opened and closed, the bypass switch 4 is less frequently switched on / off than the switching element Q1 of the conversion circuit 3. For this reason, in the bypass switch 4, the ratio of the total loss to the total loss is larger than the switching loss.

  Therefore, in the semiconductor device 1 of the present embodiment, the switching element Q1 of the conversion circuit 3 is preferably an element having a faster switching speed than the bypass switch 4. In this case, since the switching loss of the switching element Q1 can be suppressed, high efficiency can be achieved by suppressing the dominant loss of the entire loss. In addition, since the bypass switch 4 can use an element having a lower switching speed than the switching element Q1, the cost can be reduced. Whether or not to adopt the configuration is arbitrary.

<Capacitor>
Incidentally, the power conversion apparatus 10 may further include a capacitor 42 as shown in FIG. The capacitor 42 is connected to the bypass switch 4 in parallel. The capacitor 42 normally has an impedance with respect to the inrush current smaller than the impedance with respect to the inrush current of the bypass switch 4. Therefore, in this power conversion device 10, since an inrush current can flow through the capacitor 42, it is possible to prevent an inrush current from flowing through the bypass switch 4.

  Here, in the semiconductor device 1 of the present embodiment, the package 1 </ b> A may have the sub-path S <b> 11 including the capacitor 42 connected in parallel to the bypass switch 4. And at least a part of the sub-path S11 may be built in the package 1A.

  For example, as shown in FIG. 5, the capacitor 42 may be incorporated in the package 1A. In this configuration, the length of the wiring to which the capacitor 42 is connected can be shortened as compared to the case where the capacitor 42 is disposed as a discrete component outside the package 1A. For this reason, in this configuration, the wiring impedance of the path passing through the capacitor 42 can be reduced, and the inrush current can be more effectively prevented from flowing into the bypass switch 4.

  Further, the sub-path S11 may include connection terminals 14, 15, and 16, as shown in FIG. One end of each of the connection terminals 14, 15 and 16 is built in the package 1A, and the other end is connected to the capacitor 42 outside the package 1A. In this configuration, the capacitor 42 is a discrete component and is connected between the connection terminals 14 and 15. The connection terminal 16 is connected to the input terminal 13 and the output terminal 22 by the wiring conductor P2. A capacitor 421 is connected between the connection terminal 15 and the connection terminal 16. The capacitor 421 is also a discrete component.

  In this configuration, when an inrush current occurs, the inrush current flows through the loop A1. The loop A1 is a loop in which current flows in the order of the input terminal 11, the wiring conductor P5, the connection terminal 14, the capacitor 42, the connection terminal 15, the capacitor 421, the connection terminal 16, the wiring conductor P2, the input terminal 13, the capacitor C1, and the input terminal 11. It is. The loop A1 is shorter than the loop A2 passing through the capacitor C2. The loop A2 includes the input terminal 11, the wiring conductor P5, the connection terminal 14, the capacitor 42, the connection terminal 15, the wiring conductor P4, the output terminal 21, the capacitor C2, the output terminal 22, the wiring conductor P2, the input terminal 13, the capacitor C1, and the input. It is a loop that flows through the terminals 11 in order.

  Thus, in this configuration, when an inrush current is generated, the loop in which the inrush current flows through the capacitor 42 can be shortened, so that the wiring impedance in the loop can be reduced. That is, in this configuration, when an inrush current occurs, the inrush current easily flows through a path that passes through the capacitor 42 having a small wiring impedance, so that the effect of suppressing the inrush current can be enhanced. Further, in this configuration, the portion of the wiring conductor P2 connected to the connection terminal 16 extends between a plurality of (here, two) wiring conductors P4 and P5 that constitute a part of the bypass path S1. ing. In other words, the wiring conductor P2 constitutes a path between the input terminal 13 and the connection terminal 16 through the wiring conductors P4 and P5. Therefore, in this configuration, the path passing through the capacitor 42 can be made shorter as compared with the case where the wiring conductor P2 is disposed along one side of the output terminal 21 or 22 side of the package 1A.

  In this configuration, the capacitor 421 is provided. However, even in a configuration without the capacitor 421, the loop in which the inrush current flows through the capacitor 42 can be shortened.

<Diode>
In the semiconductor device 1 of the present embodiment, the package 1A further incorporates a diode 41. In particular, in the semiconductor device 1 of this embodiment, the diode 41 is a parasitic diode of the bypass switch 4 as shown in FIG. As already described, the anode of the diode 41 is connected to the source of the bypass switch 4. The cathode of the diode 41 is connected to the drain of the bypass switch 4. That is, the diode 41 is connected to the bypass switch 4 in parallel.

  In the semiconductor device 1 of the present embodiment, so-called synchronous rectification can be realized by the control circuit 5 controlling the bypass switch 4 to be turned on after the diode 41 is turned on. Since the bypass switch 4 is turned on after the diode 41 is turned on, the bypass switch 4 can be turned on with a small potential difference (potential difference between the drain and the source) at both ends of the bypass switch 4. It can be prevented from flowing.

  Further, if the semiconductor device 1 of the present embodiment further includes the capacitor 42, the parasitic diode of the bypass switch 4 and the capacitor 42 are connected in parallel. In other words, the diode 41 and the capacitor 42 are connected to the bypass switch 4 in parallel.

  Of course, as shown in FIG. 7, the diode 41 may be a component different from the bypass switch 4 instead of the parasitic diode. In this case, it is preferable that the diode 41 is more resistant to inrush current than the bypass switch 4. That is, since an inrush current generated when the DC power supply 6 is turned on or due to fluctuations in the power supply voltage of the DC power supply 6 can be caused to flow through the diode 41, the inrush current can be prevented from flowing into the bypass switch 4. In addition, the semiconductor device 1 of the present embodiment may further include a diode 41 in addition to the parasitic diode of the bypass switch 4.

  In the semiconductor device 1 of the present embodiment, the length of the wiring to which the diode 41 is connected can be shortened as compared with the case where the diode 41 is disposed as a discrete component outside the package 1A. For this reason, in the semiconductor device 1 of the present embodiment, the wiring impedance of the path passing through the diode 41 can be reduced, and it is possible to more effectively prevent an excessive current from flowing through the bypass switch 4. Whether or not the diode 41 is provided is arbitrary. Whether or not the diode 41 is built in the package 1A is also arbitrary.

<Current sensor>
In the semiconductor device 1 of the present embodiment, the package 1A may further include a current sensor 43 as shown in FIG. 8A. The current sensor 43 is provided between the input terminal 11 and the bypass switch 4 and has a function of detecting a current flowing through the bypass path S1. The current sensor 43 is configured using a shunt resistor, for example, and outputs a signal corresponding to the detected value (current value) to the control circuit 5. The control circuit 5 controls the bypass switch 4 according to the detection result of the current sensor 43.

  Specifically, the control circuit 5 compares the detection value of the current sensor 43 with a predetermined current value. Then, the control circuit 5 controls the bypass switch 4 to be turned off when the detected value exceeds a predetermined current value when a current flows in the bypass path S1. In this configuration, the current sensor 43 can prevent an excessive current from flowing through the bypass switch 4.

  In this configuration, if the bypass switch 4 includes a diode 41 (parasitic diode), the control circuit 5 can perform the following control. When the conversion circuit 3 is operating, since the input voltage V1 is lower than the output voltage V2, the diode 41 is non-conductive and no current flows through the bypass path S1. On the other hand, when the operation of the conversion circuit 3 is stopped, the input voltage V1 becomes equal to or higher than the output voltage V2, so that the diode 41 becomes conductive and a current flows through the bypass path S1. Therefore, the control circuit 5 can control the bypass switch 4 to be turned on when the operation of the conversion circuit 3 is stopped based on the detection result of the current sensor 43.

  In this configuration, the control circuit 5 can determine that an abnormality has occurred in the bypass switch 4 if the direction of the current detected by the current sensor 43 is opposite. That is, the direction of the current detected by the current sensor 43 is reversed when the bypass switch 4 is turned on even though the conversion circuit 3 is operating. This is because it has occurred.

  Here, when the current sensor 43 is arranged outside the package 1A, the length of the wiring connected to the current sensor 43 becomes long, so that electromagnetic noise induced by the current flowing through the wiring affects the current sensor 43. There is a possibility of effect. It is conceivable to provide a filter circuit as a countermeasure against this noise. However, in this case, the current waveform detected by the current sensor 43 by the filter circuit becomes dull, and the time required for detection becomes long.

  On the other hand, if the current sensor 43 is built in the package 1A as described above, the length of the wiring connected to the current sensor 43 is shortened, so that the wiring impedance can be reduced. As a result, electromagnetic noise induced by the current flowing through the wiring is also reduced, so that the capacity of the filter circuit as a countermeasure against noise can be reduced, and the time required for the current sensor 43 to detect can be shortened.

  Further, the current sensor 43 may be configured integrally with the bypass switch 4. For example, as shown in FIG. 8B, when the bypass switch 4 is formed of an IGBT, a sense terminal ST1 connected to the emitter terminal of the IGBT may be provided, and the sense terminal ST1 may be used as the current sensor 43. That is, a small current proportional to the current flowing between the collector and emitter of the bypass switch 4 flows to the sense terminal ST1. Therefore, by monitoring the output of the sense terminal ST1 generated by this minute current, it is possible to indirectly detect the current flowing through the bypass path S1.

  In addition to the control circuit 5, an overcurrent detection circuit that controls the bypass switch 4 according to the detection result of the current sensor 43 may be provided. In this case, the overcurrent detection circuit may be built in the package 1A.

<Conversion circuit>
In the power conversion device 10 described above, the conversion circuit 3 is configured by a step-up DC / DC converter, but may have other configurations. Hereinafter, various configurations of the conversion circuit 3 will be described with reference to FIGS. In addition, in FIGS. 9-11, illustration of a part of structure of the power converter device 10 is abbreviate | omitted.

  For example, as shown in FIG. 9, the conversion circuit 3 may be configured by a so-called symmetry type DC / DC converter including two booster circuits 31 and 32. The booster circuit 31 includes a reactor L1, a diode D1, and a switching element Q1. The booster circuit 32 includes a reactor L2, a diode D2, and a switching element Q2.

  A series circuit of the reactor L1 and the diode D1 is connected between the first terminal T11 and the second terminal T21 on the high potential side. The series circuit of the reactor L2 and the diode D2 is connected between the first terminal T12 and the second terminal T22 on the low potential side. The diodes D1 and D2 are opposite to each other.

  A series circuit of input capacitors C11 and C12 is connected between the pair of first terminals T11 and T12. A connection point between the input capacitors C11 and C12 is connected to a terminal T13 located between the pair of first terminals T11 and T12. A series circuit of output capacitors C21 and C22 is connected between the pair of second terminals T21 and T22. A connection point between the output capacitors C21 and C22 is connected to a terminal T23 located between the pair of second terminals T21 and T22. Further, the source of the switching element Q1 and the drain of the switching element Q2 are connected to the terminal T13 and the terminal T23.

  The power conversion apparatus 10 includes a bypass path S1 that bypasses the booster circuit 31 and a bypass path S2 that bypasses the booster circuit 32. A bypass switch 4A is provided in the bypass path S1. A bypass switch 4B is provided in the bypass path S2. The bypass switches 4A and 4B both have the same function as the bypass switch 4. Further, the bypass switches 4A and 4B are opposite to each other.

  The conversion circuit 3 boosts and outputs the input voltage V1 so that the output voltage V2 is stabilized when the control circuit 5 controls the switching elements Q1 and Q2. In this power converter 10, the control circuit 5 turns on the bypass switches 4A and 4B when the voltage (input voltage V1) input between the pair of first terminals T11 and T12 is within the target range. Execute the control to

  In the power conversion device 10 that employs the conversion circuit 3 described above, the semiconductor device 1 of the present embodiment includes two switching elements Q1 and Q2 of the conversion circuit 3, two diodes D1 and D2 of the conversion circuit 3, and two Bypass switches 4A and 4B are provided. Further, the semiconductor device 1 of the present embodiment includes one package 1A in which these are incorporated. Whether or not the diodes D1 and D2 are incorporated in the package 1A is arbitrary.

  Further, the conversion circuit 3 may be constituted by a step-down DC / DC converter, for example, as shown in FIG. The conversion circuit 3 includes a reactor L1, a diode D1, and a switching element Q1. Of both ends of the reactor L1, the first end is connected to the cathode of the diode D1, and the second end is connected to the second terminal T21 on the high potential side. The anode of the diode D1 is connected to the first terminal T12 and the second terminal T22 on the low potential side. The source of the switching element Q1 is connected to the first end of the reactor L1 and the cathode of the diode D1. The drain of the switching element Q1 is connected to the first terminal T11 on the high potential side.

  The source of the bypass switch 4 is connected to the second terminal T21 on the high potential side and the second end of the reactor L1. The drain of the bypass switch 4 is connected to the first terminal T11 on the high potential side and the drain of the switching element Q1. The diode 41 (parasitic diode) has an anode connected to the second terminal T21 on the high potential side and a cathode connected to the first terminal T11 on the high potential side.

  This conversion circuit 3 steps down the input voltage V1 and outputs it so that the output voltage V2 is stabilized by the control circuit 5 controlling the switching element Q1. Moreover, in this power converter device 10, the control circuit 5 turns on the bypass switch 4 when the voltage (input voltage V1) input between the pair of first terminals T11 and T12 is within the target range. Execute control. For example, when the “input voltage V1 is equal to or lower than the target voltage”, the control circuit 5 determines that “the input voltage V1 is within the target range” and turns on the bypass switch 4.

  In the power conversion device 10 that employs the conversion circuit 3 described above, the semiconductor device 1 of the present embodiment includes the switching element Q1 of the conversion circuit 3, the diode D1 of the conversion circuit 3, the bypass switch 4, and these. One package 1A is provided. Whether or not the diode D1 is built in the package 1A is arbitrary.

  Furthermore, the conversion circuit 3 may be formed of a bidirectional chopper circuit, for example, as shown in FIG. The conversion circuit 3 includes a reactor L1 and two switching elements Q1 and Q2. Of both ends of the reactor L1, the first end is connected to the first terminal T11 on the high potential side, and the second end is connected to the drain of the switching element Q1 and the source of the switching element Q2. The source of the switching element Q1 is connected to the first terminal T12 and the second terminal T22 on the low potential side. The drain of the switching element Q2 is connected to the second terminal T21 on the high potential side.

  The bypass switch 4 provided in the bypass path S1 that bypasses the conversion circuit 3 is a bidirectional switch. Here, the bypass switch 4 is an RB-IGBT, but may be other bidirectional switches such as bidirectional GaN and triac. Moreover, in this power converter device 10, the DC power source 6 is the storage battery 61 and the load 8 is the power system 81, but the DC power source 6 and the load 8 are not intended to be limited.

  In the conversion circuit 3, the control circuit 5 controls the switching elements Q1 and Q2, thereby converting the DC voltage input between the pair of first terminals T11 and T12 and between the pair of second terminals T21 and T22. Has a function to output. The conversion circuit 3 further has a function of converting a DC voltage input between the pair of second terminals T21 and T22 and outputting the DC voltage between the pair of first terminals T11 and T12. Therefore, in this power converter 10, it is possible to charge and discharge the storage battery 61.

  Even when the DC voltage input between the pair of second terminals T21 and T22 is converted and output between the pair of first terminals T11 and T12, the configuration of the power converter 10 described above can be employed. It is. In this case, in the description of the power conversion device 10 described above, the pair of first terminals T11 and T12 and the pair of second terminals T21 and T22 may be read each other.

  In the conversion circuit 3, the bypass switch 4 may not be a bidirectional switch but may be a MOSFET. Here, when a bidirectional switch having bidirectional withstand voltage characteristics is used as the bypass switch 4, the conversion circuit 3 is preferably composed of, for example, a bidirectional step-up / step-down chopper circuit.

  In the power conversion device 10 that employs the conversion circuit 3 described above, the semiconductor device 1 of this embodiment includes two switching elements Q1 and Q2 of the conversion circuit 3, a bypass switch 4, and one package 1A in which these are incorporated. With.

  The semiconductor device 1 and the power conversion device 10 according to the embodiment of the present invention have been described in detail above. However, the configuration described above is merely an example of the present invention, and the present invention is not limited to the above-described embodiment, and deviates from the technical idea according to the present invention even in other embodiments. Various changes can be made in accordance with the design or the like as long as they are not.

  For example, the semiconductor device 1 of the present embodiment has a configuration in which the diode D1 of the conversion circuit 3 is built in the package 1A. However, it is sufficient that at least the switching element Q1 of the conversion circuit 3 is built in, and the diode D1 is built in. It does not have to be. In addition, the semiconductor device 1 according to the present embodiment may have a configuration in which not only the switching element Q1 and the bypass switch 4 of the conversion circuit 3 but also the inverter circuit 7 is built in the package 1A. Further, when the power conversion device 10 is a so-called multistring power conditioner, the power conversion device 10 includes a plurality of conversion circuits 3 respectively corresponding to a plurality of strings. In this case, the semiconductor device 1 of the present embodiment may be configured to incorporate the switching elements Q1 of the plurality of conversion circuits 3 in one package 1A.

DESCRIPTION OF SYMBOLS 10 Power converter 1 Semiconductor device 14, 15, 16 Connection terminal 1A Package 3 Conversion circuit 4 Bypass switch 41 Diode 42 Capacitor 43 Current sensor 5 Control circuit Q1, Q2 Switching element S1, S2 Bypass path S11 Sub path T11, T12 A pair of First terminal T21, T22 A pair of second terminals

Claims (7)

A part of a conversion circuit that converts a DC voltage input between the pair of first terminals and outputs the DC voltage between the pair of second terminals, the switching element being controlled to be switched;
A bypass switch that opens and closes a bypass path that bypasses the conversion circuit between the pair of first terminals and the pair of second terminals;
A semiconductor device comprising: a package in which the switching element and the bypass switch are built. A sub-path including a capacitor connected in parallel to the bypass switch;
The semiconductor device according to claim 1, wherein at least a part of the sub-path is built in the package.   The semiconductor device according to claim 2, wherein the capacitor is built in the package. The sub-path includes a connection terminal;
3. The semiconductor device according to claim 2, wherein one end of the connection terminal is built in the package, and the other end is connected to the capacitor outside the package.   5. The semiconductor device according to claim 1, wherein the package further includes a diode connected in parallel to the bypass switch. 6.   The semiconductor device according to claim 1, wherein the switching element is an element having a switching speed faster than that of the bypass switch.   The semiconductor device according to claim 1, wherein the package further includes a current sensor that detects a current flowing through the bypass path.

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