JP2017011089A - Semiconductor device and method of controlling internal circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a method of controlling an internal circuit, capable of preventing breakage of a circuit element resulting from malfunction of the internal circuit caused by surge application.SOLUTION: A semiconductor device includes: at least one capturing part that captures electric charges diffused in a semiconductor substrate depending on a surge applied via an electrode pad; a detector that detects current generated depending on the electric charges captured by the capturing part; and an internal circuit that performs predetermined control in a case where the current is detected by the detector.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor device and an internal circuit control method.

  The following techniques are known as techniques for protecting an internal circuit of a semiconductor device from a surge applied from the outside via an electrode pad of the semiconductor device.

  For example, Patent Document 1 describes a technique for preventing the surge current from flowing into the internal circuit by forming an insulator layer on the surge current path between the internal circuit and the protection circuit.

JP 2005-924858 A

  When a surge is applied from the outside through the electrode pad of the semiconductor device, charges are injected into the semiconductor substrate. The injected charge diffuses inside the semiconductor substrate. When the electric charge diffusing inside the semiconductor substrate reaches the internal circuit, the current flowing through the internal circuit fluctuates, which may cause the internal circuit to malfunction. When the internal circuit includes, for example, a voltage regulator, the output voltage of the voltage regulator may increase with current fluctuation. A logic circuit that operates by receiving an output voltage from a voltage regulator usually includes a transistor formed by a low breakdown voltage process in which a gate oxide film is relatively thin. For this reason, when the output voltage of the voltage regulator rises with the application of a surge, the voltage supplied to circuit elements such as transistors constituting the logic circuit exceeds the withstand voltage, and the circuit elements of the logic circuit are destroyed. There is a fear.

  Conventionally, as a measure for preventing malfunction of the internal circuit due to the surge, the charge that diffuses the semiconductor substrate does not reach the internal circuit by increasing the distance between the electrode pad to which the surge is applied and the internal circuit. Layout measures have been taken. However, in recent years, in order to reduce the power consumption of semiconductor devices, the current flowing through the internal circuit has been reduced and it is becoming more susceptible to surges. In addition, the size of the semiconductor chip has been reduced, and it has become difficult to increase the distance between the electrode pad to which the surge is applied and the internal circuit, and it is becoming difficult to perform conventional layout measures. .

  The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device and an internal circuit control method capable of preventing circuit elements from being destroyed due to malfunction of the internal circuit due to surge application. And

  The semiconductor device according to the present invention includes at least one collection unit that collects charges that diffuse inside the semiconductor substrate in response to a surge applied through the electrode pad, and the charges collected by the collection unit. A detection unit that detects a current generated in response to the signal, and an internal circuit that performs predetermined control when the detection unit detects the current.

  The internal circuit control method according to the present invention collects charges that diffuse inside the semiconductor substrate in response to a surge applied through the electrode pads, detects a current generated according to the collected charges, The internal circuit is controlled when the current is detected.

  According to the semiconductor device and the internal circuit control method of the present invention, it is possible to prevent the destruction of the circuit element due to the malfunction of the internal circuit due to the surge application.

It is a circuit diagram which shows the surge protection element which comprises the semiconductor device which concerns on embodiment of this invention. Sectional drawing which shows the partial structure of the semiconductor device which concerns on embodiment of this invention It is a circuit diagram which shows the structure of the voltage regulator which concerns on embodiment of this invention. It is a figure which shows the structure of the control circuit which concerns on embodiment of this invention. It is a figure which shows an example of the layout of each component in the semiconductor chip which concerns on embodiment of this invention. It is a figure which shows the structure of the control circuit which concerns on other embodiment of this invention. It is a figure which shows an example of the layout of each component in the semiconductor chip which concerns on embodiment of this invention. It is a figure which shows an example of the layout of each component in the semiconductor chip which concerns on embodiment of this invention. It is a circuit diagram which shows the structure of the voltage regulator which concerns on other embodiment of this invention. It is a figure which shows the structure of the control circuit which concerns on other embodiment of this invention.

  Hereinafter, an example of an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or equivalent components and parts are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate.

[First embodiment]
FIG. 1 is a circuit diagram showing surge protection elements 20 and 21 constituting a semiconductor device according to an embodiment of the present invention.

  The semiconductor device according to the embodiment of the present invention has a power terminal 10 on the high potential side, an input / output terminal (I / O terminal) 11, and a power terminal (ground terminal) 12 on the low potential side. The power supply terminal 10, the input / output terminal 11 and the power supply terminal 12 are configured as electrode pads provided on the surface of the semiconductor chip.

  A power supply voltage vdd is externally supplied to the power terminal 10 on the high potential side, and a power supply voltage (ground voltage) vss is supplied to the power terminal 12 on the low potential side from the outside. An input signal from the outside is input to the input / output terminal 11, and an output signal from an internal circuit provided in the semiconductor device is output.

  A high potential side power supply line 10 a is connected to the high potential side power supply terminal 10, and a low potential side power supply line (ground line) 12 a is connected to the low potential side power supply terminal 12. A signal line 11 a is connected to the input / output terminal 11.

  The surge protection element 20 is composed of a p-channel transistor having a source, a gate, and an n-well connected to the power line 10a on the high potential side and a drain connected to the signal line 11a. On the other hand, the surge protection element 21 is composed of an n-channel transistor in which a source, a gate, and a p-well are connected to a low-potential power line (ground line) 12a and a drain is connected to the signal line 11a. The surge protection elements 20 and 21 have a function of protecting the internal circuit from a surge applied to the input / output terminal 11.

  FIG. 2 is a cross-sectional view showing a partial configuration of the semiconductor device according to the embodiment of the present invention, including surge protection elements 20 and 21.

  The surge protection element 20 includes an n-well region 20w having an n-type conductivity formed in a surface layer portion of a silicon substrate 30 having a p-type conductivity, and a p-type formed in a surface layer portion of the n-well region 20w. Provided between drain region 20d and source region 20s having conductivity type, well contact region 20c having n-type conductivity type formed in the surface layer portion of n well region 20w, and between drain region 20d and source region 20s. Gate 20g.

  The surge protection element 21 includes a p-type well region 21w having a p-type conductivity formed in the surface layer portion of the silicon substrate 30, and a drain region 21d having an n-type conductivity formed in the surface layer portion of the p-well region 21w. And a source region 21s, a p-type well contact region 21c formed in the surface layer portion of the p-well region 21w, and a gate 21g provided between the drain region 21d and the source region 21s. .

  When a surge having a negative voltage is applied to the input / output terminal 11, electrons are injected into the silicon substrate 30 from the drain region 21d of the surge protection element 21 made of an n-type semiconductor. The electrons injected into the silicon substrate 30 diffuse in the silicon substrate 30. When electrons diffusing in the silicon substrate 30 reach the transistor 22 constituting an internal circuit formed in the semiconductor device, the current flowing through the transistor 22 may fluctuate.

  FIG. 3 is a circuit diagram showing a configuration of a voltage regulator 40 which is an example of an internal circuit constituting the semiconductor device according to the embodiment of the present invention. The voltage regulator 40 includes a reference voltage generation circuit 41, an amplifier circuit 42, an output circuit 43, and a resistance voltage dividing circuit 44.

  The reference voltage generation circuit 41 includes p-channel transistors Q1, Q2, Q4 to Q7, Q12 to Q14, n-channel transistors Q3 and Q8 to Q11, capacitors C1 and C2, diodes D1 and D2, and resistance elements R1 to R3. It is comprised including. A bias voltage input terminal 14 for applying a first bias voltage is connected to the gates of the transistors Q8 and Q9, and a bias voltage input for applying a second bias voltage is connected to the gates of the transistors Q10 and Q11. Terminal 15 is connected. The reference voltage generation circuit 41 outputs the reference voltage vref at the connection point between the transistor Q14 and the resistance element R3.

  The amplifier circuit 42 includes an operational amplifier circuit (operational amplifier) 42a. In the operational amplifier circuit 42a, the non-inverting input terminal is connected to the connection point between the transistor Q14 constituting the reference voltage generation circuit 41 and the resistance element R3, and the inverting input terminal is connected to the resistance elements R4 and R5 constituting the resistance voltage dividing circuit 44. The output terminal is connected to the gate of the transistor Q15 constituting the output circuit 43.

  The output circuit 43 has a p-channel transistor Q15 having a source connected to the high-potential power supply line 10a, a drain connected to the output terminal 43a of the voltage regulator 40, and a gate connected to the output terminal of the operational amplifier circuit 42a. It is comprised including.

  The resistance voltage divider circuit 44 includes serially connected resistance elements R4 and R5 provided between the output terminal 43a of the voltage regulator 40 and the low-potential-side power line (ground line) 12a. The resistance voltage dividing circuit 44 divides the output voltage vddl output from the output terminal 43a of the voltage regulator 40 at a ratio corresponding to the resistance ratio of the resistance elements R4 and R5, and the divided voltage vs is set to the resistance elements R4 and R5. Output at the connection point with.

  Hereinafter, the operation of the voltage regulator 40 will be described. The reference voltage generation circuit 41 outputs a constant reference voltage vref regardless of the level of the power supply voltage supplied between the power terminal 10 on the high potential side and the power terminal (ground terminal) 12 on the low potential side. The operational amplifier circuit 42 a controls the output voltage of the operational amplifier circuit 42 a so that the voltage vs generated by the resistance voltage dividing circuit 44 matches the reference voltage vref generated by the reference voltage generating circuit 41. Since the transistor Q15 constituting the output circuit 43 is driven and controlled by the output voltage of the operational amplifier circuit 42a, the output voltage vddl output from the output terminal 43a is maintained at a constant level. The output voltage vddl is a constant voltage level (for example, 1.5V) lower than the power supply voltage level (for example, 5V) supplied between the power terminal 10 on the high potential side and the power terminal (ground terminal) 12 on the low potential side. ) Is maintained. Note that a logic circuit (not shown) that receives the supply of the output voltage vddl of the voltage regulator 40 is connected to the output terminal 43a. This logic circuit can perform a stable operation by keeping the output voltage vddl of the voltage regulator 40 constant.

  Here, consider a case where electrons that are injected into the silicon substrate 30 by a surge applied to the input / output terminal 11 and diffuse in the silicon substrate 30 reach the reference voltage generation circuit 41. When electrons diffusing in the silicon substrate 30 reach the reference voltage generation circuit 41, the current flowing from the drain of the n-channel transistor Q9 constituting the reference voltage generation circuit 41 toward the silicon substrate 30 increases. As a result, the potential of the node n1 connected to the drain of the transistor Q9 decreases. When the potential of the node n1 decreases, the current flowing through the transistor Q14 increases and the level of the reference voltage vref increases. When the level of the reference voltage vref increases, the output voltage vddl of the voltage regulator 40 increases. Thus, when a surge is applied to the input / output terminal 11, the output voltage vddl of the voltage regulator 40 may fluctuate to a level higher than a design value (for example, 1.5 V). As the voltage level of the surge applied to the input / output terminal 11 increases and the amount of electrons injected into the silicon substrate 30 increases, the increase width of the output voltage vddl increases, and the power supply voltage level (for example, 5V) is maximum. ). As described above, when the level of the output voltage vddl of the voltage regulator 40 increases greatly exceeding the design value, it exceeds the breakdown voltage of the circuit elements constituting the logic circuit (not shown) that operates upon receiving the supply of the output voltage vddl. As a result, the circuit elements of the logic circuit may be destroyed.

  Therefore, the semiconductor device according to the embodiment of the present invention has the transistor Q15 constituting the output circuit 43 of the voltage regulator 40 when the current corresponding to the electric charge that diffuses in the silicon substrate 30 due to the application of surge is detected. A control circuit 100 is provided that suppresses an increase in the output voltage vddl by controlling to an off state.

  FIG. 4 is a diagram showing a configuration of the control circuit 100 that constitutes the semiconductor device according to the embodiment of the present invention. The control circuit 100 includes a collection unit 110 and a detection unit 120.

  The collection unit 110 collects charges that diffuse inside the silicon substrate 30 due to a surge applied through the electrode pads that constitute the input / output terminal 11. The collection unit 110 is configured to include an n-type region made of an n-type semiconductor formed in the surface layer portion of the silicon substrate 30. The n-type region may have, for example, an n-well having n-type conductivity or an n-active form. By configuring the collection unit 110 with an n-type semiconductor, electrons that diffuse in the silicon substrate 30 are attracted to the collection unit 110 and collected.

  The detection unit 120 detects a current generated according to the charge collected by the collection unit 110. The detection unit 120 includes a resistance element 121 having one end connected to the collection unit 110 and the other end connected to the power line 10a on the high potential side. The detection unit 120 includes inverters 122 and 123 and a p-channel transistor 124 connected in series. An input end of the inverter 122 is connected to a connection line between the resistance element 121 and the collection unit 110, and an output end is connected to an input end of the inverter 123. The output terminal of the inverter 123 is connected to the gate of the transistor 124. The transistor 124 has a source connected to the power supply line 10 a and a drain serving as the output terminal 125 of the control circuit 100. The output terminal 125 of the control circuit 100 is connected to the gate of the transistor Q15 constituting the output circuit 43 of the voltage regulator 40.

  Hereinafter, the operation of the control circuit 100 will be described. In the silicon substrate 30, the input voltage of the inverter 122 that constitutes the detection unit 120 is at a high level (vdd level) during normal times when no electron diffusion due to surge application occurs, and the gate of the transistor 124 has a high level. A level (vdd level) voltage is supplied. Thereby, the transistor 124 is maintained in an OFF state, and the output voltage vddl of the voltage regulator 40 is maintained at a normal voltage level (for example, 1.5 V).

  When a surge is applied to the electrode pads constituting the input / output terminal 11, electrons are injected into the silicon substrate 30, and the injected electrons diffuse in the silicon substrate 30. At least some of the electrons diffusing in the silicon substrate 30 are collected by the collection unit 110.

  The electrons collected by the collection unit 110 flow toward the power supply line 10a via the resistance element 121 constituting the detection unit 120. Along with this, a current Is flows from the power supply line 10 a to the collection unit 110 via the resistance element 121. A voltage drop corresponding to the magnitude of the current Is occurs at both ends of the resistance element 121. The magnitude of the current Is is proportional to the amount of electrons collected by the collection unit 110.

  When the voltage drop caused by the current Is flowing through the resistance element 121 causes the input voltage of the inverter 122 to fall to the inversion level, the gate of the transistor 124 becomes low level and the transistor 124 is turned on. As a result, a high level (vdd level) voltage is output to the output terminal 125 of the control circuit 100.

  As described above, the control circuit 100 collects the charges that diffuse in the silicon substrate 30 due to the surge applied to the electrode pads by the collection unit 110, and converts the charges collected by the collection unit 110 into the charges collected. The detection unit 120 detects the current Is generated accordingly. Note that the voltage drop caused by the current Is flowing through the resistance element 121 causes the input voltage of the inverter 122 to drop to the inversion level, and a high level (vdd level) voltage is output to the output terminal 125 of the control circuit 100. It is assumed that the current Is is detected by the detection unit 120.

  The output terminal 125 of the control circuit 100 is connected to the gate of the transistor Q15 constituting the output circuit 43 of the voltage regulator 40. The transistor Q15 is turned off when a high-level (vdd level) voltage is supplied from the output terminal 125 of the control circuit 100, whereby the output voltage vddl of the voltage regulator 40 becomes a low level (vss level).

  As described above, according to the semiconductor device according to the embodiment of the present invention including the voltage regulator 40 and the control circuit 100, when a surge of a certain scale is applied to the electrode pad, the voltage regulator 40 outputs the output voltage vddl. Is controlled to a low level (vss). Therefore, even if the level of the reference voltage vref generated by the reference voltage generation circuit 41 increases with the surge application, the output voltage vddl of the voltage regulator 40 increases to a level higher than the design value accordingly. Can be prevented. As described above, the control circuit 100 controls the voltage regulator 40 so as to suppress the increase in the output voltage vddl, thereby preventing the circuit elements of the logic circuit that operates by receiving the supply of the output voltage vddl of the voltage regulator 40 from being destroyed. can do.

  FIG. 5 is a diagram showing an example of the layout of each component in the semiconductor chip 200 constituting the semiconductor device according to the present embodiment. The semiconductor chip 200 has a square or rectangular shape, and the electrode pads 201 constituting the input / output terminals 11 and the like are arranged along the outer edge of the semiconductor chip 200. The reference voltage generation circuit 41 constituting the voltage regulator 40 is arranged inside the semiconductor chip 200 with respect to the electrode pad 201. The collection unit 110 of the control circuit 100 is preferably disposed between the electrode pad 201 and the reference voltage generation circuit 41. As shown in FIG. 5, when the electrode pad 201 is disposed along each side of the semiconductor chip 200, the collection unit 110 may be disposed so as to surround the outer periphery of the reference voltage generation circuit 41. preferable. As described above, by arranging the collection unit 110 between the electrode pad 201 and the reference voltage generation circuit 41, electrons that diffuse in the silicon substrate 30 with the application of a surge to the electrode pad 201 can generate a reference voltage. Before reaching the circuit 41, it is collected by the collection unit 110. As a result, the output voltage vddl can be controlled to a low level (vss level) before the output voltage vddl of the voltage regulator 40 increases due to a surge applied to the electrode pad 201, thereby preventing the logic circuit from being destroyed. Can enhance the effect.

  Note that the density of electrons diffusing in the silicon substrate 30 decreases as the distance from the electrode pad 201 to which a surge is applied increases. Therefore, by arranging the collection unit 110 closer to the electrode pad 201, the amount of electrons collected in the collection unit 110 can be increased. That is, by arranging the collection unit 110 closer to the electrode pad 201, the current detection sensitivity in the detection unit 120 is increased, and the control circuit 100 can be operated even when a low level surge is applied. On the other hand, by arranging the collection unit 110 closer to the reference voltage generation circuit 41, the current detection sensitivity in the detection unit 120 can be suppressed, and the control circuit 100 is operated only when a high level surge is applied. Can do.

[Second Embodiment]
FIG. 6 is a diagram showing a configuration of a control circuit 100A according to the second embodiment of the present invention. The control circuit 100A is used in place of the control circuit 100 according to the first embodiment. The control circuit 100A includes a plurality of collection units 110a, 110b, 110c, and 110d. The collection units 110a to 110d are each configured to include an n-type region made of an n-type semiconductor. In addition, the control circuit 100A includes a selection unit 140 that selectively connects the plurality of collection units 110a to 110d to the resistance element 121. The selection unit 140 may be configured by a switching element such as a transistor connected to each of the plurality of collection units 110a to 110d, for example. Further, the selection unit 140 may be configured using a known trimming technique for forming or cutting a wiring that connects each of the plurality of collection units 110a to 110d and the resistance element 121 afterwards. Good. In the control circuit 100A, the resistance element 121 constituting the detection unit 120 is a variable resistance.

  FIG. 7 is a diagram illustrating an example of the arrangement of the plurality of collection units 110a to 110d. As shown in FIG. 7, the plurality of collection units 110 a to 110 d are provided between the electrode pad 201 and the reference voltage generation circuit 41 and at positions where the distances from the electrode pad 201 are substantially the same. Also good.

  According to the control circuit 100A according to the second embodiment, the current flowing through the resistance element 121 is increased or decreased by increasing or decreasing the number of collection sections connected to the resistance element 121 by the selection of the collection sections 110a to 110d by the selection section 140. It is possible to adjust the magnitude of Is. That is, the current Is has a magnitude proportional to the total amount of charges collected by each of the selected collection units. By making the current Is adjustable, the input voltage of the inverter 122 can be adjusted. Further, the input voltage of the inverter 122 can be adjusted also by the resistance value of the resistance element 121. That is, according to the control circuit 100A, it is possible to adjust the surge level at which the control circuit 100A operates. Specifically, by increasing the number of collecting parts connected to the resistance element 121 or increasing the resistance value of the resistance element 121, the current detection sensitivity in the detection part 120 can be increased, and a low level surge can be achieved. Even when is applied, the control circuit 100A can be operated. When the control circuit 100A operates excessively, the current detection sensitivity in the detection unit 120 is decreased by reducing the number of collection units connected to the resistance element 121 or by reducing the resistance value of the resistance element 121. Just do it.

  FIG. 8 is a diagram illustrating another arrangement example of the collection units 110a to 110d. The collection units 110 a to 110 d may be provided at positions that are between the electrode pad 201 and the reference voltage generation circuit 41 and at different distances from the electrode pad 201. In the example illustrated in FIG. 8, the collection unit 110 a is disposed at a position farthest from the electrode pad 201, and the collection unit 110 d is disposed at a position closest to the electrode pad 201. The density of electrons diffusing in the silicon substrate 30 decreases as the distance from the electrode pad 201 to which a surge is applied increases. Therefore, the amount of electrons collected by the collecting unit 110d having the smallest distance from the electrode pad 201 is the largest, and the amount of electrons collected by the collecting unit 110a having the largest distance from the electrode pad 201 is The least.

  The surge level at which the control operation by the control circuit 100A is activated depending on which one of the plurality of collection units 110a to 110d is connected to the resistance element 121 by arranging the plurality of collection units 110a to 110d in this way. It is possible to make adjustments. Specifically, the current detection sensitivity in the detection unit 120 can be increased by connecting the collection unit 110d that collects the largest amount of electrons to the resistance element 121, and even when a low level surge is applied. The control circuit 100A can be activated. On the other hand, the current detection sensitivity in the detection unit 120 can be suppressed by connecting the collection unit 110a that collects the least amount of electrons to the resistance element 121, and only when a high level surge is applied, the control circuit. 100A can be activated.

[Third Embodiment]
FIG. 9 is a circuit diagram showing a configuration of a voltage regulator 40A according to the third embodiment of the present invention. The voltage regulator 40A is used in place of the voltage regulator 40 according to the first embodiment. The voltage regulator 40A is different from the voltage regulator 40 according to the first embodiment in that it further includes a clamp circuit 45 configured to include p-channel type transistors Q16 and Q17. Transistor Q16 has a source connected to power supply line 10a, and a source and a gate connected to the source of transistor Q17. The transistor Q17 has a drain connected to the gate of the transistor Q15 constituting the output circuit 43, and a gate connected to the output terminal of the control circuit 100B.

  FIG. 10 is a diagram showing a configuration of a control circuit 100B according to the third embodiment of the present invention that is used together with the voltage regulator 40A. In the control circuit 100B, the detection unit 120 includes a resistance element 121 and inverters 122 and 123. The control circuit 100B outputs a low-level (vss level) voltage from the output terminal 125 when the input voltage of the inverter 122 drops to the inversion level due to a voltage drop caused by the current Is flowing through the resistance element 121. . That is, in the control circuit 100B, the polarity of the voltage output from the output terminal 125 when a certain scale of surge is applied to the electrode pad is opposite to that of the control circuit 100 according to the first embodiment. Note that the control circuit 100B may include a plurality of collection units as in the control unit 100A according to the second embodiment.

  According to the semiconductor device according to the third embodiment of the present invention including the voltage regulator 40A and the control circuit 100B, the control circuit 100B has a low level (vss) when a surge of a certain scale is applied to the electrode pad. Level) voltage. As a result, the transistor Q17 constituting the clamp circuit 45 of the voltage regulator 40A is turned on. When the transistor Q17 is turned on, the clamp circuit 45 clamps the gate voltage of the transistor Q15 to a level lower than the voltage level (vdd) of the power supply line 10a by the threshold voltage of the transistor Q16. Therefore, even if the level of the reference voltage vref generated by the reference voltage generation circuit 41 increases with surge application, the output voltage vddl of the voltage regulator 40A increases to a level higher than the design value accordingly. Can be prevented. In this way, the control circuit 100B controls the voltage regulator 40A so as to suppress the increase in the output voltage vddl, thereby preventing the circuit elements of the logic circuit that operates by receiving the output voltage vddl from the voltage regulator 40A from being destroyed. can do.

  Further, according to the semiconductor device of the third embodiment, the transistor Q15 whose gate voltage is clamped by the clamp circuit 45 is not completely turned off. That is, when the surge is applied, the output voltage vddl of the voltage regulator 40A is suppressed from rising, but the level of the output voltage vdd is maintained at a level higher than the voltage level (vss) of the power supply line (ground line) 12a. As a result, even when a surge is applied, power supply to the logic circuit is not completely cut off, and a certain level of voltage can be supplied to the logic circuit.

  In each of the above-described embodiments, the voltage regulator is exemplified as the internal circuit controlled by the control circuits 100, 100A, and 100B. However, the present invention is not limited to this. The internal circuit may be any circuit that may destroy the circuit element due to a malfunction caused by application of a surge.

  The electrode pad 201 is an example of an electrode pad in the present invention. The collection part 110, 110a-110d is an example of the collection part in this invention. The detection unit 120 is an example of the detection unit of the present invention. The voltage regulators 40 and 40A are examples of internal circuits in the present invention. The resistance element 121 is an example of a resistance element in the present invention.

DESCRIPTION OF SYMBOLS 10 Power supply terminal 11 Input / output terminal 20, 21 Surge protection element 30 Silicon substrate 40, 40A Voltage regulator 41 Reference voltage generation circuit 42 Amplifier circuit 42a Operation amplification circuit 43 Output circuit 43a Output terminal 44 Resistance voltage dividing circuit 100, 100A, 100B Control Circuit 110 Collection unit 120 Detection unit 121 Resistance element 124 Transistor 140 Selection unit 200 Semiconductor chip 201 Electrode pad

Claims (12)

At least one collection part for collecting electric charges diffusing inside the semiconductor substrate in response to a surge applied through the electrode pad;
A detection unit for detecting a current generated according to the charge collected by the collection unit;
An internal circuit that performs predetermined control when the current is detected by the detection unit;
A semiconductor device including: The semiconductor device according to claim 1, wherein the internal circuit includes a voltage regulator that controls an output voltage when the current is detected by the detection unit. The semiconductor device according to claim 2, wherein the voltage regulator is controlled such that an increase in the output voltage is suppressed when the current is detected by the detection unit. The semiconductor device according to claim 1, wherein the collection unit includes an n-type semiconductor formed on the semiconductor substrate. The detector is
A resistance element connected to the collecting portion and through which the current flows;
A transistor that turns on and off according to a voltage drop generated in the resistance element;
The semiconductor device according to claim 1, comprising: The semiconductor device according to claim 1, wherein the collection unit is provided between the electrode pad and the internal circuit. A plurality of collecting portions for collecting electric charges that diffuse inside the semiconductor substrate in response to a surge applied through the electrode pads;
7. The semiconductor device according to claim 1, wherein among the plurality of collection units, a collection unit that is a current detection target in the detection unit is configured to be selectable. 8. The semiconductor device according to claim 7, wherein the detection unit includes a variable resistance element to which the plurality of collection units are selectively connected. 9. The semiconductor device according to claim 7, wherein the plurality of collecting portions are provided at positions that are between the electrode pad and the internal circuit and at different distances from the electrode pad. Collects the electric charge that diffuses inside the semiconductor substrate in response to a surge applied through the electrode pad,
Detect the current generated according to the collected charge,
An internal circuit control method for controlling an internal circuit when the current is detected. The internal circuit is a voltage regulator;
The control method according to claim 10, wherein an output voltage of the voltage regulator is controlled when the current is detected. The control method according to claim 11, wherein when the current is detected, control is performed so as to suppress an increase in the output voltage of the voltage regulator.

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