JP2020145348A - Semiconductor device - Google Patents

Abstract

To prevent malfunctions due to parasitic elements.SOLUTION: A semiconductor device 31 includes, for example: an external terminal T1; an output element M1; a parasitic factor element D1; a first element Gon, in which a parasitic element configured to operate so as to turn on the output element M1 when a negative voltage is generated in the external terminal T1 is accompanied between the first element itself and the parasitic factor element D1; and a second element Goff, in which a parasitic element configured to operate so as to turn off the output element M1 when a negative voltage is generated in the external terminal T1 is accompanied between the second element itself and the parasitic factor element D1. At least one of the second elements Goff is formed closer to the parasitic factor element D1 compared with the first element Gon. That is, the distance between the parasitic factor element D1 and the second element Goff is shorter than the distance between the parasitic factor element D1 and the first element Gon.SELECTED DRAWING: Figure 4

Description

The inventions disclosed herein relate to semiconductor devices.

Conventionally, during the operation of a semiconductor device, a negative voltage may be generated at an external terminal of the semiconductor device due to a current applied from the outside of the device or an inductance component such as a coil or wiring.

As an example of the prior art related to the above, Patent Document 1 can be mentioned.

Japanese Unexamined Patent Publication No. 2015-29/251

When a negative voltage is generated at the external terminal of the semiconductor device, the parasitic element inside the device may operate. This parasitic element is an element that is not incorporated in the original circuit operation. Therefore, it causes an unexpected malfunction different from the original circuit operation, which may lead to a malfunction or destruction of the set on which the semiconductor device is mounted.

It is difficult to predict where the parasitic element will be formed inside the device, and even if the chip layout and circuit are devised, it is not easy to eliminate the formation of the parasitic element itself.

The invention disclosed in the present specification is an object of the present invention to provide a semiconductor device capable of preventing malfunction due to a parasitic element in view of the above-mentioned problems found by the inventors of the present application.

For example, the semiconductor device disclosed in the present specification includes an external terminal, an output element, a parasitic factor element, and a parasitic element that operates to turn on the output element when a negative voltage is generated in the external terminal. The first element in which the element is attached between itself and the parasitic factor element, and the parasitic element that operates to turn off the output element when a negative voltage is generated in the external terminal are itself and the parasitic factor element. It has a second element attached between the two elements, and at least one of the second elements is formed closer to the parasitic factor element than the first element (first configuration). There is.

In the semiconductor device having the first configuration, the first element may be surrounded by an element separation region connected to a low impedance node (second configuration).

Further, the semiconductor device having the first or second configuration forcibly forces the output element not only when it detects an abnormality to be monitored but also when a parasitic element attached to the second element operates. It is preferable to have a configuration (third configuration) further having an abnormality protection circuit that turns off.

Further, in the semiconductor device having the third configuration, the abnormality protection circuit may be an overcurrent protection circuit, an overheat protection circuit, or an overvoltage protection circuit (fourth configuration).

Further, in the semiconductor device having any of the first to fourth configurations, the first element and the second element are both constituent elements of the output drive unit that drives the output element (fifth element). Configuration) is recommended.

Further, in the semiconductor device having the fifth configuration, the output drive unit has a first current source and a second current source, the source is connected to the first current source, and the gate is connected to the first input end. The first PMOSFET has a source connected to the first current source and a gate connected to a second input terminal, and a source connected to the first end of the output element to have a gate and a drain. A third PMOSFET connected to the drain of the third PMOSFET, a fourth PMOSFET whose source is connected to the first end of the output element, a gate connected to the gate of the third PMOSFET, and a drain connected to the drain of the second PMOSFET, and a source. Is connected to the first end of the output element and the gate is connected to the gate of the third PMOSFET, and the source is connected to the first end of the output element and the gate is connected to the drain of the fourth PMOSFET. A sixth PMOSFET whose drain is connected to the control end of the output element, a first NMOSFET whose drain and gate are connected to the second current source and whose source is connected to the reference potential end, and a drain whose drain is the drain of the first PMOSFET. A second NMOSFET in which the gate is connected to the gate of the first NMOSFET and the source is connected to the reference potential end, and a drain is connected to the drain of the second PMOSFET and the gate is connected to the gate of the first NMOSFET. A third NMOSFET in which the source is connected to the reference potential end, a fourth NMOSFET in which the drain and gate are connected to the drain of the fifth PMOSFET and the source is connected to the reference potential end, and the drain is connected to the control end of the output element. A fifth NMOSFET whose gate is connected to the gate of the fourth NMOSFET and whose source is connected to a reference potential end, the third NMOSFET and the fourth NMOSFET are more parasitic elements than the second NMOSFET and the fifth NMOSFET. It is preferable to use a configuration (sixth configuration) formed near the.

Further, in the semiconductor device having the fifth configuration, the output drive unit has a first current source and a second current source, the source is connected to the first current source, and the gate is connected to the first input end. The first PMOSFET has a source connected to the first current source and a gate connected to a second input end, and a source connected to the first end of the output element to have a gate and a drain. A third PMOSFET connected to the drain of the third PMOSFET, a fourth PMOSFET whose source is connected to the first end of the output element, a gate connected to the gate of the third PMOSFET, and a drain connected to the drain of the second PMOSFET, and a source. Is connected to the first end of the output element and the gate is connected to the gate of the third PMOSFET, and the source is connected to the first end of the output element and the gate is connected to the drain of the fourth PMOSFET. A sixth PMOSFET whose drain is connected to the control end of the output element, a first NMOSFET whose drain and gate are connected to the second current source and whose source is connected to the reference potential end, and a gate whose gate is the first NMOSFET. The second NMOSFET and the third NMOSFET connected to the source connected to the reference potential end, the fourth NMOSFET connected to the drain and the gate in common and the source connected to the reference potential end, and the gate connected to the gate of the fourth NMOSFET. A fifth NMOSFET whose source is connected to the reference potential end, and a sixth NMOSFET whose drain is connected to the drain of the first PMOSFET and whose source is connected to the drain of the second NMOSFET and whose gate is connected to the constant potential end. A seventh NMOSFET in which the drain is connected to the drain of the second PMOSFET and the source is connected to the drain of the third NMOSFET and the gate is connected to the constant potential end, and the drain is connected to the drain of the fifth PMOSFET and the source is the first. The 8th N MOSFET connected to the drain of the 4N MOSFET and the gate connected to the constant potential end, and the drain connected to the control end of the output element and the source connected to the drain of the 5th N MOSFET and the gate connected to the constant potential end. The 7th N MOSFET and the 8th N MOSFET are formed closer to the parasitic factor element than the 6th N MOSFET and the 9th N MOSFET, and the 9th N MOSFET is included. The 1N MOSFET, the 2nd N MOSFET, the 3rd N MOSFET, the 4th N MOSFET, and the 5th N MOSFET are configured to be formed farther from the parasitic factor element than the 6th N MOSFET and the 9th N MOSFET (7th configuration). Good.

Further, in the semiconductor device having any of the first to seventh configurations, the parasitic factor element may be an electrostatic protection element connected to the external terminal (eighth configuration).

Further, the semiconductor device having the above-mentioned first to eighth configurations is connected to the input end of the input voltage so that the output voltage appearing at the external terminal or the feedback voltage corresponding thereto and the predetermined reference voltage match. It is preferable to have a configuration (nineth configuration) further including an output drive unit for driving the output element connected to the external terminal.

Further, for example, in the semiconductor device disclosed in the present specification, an external terminal, a parasitic factor element, and a parasitic element that operates so as to impede functional safety when a negative voltage is generated in the external terminal are themselves. A first element attached between the element and the parasitic element, and a parasitic element operating so as to contribute to functional safety when a negative voltage is generated in the external terminal are attached between the device and the parasitic element. The second element is provided, and at least one of the second elements is formed closer to the parasitic factor element than the first element (tenth configuration).

According to the semiconductor device disclosed in the present specification, it is possible to prevent malfunction due to a parasitic element.

The figure which shows the comparative example of the semiconductor device The figure which shows the vertical section of the semiconductor device The figure which shows the behavior when a negative voltage is generated in the comparative example. The figure which shows the 1st Embodiment of a semiconductor device The figure which shows the plane layout and the vertical section in 1st Embodiment The figure which shows the behavior when a negative voltage is generated in 1st Embodiment The figure which shows the 2nd Embodiment of a semiconductor device The figure which shows one modification of the plane layout in 2nd Embodiment The figure which shows the 3rd Embodiment of a semiconductor device. The figure which shows the 4th Embodiment of a semiconductor device. The figure which shows the plane layout and the vertical cross section in 4th Embodiment The figure which shows the 5th Embodiment of a semiconductor device.

<Semiconductor device (comparative example)>
First, before explaining a new embodiment of a semiconductor device, a comparative example to be compared with this will be briefly described.

FIG. 1 is a diagram showing a comparative example of a semiconductor device. The semiconductor device 100 of this comparative example is an LDO [low drop out] regulator IC that generates an output voltage VOUT from an input voltage VIN, and includes a P-channel type MOS [metal oxide semiconductor] field effect transistor M1 and resistors R1 and R2. It has an operational amplifier AMP, a Zena diode D1, an overcurrent protection circuit OCP, an overheat protection circuit TSD, and an external terminal T1 (= output terminal). Of course, the semiconductor device 100 may have other components.

The source of the transistor M1 is connected to the input end of the input voltage VIN. The drain of the transistor M1 is connected to the external terminal T1 (= the output end of each of the output voltage VOUT and the output current IOUT). The gate of the transistor M1 is connected to the output end (= application end of the gate signal G1) of the operational amplifier AMP. In this way, the transistor M1 is connected between the input end of the input voltage VIN and the output end of the output voltage VOUT, and its on-resistance value (extended) is increased according to the gate signal G1 applied from the operational amplifier AMP. Functions as an output element whose conductivity) is continuously controlled.

The resistors R1 and R2 are connected in series between the output end (= external terminal T1) of the output voltage VOUT and the ground end (= reference potential end), and the output voltage VOUT is divided from the connection nodes between them. It functions as a resistor divider circuit that outputs a feedback voltage Vfb (= VOUT × {R2 / (R1 + R2)}). When the output voltage VOUT is directly input to the operational amplifier AMP as the feedback voltage Vfb, the resistors R1 and R2 may be omitted.

The operational amplifier AMP has a gate signal of the transistor M1 so that the feedback voltage Vfb input to the non-inverting input end (+) and the predetermined reference voltage Vref input to the inverting input terminal (-) match (imaginary short). It functions as an output drive unit that continuously controls G1.

For example, when Vfb <Vref, the output voltage VOUT (and thus the feedback voltage Vfb) is raised by lowering the gate signal G1 and lowering the on-resistance value of the transistor M1 (= increasing the conductivity of the transistor M1). Can be done. On the contrary, when Vfb> Vref, the output voltage VOUT (and the feedback voltage Vfb) is lowered by raising the gate signal G1 and raising the on-resistance value of the transistor M1 (= lowering the conductivity of the transistor M1). be able to.

In this way, the output voltage VOUT can be adjusted to the target value (= Vref × {(R1 + R2) / R2}) by the output feedback control using the operational amplifier AMP.

The cathode of the Zener diode D1 is connected to the output end (= external terminal T1) of the output voltage VOUT. The anode of the Zener diode D1 is connected to the ground end. The Zener diode D1 functions as an electrostatic protection element for protecting the external terminal T1 from electrostatic discharge (ESD [electro-static discharge]). Therefore, it is desirable that the Zener diode D1 is provided in the vicinity of the external terminal T1.

The overcurrent protection circuit OCP controls the operational amplifier AMP so as to forcibly pull up the gate signal G1 and close the transistor M1 when the input current IIN flowing through the transistor M1 becomes larger than the overcurrent protection value IOCP. Therefore, as long as the overcurrent protection circuit OCP is operating correctly, the input current IIN can be limited to the overcurrent protection value IOCP or less.

The superheat protection circuit TSD controls the operational amplifier AMP so as to forcibly pull up the gate signal G1 and close the transistor M1 when the junction temperature Tj of the semiconductor device 100 becomes higher than the superheat protection value Ttsd. Therefore, as long as the superheat protection circuit TSD is operating correctly, the junction temperature Tj of the semiconductor device 100 can be limited to the superheat protection value Ttsd or less.

By the way, the semiconductor device 100 is accompanied by a parasitic element (for example, an npn-type bipolar transistor Q0, which is hereinafter referred to as a parasitic transistor Q0) that is not incorporated in the original circuit operation due to its device structure.

According to this figure, the parasitic transistor Q0 is based on a P-type semiconductor substrate (Psub), has an N-type semiconductor region (= cathode) of the Zena diode D1 as an emitter, and has an N-type semiconductor region (for example, a cathode) of an internal circuit. , The drain of the N-channel type MOS field effect transistor M2 connected to the gate of the transistor M1 as the output stage of the operational capacitor AMP) is formed as a collector. Hereinafter, the description of the parasitic transistor Q0 will be continued with reference to a schematic vertical cross section of the semiconductor device 100.

FIG. 2 is a diagram showing a vertical cross section of the semiconductor device 100. N-type semiconductor wells 102 and 103 are formed on the P-type semiconductor substrate 101 of the semiconductor device 100. An N-type semiconductor contact 104 is formed in the N-type semiconductor well 102. N-type semiconductor contacts 105 and 106 are formed in the N-type semiconductor well 103. Further, a P-type semiconductor well 107 is formed in the N-type semiconductor well 103. A P-type semiconductor contact 108 is formed in the P-type semiconductor well 107.

The N-type semiconductor well 102 is an N-type semiconductor region for forming an internal circuit (NMOS, MOSFET, npn, pnp, etc.), and the drain of the transistor M2 in FIG. 1 corresponds to this. The N-type semiconductor well 102 is connected to another internal circuit (for example, the gate of the transistor M1 in FIG. 1) via the N-type semiconductor contact 104.

The N-type semiconductor well 103 is an N-type semiconductor region for forming an electrostatic protection element, and the cathode of the Zener diode D1 in FIG. 1 corresponds to this, for example. The N-type semiconductor well 103 is connected to the external terminal T1 via the N-type semiconductor contacts 105 and 106.

The P-type semiconductor well 107 is a P-type semiconductor region for forming an electrostatic protection element, and the anode of the Zener diode D1 in FIG. 1 corresponds to this, for example. The P-type semiconductor well 107 is connected to the ground end via the P-type semiconductor contact 108.

In the semiconductor device 100 having the above device structure, the parasitic transistor Q0 is based on the P-type semiconductor substrate 101, and uses the N-type semiconductor well 103 or the N-type semiconductor contacts 105 and 106 (= cathode of the Zena diode D1) as emitters. It is formed as an npn-type bipolar transistor having an N-type semiconductor well 102 or an N-type semiconductor contact 104 (= drain of the transistor M2) as a collector.

In the semiconductor device 100 accompanied by such a parasitic transistor Q0, for example, when an output current IOUT larger than the overcurrent protection value IOCP is drawn from the external terminal T1, the output current IOUT is drawn from the ground end to the external terminal T1 via the Zener diode D1. A directed forward diode current IDi (= IOUT-IOCP) flows. Therefore, a negative voltage (= −Vf (D1)) corresponding to the forward voltage drop Vf (D1) of the Zener diode D1 is generated at the external terminal T1.

When a potential difference of more than the forward voltage drop Vf (Q0) occurs between the base and emitter of the parasitic transistor Q0 due to the generation of the negative voltage, the parasitic transistor Q0 is turned on and the drain of the transistor M2 (and the gate of the transistor M1) is turned on. ), The current is drawn. As a result, contrary to the gate control of the operational amplifier AMP, the transistor M1 may be erroneously turned on, which may lead to malfunction or destruction of the set on which the semiconductor device 100 is mounted.

In addition to the electrostatic protection element (for example, Zener diode D1), the parasitic factor element that is connected to the external terminal T1 where a negative voltage can be generated and causes the parasitic transistor Q0 includes an N-channel type MOS field effect transistor and the like. Can be mentioned.

Hereinafter, the behavior of the external terminal T1 when a negative voltage is generated will be specifically described with reference to the drawings.

FIG. 3 is a diagram showing the behavior when a negative voltage is generated in the comparative example. In order from the top, each of the output voltage VOUT, the input current IIN, the diode current IDi, and the lost power Plus is correlated with the output current IOUT. The relationship is depicted.

The period (1) corresponds to the normal operation period of the semiconductor device 100. That is, in the period (1), no negative voltage is generated in the external terminal T1 and the parasitic transistor Q0 is not turned on. Further, when the input current IIN reaches the overcurrent protection value IOCP, the overcurrent protection circuit OCP operates so that no more current flows. Therefore, basically, the input current IIN does not flow beyond the overcurrent protection value IOCP. In the period (1), the lost power Plus determined by P1 = (VIN-VOUT) × IOUT is generated.

The period (2) corresponds to the current limiting period by the overcurrent protection circuit OCP. When an inductance component is present in the external terminal T1 or a forced load test is performed, an output current IOUT larger than the overcurrent protection value IOCP may be drawn from the external terminal T1. At this time, since the input current IIN is limited to the overcurrent protection value IOCP, the insufficient current flows as the diode current IDi. As a result, a negative voltage (= −Vf (D1)) corresponding to the forward voltage drop Vf (D1) of the Zener diode D1 is generated at the external terminal T1. However, in the period (2), Vf (D1) <Vf (Q0) is still satisfied, and the parasitic transistor Q0 does not turn on. Therefore, in the period (2), the power loss loss determined by P2 = (VIN + Vf (D1)) × IOCP + Vf (D1) × (IOUT-IOCP) is generated.

The length of the period (2) is determined by the layout of the semiconductor device 100, the internal circuit, the impedance, and the like. The parasitic element (for example, the parasitic transistor Q0) may cause the internal circuit to malfunction immediately after the generation of the negative voltage, or the parasitic element may not cause the malfunction.

The period (3) corresponds to a malfunction period due to the parasitic element. When a negative voltage (= −Vf (D1)) is generated, a potential difference of more than the forward voltage drop Vf (Q0) occurs between the base and emitter of the parasitic transistor Q0 and the parasitic transistor Q0 is turned on, the internal circuit malfunctions.

For example, consider the case where the drain of the transistor M2 forming the output stage of the operational amplifier AMP becomes the collector of the parasitic transistor Q0, as shown in FIG. 1 above. In this case, a collector current (for example, mA order) that is much larger than the off current (for example, μA order) that the overcurrent protection circuit OCP (or overheat protection circuit TSD) is flowing into the gate of the transistor M1 is parasitic from the gate of the transistor M1. It can be pulled out by transistor Q0.

In such a situation, the overcurrent protection circuit OCP cannot maintain the gate signal G1 at a high level, and the transistor M1 is erroneously turned on. As a result, the input current IIN (and thus the output current IOUT) increases beyond the overcurrent protection value IOCP, which may lead to the destruction of the semiconductor device 100 and the set on which the semiconductor device 100 is mounted.

In the period (3), the power loss loss determined by P3 = (VIN + Vf (D1)) × (IOUT-Idi) + Vf (D1) × IDi is generated. That is, the higher the input voltage VIN, the larger the power loss loss, and the higher the possibility that the semiconductor device 100 and the set on which the semiconductor device 100 is mounted will be destroyed.

Hereinafter, various embodiments that can solve the above-mentioned problems will be described.

<Semiconductor device (first embodiment)>
FIG. 4 is a diagram showing a first embodiment of the semiconductor device. The semiconductor device 31 of the present embodiment is based on the above-mentioned comparative example (FIG. 1), and the layout of the elements forming the operational amplifier AMP has been devised.

The elements forming the operational amplifier AMP can be roughly classified into an on-related element Gon (= corresponding to the first element) and an off-related element Goff (= corresponding to the second element).

The on-related element Gon is an element (NMOS, MOSFET, npn,) in which a parasitic element that operates to turn on the transistor M1 when a negative voltage is generated in the external terminal T1 is attached between itself and the cathode of the Zener diode D1. pnp, etc.), for example, the transistor M2 in FIG. 1 corresponds to this.

Therefore, when a negative voltage is generated in the external terminal T1, if the parasitic element attached to the on-related element Gon draws a current, the operational amplifier AMP malfunctions so that the transistor M1 turns on, so that the semiconductor device 31 and this There is a risk of destroying the set equipped with.

On the other hand, in the off-related element Goff, a parasitic element (see the parasitic transistor Q0 in this figure) that operates to turn off the transistor M1 when a negative voltage is generated in the external terminal T1 is formed between itself and the cathode of the Zener diode D1. Elements that accompany it (NMOS, MOSFET, npn, pnp, etc.).

Therefore, when a negative voltage is generated in the external terminal T1, if a parasitic element attached to the off-related element Goff draws a current, the operational amplifier AMP malfunctions so that the transistor M1 turns off (= contributes to the functional safety of the semiconductor device 31). Since the fail-safe operation) occurs, there is no risk of damaging the semiconductor device 31 or the set on which the semiconductor device 31 is mounted.

The current flowing through the parasitic element basically depends on the mutual distance between the N-type semiconductor region corresponding to the emitter and the N-type semiconductor region corresponding to the collector.

For example, the parasitic transistor Q0 in this figure can draw a current by using the N-type semiconductor region formed at various places on the P-type semiconductor substrate as a collector, but in reality, the emitter of the parasitic transistor Q0 (= Zena diode D1) From the viewpoint of the cathode of the N-type semiconductor region, the current is drawn in faster and larger in order from the N-type semiconductor region.

In view of the above findings, at least one of the off-related elements Goff is formed closer to the cathode of the Zener diode D1 than the on-related element Gon. In other words, the distance between the Zener diode D1 and the off-related element Goff is shorter than the distance between the Zener diode D1 and the on-related element Gon. If such an arrangement layout is adopted, even if a negative voltage is generated at the external terminal T1 and the parasitic transistor Q0 operates, the operational amplifier AMP malfunctions (fail-safe operation) so that the transistor M1 turns off. It is not necessary to cause the destruction of the device 31 and the set on which the device 31 is mounted.

In the following, the description of the on-related element Gon and the off-related element Goff will be continued with reference to the schematic planar layout and vertical cross section of the semiconductor device 31.

FIG. 5 is a diagram showing a planar layout (upper row) and a vertical cross section (lower row) of the semiconductor device 31. As shown in this figure, a plurality of element forming regions (in this figure, three element forming regions 310, 320, and 330 are exemplified) are formed in the P-type semiconductor substrate 300 of the semiconductor device 31.

The element forming region 310 corresponds to the forming region of the electrostatic protection element (for example, the Zener diode D1). In the element forming region 310, an N-type semiconductor well 311 is formed on the P-type semiconductor substrate 300. N-type semiconductor contacts 312 and 313 are formed in the N-type semiconductor well 311. Further, a P-type semiconductor well 314 is formed in the N-type semiconductor well 311. A P-type semiconductor contact 315 is formed in the P-type semiconductor well 314.

The N-type semiconductor well 311 corresponds to the cathode (C) of the Zener diode D1 and is connected to the external terminal T1 via the N-type semiconductor contacts 312 and 313. On the other hand, the P-type semiconductor well 314 corresponds to the anode (A) of the Zener diode D1 and is connected to the ground end via the P-type semiconductor contact 315.

The element forming region 320 corresponds to the forming region of the on-related element Gon (for example, NMOSFET). In the element forming region 320, the P-type semiconductor well 321 is formed on the P-type semiconductor substrate 300. A P-type semiconductor contact 322 is formed in the P-type semiconductor well 321. Further, N-type semiconductor regions 323 and 324 are formed in the P-type semiconductor well 321.

The N-type semiconductor regions 323 and 324 correspond to the source (S) and drain (D) of the on-related element Gon, and a gate (G) is formed on the channel region between them with an insulating layer interposed therebetween. ing. On the other hand, the P-type semiconductor well 321 and the P-type semiconductor contact 322 correspond to the back gate (BG) of the on-related element Gon.

The element forming region 330 corresponds to the forming region of the off-related element Goff (for example, NMOSFET). As shown in this figure, the element forming region 330 is arranged at a position closer to the element forming region 310 than the element forming region 320 (for example, between the element forming region 310 and the element forming region 320). .. In other words, the distance dx between the element forming region 310 and the element forming region 330 is shorter than the distance dy between the element forming region 310 and the element forming region 320.

In the element forming region 330, the P-type semiconductor well 331 is formed on the P-type semiconductor substrate 300. A P-type semiconductor contact 332 is formed in the P-type semiconductor well 331. Further, N-type semiconductor regions 333 and 334 are formed in the P-type semiconductor well 331.

The N-type semiconductor regions 333 and 334 correspond to the source (S) and drain (D) of the off-related element Goff, and a gate (G) is formed on the channel region between them with an insulating layer interposed therebetween. ing. On the other hand, the P-type semiconductor well 331 and the P-type semiconductor contact 332 correspond to the back gate (BG) of the off-related element Goff.

In the semiconductor device 31 having the above device structure, the parasitic transistor Q0 is based on, for example, the P-type semiconductor substrate 300, and uses the N-type semiconductor well 311 and the N-type semiconductor contacts 312 and 313 (= cathode of the Zena diode D1) as emitters. , N-type semiconductor region 334 closest to this (= drain of off-related element Goff) is formed as an npn-type bipolar transistor as a collector.

In the semiconductor device 31 accompanied by such a parasitic transistor Q0, for example, when an output current IOUT larger than the overcurrent protection value IOCP is drawn from the external terminal T1, the output current IOUT is drawn from the ground end to the external terminal T1 via the Zener diode D1. A directed forward diode current IDi (= IOUT-IOCP) flows. Therefore, a negative voltage (= −Vf (D1)) corresponding to the forward voltage drop Vf (D1) of the Zener diode D1 is generated at the external terminal T1.

When the generation of the negative voltage causes a potential difference of the forward voltage drop Vf (Q0) or more between the base and the emitter of the parasitic transistor Q0, the parasitic transistor Q0 is turned on. At this time, the parasitic transistor Q0 draws a current by using the N-type semiconductor region existing closer to the emitter as a collector when viewed from the N-type semiconductor region (= N-type semiconductor well 311 and N-type semiconductor contacts 312 and 313). start.

According to this figure, the parasitic transistor Q0 has a drain (= N-type semiconductor region) of the off-related element Goff before starting to draw a current from the drain (= N-type semiconductor region 324) of the on-related element Gon. Start drawing current from 334). As a result, the transistor M1 is turned off by the fail-safe operation of the operational amplifier AMP. Hereinafter, the behavior when such a negative voltage is generated will be specifically described with reference to the drawings.

FIG. 6 is a diagram showing the behavior when a negative voltage is generated in the first embodiment, and as in FIG. 3 above, the output voltage VOUT, the input current IIN, the diode current IDi, and the lost power Pass are arranged in this order from the top. For each, the correlation with the output current IOUT is depicted.

The period (1) corresponds to the normal operation period of the semiconductor device 31. That is, in the period (1), since no negative voltage is generated in the external terminal T1 and the parasitic transistor Q0 is not turned on, the drive control of the transistor M1 by the operational amplifier AMP is performed as usual. In the period (1), the lost power Plus determined by P1 = (VIN-VOUT) × IOUT is generated. As described above, the normal operation period of the semiconductor device 31 is no different from that of the above-mentioned comparative example (see FIG. 3).

The period (2) corresponds to the current limiting period by the overcurrent protection circuit OCP. As described above, when an inductance component is present in the external terminal T1 or when a forced load test is performed, an output current IOUT larger than the overcurrent protection value IOCP may be drawn from the external terminal T1. At this time, since the input current IIN is limited to the overcurrent protection value IOCP, the insufficient current flows as the diode current IDi. As a result, a negative voltage (= −Vf (D1)) corresponding to the forward voltage drop Vf (D1) of the Zener diode D1 is generated at the external terminal T1. However, in the period (2), Vf (D1) <Vf (Q0) is still satisfied, and the parasitic transistor Q0 does not turn on. Therefore, in the period (2), the power loss loss determined by P2 = (VIN + Vf (D1)) × IOCP + Vf (D1) × (IOUT-IOCP) is generated.

As described above, the current limiting period by the overcurrent protection circuit OCP is basically the same as that of the above-mentioned comparative example (FIG. 3). However, the timing at which the parasitic transistor Q0 starts drawing a current from the drain of the off-related element Goff is earlier than the timing at which the parasitic transistor Q0 starts drawing a current from the drain of the on-related element Gon (for example, the transistor M2). Therefore, the length of the period (2) is shorter than that of the previous comparative example (see FIG. 3).

The period (3) corresponds to the output off period due to the parasitic operation. When the output voltage OUT further decreases negatively as the diode current IDi increases and a potential difference of the forward voltage drop voltage Vf (Q0) or more occurs between the base and emitter of the parasitic transistor Q0, the parasitic transistor Q0 is off-related. Start drawing current from the drain of the element Goff. As a result, the transistor M1 is turned off by the fail-safe operation of the operational amplifier AMP, so that the input current IIN is cut off.

In the period (3), since the output current IOUT drawn from the external terminal T1 is entirely covered by the diode current IDi, it is determined by P3 = Vf (D1) × IOUT, unlike the previous comparative example (FIG. 3). Only the lost power Pass is generated. In other words, the lost power Pass does not depend on the input voltage VIN.

Therefore, even when the input voltage VIN is high, the forward voltage drop Vf (D1) of the Zener diode D1 is low, so that the power loss loss can be suppressed to a small value, and the semiconductor device 31 or a set equipped with the semiconductor device 31 can be suppressed. It is possible to prevent the destruction of the diode.

<Semiconductor device (second embodiment)>
FIG. 7 is a diagram showing a second embodiment of the semiconductor device (upper row: planar layout, lower row: vertical cross section). The semiconductor device 32 of the present embodiment is based on the first embodiment (FIGS. 4 and 5), and has an on-related element Gon having a floating structure.

Specifically, in the element forming region 320 in which the on-related element Gon is formed, the N-type semiconductor well 325 (= element) so as to include the P-type semiconductor well 321 described above in the P-type semiconductor substrate 300. (Corresponding to the separation region) is formed. The N-type semiconductor well 325 is connected to a low impedance node (for example, a power supply) via an N-type semiconductor contact 326. That is, the on-related element Gon is surrounded by an element separation region connected to the low impedance node.

By adopting such a device structure, the parasitic transistor Q0 draws current preferentially from the low impedance node over the drain of the on-related element Gon. Therefore, since it is possible to more reliably prevent the transistor M1 from being erroneously turned on, it is possible to improve the safety of the semiconductor device 32 and the set on which the transistor M1 is mounted.

Since the behavior when a negative voltage is generated in the second embodiment is exactly the same as that in the first embodiment (FIG. 6), a duplicate description is omitted.

FIG. 8 is a diagram showing a modified example of the plane layout in the second embodiment. As shown in this figure, for example, consider a case where the on-related elements Gon1 and Gon2 are dispersedly arranged in a plurality of directions when viewed from the Zener diode D1. In such a case, the off-related elements Goff1 and Goff2 may be formed between the Zener diode D1 and the on-related element Gon1 and between the Zener diode D1 and the on-related element Gon2, respectively.

As a result, the distance dx1 between the Zener diode D1 and the off-related element Goff1 and the distance dx2 between the Zener diode D1 and the off-related element Goff2 are the distance dy1 between the Zener diode D1 and the on-related element Gon1 and the Zener, respectively. The distance between the diode D1 and the on-related element Gon2 is shorter than the distance dy2.

Further, as described above, the on-related elements Gon1 and Gon2 are each floating by being surrounded by an element separation region (N-type semiconductor region) connected to a low impedance node (for example, an external terminal T2 connected to a power supply). It should be set as a structure.

By adopting such a device structure, when a negative voltage is generated in the external terminal T1, the parasitic element attached between the cathode of the Zener diode D1 and the drains of the off-related elements Goff1 and Goff2 is turned on first. Therefore, it is possible to more reliably prevent the transistor M1 from being erroneously turned on.

<Semiconductor device (third embodiment)>
FIG. 9 is a diagram showing a third embodiment of the semiconductor device (upper row: planar layout, lower row: vertical cross section). The semiconductor device 33 of the present embodiment is based on the first embodiment (FIG. 4) or the second embodiment (FIG. 7) described above, and is abnormal when the parasitic element associated with the off-related element Goff operates. The transistor M1 is forcibly turned off via a protection circuit (for example, an overheat protection circuit TSD). In this case, the off-related element Goff may be understood as a component of the abnormality protection circuit, not as a component of the operational amplifier AMP.

For example, in the element forming region 330 in which the off-related element Goff (npn-type bipolar transistor in this figure) is formed, the N-type semiconductor well 335 is formed on the P-type semiconductor substrate 300. An N-type semiconductor contact 336 is formed in the N-type semiconductor well 335. Further, a P-type semiconductor well 337 is formed in the N-type semiconductor well 335. A P-type semiconductor contact 338 and an N-type semiconductor region 339 are formed in the P-type semiconductor well 337.

The N-type semiconductor well 335 and the N-type semiconductor contact 336 correspond to the collector (C) of the off-related element Goff, and are connected to, for example, the overheat protection circuit TSD. On the other hand, the P-type semiconductor well 337 and the P-type semiconductor contact 338 correspond to the base (B) of the off-related element Goff. Further, the N-type semiconductor region 339 corresponds to the emitter (E) of the off-related element Goff.

In the semiconductor device 33 having the above device structure, the parasitic transistor Q0 is based on the P-type semiconductor substrate 300, and uses the N-type semiconductor well 311 and the N-type semiconductor contacts 312 and 313 (= cathode of the Zena diode D1) as emitters. It is formed as an npn-type bipolar transistor having an N-type semiconductor well 335 or an N-type semiconductor contact 336 (= collector of the off-related element Goff) as a collector.

The superheat protection circuit TSD forces the transistor M1 not only when the junction temperature Tj of the semiconductor device 33 becomes higher than the superheat protection value Ttsd, but also when the parasitic transistor Q0 associated with the off-related element Goff operates. It has a function to turn off the target.

As described above, the off-related element Goff to be arranged in the vicinity of the Zener diode D1 does not necessarily have to be a component of the operational amplifier AMP, and may be, for example, a component of the abnormality protection circuit.

Further, the abnormality protection circuit for forcibly turning off the transistor M1 is not limited to the overheat protection circuit TSD, and may be an overcurrent protection circuit OCP or an overvoltage protection circuit OVP. That is, the original monitoring is performed as long as the abnormality protection circuit has a function of forcibly turning off the transistor M1 not only when the abnormality to be monitored is detected by itself but also when the parasitic transistor Q0 is turned on. The target is unquestioned.

Since the behavior when a negative voltage is generated in the third embodiment is exactly the same as that in the first embodiment (FIG. 6), a duplicate description is omitted.

<Semiconductor device (fourth embodiment)>
FIG. 10 is a diagram showing a fourth embodiment of the semiconductor device. In the semiconductor device 34 of the present embodiment, a circuit configuration example of the operational amplifier AMP is specifically specified while being based on the first embodiment (FIG. 4) or the second embodiment (FIG. 7).

According to this figure, the operational amplifier AMP includes current sources CS1 and CS2, P-channel type MOS field effect transistors M11 to M16 (= corresponding to the first PMOSFET to the sixth PMOSFET), and an N-channel type MOS field effect transistor M21. ~ M25 (= corresponding to the first NMOSFET to the fifth NMOSFET) and the resistor R4 are included.

The sources of the transistors M11 and M12 are both connected to the current source CS1. The gate of the transistor M11 is connected to the input end (= corresponding to the first input end) of the reference voltage Vref as the inverting input end (−) of the operational amplifier AMP. The gate of the transistor M12 is connected to the input end (= corresponding to the second input end) of the feedback voltage Vfb as the non-inverting input end (+) of the operational amplifier AMP.

The sources of the transistors M13 to M16 are all connected to the source of the transistor M1. The gates of the transistors M13 to M15 are all connected to the drain of the transistor M13. The drain of the transistor M13 is connected to the drain of the transistor M11. The drain of the transistor M14 is connected to the drain of the transistor M12. The gate of the transistor M16 is connected to the drain of the transistor M14. The drain of the transistor M16 is connected to the gate of the transistor M1.

The sources of the transistors M21 to M25 are all connected to the ground end (= reference potential end). The gates of the transistors M21 to M23 are all connected to the drain of the transistor M21. The drain of the transistor M21 is connected to the current source CS2. The drain of the transistor M22 is connected to the drain of the transistor M11. The drain of the transistor M23 is connected to the drain of the transistor M12. The gates of the transistors M24 and M25 are both connected to the drain of the transistor M24. The drain of the transistor M24 is connected to the drain of the transistor M15. The drain of the transistor M25 is connected to the gate of the transistor M1.

The basic operation of the operational amplifier AMP having the above configuration will be briefly described. When Vfb <Vref, the drain current of the transistor M11 becomes relatively smaller than the drain current of the transistor M12. As a result, the drain current of the transistor M13 becomes large, so that the drain current of the transistor M14 mirroring the drain current also becomes large, and the gate voltage of the transistor M16 rises. Therefore, the on-resistance value of the transistor M16 becomes high. Further, as the drain current of the transistor M13 increases, the drain currents of the transistors M15 and M24 that mirror the transistors M13 also increase, so that the drain current of the transistor M25 that mirrors them also increases. Since the gate signal G1 of the transistor M1 is lowered by the above series of operations, the on-resistance value of the transistor M1 is lowered, and the output voltage VOUT (and the feedback voltage Vfb) is raised.

On the other hand, when Vfb> Vref, the drain current of the transistor M11 becomes relatively larger than the drain current of the transistor M12. As a result, the drain current of the transistor M13 becomes smaller, so that the drain current of the transistor M14 mirroring the drain current also becomes smaller, and the gate voltage of the transistor M16 decreases. Therefore, the on-resistance value of the transistor M16 becomes low. Further, when the drain current of the transistor M13 becomes small, the drain currents of the transistors M15 and M24 that mirror the transistors M13 also become small, so that the drain current of the transistor M25 that mirrors them also becomes small. Since the gate signal G1 of the transistor M1 rises by the above series of operations, the on-resistance value of the transistor M1 becomes high, and the output voltage VOUT (and thus the feedback voltage Vfb) is lowered.

By the way, in the operational amplifier AMP having the above configuration, for example, when a parasitic element (npn type bipolar transistor) attached between the drain of each of the transistors M25 or M22 and the cathode of the Zener diode D1 is turned on, the gate signal of the transistor M1 Since G1 is lowered, the transistor M1 may be erroneously turned on. That is, the transistors M25 and M22 correspond to the above-mentioned on-related element Gon.

On the other hand, when a parasitic element (npn type bipolar transistor) attached between the drain of each of the transistors M24 or M23 and the cathode of the Zener diode D1 is turned on, the gate signal G1 of the transistor M1 rises, so that the transistor M1 is particularly special. It is likely to turn off automatically without the need for control. That is, the transistors M24 and M23 correspond to the above-mentioned off-related element Goff.

Therefore, it is desirable that the transistors M23 and M24 are arranged closer to the Zener diode D1 than the transistors M22 and M25. Therefore, in the semiconductor device 34 of the present embodiment, the transistors M23 and M24 are arranged in the vicinity of the Zener diode D1, and the transistors M22 and M25 are arranged apart from the Zener diode D1. Hereinafter, a specific description will be given with reference to the drawings.

FIG. 11 is a diagram showing a planar layout (upper row) and a vertical cross section (lower row) of the semiconductor device 34. As shown in this figure, the semiconductor device 34 is based on the second embodiment (FIG. 7), and the element forming regions 320 and 330 have been modified.

As the first change, the N-type semiconductor regions 323a and 323b and the N-type semiconductor regions 324a and 324b are formed in the P-type semiconductor well 321. The N-type semiconductor regions 323a and 324a correspond to the source (S) and drain (D) of the transistor M22, and a gate (G) is formed on the channel region between them with an insulating layer interposed therebetween. The N-type semiconductor regions 323b and 324b correspond to the source (S) and drain (D) of the transistor M25, and a gate (G) is formed on the channel region between them with an insulating layer interposed therebetween. On the other hand, the P-type semiconductor well 321 and the P-type semiconductor contact 322 correspond to the back gates (BG) of the transistors M22 and M25, respectively.

As a second change, the P-type semiconductor well 331 is formed with N-type semiconductor regions 333a and 333b and N-type semiconductor regions 334a and 334b. The N-type semiconductor regions 333a and 334a correspond to the source (S) and drain (D) of the transistor M23, and a gate (G) is formed on the channel region between them with an insulating layer interposed therebetween. The N-type semiconductor regions 333b and 334b correspond to the source (S) and drain (D) of the transistor M24, and a gate (G) is formed on the channel region between them with an insulating layer interposed therebetween. On the other hand, the P-type semiconductor well 331 and the P-type semiconductor contact 332 correspond to the back gates (BG) of the transistors M23 and M24, respectively.

In the semiconductor device 34 having the above device structure, the parasitic transistor Q0 is based on, for example, the P-type semiconductor substrate 300, and uses the N-type semiconductor well 311 and the N-type semiconductor contacts 312 and 313 (= cathode of the Zena diode D1) as emitters. , N-type semiconductor regions 334a and 334b (= drains of transistors M23 and M24, respectively) closest to this are used as collectors to form npn-type bipolar transistors.

By adopting such a device structure, even if a negative voltage is generated in the external terminal T1 and the parasitic transistor Q0 operates, the operational amplifier AMP malfunctions (fail-safe operation) so that the transistor M1 turns off. , The semiconductor device 34 and the set on which the semiconductor device 34 is mounted are not destroyed.

<Semiconductor device (fifth embodiment)>
FIG. 12 is a diagram showing a fifth embodiment of the semiconductor device. The semiconductor device 35 of this embodiment is based on the fourth embodiment (FIG. 10), and corresponds to N-channel type MOS field effect transistors M26 to M29 (= 6th NMOSFETs to 9th NMOSFETs) as components of the operational amplifier AMP. ) Has been added. The changes will be mainly described below.

The transistor M26 is inserted between the drain of the transistor M13 and the drain of the transistor M22. Specifically, the drain of the transistor M26 is connected to the drain of the transistor M13. The source of the transistor M26 is connected to the drain of the transistor M22. The gate of the transistor M26 is connected to the application end (= corresponding to the constant potential end) of the clamp voltage Vclp (<VIN).

The transistor M27 is inserted between the drain of the transistor M14 and the drain of the transistor M23. Specifically, the drain of the transistor M27 is connected to the drain of the transistor M14. The source of the transistor M27 is connected to the drain of the transistor M23. The gate of the transistor M27 is connected to the application end of the clamp voltage Vclp.

The transistor M28 is inserted between the drain of the transistor M15 and the drain of the transistor M24. Specifically, the drain of the transistor M28 is connected to the drain of the transistor M15. The source of the transistor M28 is connected to the drain of the transistor M24. The gate of the transistor M28 is connected to the application end of the clamp voltage Vclp.

The transistor M29 is inserted between the drain of the transistor M16 and the drain of the transistor M25. Specifically, the drain of the transistor M29 is connected to the drain of the transistor M16. The source of the transistor M29 is connected to the drain of the transistor M25. The gate of the transistor M29 is connected to the application end of the clamp voltage Vclp.

By providing such transistors M26 to M29, the drain-source voltage of each of the transistors M21 to M25 can be limited to the clamp voltage Vclp or less. Therefore, as the transistors M21 to M25, a low withstand voltage element (= an element that can withstand the application of the clamp voltage Vclp) can be used, which is advantageous in ensuring the pairability of the current mirror. As the transistors M26 to M29, it is necessary to use a high withstand voltage element (= an element that can withstand the application of the input voltage VIN).

By the way, in the operational amplifier AMP having the above configuration, the transistors M25 and M22, as well as the transistors M29 and M26, correspond to the above-mentioned on-related element Gon. On the other hand, as the above-mentioned off-related element Goff, in addition to the transistors M24 and M23, the transistors M27 and M28 correspond to this.

Since the transistors M21 to M23 and the transistors M24 and M25 each form a current mirror, pairing with each other is important. On the other hand, for the transistors M26 to M29, the pairing between them is not so important.

Therefore, in the semiconductor device 35 of the present embodiment, the transistors M27 and M28 are arranged closer to the Zena diode D1 than the transistors M26 and M29, and the transistors M21 to M25 are arranged farther from the Zena diode D1 than the transistors M26 and M29. ing. By adopting such a device structure, it is possible to realize the above-mentioned fail-safe operation while maintaining the characteristics of the operational amplifier AMP.

In this way, it is not always necessary to arrange all of the plurality of off-related elements Goff (for example, transistors M23, M24, M27, M28) in the immediate vicinity of the Zener diode D1, and the need for pairing and the applicability of the floating structure are applicable. The layout may be optimized in consideration of the characteristics.

<Upper conceptualization>
In the first to fifth embodiments described so far, the arrangement layout of the elements has been devised so that the parasitic element that turns off the output element when a negative voltage is generated operates first, but the functional safety of the semiconductor device is improved. The contributing operation is not necessarily limited to turning off the output element, and naturally includes, for example, switching the error signal to the logic level at the time of abnormality and switching the enable signal to the logic level at the time of disabling. Is done. That is, the parasitic element that operates first when a negative voltage is generated may be any one that induces a fail-safe operation of the semiconductor device.

In view of this, the semiconductor device impedes functional safety when a negative voltage is generated in the external terminal (for example, the above-mentioned external terminal T1), the parasitic factor element (for example, the above-mentioned Zena diode D1), and the external terminal. The parasitic element that operates in the above operates so as to contribute to functional safety when a negative voltage is generated in the first element (for example, the on-related element Gon described above) attached between itself and the parasitic factor element and the external terminal. The parasitic element has a second element (for example, the above-mentioned off-related element Goff) attached between itself and the parasitic factor element, and at least one of the second elements is a parasitic factor element rather than the first element. It suffices if it is formed nearby, and it does not matter what the fail-safe operation is.

<Other variants>
In the above embodiment, an example of application to the LDO regulator IC has been given, but the application target is not limited to this. As described above, the various technical features disclosed in the present specification can be modified in addition to the above-described embodiment without departing from the spirit of the technical creation. That is, it should be considered that the above-described embodiment is exemplary in all respects and is not restrictive, and the technical scope of the present invention is not limited to the above-described embodiment, and claims for patent It should be understood that the meaning equivalent to the scope of and all changes belonging to the scope are included.

The invention disclosed in the present specification can be widely used in all semiconductor devices having a parasitic element.

31-35, 100 Semiconductor device 101 P-type semiconductor substrate 102, 103 N-type semiconductor well 104, 105, 106 N-type semiconductor contact 107 P-type semiconductor well 108 P-type semiconductor contact 300 P-type semiconductor substrate 310 Element formation region 311 N-type Semiconductor well 312, 313 N-type semiconductor contact 314 P-type semiconductor well 315 P-type semiconductor contact 320 Element formation area 321 P-type well 322 P-type semiconductor contact 323, 324 N-type semiconductor area 325 N-type semiconductor well (element separation area)
326 N-type semiconductor contact 330 Element formation area 331 P-type semiconductor well 332 P-type semiconductor contact 333, 334 N-type semiconductor area 335 N-type semiconductor well 336 N-type semiconductor contact 337 P-type semiconductor well 338 P-type semiconductor contact 339 N-type semiconductor Area AMP optotype (output drive unit)
CS1, CS2 Current source D1 Zener diode (electrostatic protection element, parasitic factor element)
Gon, Gon1, Gon2 on-related element (first element)
Goff, Goff1, Goff2 Off-related element (second element)
M1 P-channel type MOS field effect transistor (output element)
M2 N-channel type MOS field-effect transistor M11-M16 P-channel type MOS field-effect transistor M21-M29 N-channel type MOS field-effect transistor OCP overcurrent protection circuit Q0 npn type bipolar transistor (parasitic element)
R1, R2, R4 Resistor T1, T2 External terminal TSD Overheat protection circuit

Claims (10)

With external terminals
Output element and
Parasitic element and
A first element in which a parasitic element that operates to turn on the output element when a negative voltage is generated in the external terminal is attached between itself and the parasitic factor element, and
A second element in which a parasitic element that operates to turn off the output element when a negative voltage is generated in the external terminal is attached between itself and the parasitic factor element, and
Have,
A semiconductor device characterized in that at least one of the second elements is formed closer to the parasitic factor element than the first element. The semiconductor device according to claim 1, wherein the first element is surrounded by an element separation region connected to a low impedance node. The claim is further characterized by further having an abnormality protection circuit that forcibly turns off the output element not only when it detects an abnormality to be monitored but also when a parasitic element attached to the second element operates. 1 or the semiconductor device according to claim 2. The semiconductor device according to claim 3, wherein the abnormality protection circuit is an overcurrent protection circuit, an overheat protection circuit, or an overvoltage protection circuit. The semiconductor device according to any one of claims 1 to 4, wherein both the first element and the second element are constituent elements of an output drive unit that drives the output element. The output drive unit
The first current source and the second current source,
A first PMOSFET whose source is connected to the first current source and whose gate is connected to the first input end,
A second PMOSFET whose source is connected to the first current source and whose gate is connected to the second input end,
A third PMOSFET in which the source is connected to the first end of the output element and the gate and drain are connected to the drain of the first PMOSFET.
A fourth PMOSFET in which the source is connected to the first end of the output element, the gate is connected to the gate of the third PMOSFET, and the drain is connected to the drain of the second PMOSFET.
A fifth PMOSFET whose source is connected to the first end of the output element and whose gate is connected to the gate of the third PMOSFET.
A sixth PMOSFET in which the source is connected to the first end of the output element, the gate is connected to the drain of the fourth PMOSFET, and the drain is connected to the control end of the output element.
A first NMOSFET in which the drain and gate are connected to the second current source and the source is connected to the reference potential end,
A second NMOSFET in which the drain is connected to the drain of the first PMOSFET, the gate is connected to the gate of the first NMOSFET, and the source is connected to the reference potential end.
A third NMOSFET with a drain connected to the drain of the second PMOSFET, a gate connected to the gate of the first NMOSFET, and a source connected to the reference potential end.
A fourth NMOSFET in which the drain and gate are connected to the drain of the fifth PMOSFET and the source is connected to the reference potential end,
A fifth NMOSFET in which the drain is connected to the control end of the output element, the gate is connected to the gate of the fourth NMOSFET, and the source is connected to the reference potential end.
Including
The semiconductor device according to claim 5, wherein the third N MOSFET and the fourth N MOSFET are formed closer to the parasitic factor element than the second N MOSFET and the fifth N MOSFET. The output drive unit
The first current source and the second current source,
A first PMOSFET whose source is connected to the first current source and whose gate is connected to the first input end,
A second PMOSFET whose source is connected to the first current source and whose gate is connected to the second input end,
A third PMOSFET in which the source is connected to the first end of the output element and the gate and drain are connected to the drain of the first PMOSFET.
A fourth PMOSFET in which the source is connected to the first end of the output element, the gate is connected to the gate of the third PMOSFET, and the drain is connected to the drain of the second PMOSFET.
A fifth PMOSFET whose source is connected to the first end of the output element and whose gate is connected to the gate of the third PMOSFET.
A sixth PMOSFET in which the source is connected to the first end of the output element, the gate is connected to the drain of the fourth PMOSFET, and the drain is connected to the control end of the output element.
A first NMOSFET in which the drain and gate are connected to the second current source and the source is connected to the reference potential end,
The second NMOSFET and the third NMOSFET in which the gate is connected to the gate of the first NMOSFET and the source is connected to the reference potential end,
The 4th NMOSFET with the drain and gate connected in common and the source connected to the reference potential end,
A fifth NMOSFET whose gate is connected to the gate of the fourth NMOSFET and whose source is connected to the reference potential end,
A sixth NMOSFET in which the drain is connected to the drain of the first PMOSFET, the source is connected to the drain of the second NMOSFET, and the gate is connected to the constant potential end.
A seventh NMOSFET in which the drain is connected to the drain of the second PMOSFET, the source is connected to the drain of the third NMOSFET, and the gate is connected to the constant potential end.
An eighth NMOSFET in which the drain is connected to the drain of the fifth PMOSFET, the source is connected to the drain of the fourth NMOSFET, and the gate is connected to the constant potential end.
A ninth NMOSFET in which the drain is connected to the control end of the output element, the source is connected to the drain of the fifth NMOSFET, and the gate is connected to the constant potential end.
Including
The 7th N MOSFET and the 8th N MOSFET are formed closer to the parasitic factor element than the 6th N MOSFET and the 9th N MOSFET.
A claim, wherein the first N MOSFET, the second N MOSFET, the third N MOSFET, the fourth N MOSFET, and the fifth N MOSFET are formed farther from the parasitic factor element than the sixth N MOSFET and the ninth N MOSFET. 5. The semiconductor device according to 5. The semiconductor device according to any one of claims 1 to 7, wherein the parasitic element is an electrostatic protection element connected to the external terminal. An output drive that drives the output element connected between the input end of the input voltage and the external terminal so that the output voltage appearing at the external terminal or the feedback voltage corresponding thereto and the predetermined reference voltage match. The semiconductor device according to any one of claims 1 to 8, further comprising a part. With external terminals
Parasitic element and
A first element in which a parasitic element that operates so as to impede functional safety when a negative voltage is generated in the external terminal is attached between itself and the parasitic factor element, and
A second element in which a parasitic element that operates so as to contribute to functional safety when a negative voltage is generated in the external terminal is attached between itself and the parasitic factor element, and
Have,
A semiconductor device characterized in that at least one of the second elements is formed closer to the parasitic factor element than the first element.

Images