JP2017010220A - Arbitration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform arbitration processing in a case of confliction of memory access at a batch.SOLUTION: The present invention relates to an arbitration circuit which comprises a CPU and a memory subordinate to the CPU, and arbitrates memory access by the processor where a plurality of devices accessing the memory through a common bus are connected, the arbitration circuit comprising: an arbitration part which arbitrates access to the common bus according to priority in a case of access conflict among a plurality of devices; a priority storage part which groups the plurality of devices and hold priority in arbitration among and in groups; and an arbitration control part which controls the arbitration processing and can set priority among and in the groups. The arbitration control part enables a plurality of arbitration processes to be performed at a batch by determining final priority based upon the priority set among and in the device groups when a plurality of devices make access requests.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an arbitration circuit that arbitrates memory access for a processor that includes a shared bus accessible to a memory and a plurality of devices that access the memory via the shared bus.

  In a processor having a CPU, a subordinate memory, and a shared bus, to which a plurality of devices accessing the memory via the shared bus are connected, generally, a DMA request from a plurality of DMA controllers is determined. Arbitration processing is performed in the priority order, and data transfer is executed. At this time, as a means of solving the problem that requests from the DMA controller having a high priority keep occupying the bus in the case of the fixed priority, the priority is circulated at a fixed rate such as weighted round robin. There is a way to mediate. The cyclic type priority setting is equal to the ratio of the bus bandwidth allocated to each DMA controller.

The fixed priority order and the cyclic arbitration have a problem that the more the number of DMA controllers connected to the bus, the more complicated the circuit for determining the priority order and the lower the degree of freedom in adjusting the bandwidth.
In order to solve this problem, a register for setting and holding the priority order is provided for the DMA controller as in Patent Document 1, and at the same time, a plurality of DMA controllers are divided into several groups and fixed priority order or cyclic type There is a technology for setting priorities, and it is possible to improve the flexibility of band adjustment.
In the arbitration circuit of Patent Document 1, it is possible to change, as an initial value, data indicating a priority order that is divided into a plurality of groups including a cyclic order group whose priority order is updated when access permission is issued and held in the priority order register. By obtaining a desired priority for each request source, it is possible to increase the degree of freedom in adjusting the bandwidth.

  The priorities described above are set in advance. Therefore, if the DMA access request characteristics (bus occupancy time in requests, cycle between requests, number of consecutive requests issued, etc.) are different in each of multiple DMA controllers, each performance is different from the bus bandwidth ratio by priority setting. There is a problem that the error becomes large. In order to solve this problem, a technique for notifying the accumulation state of the FIFO buffer in the DMA controller to the arbitration circuit as in Patent Document 2 and changing the priority order of access requests, as in Patent Document 3, There is a technique for changing the priority order of access requests in accordance with the compression / decompression rate processed by the image processing circuit in the controller, thereby enabling adjustment of a desired bus bandwidth.

In Patent Document 2, the access request issued from the functional block is buffered, the number of access requests stored in the buffer is notified, and the priority of the access requests is changed based on the storage state of the access requests. A memory control device that often controls access requests is realized.
In Patent Document 3, the memory control circuit acquires a compression rate of image data read in response to a request received from the image processing circuit, and changes a predetermined priority standard of the memory control circuit in accordance with the acquired compression rate. An object of the present invention is to improve printer performance in a printer controller with a small bus bandwidth.

JP 2007-52545 A JP 2007-323279 A JP 2004-284056 A

However, although Patent Document 1 describes priority processing within a group, although priority can be assigned to priority processing between groups, there is no description of a specific example thereof. In general, when the objects to be arbitrated are divided into a plurality of groups or when the arbitration has a multi-stage configuration, a plurality of arbitration circuits are required, and the circuit scale becomes large and complicated. It conflicts with the simplification and speeding up of a circuit.
Further, for example, in Patent Document 2, it is difficult to adjust the bandwidth by changing the priority when the FIFO buffer capacity in the DMA controller is small, and in Patent Document 3, it is difficult to adjust the bandwidth similarly when the width of the compression / decompression ratio is small. In addition, there is a problem that it is impossible to adjust the bandwidth with a DMA controller without a FIFO buffer or compression / decompression processing.

In one embodiment of the present invention, priority processing between groups is possible, and arbitration processing for determining priority order is performed in a batch, thereby improving both freedom of bandwidth adjustment and bandwidth efficiency and simplifying and speeding up the circuit. For the purpose of
Another object of the present invention is to define a common access request characteristic item possessed by a plurality of DMA controllers to enable bandwidth adjustment between the DMA controllers and to improve memory bandwidth efficiency.

Of the arbitration circuit of the present invention, the first aspect of the present invention is:
Arbitration for arbitrating memory access in a processor comprising a CPU, a memory subordinate to the CPU, and a shared bus accessible to the memory, to which a plurality of devices that access the memory via the shared bus are connected A circuit,
An arbitration unit that arbitrates access to the shared bus according to priority when access conflicts by the plurality of devices;
A priority storage unit that groups the plurality of devices and retains a priority between groups and within the group during arbitration;
An arbitration control unit that controls arbitration processing and can set priorities between the groups and within the groups;
The arbitration control unit determines a final priority based on a priority set between device groups and within a group when an access request is generated by a plurality of devices, and enables batch processing of a plurality of arbitrations. Features.

  In another embodiment of the arbitration circuit according to the present invention, the processor includes one or more DMA controllers.

  The arbitration circuit according to another aspect is characterized in that, in the present invention according to the aspect, the group is associated with the DMA controller.

  In another aspect of the arbitration circuit according to the present invention, the arbitration control unit performs a concatenation process on the bits with the priority between the groups as the upper bits and the priority within the group as the lower bits. The priority order is determined.

In another aspect of the arbitration circuit according to the present invention, the arbitration circuit includes an access request characteristic storage unit that holds access request characteristic information for the shared bus of the device,
The arbitration control unit can set the priority in arbitration according to the access request characteristic information, and determines the final priority based on the priority set / changed by each access request characteristic information when an access request is generated by a plurality of devices. Thus, it is possible to perform batch processing of a plurality of mediations.

In another form of the arbitration circuit according to the present invention, the arbitration control unit can receive notification of access request characteristic information for the shared bus of the device,
The arbitration control unit can set the priority in arbitration according to the access request characteristic information, and determines the final priority based on the priority set / changed by each access request characteristic information when an access request is generated by a plurality of devices. Thus, it is possible to perform batch processing of a plurality of mediations.

  In another aspect of the arbitration circuit according to the present invention, the arbitration control unit changes the priority in arbitration between groups and within a group according to access request characteristic information.

  The present invention enables priority processing between groups and can perform both arbitration processing for priority determination at the same time to improve both bandwidth adjustment freedom and bandwidth efficiency and simplify and speed up the circuit. Has the effect of

It is a figure which shows the control block of the arbitration circuit of one Embodiment of this invention, its peripheral processor, and a device. Similarly, it is a figure which shows the flow of an arbitration process. Similarly, it is a figure explaining the connection process which determines a final priority based on the priority between groups and the priority within a group. Similarly, it is a figure explaining the connection process which determines the final priority in an arbitration process according to access request characteristic information. FIG. 10 is a diagram illustrating a state in which an arbitration circuit receives notification of access request characteristic information from a DMA controller in another embodiment. FIG. 6 is a diagram illustrating a state processed according to access request characteristic information in an embodiment of the present invention. Similarly, it is a figure which shows the timing chart which performs a data process by continuous memory access in a device. In another form, it is a figure which shows the timing chart which performs a data process by continuous memory access in a device.

(Embodiment 1)
Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.
An embodiment of a processor to which the present invention is applied includes a CPU 1, a shared bus 2, and a memory 3 connected to the shared bus 2, and a plurality of devices 30 are connected to the shared bus 2. In this figure, a plurality of devices 30 are described as one block for convenience, but each device is composed of a plurality of devices that can make access requests. Examples of the device include those provided in an image forming apparatus. Examples of the device include various devices such as a scanner, a double-sided reading unit, an image processing unit, and a printer.

  Furthermore, a DMA controller is connected to the shared bus 2. In this embodiment, a first DMA controller 21, a second DMA controller 22, a third DMA controller 23, a fourth DMA controller 24, and a fifth DMA controller 25 are connected. Each DMA controller can receive an access request from a device. Each DMA controller is assigned one or more devices.

An arbitration circuit 10 is connected to the shared bus 2.
The arbitration circuit 10 includes an arbitration control unit 11 that controls arbitration processing, an arbitration unit 12 that arbitrates access to the shared bus 2 when there is an access conflict by a plurality of devices according to priority, and groups a plurality of devices between groups. And a register 13 that holds the priority order during arbitration within the group.
The arbitration control unit 11 can be configured by, for example, a CPU and a program that operates the CPU. The register 13 functions as a priority storage unit of the present invention.
The arbitration control unit 11 can set and change the priority order registered in the register 13.
In the initial setting of the priority order, for example, setting information may be installed, or the user may be able to input settings through the operation unit.

  In the register 13, for each device, an inter-group priority in the subordinate group, a device priority, an inter-group priority processing content, and an intra-group priority processing content are set and held.

Table 1 shows the setting contents held in the register 13. Groups A, B, and C are set as subordinate groups, and the inter-group priority processing of groups A, B, and C is set to fixed priority. For group A, the group priority is set to 2 and the intra-group priority process is set to a fixed priority.
In the group B, the group priority is set to 1, and the intra-group priority process is set to a fixed priority. Group C has a group priority of 3 and an intra-group priority process set to round robin.
Note that the higher the priority, the higher the priority. The same applies to the following.

For each device (in this embodiment, expressed as DMAC1 to DMAC5), a subordinate group and a device priority are set.
In the device of DMAC1, the subordinate group is A and the device priority is set to 1.
In the device of DMAC2, the subordinate group is B and the device priority is set to 1.
In the device of DMAC3, the subordinate group is B and the device priority is set to 2.
In the DMAC4 device, the subordinate group is C and the device priority is set to 3.
In the DMAC5 device, the subordinate group is C and the device priority is set to 1.

  The above-described groups and devices are shown as an example, and other groups and devices may exist. Moreover, a group and a device may be changed by changing the machine configuration.

Note that the arbitration control unit 11 determines the final priority based on the priorities set for the device groups and within the groups at the time of access conflict by devices, and enables batch processing of a plurality of mediations.
A processing flow by the arbitration control unit 11 is shown in FIG.
The access by the device is transmitted to the first DMA controller 21 to the fifth DMA controller 25, the access request is transmitted to the arbitration circuit 10, and the access control unit 11 determines access contention (step s1).

In the arbitration control unit 11, inter-group arbitration (step s2) performed by reading the group priority from the register 13 and intra-group arbitration (step s3) performed by reading the intra-group priority from the register 13 are collectively processed. The
The final priority is determined by the batch processing, and the priority of the register 13 is updated (step s4). The arbitration control unit 11 instructs the arbitration unit 12 to perform arbitration processing. The arbitration unit 12 performs memory access arbitration in accordance with the priority order set in the register 13.

In the batch processing, the bit connection processing is performed with the group priority set to the upper bit side and the device priority set to the lower bit side. Furthermore, the final priority is determined by comparing the magnitudes of the results. By this method, priority processing between groups and priority processing within a group can be performed collectively. An example is shown in FIG.
In each device, the inter-group priority and the intra-group priority are connected. For example, in DMAC1, the inter-group priority 2'h2 and the intra-group priority 2'h1 are obtained. When these are concatenated, a value of 9 in decimal is obtained. By performing the same processing in each device, a result with the highest priority in DMAC4 and the lowest priority in DMAC2 is obtained.

(Embodiment 2)
Next, another mode for determining priority by referring to access request characteristic information will be described.
In this embodiment, access request characteristic information is held in the register 13. In this embodiment, the register 13 functions as an access request characteristic storage unit of the present invention. In the adjustment circuit 10, access request characteristic information may be held in a register other than the register 13.

In this embodiment, for each device set in the register 13, the setting contents of the subordinate group and the priority of each device are the same as in the above embodiment.
That is, groups A, B, and C are set as subordinate groups, and the inter-group priority process is set to fixed priority. Group A has group priority 2 and intra-group priority processing is set to fixed priority. Group B has group priority 1 and intra-group priority processing is set to fixed priority. Group C has group priority. The degree is 3 and the intra-group priority processing is set to round robin.

  In the DMAC1 device, the subordinate group is A and the device priority is set to 1. In the DMAC2 device, the subordinate group is B and the device priority is set to 1. In the DMAC3 device, the subordinate group is B. The device priority is set to 2, and in the DMAC4 device, the subordinate group is C and the device priority is set to 3, and in the DMAC5 device, the subordinate group is C and the device priority is set to 1.

Further, as the access request characteristic information, for each device, the number of continuous access processes, the priority during continuous access, the fallow cycle after continuous access, and the priority during fallow are set.
These setting contents may be registered in the register as an initial setting, may be installed as setting information, and may be set by the user through the operation unit or the like.

For example, for the device of DMAC1, the number of consecutive access processes is set to 1, the priority during continuous access is set to 3, the fallow cycle after continuous access is set to 1, and the priority during fallow is set to 1.
For the DMAC2 device, the number of consecutive access processes is set to 4, the priority during continuous access is set to 3, the fallow cycle after continuous access is set to 10, and the priority during fallow is set to 1.

According to the access request characteristic information, the arbitration control unit 11 determines the final priority. An example will be described with reference to FIG.
First, when there is no access contention when an access request occurs and an access request for only DMAC2 occurs, the final priority order is determined based on the priority order set between device groups and within the group as shown in the upper part of FIG. Is done. In this example, the final priority is set to 5.

  On the other hand, when continuous processing is performed in the DMAC 2 based on the access request characteristics, the number of continuous processing is 4 as shown in Table 2, and therefore, as shown in the middle part of FIG. Further, the priority at the time of continuous access is changed to priority 3, and the priority is changed to 7 by the bit concatenation process. The changed priority is registered in the register 13.

Also, after the DMAC2 access is processed four times, during the fallow cycle of 10 cycles, the priority during fallowing is changed to 1 as shown in the lower part of FIG. Is changed to 5.
After the fallow cycle, the priority returns to the original priority, and the priority becomes 5 by the bit concatenation process, as shown in the bottom row of FIG.
In this example, the device priority of the DMAC 2 at normal time and the device priority at rest are the same numerical value, so the final priority is the same. However, the priorities are different from each other. The final priority will be different.

  In the above example, the access request characteristic information is stored in the register. However, the access request characteristic information is received from outside the arbitration circuit, for example, from the DMA controller, and the access request characteristic information is stored in the access request characteristic information. A corresponding arbitration process may be performed.

FIG. 5 is a block diagram illustrating an example of the change and a state in which the first DMA controller 21 notifies the arbitration circuit 10. The notification can be received by the arbitration control unit 11 of the arbitration circuit 10, for example.
In the above embodiment, in the arbitration circuit 10 that arbitrates DMA requests to a memory or the like by a plurality of devices, the request source is divided into a plurality of groups, and the priority order between the groups and the priority order within the group can be changed and batch processing is performed. The bandwidth efficiency can be improved by changing the priority in accordance with the characteristics such as the number of continuous accesses and the access cycle of the request source.

FIG. 6 is a block diagram illustrating a situation where access request characteristic information is given.
In the DMAC1, image data is input in units of pixels in the horizontal direction from the top, stored in a buffer for 4 lines, and then the array of image data is converted into units of 4 × 4 pixels and written out to a memory. is there.

  Specifically, in the DMAC 1, input is performed in units of one line (in the horizontal direction) in the image input unit, and then an array of image data is converted in units of 4 × 4 pixels by array conversion + buffer, and an image output unit Then, data is output from the memory to the shared bus in units of 4 × 4 pixels and transferred to the memory 3.

  In the DMAC2, image data arranged and stored in the memory in units of 4 × 4 pixels is read and stored in the buffer, and then image processing is performed in units of 4 × 4 pixels or 8 × 8 pixels. Alternatively, data is output in units of 8 × 8 pixels.

  Specifically, in the DMAC 2, data in units of pixels is input from the memory 3 to the image input unit, and then image processing is performed in units of 4 × 4 or 8 × 8 pixels by the image processing unit + buffer. The output unit outputs data in units of 4 × 4 or 8 × 8 pixels.

The above operation will be described with reference to timing charts of FIGS.
As shown in FIG. 7, in the DMAC1 operation example, the input image is input line by line according to the clock cycle. On the other hand, since an output image for memory access outputs an image for four lines, it has a continuous memory access period in which continuous access to the memory is performed, and a memory access fallow period between continuous accesses.

  For example, when the input image is 8000 pixels per line, data for four lines is stored. There are 2000 blocks of 4 × 4 units in the buffer. When 100 blocks are transferred by one write access to the memory, the number of continuous access requests is 20, which is an access request characteristic. Further, after the output of the 1st to 4th lines, there is a fallow period in which the image of the 5th to 8th lines is not accessed until the input is completed. This is also an access request characteristic. In the example of the above timing diagram, 16000 to 20000 clock cycles are fallow cycles, which are access request characteristics.

Also, as shown in FIG. 8, in the DMAC2 operation example, in the 4 × 4 image processing mode, in order to obtain 1 to 4 lines of pixel data by memory access, continuous memory access is performed to obtain 4 × 4 pixels. Input from the memory 3. During this continuous memory access period, there is a fallow period.
The image is output regardless of the memory access, and a 4 × 4 output image of 1 to 4 lines is output.
In the 4 × 4 image processing mode, one-time image processing can be performed by memory read access for one block. Therefore, the number of continuous memory accesses becomes the minimum value, and this is necessary when processing image processing all at once. It is an integral multiple of the minimum value. (Adjust the optimum value with the buffer size)

Further, in the 8 × 8 image output mode, the memory for the first to eighth lines is obtained from the memory 3 by continuous memory access depending on the number of 4 × 4 pixels. During this continuous memory access period, there is a fallow period.
The output of the image is an 8 × 8 output image of 1 to 8 lines regardless of the memory access.
In the 8 × 8 image processing mode, one-time image processing can be performed by memory read access for four blocks, so the number of consecutive memory accesses is a minimum of four times, and image processing is performed all at once as described above. Is an integer multiple of this minimum value.

  As described above, the present invention has been described based on the above embodiment, but appropriate modifications can be made to the embodiment without departing from the scope of the present invention.

1 CPU
2 Shared Bus 3 Memory 10 Arbitration Circuit 11 Arbitration Control Unit 12 Arbitration Unit 13 Register 21 First DMA Controller 22 Second DMA Controller 23 Third DMA Controller 24 Fourth DMA Controller 25 Fifth DMA Controller 30 Multiple Devices

Claims (7)

Arbitration for arbitrating memory access in a processor comprising a CPU, a memory subordinate to the CPU, and a shared bus accessible to the memory, to which a plurality of devices that access the memory via the shared bus are connected A circuit,
An arbitration unit that arbitrates access to the shared bus according to priority when access conflicts by the plurality of devices;
A priority storage unit that groups the plurality of devices and retains a priority between groups and within the group during arbitration;
An arbitration control unit that controls arbitration processing and can set priorities between the groups and within the groups;
The arbitration control unit determines a final priority based on a priority set between device groups and within a group when an access request is generated by a plurality of devices, and enables batch processing of a plurality of arbitrations. A characteristic arbitration circuit.   The arbitration circuit according to claim 1, wherein the processor includes one or more DMA controllers.   The arbitration circuit according to claim 1, wherein the group is associated with the DMA controller.   The arbitration control unit determines a final priority by concatenating the bits with the priority between the groups as an upper bit and the priority within the group as a lower bit. The arbitration circuit according to any one of the above. An access request characteristic storage unit for holding access request characteristic information for the shared bus of the device;
The arbitration control unit can set the priority in arbitration according to the access request characteristic information, and determines the final priority based on the priority set / changed by each access request characteristic information when an access request is generated by a plurality of devices. Then, the arbitration circuit according to any one of claims 1 to 4, which enables batch processing of a plurality of arbitrations. The arbitration control unit is capable of receiving notification of access request characteristic information for the shared bus of the device,
The arbitration control unit can set the priority in arbitration according to the access request characteristic information, and determines the final priority based on the priority set / changed by each access request characteristic information when an access request is generated by a plurality of devices. Then, the arbitration circuit according to any one of claims 1 to 5, which enables batch processing of a plurality of arbitrations.   7. The arbitration circuit according to claim 5, wherein the arbitration control unit changes priority in arbitration between groups and within a group based on access request characteristic information.

Images