JP4958596B2 - Arbitration device - Google Patents

Description

  The present invention relates to an arbitration device.

  The arbitration device arbitrates a plurality of shared resource use requests from a plurality of bus masters connected to a shared resource via a shared bus according to a predetermined priority, and shares the shared resource via the shared bus. The bus master to which the use permission is granted is determined. For example, an arbitration device is used when a plurality of CPUs (bus masters) use a common memory (shared resource) via a shared bus in a multiprocessor environment, or when a CPU (shared resource) and a plurality of peripheral devices are used for a system bus. Necessary when a plurality of peripheral devices use a CPU via a system bus, etc.

  FIG. 7 is a diagram showing a configuration of a conventional arbitration device 500. Arbitration device 500 arbitrates shared resource use requests REQ1 to REQn from N devices 20-1 to 20n assigned channel numbers CH1 to CHn, respectively, and grants the use permission of shared resource 10. . In the priority setting register 525, the priority is set in advance for each of the channel numbers CH1 to CHn. The arbitration device 500 arbitrates the shared resource use requests REQ1 to REQn as follows according to the priority set in the priority setting register 525.

  The request detection unit 510 receives the shared resource use requests REQ1 to REQn. The access request adjustment unit 520 adjusts the received shared resource use requests REQ1 to REQn, and writes the corresponding channel numbers CH1 to CHn in the queue register 530 according to the adjustment result. The queue register 530 is a FIFO (First In First Out) type shift register. The data Q1 stored in the uppermost unit of the queue register 530 represents the channel number to which access right is currently given to the shared resource 10, and is stored in order in units lower than the uppermost unit. Data Q2 to Qn represent standby channel numbers. The data Qn represents the channel number to which the nth processing waiting order is given.

  The bus acknowledge select unit 540 outputs the shared resource use permission ACK1 to ACKn to the devices 20-1 to 20-n corresponding to the data Q1 stored in the highest unit of the queue register 530. As a result, the devices 20-1 to 20-n that have received the shared resource use permission ACK 1 to ACKn can access the shared resource 10 via the shared bus 15.

  The access request adjustment unit 520 includes a request contention arbitration unit 5201 and a priority selection unit 5202 that perform processing using the priority set in the priority setting register 525. In principle, the access request adjustment unit 520 registers channel numbers in the queue register 530 in the order in which the shared resource use requests REQ1 to REQn are received. On the other hand, when a plurality of shared resource usage requests REQ1 to REQn are received simultaneously, that is, when a plurality of shared resource usage requests REQ1 to REQn compete, the request contention arbitration unit 5201 gives priority from the priority selection unit 5202. The channel numbers are registered in the queue register 530 in order of priority with reference to the data of the times. As a result, when a plurality of shared resource usage requests REQ1 to REQn compete, the access request adjustment unit 520 arbitrates the shared resource usage requests REQ1 to REQn according to a predetermined priority.

As described above, when a plurality of shared resource use request conflicts occur, the conventional arbitration device determines the priority before performing registration in the FIFO queue register. Furthermore, after a plurality of conflicting shared resource use requests are sorted in the order of the determined priority, registration is performed in order from the last column bit of the queue register.
JP 2004-302633 A

  By the way, in a conventional arbitration device, when it is attempted to implement priority determination and sorting in order of priority when a plurality of shared resource use request conflicts occur, increase in device scale or processing delay Therefore, it has been extremely difficult to realize.

  For example, the sorting processing of n pieces of data requires a huge amount of calculation such as O (square of n) in the case of a low-speed algorithm (such as bubble sort) and O (nlogn) in the case of a high-speed algorithm (such as quick sort). It is known that Therefore, in the arbitration device, when a processing for sorting a plurality of shared resource usage requests is to be realized by a digital circuit, the problem of an increase in circuit scale becomes significant. In addition, due to the enormous amount of calculation of the sorting process, it takes a lot of processing time from the reception of a plurality of competing shared resource use requests to the completion of all registration in the queue register. Therefore, if it is attempted to increase the frequency of the clock signal of the digital circuit, it is extremely difficult to execute a sorting process or the like and register it in the queue register within one machine cycle.

  Further, when registering a plurality of conflicting shared resource use requests in the queue register one by one in order of priority, it is necessary to provide a holding circuit for the remaining shared resource use requests waiting for registration in the queue register. is there. This holding circuit causes an increase in circuit scale. For example, if there are N bus masters, M (M ≦ N) shared resource use requests may occur simultaneously. At this time, if one shared resource use request with the highest priority is registered in the queue register, the remaining M-1 shares are shared until the registration of the remaining M-1 shared resource use requests is completed. A holding circuit for holding the resource use request is required. There is also a possibility that a maximum of NM conflicting shared resource usage requests may be generated until the registration of the remaining M-1 shared resource usage requests is completed. Therefore, a holding circuit for holding these newly competing shared resource use requests is required.

  A main aspect of the present invention for solving the above-described problem is that an arbitration apparatus that arbitrates shared resource use requests from a plurality of signal processing apparatuses connected to the shared resource, one to one with the plurality of signal processing apparatuses. A plurality of shift registers that register and store the shared resource use request, and a request selection unit that selects the shared resource use request registered in any one of the first bits of the plurality of shift registers; And a request permission unit that grants the use permission of the shared resource to the signal processing device that has issued the shared resource use request selected by the request selection unit.

  According to the present invention, it is possible to provide an arbitration device capable of operating at high speed while suppressing an increase in the device scale.

<< First Embodiment >>
=== Configuration of Arbitration Device ===
The configuration of the arbitration device 100 according to the first embodiment of the present invention will be described with reference to FIG.

  The arbitration device 100 arbitrates the shared resource use requests REQ1 to REQn from the N devices 20-1 to 20-n (bus masters) to which the channel numbers CH1 to CHn are assigned, respectively. It gives permission to use. The arbitration device 100 includes a request detection unit 110, a request registration unit 120, a FIFO register unit 130, a shift control unit 140, a priority setting unit 160, a request selection unit 170, and a request permission unit 180. These functions are realized using hardware.

  The request detection unit 110 accepts shared resource use requests REQ1 to REQn from the N devices 20-1 to 20-n. The shared resource use requests REQ1 to REQn are expressed, for example, as one pulse corresponding to one bit of “L” indicating that a request for using the shared resource 10 has been issued. The request detection unit 110 takes in the one pulse at the timing when the edge of the system clock CLK supplied from the shift control unit 140 is generated, and outputs the corresponding channel numbers CH1 to CHn as 1-bit “H”. That is, the request detection unit 110 has table information (not shown) in which the shared resource use requests REQ1 to REQn are associated with the channel numbers CH1 to CHn. Then, referring to the table information, the corresponding channel numbers CH1 to CHn are output as 1-bit “H”.

  The request registration unit 120 uses the channel numbers CH1 to CHn output from the request detection unit 110 to correspond to the FIFO registers in the FIFO register unit 130 according to the timing at which the edge of the system clock CLK supplied from the shift control unit 140 is generated. Output to 135-1 to 135-n.

  The FIFO register unit 130 has N FIFO registers 135-1 to 135-n corresponding to the N devices 20-1 to 20-n (N bus masters). That is, a FIFO register 135-1 is provided for the device 20-1, a FIFO register 135-2 is provided for the device 20-2, and a FIFO register 135-n is provided for the device 20-n. Thus, the devices 20-1 to 20-n and the FIFO registers 135-1 to 135-n have a one-to-one relationship.

  The FIFO registers 135-1 to 135-n embody a data structure called “queue (queue)” adopting a FIFO (First In First Out) system that outputs first from the first input data by hardware. It is a thing.

  Specifically, the FIFO registers 135-1 to 135-n use the channel numbers CH1 to CHn output from the request registration unit 120 at the timing when the edge of the system clock CLK supplied from the shift control unit 140 is generated. It is composed of an N-bit shift register that shifts from the last column bit LSB (Least Significant Bit) toward the first bit MSB (Most Significant Bit). The FIFO register unit 130 can hold a maximum of N channel numbers CH1 to CHn.

  The shift control unit 140 supplies a system clock CLK that controls the shift operation to each of the N FIFO registers 135-1 to 135-n. The system clock CLK is used as a clock that synchronizes the timing of hardware operations of all the arbitration devices 100 including the shift operation of the shift control unit 140.

  The priority setting unit 160 sets priorities for the shared resource use requests REQ1 to REQn in advance. In the case of this embodiment, a priority table in which priorities 1 to n are assigned to the first bits MSB1 to MSBn of the FIFO registers 135-1 to 135-n is used in preparation for the case where the shared resource use requests REQ1 to REQn compete. To set. Note that the priority n represents the nth priority.

  The request selection unit 170 selects shared resource use requests REQ1 to REQn that give permission to occupy the right to use the shared bus 15 based on the first bits MSB1 to MSBn of the FIFO registers 135-1 to 135-n. Specifically, among the first bits MSB1 to MSBn of the FIFO registers 135-1 to 135-n, the shared resource use requests REQ1 to REQn corresponding to the first bits MSB1 to MSBn indicating “H” are selected.

  When the shared resource use requests REQ1 to REQn compete, two or more first bits MSB1 to MSBn indicating “H” appear among the first bits MSB1 to MSBn of the FIFO registers 135-1 to 135-n. At this time, the request selection unit 170 selects the shared resource use requests REQ1 to REQn corresponding to the first bits MSB1 to MSBn indicating “H” according to the priorities 1 to n set in the priority setting unit 160.

  The request permission unit 180 grants the device 20-1 to 20-n corresponding to the shared resource use requests REQ1 to REQn selected by the request selection unit 170 with permission to occupy the right to use the shared resource 10 for a certain period. The resource use permission ACK1 to ACKn is output. As a result, the devices 20-1 to 20-n that have received the shared resource use permission ACK 1 to ACKn can access the shared resource 10 via the shared bus 15.

  The request permission unit 180 prohibits the shift control unit 140 from shifting the first bits MSB1 to MSBn of the FIFO registers 135-1 to 135-n while outputting the shared resource use permission ACK1 to ACKn. WAIT signal is output. This is because when the shared resource use requests REQ1 to REQn compete, it is necessary to hold them in the first bits MSB1 to MSBn until the shared resource use permission is given to all the shared resource use requests REQ1 to REQn. Specifically, when the WAIT signal is generated, the shift control unit 140 fixes the system clock CLK only in the registers corresponding to the first bits MSB1 to MSBn, or restricts data input from the previous register. realizable.

=== Operation of Arbitration Device ===
The operation of the arbitration device 100 will be described using a specific example shown in FIG.
In the specific example shown in FIG. 2, four devices 20-1, 20-2, 20-3, and 20-4 are connected to the shared resource 10 via the shared bus 15. Therefore, in this case, the FIFO register unit 130 corresponds to the four devices 20-1, 20-2, 20-3, 20-4, and the four FIFO registers 135-1, 135-2, 135-3, 135. -4. In addition, the priority of the shared resource use requests REQ1, REQ2, REQ3, and REQ4 generated by the four devices 20-1, 20-2, 20-3, and 20-4 is in order from the highest to the lowest REQ1, REQ2, REQ3, and REQ4 And

  2, “t1 to t12” represents one cycle of the system clock CLK, and “1 to 4” represented by REQ represents shared resources generated by the four devices 20-1 to 20-4. The use requests REQ1 to REQ4 are represented, and “1 to 4” shown in the SET represents channel numbers CH1 to CH4 registered in the four FIFO registers 135-1 to 135-4, and “1 to 4” shown in the ACK is 4 The shared resource use permission ACK1 to ACK4 indicating that permission has been given to the two apparatuses 20-1 to 20-4.

In the first cycle t1, a shared resource use request REQ2 is generated from the device 20-2.
In the second period t2, a shared resource use request REQ1 from the device 20-1 and a shared resource use request REQ3 from the device 20-3 are newly generated. Further, the channel number CH2 corresponding to the shared resource use request REQ2 generated in the first cycle t1 is stored in the last column bit LSB of the FIFO register 135-2.

  In the third period t3, the channel number CH2 corresponding to the shared resource use request REQ2 is shifted to the second bit from the last column bit LSB of the FIFO register 135-2. Further, channel numbers CH1 and CH3 corresponding to the shared resource use requests REQ1 and REQ3 generated in the second period t2 are stored in the last column bits LSB of the FIFO registers 135-1 and 135-3. At this time, the shared resource use requests REQ1 and REQ3 store the channel numbers CH1 and CH3 in the last column bits LSB of the FIFO registers 135-1 and 135-3 without determining the priority.

  In the fourth period t4, the channel number CH2 is shifted from the second bit to the third bit from the last column bit LSB of the FIFO register 135-2, and the channel numbers CH1 and CH3 are shifted to the FIFO registers 135-1 and 135-3. Shift from the last column bit LSB to the second bit.

  In the fifth period t5, the channel number CH2 is shifted from the third bit to the first bit MSB from the last column bit LSB of the FIFO register 135-2, and the channel numbers CH1 and CH3 are the last of the FIFO registers 135-1 and 135-3. The column bit LSB is shifted from the second bit to the third bit. In addition, a shared resource use request REQ4 is newly generated from the device 20-4. That is, the channel number CH2 is stored in the first bit MSB of the FIFO register 135-2 and is selected by the request selection unit 170.

  In the sixth period t6, the channel number CH2 selected by the request selection unit 170 is deleted from the FIFO register 135-2. Then, the request permission unit 180 outputs a shared resource use permission ACK2 to the device 20-2 that has generated the shared resource use request REQ2 corresponding to the channel number CH2. As a result, the device 20-2 is given permission to use the shared resource 10 via the shared bus 15. At this time, the channel numbers CH1 and CH3 are not shifted from the third bit to the first bit MSB from the last column bit LSB, respectively, and the channel numbers corresponding to the shared resource use request REQ4 generated at the fifth period t5 CH4 is stored in the last column bit LSB of the FIFO register 135-4. By not shifting the channel numbers CH1 and CH3, the request permission unit 180 can reliably output the shared resource use permission ACK2 to the device 20-2.

  In the seventh period t7, the channel numbers CH1 and CH3 are shifted from the third bit to the first bit MSB from the last column bit LSB of the FIFO registers 135-1 and 135-3, and the channel number CH4 is shifted from the last column bit LSB to the last column. Shift from bit LSB to second bit. Thereby, since the channel numbers CH1 and CH3 are stored in the first bit MSB of the FIFO registers 135-1 and 135-3, the request selection unit 170 selects the channel numbers CH1 and CH3 according to the priority. However, since the shared resource 10 is processing the device 20-2 at the time point of the seventh period t7, the request selection unit 170 does not select the channel number CH1 or the channel number CH3.

  In the eighth period t8, the channel numbers CH1 and CH3 are held in the last column bit LSB of the FIFO registers 135-1 and 135-3, and the channel number CH4 is the third bit from the second bit from the last column bit LSB. Shifted to bits. As for the channel numbers CH1 and CH3, as in the seventh period t7, since the shared resource 10 performs processing for the device 20-2, the request selection unit 170 sets the priority of the channel number CH1 or the channel number CH3. Do not select based on.

  In the ninth period t9, the shared resource 10 ends the process for the device 20-2. Thereby, the request selection unit 170 identifies that the shared resource use request REQ1 corresponding to the channel number CH1 and the shared resource use request REQ3 corresponding to the channel number CH3 are in conflict, and the channel number CH1 and the channel number CH3 are Among them, the channel number CH1 having a high priority is selected. At the time of the ninth period t9, since the channel number CH1 and the channel number CH3 are held in the first bit MSB, the channel number CH4 is not shifted from the third bit from the last column bit LSB to the first bit MSB, It is held in the third bit from the last column bit LSB.

  At the tenth cycle t10, the channel number CH1 selected by the request selection unit 170 is deleted from the FIFO register 135-1, and at the tenth cycle t10, a new shared resource use request REQ2 is generated from the device 20-2. To do. Then, the request permission unit 180 outputs a shared resource use permission ACK1 to the device 20-1 that has generated the shared resource use request REQ1 corresponding to the channel number CH1. As a result, the device 20-1 is given permission to use the shared resource 10 via the shared bus 15. The channel number CH3 is held in the first bit MSB, and the channel number CH4 is held in the third bit from the last column bit LSB.

  In the eleventh period t11, since the shared resource 10 performs processing for the device 20-1, the channel number CH3 is held in the first bit MSB, and the channel number CH4 is held in the third bit from the last column bit LSB. In addition, the channel number CH2 corresponding to the shared resource use request REQ2 is stored in the last column bit LSB of the FIFO register 135-2.

  In the twelfth cycle t12, the shared resource 10 ends the process for the device 20-1. Thereby, the request selection unit 170 selects the channel number CH3 stored in the first bit MSB.

  In the first embodiment, the arbitration device 100 receives the shared resource use requests REQ1 to REQn from a plurality of devices 20-1 to 20-n, and determines the priority without making a priority determination. Register. That is, in the arbitration device 100, unlike the conventional arbitration device 500 shown in FIG. 7, prior to registering the conflicting shared resource use requests REQ1 to REQn in the FIFO register unit 130, the priority is determined and based on the result. A hardware configuration for performing the sorting process becomes unnecessary. Thereby, the arbitration apparatus 100 can be configured while suppressing an increase in the scale of the apparatus.

  In the first embodiment, the priority determination of the conflicting shared resource use requests REQ1 to REQn is performed on the channel number stored in the first bit MSB of the FIFO registers 135-1 to 135-n by the request selection unit 170. , Based on a preset priority. Therefore, according to the first embodiment, when the shared resource use requests REQ1 to REQn compete with each other, it is possible to suitably determine the priorities thereof.

<<< Second Embodiment >>
=== Configuration of Arbitration Device ===
The configuration of the arbitration apparatus 200 according to the second embodiment of the present invention will be described with reference to FIG. In addition, the same code | symbol is attached | subjected about the thing of the same structure as the arbitration apparatus 100 concerning 1st Embodiment of this invention shown in FIG. 1, and description is abbreviate | omitted.

  In the arbitration device 200, unlike the arbitration device 100, an empty state monitoring unit 150 is provided. The empty state monitoring unit 150 determines whether or not the first empty state (all bits are all “L”) in which “H” data is not stored in all the bits (N × N bits) of the FIFO register unit 130. To monitor. When the first empty state is identified, the first EMPTY signal is output to the request registration unit 120.

  The empty state monitoring unit 150 includes an OR element 152 that calculates a logical sum of all bits (N × N bits) of the N FIFO registers 135-1 to 135-n, and outputs the OR element 152 to the first EMPTY. It can be a signal. When the first EMPTY signal is “L”, the FIFO register unit 130 is in the first empty state. On the other hand, when the first EMPTY signal is “H”, “H” data is stored in at least one bit of all the bits of the FIFO register unit 130, and the FIFO register unit 130 is in the first empty state. It means not.

  In the first embodiment, the request registration unit 120 stores the channel numbers CH1 to CHn output from the request detection unit 110 in the last column bits LSB of the FIFO registers 135-1 to 135-n. However, even if the FIFO register unit 130 is in the first empty state, if the channel numbers CH1 to CHn are stored in the last column bit LSB, the last time until the shared resource use requests REQ1 to REQn are permitted. There is a waiting time required to transfer from the column bit LSB to the first bit MSB.

  Therefore, the request registration unit 120 in the second embodiment receives the “L” first EMPTY signal from the availability monitoring unit 150, that is, when the request registration unit 120 is in the first availability state, the request detection unit 110. Are provided with switch circuits 122-1 to 122-n for storing the channel numbers CH1 to CHn output from the first bit MSB instead of the last column bit LSB.

  When the “L” first EMPTY signal is input from the empty state monitoring unit 150, the switch circuits 122-1 to 122-n use the channel numbers CH1 to CHn output from the request detection unit 110 as the first bits MSB. Store. On the other hand, when the first EMPTY signal of “H” is input from the empty state monitoring unit 150, the channel numbers CH1 to CHn output from the request detection unit 110 are stored in the last column bit LSB.

=== Operation of Arbitration Device ===
The operation of the arbitration device 200 will be described using a specific example shown in FIG. The symbols shown in FIG. 4 represent the same contents as the symbols shown in FIG. In the following, the operation related to the operation of the empty state monitoring unit 150 in the operation example shown in FIG. 4 will be described.

  In the first cycle t1, a shared resource use request REQ2 is generated from the device 20-2. At this time, the FIFO register unit 130 does not store “H” data (channel numbers CH1 to CH4) in all bits, and is in a first empty state (all bits are all “L”). Therefore, the empty state monitoring unit 150 outputs a first EMPTY signal of “L”. As a result, the request registration unit 120 selects the path of the first bit MSB based on the first EMPTY signal of “L”.

  In the second period t2, the channel number CH2 corresponding to the shared resource use request REQ2 generated in the first period t1 is stored in the first bit MSB of the FIFO register 135-2 based on the first EMPTY signal of "L". At the same time, shared resource use requests REQ1 and REQ3 from the devices 20-1 and 20-3 are newly generated. That is, the channel number CH2 is stored in the first bit MSB of the FIFO register 135-2 and is selected by the request selection unit 170. At this time, since the FIFO register 135 is not in the first empty state, the empty state monitoring unit 150 outputs the first EMPTY signal of “H”.

  In the third period t3, the request registering unit 120 sets the channel numbers CH1 and CH3 corresponding to the shared resource use requests REQ1 and REQ3 generated in the second period t2 based on the first EMPTY signal of “H” as FIFO registers. Stored in the last column bit LSB of 135-1, 135-3.

  In the third period t3, the channel number CH2 selected by the request selection unit 170 is deleted from the FIFO register 135-2. Then, the request permission unit 180 outputs a shared resource use permission ACK2 to the device 20-2 that has generated the shared resource use request REQ1 corresponding to the channel number CH2. As a result, the device 20-2 is given permission to use the shared resource 10 via the shared bus 15.

  After the fourth cycle t4, the shared resource use request REQ4 generated from the device 20-4 in the fifth cycle t5 is based on the first EMPTY signal of “H”, and in the next sixth cycle t7, the FIFO register 135- 4 in the last column bit LSB. The shared resource use request REQ2 generated from the device 20-2 in the tenth cycle t10 is based on the first EMPTY signal of “H”, and the last column bit of the FIFO register 135-2 in the next eleventh cycle t11. Stored in LSB. Other operations are basically the same as those of the arbitration device 100 according to the first embodiment.

  In the second embodiment, the arbitration device 200 stores the channel numbers CH1 to CHn in the first bit MSB instead of the last column bit LSB when the FIFO register unit 130 is in the first empty state. As a result, the arbitration device 200 can select the channel numbers CH1 to CHn stored in the first bit MSB of the FIFO register unit 130 without giving a wasteful waiting time. In other words, the arbitration device 200 can output the shared resource use permissions ACK1 to ACKn faster than the arbitration device 100 in the first empty state.

<<< Third Embodiment >>>
=== Configuration of Arbitration Device ===
The configuration of the arbitration device 300 according to the third embodiment of the present invention will be described with reference to FIG. 3 having the same configuration as that of the arbitration device 200 shown in FIG.

  In the first and second embodiments of the present invention described above, the N devices 20-1 to 20-n occupy the right to use the shared resource 10 via the shared bus 15 for two or more periods of the system clock CLK. Explained as a case. On the other hand, in the third embodiment of the present invention, N devices 20-1 to 20-n release the right to use the shared resource 10 via the shared bus 15 in one cycle of the system clock CLK. explain.

  The arbitration device 300 outputs a second EMPTY signal in addition to the first EMPTY signal from the empty state monitoring unit 150 to the request registration unit 120.

  In the second EMPTY signal, “H” data is stored in any one of the first bits MSB of the FIFO registers 135-1 to 135-n, and the first bits of the FIFO registers 135-1 to 135-n. This is a status signal indicating a second empty state in which “H” data is not stored in N × (N−1) bits other than the MSB.

  When the second EMPTY signal is output from the empty state monitoring unit 150, the request registration unit 120 uses the channel numbers CH1 to CHn output from the request detection unit 110 as the first bits of the FIFO registers 135-1 to 135-n. Store in the second bit from the MSB. Thereby, permission can be given to the newly received shared resource use requests REQ1 to REQn without causing unnecessary waiting time.

  In order to realize the mechanism as described above, the empty state monitoring unit 150 includes a NOR element 154 that calculates a logical sum of all bits other than the first bits MSB1 to MSBn of the FIFO registers 135-1 to 135-n, and a NOR element 154. And an NAND element 158 for calculating the logical product of the output of the OR element 152. When the output of the AND element 158 becomes the second EMPTY signal and the second EMPTY signal is “L”, it indicates that the FIFO register unit 130 is in the second empty state.

  Further, the request registration unit 120 uses the channel numbers CH1 to CHn output from the request detection unit 110 based on the first EMPTY signal and the second EMPTY signal input from the empty state monitoring unit 150 as the first bit MSB. , Switch circuits 124-1 to 124-n for storing in the second bit from the first bit MSB or the last bit LSB.

  Specifically, when the “L” first EMPTY signal is input from the empty state monitoring unit 150, the switch circuits 124-1 to 124-n are the channel numbers CH 1 to CHn output from the request detection unit 110. Is selected in the first bit MSB.

  When the “H” first EMPTY signal is input from the empty state monitoring unit 150 and the “H” second EMPTY signal is input, the switch circuits 124-1 to 124n are switched from the request detection unit 110. A path for storing the output channel numbers CH1 to CHn in the last column bit LSB is selected.

  When the “H” first EMPTY signal is input from the empty state monitoring unit 150 and the “L” second EMPTY signal is input, the switch circuits 124-1 to 124-n The path for storing the channel numbers CH1 to CHn output from 110 in the second bit from the first bit MSB is selected.

=== Specific Example of Arbitration Device Operation ===
The operation of the arbitration device 300 will be described using a specific example shown in FIG. The symbols shown in FIG. 6 represent the same contents as the symbols shown in FIG.

The operation of the arbitration device 300 shown in FIG. 6 will be described.
In the first cycle t1, a shared resource use request REQ2 is generated from the device 20-2. At this time, “H” data (channel numbers CH1 to CH4) is not stored in all the bits of the FIFO register unit 130. Therefore, the FIFO register unit 130 is in the first empty state (all bits are all “L”), but not in the second empty state. Therefore, the vacant state monitoring unit 150 outputs the “L” first EMPTY signal and the “H” second EMPTY signal. As a result, the request registration unit 120 selects the path of the first bit MSB.

  In the second cycle t2, a new shared resource use request from the shared resource use request REQ1 from the device 20-1 is newly generated, and the channel number CH2 corresponding to the shared resource use request REQ2 generated in the first cycle t1 is Based on the “L” first EMPTY signal and the “H” second EMPTY signal output from the empty state monitoring unit 150, the first bit MSB of the FIFO register 135-2 is stored. That is, the channel number CH2 is stored in the first bit MSB of the FIFO register 135-2 and is selected by the request selection unit 170. Note that “H” data is not stored in all bits other than the first bit MSB of the FIFO registers 135-1, 135-2, 135-3, and 135-4. Accordingly, in the second period t2, the FIFO register unit 130 is not in the first empty state but is in the second empty state, and the empty state monitoring unit 150 sets the first EMPTY signal of “H” and the second of “L”. EMPTY signal is output.

  In the third period t3, the channel number CH1 corresponding to the shared resource use request REQ1 generated in the second period t2 is the first “H” EMPTY signal output from the empty state monitoring unit 150 and the “L” number. 2 is stored in the second bit of the FIFO register 135-1 based on the EMPTY signal of 2. Accordingly, in the third period t3, the FIFO register unit 130 is neither in the first empty state nor in the second empty state, and the empty state monitoring unit 150 detects the first EMPTY signal of “H” and the second of “H”. EMPTY signal is output.

  In the third period t3, the channel number CH2 selected by the request selection unit 170 is deleted from the FIFO register 135-2. Then, the request permission unit 180 outputs a shared resource use permission ACK2 to the device 20-2 that has generated the shared resource use request REQ1 corresponding to the channel number CH2. As a result, the device 20-2 is given permission to use the shared resource 10 via the shared bus 15.

  In the fourth period t4, the channel number CH1 is shifted from the third bit to the first bit MSB from the last column bit LSB of the FIFO register 135-1, and is selected by the request selection unit 170. At this time, the shared resource 10 ends the process for the device 20-2.

  In the fifth period t5, the channel number CH1 is deleted from the FIFO register 135-1, and the shared resource use permission ACK1 is output to the device 20-1 that has generated the shared resource use request REQ1. As a result, the shared resource 10 starts processing for the device 20-1.

  In the third embodiment, in the case of the arbitration device 300, since two cycles are required from when the shared resource use request REQ1 is registered in the FIFO register 135-1 until permission is granted, the processing for the device 20-1 is performed. Can be started immediately.

  As mentioned above, although embodiment of this invention was described, embodiment mentioned above is for making an understanding of this invention easy, and is not for limiting and interpreting this invention. The present invention can be changed / improved without departing from the gist thereof, and equivalents thereof are also included.

It is the figure which showed the structure of the arbitration apparatus which concerns on 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the arbitration apparatus which concerns on 1st Embodiment of this invention. It is a figure for demonstrating the structure of the arbitration apparatus which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating operation | movement of the arbitration apparatus which concerns on 2nd Embodiment of this invention. It is a figure for demonstrating the structure of the arbitration apparatus which concerns on 3rd Embodiment of this invention. It is a figure for demonstrating operation | movement of the arbitration apparatus which concerns on 3rd Embodiment of this invention. It is the figure which showed the structure of the conventional arbitration apparatus.

Explanation of symbols

10 shared resource 15 shared bus 20-1, 20-2, 20-3, 20-4, 20-n device 110 request detection unit 120 request registration unit 122a, 124a switch circuit 130 FIFO register unit 135-1, 135-2 , 135-3, 135-4, 135-n FIFO register 140 shift control unit 150 state monitoring unit 152, 154 OR element 156 NOR element 158 AND element 160 priority setting unit 170 request selection unit 180 request permission unit 100, 200, 300, 500 Arbitration device 510 Request detection unit 520 Access request adjustment unit 525 Priority setting register 530 Matrix register 540 Bus acknowledge selection unit 5201 Request contention arbitration unit 5202 Priority selection unit

Claims (3)

In an arbitration device for arbitrating shared resource use requests from a plurality of signal processing devices connected to the shared resource,
A plurality of shift registers corresponding to the plurality of signal processing devices on a one-to-one basis and registering and storing the shared resource use request;
A request selection unit that selects the shared resource use request registered in any one of the first bits of the plurality of shift registers;
A request permission unit that gives permission to use the shared resource to the signal processing device that has issued the shared resource use request selected by the request selection unit;
An arbitration device comprising: The arbitration device according to claim 1, wherein
A priority setting unit that sets a priority for each of the shared resource use requests from the plurality of signal processing devices;
The request selection unit is registered in the first bits based on the priority set in the priority setting unit when a plurality of shared resource use requests are registered in the first bits of the plurality of shift registers. Granting permission to use the shared resource in response to one of the plurality of shared resource usage requests;
Arbitration device characterized by. The arbitration device according to claim 1, wherein
A free state monitoring unit that monitors whether or not the shared resource use request is registered in each bit of the plurality of shift registers;
A shared resource usage request registration unit that receives the shared resource usage request from the plurality of signal processing devices and registers the shared resource usage request in the shift register corresponding to the signal processing device that has issued the shared resource usage request. When,
Have
The shared resource use request registration unit selectively stores the shared resource use request in a first bit of the shift register or a bit other than the first bit of the shift register based on the monitoring result of the free state monitoring unit. ,
Arbitration device characterized by.

Images