JPS63180239A - Access competition arbitration circuit - Google Patents

Abstract

PURPOSE:To arbitrate access requests between plural processors by storing the order of the occurrences of access requests limiting on such processors as newly issuing the access requests, and conferring sequential access right. CONSTITUTION:In an access request monitor circuit 11, a clock of different phase is supplied to FFs 200-205 to latch only one access request, and one pulse is generated by rising detection circuits 206-209 only at a time when a new access request is generated. The FFs 301-304 of an access right generation circuit 12, if at least one of the four input signals changes, latch a new combination of signals under a clock which is the sum of the outputs of rising/ dropping detection circuits 210-230; the output of the monitor circuit 11 is stored in the four-stage FFs filling in front, and an information in the fourth- stage FF is outputted as a signal respresenting an access right, and thus access requests more than three pieces are arbitrated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an access conflict arbitration circuit that arbitrates access conflicts between a plurality of processors when they access one device such as a memory.

BACKGROUND OF THE INVENTION FIG. 6 shows an example of the configuration of a conventional bus access contention arbitration circuit. 4. Two flip-flops 41 and 42
．． 42 to input clocks with different phases to each processor to latch access requests from each processor. The latched flip-flop 41 or 42 resets the other flip-flop 42 or 41 and does not hand over the access right to the other party until there is no longer an access request. In this way, even the conventional circuit described above can perform access conflict arbitration between two processors.

Problems to be Solved by the Invention However, the conventional method described above has a problem in that it is not possible to properly arbitrate conflicts among three or more processors. This is because after the reset of the reset flip-flop is released, other flip-flops will latch the access request before the clock for itself arrives, and if this continues, this access request will not be latched and the access right will be lost. You may not have the opportunity to get it.

The present invention solves these conventional problems, and aims to provide an excellent bus access contention arbitration circuit that can arbitrate contention between three or more processors on a first-come, first-served basis. be.

Means for Solving the Problems In order to achieve the above object, the present invention provides an access request monitoring circuit that monitors access request signals from each processor, limits one processor to which a new access request has been generated, and generates the signal as a signal. The processor is equipped with an access right generating circuit which stores the processors making access requests and the order in which they occurred based on the signals, and generates an access right signal to the processor whose turn has come.

According to the present invention, it is possible to arbitrate conflicts among three or more access requests and provide access rights on a first-come, first-served basis.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention.
This is to arbitrate contention among multiple processors. In FIG. 1, 11 is an access request monitoring circuit, and 12 is an access right generation circuit. FIG. 2 shows details of the access request monitoring circuit.

200 to 205 are 0-flip-flops (hereinafter abbreviated as F and F). Access request signals 1 to 4 from each processor are input to F and F202 to F205. In F, F200 and F201, clocks having different phases are generated. The outputs of F and F202-205 are arranged so that one pulse is generated only when a change occurs in the rise detection circuits 206-209. A timing chart of the rise detection circuits 206-209 is shown in FIG. Furthermore, rising and falling detection circuits 210 to 2
One pulse is generated only when a change occurs in step 13. The rising and falling edges indicate the details of the circuit. 30
There are 16 low flip-flops from 1 to 316,
Four stages are prepared for each access request.

All the flip-flops latch the sum of the output signals of F and F210 to F213. Furthermore, when all four outputs of the second stage are “0”, the second stage latches and the same goes for 20, 4.
The stage also latches when its outputs are all "0". The output of the fourth stage becomes a signal representing the access right.

Next, the operation of the above embodiment will be explained. In the above embodiment, the access request monitoring circuit 11 includes F, F200 to
By inputting clocks with different phases to the four flip-flops 205, only one access request is latched. One pulse is generated only when a new access request is generated by the rising edge detection circuits 206-209.

Access right generation circuit 12 which receives these four signals as input
If even one of the four signals changes, F and F301 to F304 latch the new combination of signals using the sum of the outputs of the rising and falling detection circuits 210 to 213 as a clock. If the flip-flops in the second stage are all "0"', the information in the first stage is transmitted to the second stage. Similarly, if the next stage is empty, the information of that stage is transmitted to the next stage. In this way, the output of the access request monitoring circuit 11 is stored in the four stages of flip-flops in a front-aligned manner, and the information on the fourth stage is output as a signal representing the access right. In this way, according to the above embodiment, it is possible to mediate conflicts among access requests from four processors and grant access rights on a first-come, first-served basis. The case of 3 pieces or the case of 5 or more pieces can be realized in the same way.

That is, the access request signal from each processor is latched in each flip-flop using a clock having a different phase. The access request monitoring circuit outputs "1" only when the outputs of these flip-flops change from "0" to "1"', and otherwise outputs "o". In other words, when a new access request occurs, only the corresponding output is set to 11111, and the others are set to 0". Also, when the output of a flip-flop changes, only the corresponding output is set to 11111.
", and outputs the sum as a clock indicating a change in access request. Next, the first stage flip-flop of the access right generation circuit latches these signals at the timing of the clock indicating a change in access request. If the memory contents of the next stage flip-flop are all “0”, the contents are moved to the next stage.If the contents include “1”, they are not moved to the next stage.At the clock of the next access request change, the contents are moved to the next stage. Move to the next stage.The output of the final stage of the flip-flop becomes the output of the access right generation circuit, that is, it is a signal that gives access rights, and it is a ready signal to each processor, a chip select to the device to be accessed, and a signal to that device. It can be used as a gate enable signal for an address/data bus to be input.

Effects of the Invention As is clear from the embodiments described above, the present invention monitors access request signals in response to access requests from three or more processors, limits the access request to only one processor, and determines the order in which the access requests are generated. Since the information is stored and access rights are sequentially granted, there is an advantage that access requests between the processors can be adjusted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an access contention arbitration circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific configuration of the circuit, FIG. 3 is a timing chart of F and F in FIG. 2, and FIG. 5 is a timing chart of the rise detection circuit of FIG. 2, FIG. 5 is a timing chart of the rise and fall detection circuit of FIG. 2, and FIG. 6 is a circuit diagram showing the configuration of a conventional example. 11...Access request monitoring circuit, 12. Mountain...
Access right generation circuit, 202-205...D-
Flip-flops, 206-209...Rise detection circuit, 210-213...Rise and fall detection circuit, 301-316...D-
Flip-flop, 41.42...D-flip-flop.

Claims (1)

[Claims] an access request monitoring circuit that monitors access request signals from three or more processors, and when a new processor generates the access request signal, limits one of the processors to generate an output signal; An access contention arbitration circuit comprising an access right generation circuit that stores the processors issuing the access request signals and the order in which they are generated, and generates an access right signal to the processor whose turn has come.