JPS63116260A - Priority order determining circuit - Google Patents

Abstract

PURPOSE:To provide a chance for acquiring a fair bus using right by storing plural bus requests temporarily, resetting the requests at the time of starting the use of the bus and inhibiting the input of a new bus using request until all the bus using requests in respective storage parts are completely reset. CONSTITUTION:The storage parts 11-14 store bus using requests from respective bus masters. Bus request signals R1-R4 are inputted to REQ terminals of respective storage parts 11-14. The reset signal, the inverse of RST is inputted to RST terminals of the storage parts 11-14, and positive logical signals are outputted from respective RQ terminals and connected to a fixed priority order determining circuit 16 and a NOR gate 17. A signal indicating a bus request empty state is inputted from the gate 17 to EMP terminals of the storage parts 11-14. An OR gate 15 ORs the PD signals outputted from the storage parts 11-14 to indicate that a bus request is held in any one of the storage part. The output terminals A1-A4 of the circuit 16 are connected to the PRN input terminals of respective storage parts 11-14.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bus usage right priority determining circuit, and in particular to an arbitration system for bus usage rights when a plurality of bus usage requests share a single bus. Regarding.

[Conventional technology]

Conventionally, two types of priority determining circuits have been known: a fixed priority determining circuit and a rotating priority determining circuit.

The fixed priority determination circuit is a circuit that uniquely (in a predetermined order) gives priority to a plurality of bus usage requests. For example, four bus usage requests R1, R2, R3
, R4, the priority order for these four requests is set as R1>R2>R3>R4. That is,
This fixed priority determining circuit functions as shown in FIG. 7, with R1 given the highest priority. In FIG. 7, bus use request R1
, R2, R3, and R4 each acquire the right to use the n bus,
A2. Compatible with A5 and A4. For bus use requests, 1 indicates that there is a bus use request, @o"h indicates that there is no bus use request, and X indicates that there is either a bus use request or no bus use request. (That means 9 is functionally unrelated to 1.0). on the other hand.

In acquiring the right to use the bus, "1" indicates that the right to use the bus has been acquired, and "0" indicates that the right to use the bus has not been acquired.

The rotation priority determination circuit responds to multiple bus usage requests.
Dynamically changing priorities. For example, considering the priority order of the four bus use requests R1, R2, R3, and R4, these have the same meaning as the priority of the bus use requests.

[Problem that the invention seeks to solve]

By the way, in the case of a fixed priority determination circuit, it has the advantage that it can be realized with simpler hardware than other circuits, that is, one-rotation priority determination circuit, but on the other hand, as shown in Fig. If a bus requester (for example, R1) frequently uses the bus, n or more requests) - (R2°R3, R4),
In particular, there is a problem that R4 cannot acquire the right to use the bus. On the other hand, in the case of the 9-rotation priority determination circuit, all bus requesters are guaranteed the opportunity to acquire the right to use the bus, but on the other hand, priority determination is performed immediately before bus switching.
For example, as shown in FIG. 6, does R4 signal a bus use request earlier than R3? Even though it was outputting, R6 is better than R4
It happens that Yoshi also acquires the right to use the bus quickly.

For this reason, there is a problem in that the rotational superiority determination circuit cannot give a fair opportunity to all requesters to use the bus.

An object of the present invention is to provide a circuit that gives all bus usage requests a fair opportunity to acquire bus usage rights, and furthermore, to provide a priority determining circuit that can grant bus usage rights in the order of bus usage requests. It is about providing.

[Means for solving problems]

The priority determination circuit of the present invention includes a storage circuit that temporarily stores bus usage requests, and a first detection circuit that detects that the storage circuit does not store any bus usage requests, that is, is empty. a second detection circuit for detecting that a request to use the bus is pending in the storage circuit; The feature is that when all the original requests are reset and the storage circuit becomes empty, a new bus use request is stored.

〔Example〕

Next, the present invention will be explained with reference to examples.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, four bus use request sources (hereinafter referred to as bus masters) are considered. Referring to FIG. 1, 1 to 4 indicate bus masters, and 5 indicates a priority order determining circuit. show.

The bus use request terminal R of the bus master 1 is connected to the terminal R1 of the priority order determination circuit 5, and its bus use permission signal terminal Aid is connected to the terminal A1 of the priority order determination circuit 5. Similarly, the bus use request terminal R and the bus use permission signal terminal A of the bus master 2 are connected to the priority order determining circuit 5.
The bus use request terminal R and the bus use permission signal terminal A of the bus master 3 are connected to the terminal R2 and the terminal A2 of the bus master 3, and the bus use request terminal R of the bus master 4 is connected to the terminal R3 and the terminal A6 of the priority determination circuit 5. Tohas use permission signal terminal Aidson
It is connected to the terminal R3 and the terminal A3 of the priority order determining circuit 5.

A busy signal indicating that the bus is in use is sent from the terminals of bus masters 1 to 4, and each bus master 1 to 4 sets the busy signal to Active (0'') when it starts using the bus, and when it ends, it outputs the busy signal. nactiveθ(-″)
Make it. Furthermore, when you finish using the bus, request R to use the bus.
is also 1n-active (in addition, the bus use request R
is positive logic, so in this case (nactiVθ) is 0
Then, the terminals of the bus masters 1 to 4 and the terminal BUSY of the priority determining circuit 5 are connected.

A clock signal CLK is connected to the terminals C of the bus masters 1 to 4 and the terminal CLK of the priority order determining circuit 5. The reset signal R8T remains active (1
0''), initializes each bus master 1 to 4 and the priority determination circuit 5. Then, the reset signal RS T f
3 becomes Inactive (11''). The reset signal R8T is connected to the bus masters 1 to 4 and the terminal R6T of the priority order determining circuit 5.

FIG. 2 shows the configuration of the priority order determining circuit 5.

Referring to FIG. 2, storage units 11-14 store bus use requests (hereinafter referred to as bus requests) from bus masters 1-4. This storage unit exists for each bus request, that is, for each bus master. Positive logic bus request signals R1 to R4u storage units 11 to 140
REQ.

input to the terminal. The clock signal CLK is sent to the storage unit 11~
14 of 0LOf:! terminal and window generation circuit (WI
(NDOW generation circuit) 18.

The above-mentioned reset signal R8Tlj R8 of the storage units 11 to 14
Input to T terminal. Positive logic signals are output from the RQ terminals of the storage units 11 to 14 as described later. This RQ
, the terminals are connected to the fixed priority determination circuit 16 and the NOR gate (N
(OR gate) 17. An empty (EMPTY) signal is output from the NOR gate 7, and this EMP
The TY signal becomes logic "1" when there is no bus request in any of the storage units 11-14. That is, E with
The MPTY signal is a signal indicating that the bus request is empty, and is input to the KMP terminals of the storage units 11 to 14.

The FD terminals of the storage units 11 to 14 output a logic 11'' signal when a bus request exists and there is no bus use permission signal. That is, it indicates that the bus request is pending. Request bending (R
FiQ, UESTP]lf: ND engineering NG) signal is output, and this signal is input to the OR gate (OR gate) 15.

The OR gate 15 outputs PDs from the storage units 11 to 14.
The logical sum of the double signals is taken, and the output is used in the storage units 11 to 1.
This indicates that a bus request is pending in chair No. 4. The output signal of the OR gate 15 is then
1 to 140 FEND input terminal and WINDOW generation circuit 1
Enter 8. Output terminal A1 of fixed priority determination circuit
-A4u are connected to the PRN input terminals of the storage units 11-14. Note that the BUSY terminal is connected to the WINDOW generation circuit 18.

The output of the WINDOW generation circuit 18 is input to the W input terminals of the storage units 11 to 14.

FIG. 6 shows the configuration of the bus request storage section.

Referring to FIG. 6, the RKQ terminal is connected to an AND gate (AND
(gate) connected to LO2 and 104. The EMP terminal is connected to an AND gate 102. The FIND terminal is connected to AND gate 102. The ND terminal of W is connected to AND gate 103. PRN terminal u connected to AND gate 103 and inverter 101 n
ing. Output 1j of inverter 101 AND gate 10
Enter 4. The output of the AND gate 102 is input to the J terminal of a flip-flop (hereinafter referred to as F/F) 105 at T-. AND gate 10
The output of 6 is connected to the terminal of T-KF/F105 and DF'/F.
'10<S input to D terminal. The output of the DF/F 106 is an active low mask (MASK) signal.5. The signal is input to AND gate 102.

C1ock terminal is T-K F/F 105 and D F
' / Connect to the cp terminal of F106. Also, the R8T terminal is J-K F/F 105 and DF/F106
, is connected to the R8T terminal of . AND gate 104 is P
Connected to D terminal 3. , TK F/F' 105 are connected to the PQ terminal.

, T-K F'/F 105 and DF'/F10 (S is initialized to logic 60'' by the R8T signal.

That is, the RQ terminal becomes logic "0" due to the R8T signal. In this case, the RQ terminal of the storage units 11 to 14 becomes logic "0".
0" is output, the KMP from NOR gate 17
The TY signal becomes logic "1". In addition, logic "0" is output from the output terminals A1 to A4 of the fixed priority order determining circuit 16, and as a result, the memory units 11 to 140 PRN terminals Kti logic 11011 are inputted to one input terminal of the AND gate 104. Logic 61'' is also supplied.

J-K F/F 105's terminal and DF/F106's D
A logic "0" is supplied to the terminal. moreover.

When the REQ terminal of the storage units 11 to 14 is at logic "0", the output of the AND gate 102, ie.

J-K F/F 105 J terminal input and AND game)
The output of C04, that is, the FD terminal output becomes logic "0".

Next, the operation of the priority determining circuit according to the present invention will be explained with reference to FIG. In addition, in this case, bus master 1
and 6 output bus requests at the same time, and then bus masters 2 and 4 output bus requests. Logic “1” is applied to terminals R1 and R6 of the priority order determining circuit 5.
When this is input, logic "1" is input to the REQ terminals of the storage units 11 and 16. When logic "1" is input to the REQ terminal, the AND gate 104 outputs the logic "1".

That is, logic "1" is output from the FD terminal.

As a result, logic "1" is output from the OR gate 15, and P
Logic “1” is input to the END terminal.

All inputs of AND gate 102 are logic "1". Therefore, the output of AND gate 102.

That is, the J terminal input of the J-K F/F 105 becomes logic "1", and the output terminal P of the T-K F/F 105
The signal from Q changes from logic "O" to logic "1" at the change point () of clock signal CLK. After that, the DEMPTY signal from the NOR gate changes to logic "0".
'. Therefore, the J-K F/F of storage units 11 to 14
' The J terminal input of 105 becomes logic "0". On the other hand, the fixed priority determining circuit 16 determines the priority and outputs the logic "1n" from the output terminal A1.As a result, the storage unit 11
Logic "1" is input to the PRN terminal of jL, and the PD terminal output becomes logic "0". On the other hand, the bus master 1 inputs a logic "0" to the terminal BUSY of the priority order determining circuit in response to the logic "1" from the output terminal A1.

Bus master 1 begins using the bus.

In the WINDOW generation circuit 18, the signal from the BUSY terminal is logic "ON" and the REQUEST PEND operation is NG.
Since the signal is logic "1", the clock signal 0LKO1
Outputs logic "1" during the clock cycle (between ■ and ■). Therefore, the ANDNO gate 17 output of the storage unit 11 becomes logic "1", and the terminal and D
Logic "1" is output from the D terminal of F/F'106.

Then, at the next change point of the clock signal CLK, T-KF/
Output of F105, ie, RQ of storage section 11.

Logic "0" is output from the terminal n, and the output of D F/F 1o6, that is, the MARK signal becomes logic "D".

Then, the W_NDOW signal becomes logic "0" again after one clock cycle of the clock signal C'LK.

The MASK signal also occurs one clock after the clock signal CI,
The logic becomes "1" again.

As a result, the fixed priority determination circuit 16 outputs a logic 10'' to the terminal A1 and a logic ``1'' to the -blade terminal A6. Therefore, a logic ``0'' is input to the PRN terminal of the storage unit 11. Then, logic "1" is output from the PD terminal again.

However.

In this case, the EMP signal is at logic "0".

J-K F/F 1 D 5 C7) J terminal ICf'i
Logic "On" is input n, and further PRN terminal and W terminal
Since logic "0" is input to the terminal, J-KF
Logic "0" is input to the terminal of /F105. Therefore, the output of the RQ terminal of the storage unit 11 is held at the logic "O" state. Also, T-K F/F 1Q5 in the storage unit 16
When a logic "0" is input to both the J terminal and the terminal, the output of the RQ terminal of the storage section 13 is held at a logic "1" state.

Here, if logic "1" is output from the terminal R2 of the bus master 2 and the terminal R4 of the bus master 4 at O2 after two clocks of the clock signal CLK, at this point, the EM
Since the PTY signal is logic "0", the storage units 12 and 14
The J terminal input of 0J-KF/F105 is in the state of logic "0", therefore, the RQ of the storage section 12, the terminal and the storage section 14
The output from the RQ terminal is in the logic "0" state.

4, the bus master 1 finishes using the bus, outputs the logic 10'' from the terminal R1, and further inputs the logic 111+1 to the BUSY terminal of the priority determination circuit 5.The bus master 3 After recognizing that the BUEIY terminal is "1", move to the bus usage state and turn the BU
Input logic "0" to the SY terminal (■ shown in FIG. 4).

On the other hand, the WINDOW generation circuit 18 is RFiQ, UKST
PEND operation is in NG state and logic 111 is set to BUSY.
Since 11 was input, that is, it became Active, WI was activated for one clock period from ■ to ■ shown in Figure 4.
Outputs NDOW signal. At this time.

Since the logic 11'' is output from the A3 terminal of the fixed priority determination circuit 16, the J-K F/F 1 of the storage section 16
05 has no terminal input! becomes “1”, and ■ as shown in Figure 4.
At this time, a logic "0" is output from the RQ terminal of the storage unit 16. As a result, the signal from the RQ terminal of the storage units 11 to 14 becomes a logic "0", and the EMPTY signal becomes a logic "0".
The MASK signal, which is the output of the DF/F 106 of the storage unit 13, becomes logic "0" during one clock cycle from (1) to (4) shown in FIG.

When the EMPTY signal becomes logic "1", the AND gates 1o2 of the storage units 12 and 14 all have their inputs logic "1".
”, so the logic “1” is supplied to the J terminal input of the J-K F/F 105.

On the other hand, regarding the storage unit 16, the MASK signal is at logic "0".
", so the output of the AND gate 1o2 is logic"
0''. Then, at the next change point (3) of the clock signal CLK, the memory sections 12 and 14 are held at the J-K F/F 10.
The output of 5 changes from logic "o" to "1". On the other hand, the output of the J-K F/F 105 of the storage unit 13 is logic "0"
It remains as it is. As a result, the EMPTY signal becomes logic again.
0'', and the state change of the J-KF/F 105 in the storage units 11 to 14 is prohibited.The fixed priority order determining circuit 16 receives the signal from the RQ terminal of the storage unit 12, that is, the bus master 2 and the storage unit. 14 RQs.

The signal from the terminal, that is, the priority order with respect to the bus master 4 is determined, and the output of the output terminal A2 is set to logic "1". Thereafter, the right to use the bus is switched in the same manner.

〔Effect of the invention〕

As explained above, this crystallization priority order determining circuit bus request is reset and new bus usage requests are not taken in until all bus requests in the storage section are reset, so all bus usage It is possible to give requesters a fair opportunity to acquire the right to use the bus, and the requester who outputs the bus use request early gets the right to use the bus first. It has the effect of being able to be acquired.

Remaining days below

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a device using the priority determining circuit of the present invention, FIG. 2 is a block diagram of the priority determining circuit of the present invention, FIG. 3 is a block diagram showing the storage section in detail, and FIG.
The figure is a time chart for explaining the operation of the priority order determining circuit of the present invention, FIG. 5 is a time chart for explaining the operation of the fixed priority order determining circuit, and FIG. 6 is a time chart for explaining the operation of the rotating priority order determining circuit. A time chart for explanation, Figure 7 is a diagram showing the truth table of the fixed priority determination circuit, and Figure 8 is a diagram showing the truth table of the fixed priority determination circuit.
The figure is a diagram showing a truth table of the rotation priority order determining circuit. 1 to 4...Bus master 5...Priority determining circuit. 11-14...Bus request storage section, 15...O
R gate, 16... fixed priority determination circuit, 17...
・NOR gate, 15-w NDOW generation circuit, 1o1
-NOT'7'-), 102 to 104
・AND gate. 105...Flip-flop to J-, 1o6...D
flip flop. Figure 1 Figure 3 Hayabusa Figure 6

Claims (1)

[Claims] 1. In a priority determination circuit that determines the priority order of a plurality of bus use request signals and outputs a common bus use permission signal, there is a memory circuit that temporarily stores the bus use request signal, and a memory circuit that is empty. a first detection circuit for detecting that the bus use request signal is pending in the storage circuit; and a second detection circuit for indicating that the common bus has started to be used. a reset circuit configured to reset, in response to a start signal, a bus use request signal stored in the storage circuit that permits use of the common bus; all bus use request signals stored in the storage circuit are reset; 1. A priority determination circuit, wherein a new bus use request signal is stored in the storage circuit when the storage circuit becomes empty.