AU8066887A - Bus priority assignment control with a lockout circuit - Google Patents
Bus priority assignment control with a lockout circuitInfo
- Publication number
- AU8066887A AU8066887A AU80668/87A AU8066887A AU8066887A AU 8066887 A AU8066887 A AU 8066887A AU 80668/87 A AU80668/87 A AU 80668/87A AU 8066887 A AU8066887 A AU 8066887A AU 8066887 A AU8066887 A AU 8066887A
- Authority
- AU
- Australia
- Prior art keywords
- assignment control
- priority assignment
- lockout circuit
- bus priority
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61-262042 | 1986-11-05 | ||
JP26204286A JPS63116260A (en) | 1986-11-05 | 1986-11-05 | Priority order determining circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
AU8066887A true AU8066887A (en) | 1988-05-12 |
AU595074B2 AU595074B2 (en) | 1990-03-22 |
Family
ID=17370220
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU80668/87A Expired AU595074B2 (en) | 1986-11-05 | 1987-11-04 | Bus priority assignment control with a lockout circuit |
Country Status (2)
Country | Link |
---|---|
JP (1) | JPS63116260A (en) |
AU (1) | AU595074B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR980004877A (en) | 1996-06-24 | 1998-03-30 | 김광호 | Priority Control System and Method for Memory Access |
JPH1131123A (en) | 1997-07-14 | 1999-02-02 | Saitama Nippon Denki Kk | Bus arbitration circuit |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53146550A (en) * | 1977-05-27 | 1978-12-20 | Nippon Telegr & Teleph Corp <Ntt> | Conflict circuit |
-
1986
- 1986-11-05 JP JP26204286A patent/JPS63116260A/en active Pending
-
1987
- 1987-11-04 AU AU80668/87A patent/AU595074B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS63116260A (en) | 1988-05-20 |
AU595074B2 (en) | 1990-03-22 |
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