JP2005316866A - Bus device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus device capable of efficiently using a bus even if the generation frequency of data transfer processing requests of each master device changes. <P>SOLUTION: The bus device 1 is provided with data FIFOs 11a, 11b for accumulating data transfer processing requests from the corresponding master devices 2a, 2b; counters 12a, 12b for counting the number of data transfer processing requests accumulated in the respective data FIFOs 11a, 11b; and a data multiplex circuit 16 taking out data transfer processing requests preferentially from the data FIFO most in the number of accumulated data transfer processing requests based on count values of the counters 12a, 12b, to assign them to a time slot 14, taking out the data transfer processing requests from the data FIFO according to the order of priority preset to a register 13, to assign them to the time slot 14 when numbers of the data transfer processing requests accumulated in the respective data FIFOs are equal, and outputting them to the data bus 15. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bus device that is connected between a plurality of master devices and a plurality of slave devices, and performs data transfer between the plurality of master devices and the plurality of slave devices.

  A conventional bus device selects a data transfer processing request to be assigned to a time slot according to a preset priority (see, for example, Patent Document 1). In addition, a method has been proposed in which a master device having a low priority has a function of rewriting the priority order to prevent a master device having a high priority from occupying the bus (for example, see Patent Document 2).

JP-A-2-45857 JP-A-9-198342

  Since the conventional bus device is configured as described above, since the rules for assigning to time slots are fixed, if the frequency of data transfer processing requests of a certain master device decreases locally, the time There are no data transfer processing requests to be assigned to slots, empty slots are generated in time slots, and the bandwidth of the bus device cannot be used effectively.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a bus device that can efficiently use a bus even when the frequency of data transfer processing requests of each master device changes. .

  The bus device according to the present invention is provided corresponding to each master device, and counts the data FIFO for storing data transfer processing requests from the corresponding master device and the number of data transfer processing requests stored in each data FIFO. And a data transfer processing request is preferentially extracted from the data FIFO having the largest number of stored data transfer processing requests based on the counter value and assigned to the time slot, and the data transfer stored in each data FIFO is performed. A data multiplexing circuit that extracts a data transfer processing request from the data FIFO and assigns it to a time slot in accordance with a preset priority when the number of processing requests is the same.

  According to the present invention, the data transfer processing request is preferentially extracted from the data FIFO having the largest number of stored data transfer processing requests and assigned to the time slot. There is an effect that the bus can be used efficiently without a vacant slot being generated in the time slot even when the locality is reduced locally.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a bus device according to a first embodiment of the present invention. In FIG. 1, a bus device 1 includes a master device 2a, 2b and a slave device 3a, 3b connected to each other, and their connection. The data transfer processing requests between the master devices 2a and 2b and the slave devices 3a and 3b are processed. As the master devices 2a and 2b, devices such as computers or H / W I / Ps for specific applications are applied, and as the slave devices 3a and 3b, storage devices such as SDRAM are applied. It is.

  In the bus device 1, the data FIFO 11a stores data transfer processing requests from the corresponding master device 2a, and the data FIFO 11b stores data transfer processing requests from the corresponding master device 2b. The counter 12a counts the number of data transfer processing requests accumulated in the data FIFO 11a, and the counter 12b counts the number of data transfer processing requests accumulated in the data FIFO 11b. The register 13 has a priority set in advance between the data FIFO 11a and the data FIFO 11b.

In the time slot 14, a data transfer processing request is assigned to a plurality of one-dimensionally formed slots, and the data transfer processing request is processed in the assigned order. The data bus 15 is connected to the bus device 1. Data is transmitted and received between the slave devices 3a and 3b. Based on the count values of the counters 12a and 12b, the data multiplexing circuit 16 preferentially takes out the data transfer processing requests from the accumulated data FIFO having a large number of data transfer processing requests and assigns them to the time slot 14, and each data FIFO 11a, When the number of data transfer processing requests stored in 11b is equal, the data transfer processing request is taken out from the data FIFO according to the priority set in advance in the register 13, assigned to the time slot 14, and output to the data bus 15. is there.
FIG. 2 is an explanatory diagram showing the format of a data transfer processing request.

Next, the operation will be described.
In FIG. 1, data transfer processing requests are sequentially transferred from the master device 2a to the data FIFO 11a and from the master device 2b to the data FIFO 11b.
FIG. 2 shows an example of the format of the data transfer processing request. Items include a master ID indicating the transfer source master device, a slave ID indicating the transfer destination slave device, and a command indicating a specific command. There is write data in the case of a write request to the slave device. The commands are formed in a hierarchical manner, and include a slave device address, whether the request to the slave device is a read request or a write request, byte enable, burst instruction, and the like.

In FIG. 1, such data transfer processing requests are sequentially stored in the data FIFOs 11a and 11b, and the counter 12a counts the number of data transfer processing requests accumulated in the data FIFO 11a, the count value is M, and the counter 12b. Assume that the number of data transfer processing requests accumulated in the data FIFO 11b is counted and the count value is N.
The data multiplexing circuit 16 compares the count values M and N by the counter 12a and the counter 12b.
Here, first, if M> N, the data multiplexing circuit 16 preferentially takes out one data transfer processing request from the accumulated data FIFO 11a having a large number of data transfer processing requests, assigns it to the time slot 14, and assigns it to the data bus 15. At the same time, the count value of the counter 12a is decremented by one (M-1).
If M <N, the data multiplexing circuit 16 preferentially takes out one data transfer processing request from the accumulated data FIFO 11b having a large number of data transfer processing requests, assigns it to the time slot 14, and outputs it to the data bus 15. At the same time, the count value of the counter 12b is decremented by one (N-1).

  Further, if M = N, the data multiplexing circuit 16 follows the priority set in the register 13 in advance. That is, when a value for giving priority to the master device 2a is set in the register 13, one data transfer processing request is preferentially taken out from the data FIFO 11a, assigned to the time slot 14, and output to the data bus 15, and at the same time the counter The count value of 12a is decremented by one (M-1). Further, when a value for giving priority to the master device 2b is set in the register 13, one data transfer processing request is preferentially extracted from the data FIFO 11b, assigned to the time slot 14, and output to the data bus 15, and at the same time the counter The count value of 12b is decremented by one (N-1).

In the time slot 14 in FIG. 1, the data transfer processing request from the master device 2a is assigned to the # 1, # 3 to # 5 slots, the data transfer processing request from the master device 2b is assigned to the # 2 slot, and # 6 ~ Slot # 8 is an empty slot. As described above, since the data transfer processing request is preferentially extracted from the data FIFO having the largest number of stored data transfer processing requests among the data FIFOs 11a and 11b and assigned to the time slot 14, either the data FIFO 11a or 11b is selected. As long as the number of data transfer processing requests is stored, no bus is generated in the # 1 slot of the time slot 14, and the bus can be used efficiently.
Thereafter, the data bus 15 processes data transfer processing requests in the order assigned to the time slot 14. That is, the data transfer processing request is transferred to the slave device corresponding to the slave ID.

As described above, according to the first embodiment, since a data transfer processing request is preferentially extracted from the data FIFO having the largest number of stored data transfer processing requests and assigned to the time slot 14, a certain master Even when the frequency of the data transfer processing request of the apparatus is locally reduced, the bus can be used efficiently without an empty slot being generated in the time slot 14.
In the first embodiment, the case where there are two master devices and slave devices has been described, but any number of both devices may be connected.

1 is a block diagram showing a bus device according to Embodiment 1 of the present invention. It is explanatory drawing which shows the format of a data transfer process request.

Explanation of symbols

  1 bus device, 2a, 2b master device, 3a, 3b slave device, 11a, 11b data FIFO, 12a, 12b counter, 13 registers, 14 time slots, 15 data bus, 16 data multiplexing circuit.

Claims (1)

In a bus device that assigns individual data transfer processing requests generated between a plurality of master devices and slave devices to a one-dimensional time slot and processes the data transfer processing requests in the order assigned to the time slots. ,
A data FIFO that is provided for each of the master devices, and stores data transfer processing requests from the corresponding master devices;
A counter for counting the number of data transfer processing requests accumulated in each of the data FIFOs;
Based on the count value by the counter, a data transfer processing request is preferentially extracted from the data FIFO having the largest number of stored data transfer processing requests and assigned to the time slot, and the data transfer processing stored in each data FIFO is stored. A bus device comprising: a data multiplexing circuit that extracts a data transfer processing request from a data FIFO according to a preset priority order and allocates the request to the time slot when the number of requests is equal.

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