JP2017005179A - On-vehicle semiconductor chip - Google Patents

On-vehicle semiconductor chip Download PDF

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JP2017005179A
JP2017005179A JP2015119886A JP2015119886A JP2017005179A JP 2017005179 A JP2017005179 A JP 2017005179A JP 2015119886 A JP2015119886 A JP 2015119886A JP 2015119886 A JP2015119886 A JP 2015119886A JP 2017005179 A JP2017005179 A JP 2017005179A
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semiconductor chip
well
terminal portion
chip according
pad
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JP6453163B2 (en
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善光 柳川
Yoshimitsu Yanagawa
善光 柳川
松本　昌大
Masahiro Matsumoto
昌大 松本
中野　洋
Hiroshi Nakano
洋 中野
晃 小田部
Akira Kotabe
晃 小田部
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Hitachi Astemo Ltd
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Hitachi Automotive Systems Ltd
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Priority to PCT/JP2016/066093 priority patent/WO2016203942A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip that has a protection circuit with a reduced area and a high noise resistance.SOLUTION: An on-vehicle semiconductor chip comprises: a semiconductor substrate of a first conductivity type; a pad; an inner circuit; a first well of the first conductivity type; a floating second well of a second conductivity type; and a diffusion resistor of the first conductivity type. The diffusion resistor is electrically connected with the pad and the inner circuit. The first well is formed between the second well and the diffusion resistor.SELECTED DRAWING: Figure 1

Description

本発明は、車載用の半導体チップに関する。   The present invention relates to an on-vehicle semiconductor chip.

静電気やサージなどのノイズにより半導体チップの内部回路に過大な電圧がかかると、ゲート酸化膜の絶縁破壊や、ＰＮ接合部の破壊を引き起こし、半導体チップの恒久故障や回路特性の変化などを引き起こす。こうしたノイズによる内部回路の破壊や劣化を防ぎ、信頼性の高い半導体チップを実現するためには、パッドと内部回路との間に保護回路を設け、ノイズ印加時にも内部回路に過大な電圧がかからないようにする必要がある。   If an excessive voltage is applied to the internal circuit of the semiconductor chip due to noise such as static electricity or surge, it causes dielectric breakdown of the gate oxide film or PN junction, thereby causing a permanent failure of the semiconductor chip or a change in circuit characteristics. In order to prevent destruction and deterioration of the internal circuit due to such noise and to realize a highly reliable semiconductor chip, a protective circuit is provided between the pad and the internal circuit, and no excessive voltage is applied to the internal circuit even when noise is applied. It is necessary to do so.

特許文献１に記載の技術は、入力パッドと内部回路との間に、ポリシリコンで形成された保護抵抗とクランプトランジスタを備える。パッドに過電圧が印加されると、クランプトランジスタがブレイクダウンまたはスナップバック動作して低抵抗状態となり、ポリシリコン抵抗とクランプトランジスタを経由してパッドからグランド端子部に向かって電流が流れる。このとき、ノイズのエネルギーの大部分はポリシリコン抵抗で吸収され、内部回路に印加される電圧は一定値以下にクランプされるため、前記のような内部回路の破壊や半導体チップの特性の劣化を防ぐことが出来る。   The technique described in Patent Document 1 includes a protective resistor and a clamp transistor formed of polysilicon between an input pad and an internal circuit. When an overvoltage is applied to the pad, the clamp transistor performs a breakdown or snapback operation to enter a low resistance state, and a current flows from the pad toward the ground terminal via the polysilicon resistor and the clamp transistor. At this time, most of the energy of the noise is absorbed by the polysilicon resistor, and the voltage applied to the internal circuit is clamped to a certain value or less, so that the breakdown of the internal circuit and the deterioration of the characteristics of the semiconductor chip as described above are caused. Can be prevented.

特許文献２には拡散層抵抗を入力保護抵抗として利用する技術が開示されている。特許文献２に記載の保護抵抗はＰ型基板上のＮウェルの中にＰ＋拡散層の保護抵抗を形成している。保護抵抗と基板との間には、２つのＰＮ接合が、互いに逆向きになるように直列に入るため正負の両極性のノイズに対してクランプとして動作する。   Patent Document 2 discloses a technique that uses a diffusion layer resistance as an input protection resistance. The protective resistance described in Patent Document 2 forms a protective resistance of a P + diffusion layer in an N well on a P-type substrate. Between the protective resistor and the substrate, two PN junctions enter in series so as to be opposite to each other, and thus operate as a clamp against both positive and negative noises.

特開昭６１−３２５６３号公報JP-A-61-32563 特開昭６２−１２２１６４号公報JP-A-62-122164

保護抵抗により吸収されたエネルギーは、抵抗のジュール熱として消費される。この発熱により、保護抵抗の温度が保護抵抗の材料（前述の場合であればポリシリコン）や、コンタクト金属、もしくはこれらの化合物であるシリサイドが加熱され、これらの熱に起因する劣化が生じ、製品寿命を縮める原因となる。したがって、保護回路を設計する際は抵抗の放熱について注意しなければならない。保護抵抗の主な放熱先は、熱伝導率が低く、熱容量が大きいシリコン基板である。ところが、特許文献１に記載のように、ポリシリコン抵抗と基板との間には厚いフィールド酸化膜が存在し、これが保護抵抗の放熱を阻害する要因となっている。フィールド酸化膜の材料であるＳｉＯ２の熱伝導率はおよそ１．３Ｗ／ｍ／Ｋであり、シリコン（１６０Ｗ／ｍ／Ｋ）より２桁程度悪いためである。ポリシリコン抵抗が吸収可能なエネルギー量、すなわち許容損失を大きくするためには、抵抗の底面積を拡大して放熱量を増やすことで対応可能であるが、半導体チップ面積が増大する課題がある。   The energy absorbed by the protective resistance is consumed as Joule heat of resistance. Due to this heat generation, the temperature of the protective resistor is heated to the material of the protective resistor (polysilicon in the above case), the contact metal, or silicide, which is a compound thereof, and the deterioration due to the heat occurs, and the product This will shorten the service life. Therefore, when designing the protection circuit, care must be taken regarding the heat dissipation of the resistors. The main heat radiation destination of the protective resistor is a silicon substrate having a low thermal conductivity and a large heat capacity. However, as described in Patent Document 1, there is a thick field oxide film between the polysilicon resistor and the substrate, which is a factor that hinders the heat radiation of the protective resistor. This is because the thermal conductivity of SiO2, which is the material of the field oxide film, is about 1.3 W / m / K, which is about two orders of magnitude worse than silicon (160 W / m / K). In order to increase the amount of energy that can be absorbed by the polysilicon resistor, that is, the allowable loss, it can be dealt with by increasing the amount of heat dissipation by expanding the bottom area of the resistor, but there is a problem that the area of the semiconductor chip increases.

他方、特許文献２に記載の技術では、車載用の半導体チップの課題について十分に検討がされていない。すなわち、過大な電圧が入力端子部に印加された場合、基板との間のＰＮ接合がブレイクダウンし、抵抗から基板に向かって急激に大きな降伏電流が流れる。この降伏電流により、ＰＮ接合が破壊されたり、コンタクトが焼損されたりしてしまう。この課題を防ぐにはコンタクト数を増やすなどの対策が必要で、結果的に保護抵抗領域の面積が増大し、半導体チップの小型化を阻害する課題がある。   On the other hand, in the technique described in Patent Document 2, the problem of the in-vehicle semiconductor chip has not been sufficiently studied. That is, when an excessive voltage is applied to the input terminal portion, the PN junction with the substrate is broken down, and a large breakdown current flows from the resistor toward the substrate. Due to this breakdown current, the PN junction is broken or the contact is burned out. In order to prevent this problem, it is necessary to take measures such as increasing the number of contacts. As a result, the area of the protective resistance region increases, and there is a problem that hinders downsizing of the semiconductor chip.

本発明は上記事情に鑑みてなされたものであり、その目的は、省面積でノイズ耐性の高い車載用の半導体チップを提供することにある。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an in-vehicle semiconductor chip having a small area and high noise resistance.

上記目的を達成する本発明の半導体チップは、第１導電型の半導体基板と、パッドと、
内部回路と、第１導電型の第１のウェルと、第２導電型で、かつ、フローティングの第２のウェルと、第１導電型の拡散抵抗と、を有し、前記拡散抵抗は、前記パッドと前記内部回路と電気的に接続され、前記第１のウェルは、前記第２のウェルと前記拡散抵抗の間に形成される車載用の半導体チップ。 A semiconductor chip of the present invention that achieves the above object includes a first conductivity type semiconductor substrate, a pad,
An internal circuit; a first well of a first conductivity type; a second well of a second conductivity type and floating; and a diffusion resistor of a first conductivity type; A vehicle-mounted semiconductor chip that is electrically connected to a pad and the internal circuit, and wherein the first well is formed between the second well and the diffused resistor.

本発明により、省面積でノイズ耐性の高い車載用の半導体チップを提供するこが出来る。   According to the present invention, an in-vehicle semiconductor chip having a small area and high noise resistance can be provided.

第１実施例をなす半導体チップの保護抵抗の断面図Sectional drawing of the protection resistance of the semiconductor chip which makes a 1st Example 第１実施例をなす半導体チップの回路図Circuit diagram of semiconductor chip according to the first embodiment. 第２実施例をなす半導体チップの保護抵抗の断面図Sectional drawing of the protection resistance of the semiconductor chip which makes a 2nd Example 第１実施例の変形例を示す半導体チップの断面図Sectional drawing of the semiconductor chip which shows the modification of 1st Example 第１実施例の変形例を示す半導体チップの上面図The top view of the semiconductor chip which shows the modification of 1st Example 第１実施例の変形例を示す半導体チップの断面図Sectional drawing of the semiconductor chip which shows the modification of 1st Example 第３実施例をなす半導体チップの保護抵抗の断面図Sectional drawing of the protection resistance of the semiconductor chip which makes a 3rd Example 第３実施例の変形例を示す半導体チップの断面図Sectional drawing of the semiconductor chip which shows the modification of 3rd Example 第３実施例の変形例を示す半導体チップの上面図The top view of the semiconductor chip which shows the modification of 3rd Example 第４実施例をなす半導体チップの保護抵抗の断面図Sectional drawing of the protection resistance of the semiconductor chip which makes a 4th Example 第４実施例をなす半導体チップの回路図Circuit diagram of semiconductor chip according to fourth embodiment 第４実施例の抵抗値と抵抗面積、抵抗の端子部電圧の関係を説明する図The figure explaining the relationship between the resistance value of 4th Example, resistance area, and the terminal voltage of resistance. 第５実施例をなす半導体チップの回路図Circuit diagram of semiconductor chip according to fifth embodiment 電波照射時の出力信号の変動を説明する波形図Waveform diagram explaining fluctuation of output signal during radio wave irradiation 第６実施例をなす半導体チップの回路図Circuit diagram of semiconductor chip according to sixth embodiment 第６実施例の変形例を示す回路図Circuit diagram showing a modification of the sixth embodiment 第６実施例の変形例を示す半導体チップの回路図Circuit diagram of a semiconductor chip showing a modification of the sixth embodiment 第６実施例の変形例を示す半導体チップの断面図Sectional drawing of the semiconductor chip which shows the modification of 6th Example 第７実施例をなす半導体チップを含むセンサ装置のブロック図Block diagram of a sensor device including a semiconductor chip according to a seventh embodiment 第１から第７実施例をなす半導体チップの発展形状を示すブロック図The block diagram which shows the developed shape of the semiconductor chip which makes the 1st-7th Example

以下、本発明の実施の形態について、図面を参照して説明する。本発明の第１実施例をなす半導体チップを図１、２により説明する。図１は第１実施例をなす半導体チップの保護抵抗の断面図をしめす。図２は図１の保護抵抗の等価的な回路図である。本実施例における半導体チップの構成を図１により説明する。本実施例における半導体チップは、パッド１００、Ｐ型の拡散層からなる保護抵抗１０１、フィールド酸化膜１０２、内部回路１０３、Ｐ型シリコン基板１０４、Ｐ型ウェル１０５、Ｎ型ウェル１０６、およびグラウンド端子部１０９を備える。保護抵抗１０１はさらに、パッド１００に接続される第１端子部１０７と、内部回路側に接続される第２端子部１０８をもつ。簡単のため図示していないが、各端子部１０７、１０８はタングステンなどの金属材料で構成されるコンタクト、拡散層１０１の表面に形成され、コンタクトと拡散層とを低抵抗で接続するシリサイド領域と、シリサイド領域の下層の拡散層とを含む。図１に示す通り、第１端子部１０７の底面、すなわちＰ型の拡散層の底面は、同じＰ型ウェル１０５に接し、さらにＰ型ウェル１０５の底面はフローティングのＮ型ウェル１０６に接している。Ｎ型ウェル１０６はＰ型シリコン基板１０４内に形成されている。また、Ｎ型ウェル１０６は電源やグラウンドに接続しないフローティング状態にしてある。拡散層１０１の不純物濃度はＰ型ウェル１０６やＮ型ウェル１０７よりも２〜３桁程度高く、一般的には１０＾１８〜１０＾２０／ｃｍ＾３程度である。   Embodiments of the present invention will be described below with reference to the drawings. A semiconductor chip constituting a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a sectional view of the protective resistance of the semiconductor chip according to the first embodiment. FIG. 2 is an equivalent circuit diagram of the protective resistor of FIG. The configuration of the semiconductor chip in this embodiment will be described with reference to FIG. The semiconductor chip in this embodiment includes a pad 100, a protective resistor 101 made of a P-type diffusion layer, a field oxide film 102, an internal circuit 103, a P-type silicon substrate 104, a P-type well 105, an N-type well 106, and a ground terminal. Part 109 is provided. The protective resistor 101 further has a first terminal portion 107 connected to the pad 100 and a second terminal portion 108 connected to the internal circuit side. Although not shown for simplicity, each of the terminal portions 107 and 108 is a contact made of a metal material such as tungsten, formed on the surface of the diffusion layer 101, and a silicide region that connects the contact and the diffusion layer with low resistance. And a diffusion layer below the silicide region. As shown in FIG. 1, the bottom surface of the first terminal portion 107, that is, the bottom surface of the P-type diffusion layer is in contact with the same P-type well 105, and the bottom surface of the P-type well 105 is in contact with the floating N-type well 106. . N-type well 106 is formed in P-type silicon substrate 104. The N-type well 106 is in a floating state that is not connected to a power source or ground. The impurity concentration of the diffusion layer 101 is about two to three orders of magnitude higher than that of the P-type well 106 and the N-type well 107, and is generally about 10 ^ 18 to 10 ^ 20 / cm ^ 3.

本実施例のノイズ印加時の動作について図２を用いて説明する。図２は図１の保護抵抗の等価的な回路図である。パッド１００と内部回路１０３との間に直列に拡散層抵抗１０１が接続される。また、図１の拡散層抵抗１０１と基板１０４との間には抵抗２００、ダイオード２０１とダイオード２０２が直列に接続される。ここで抵抗２００は、Ｐ型拡散層１０１とＮ型ウェル１０６との間に形成されるＰ型ウェル１０６の寄生抵抗、ダイオード２０１は図１のＰ型ウェル１０６とＮ型ウェル１０７との間の寄生ダイオード、ダイオード２０２は図１のＮ型ウェル１０７とＰ型基板１０４との間の寄生ダイオードである。ダイオード２０１とダイオード２０２は互いに極性が逆になるように接続される。パッド１００に正のノイズ電圧ＶＳＵＧが印加されると、パッド１００から内部回路１０３に向かう方向に保護抵抗１０１に電流が流れる。このとき保護抵抗１０１によってノイズのエネルギーがジュール熱として消費され、また、内部回路に向かって電流が流れることで内部回路の電圧上昇が抑制されるため、内部回路が保護される。ノイズ電圧ＶＳＵＧが更に上昇し、ダイオード２０２のブレイクダウン電圧ＶＭＡＸ２を超えると、保護抵抗の第１の端子部１０７付近から基板に向かって電流（以下、ブレイクダウン電流と称する）が流れるが、抵抗２００によって電流が制限されるため、パッド１００と第１の端子部１０７を接続するコンタクトやダイオード２０１、２０２のＰＮ接合部が保護される。   The operation when applying noise in this embodiment will be described with reference to FIG. FIG. 2 is an equivalent circuit diagram of the protective resistor of FIG. A diffusion layer resistor 101 is connected in series between the pad 100 and the internal circuit 103. A resistor 200, a diode 201, and a diode 202 are connected in series between the diffusion layer resistor 101 and the substrate 104 in FIG. Here, the resistor 200 is a parasitic resistance of the P-type well 106 formed between the P-type diffusion layer 101 and the N-type well 106, and the diode 201 is between the P-type well 106 and the N-type well 107 of FIG. A parasitic diode, diode 202, is a parasitic diode between the N-type well 107 and the P-type substrate 104 in FIG. The diode 201 and the diode 202 are connected so that their polarities are opposite to each other. When a positive noise voltage VSUG is applied to the pad 100, a current flows through the protective resistor 101 in a direction from the pad 100 toward the internal circuit 103. At this time, noise energy is consumed as Joule heat by the protective resistor 101, and a current flows toward the internal circuit to suppress an increase in voltage of the internal circuit, thereby protecting the internal circuit. When the noise voltage VSUG further rises and exceeds the breakdown voltage VMAX2 of the diode 202, a current (hereinafter referred to as a breakdown current) flows from the vicinity of the first terminal portion 107 of the protective resistor toward the substrate. As a result, the current is limited, so that the contact connecting the pad 100 and the first terminal 107 and the PN junction of the diodes 201 and 202 are protected.

パッド１００に負のノイズ電圧―ＶＳＵＧが印加されると、内部回路１０３からパッドに向かう方向に保護抵抗１０１に電流が流れる。このとき保護抵抗１０１によってノイズのエネルギーがジュール熱として消費され、また、保護抵抗１０１をパッド向かって電流が流れることで内部回路の電圧低下が抑制されるため、内部回路が保護される。ノイズ電圧―ＶＳＵＧが更に低下し、ダイオード２０１のブレイクダウン電圧ＶＭＡＸ１を超えると、基板から保護抵抗の第１の端子部１０７付近に向かってブレイクダウン電流が流れるが、抵抗２００によって電流が制限されるため、パッド１００と第１の端子部１０７を接続するコンタクトやダイオード２０１、２０２のＰＮ接合部が保護される。   When a negative noise voltage −VSUG is applied to the pad 100, a current flows through the protective resistor 101 in a direction from the internal circuit 103 toward the pad. At this time, noise energy is consumed as Joule heat by the protective resistor 101, and a current flows through the protective resistor 101 toward the pad to suppress a voltage drop of the internal circuit, so that the internal circuit is protected. When the noise voltage-VSUG further decreases and exceeds the breakdown voltage VMAX1 of the diode 201, a breakdown current flows from the substrate toward the vicinity of the first terminal portion 107 of the protective resistor, but the current is limited by the resistor 200. Therefore, the contact connecting the pad 100 and the first terminal portion 107 and the PN junction portion of the diodes 201 and 202 are protected.

ダイオード２０１、２０２のブレイクダウン電圧ＶＭＡＸ１、ＶＭＡＸ２は高いほうが望ましい。これは、より絶対値の高いノイズ電圧ＶＳＵＧが印加されてもブレイクダウン電流が流れないからである。いま、理想的なＰＮ接合のブレイクダウン電圧ＢＶは、不純物濃度を用いて以下の式から算出できる（Ｐａｕｌ Ｒ．Ｇｒａｙ、Ｒｏｂｅｒｔ Ｇ．Ｍｅｙｅｒ、Ａｎａｌｙｓｉｓ ａｎｄ Ｄｅｓｉｇｎ ｏｆ Ａｎａｌｏｇ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔｅｓ Ｓｅｃｏｎｄ Ｅｄｉｔｉｏｎ）。   It is desirable that the breakdown voltages VMAX1, VMAX2 of the diodes 201, 202 are higher. This is because a breakdown current does not flow even when a noise voltage VSUG having a higher absolute value is applied. Now, the ideal breakdown voltage BV of the PN junction can be calculated from the following equation using the impurity concentration (Paul R. Gray, Robert G. Meyer, Analysis and Design of Analyzed Circuits Second Edition).

Figure 2017005179
Figure 2017005179

ここで、εはシリコンの誘電率、ＮＡはアクセプタ濃度、ＮＤはドナー濃度、ｑは電荷素量、εｃｒｉｔはアバランシェ降伏が起こるのに必要な空乏層電界である。数１からわかるとおり、不純物濃度が薄いほどブレイクダウン電圧ＢＶが高くなる。従って、従来技術のようにＰ＋拡散層とＮウェルとの間の寄生ダイオードに比べると、拡散層よりも濃度の薄いＰウェルとＮウェルとの間に形成されたダイオード２０１のほうが耐圧が高くなり、負の電圧ノイズに対してより信頼性の高い保護抵抗が実現できる。たとえば、拡散層１０１の不純物濃度を１０＾１９／ｃｍ＾３、Ｐウェル１０５の不純物濃度を１０＾１６／ｃｍ＾３、Ｎウェル１０６の不純物濃度を１０＾１６／ｃｍ＾３と仮定して（１）式を計算すると、Ｐウェルがない場合のブレイクダウン電圧が２９Ｖとなるのに対し、Ｐウェルを追加すると５９Ｖとなり、２倍程度耐圧が向上される。 Here, epsilon is the dielectric constant of silicon, the N A acceptor concentration, N D is the donor concentration, q is the elementary charge, epsilon crit is the depletion layer electric field required for avalanche breakdown occurs. As can be seen from Equation 1, the lower the impurity concentration, the higher the breakdown voltage BV. Therefore, compared to the parasitic diode between the P + diffusion layer and the N well as in the prior art, the diode 201 formed between the P well and the N well having a lower concentration than the diffusion layer has a higher breakdown voltage. A more reliable protection resistance against negative voltage noise can be realized. For example, assuming that the impurity concentration of diffusion layer 101 is 10 ^ 19 / cm ^ 3, the impurity concentration of P well 105 is 10 ^ 16 / cm ^ 3, and the impurity concentration of N well 106 is 10 ^ 16 / cm ^ 3. When the equation (1) is calculated, the breakdown voltage when there is no P-well is 29V, whereas when the P-well is added, it becomes 59V, and the breakdown voltage is improved about twice.

本実施例における半導体チップの効果を説明する。第１の効果は、拡散抵抗１０１と基板１０４との間にウェル抵抗２００が接続されることで、ブレイクダウン電流が抑制され、第１端子部１０７のコンタクトやダイオード２０１、２０２に流れる電流が抑制されるため、ノイズに対して保護抵抗１０１が破壊されにくくなると同時に、コンタクトの本数も少なくて済むため、より省面積で信頼性の高い保護抵抗を提供できる。第２の効果は、ダイオード２０１の耐圧が向上するため、より絶対値の高い負電圧ノイズに対しても保護機能を提供できる点である。   The effect of the semiconductor chip in this embodiment will be described. The first effect is that the well resistor 200 is connected between the diffused resistor 101 and the substrate 104, so that the breakdown current is suppressed, and the current flowing through the contact of the first terminal portion 107 and the diodes 201 and 202 is suppressed. Therefore, the protective resistor 101 is less likely to be destroyed by noise, and at the same time, the number of contacts can be reduced, so that it is possible to provide a protective resistor with higher area and higher reliability. The second effect is that since the withstand voltage of the diode 201 is improved, a protection function can be provided even for negative voltage noise having a higher absolute value.

図４は第１実施例をなす半導体チップの保護抵抗の変形例である。第１端子部１０７の周辺において、Ｐウェル１０５の突き出し量４０１をＰウェル１０５の深さ４０２以上とし、Ｎウェルの突き出し量４００をＮウェルの深さ４０３以上としたことを特徴とする。ここで、Ｐウェル１０５の突き出し量４０１とは、拡散層のエッジ４０４に対するＰウェルのエッジ４０５の水平方向のはみ出し距離であり、同様にＮウェル１０６の突き出し量４００とは、Ｐウェルのエッジ４０５に対するＮウェル１０６のエッジ４０６の水平方向のはみ出し距離である。また、Ｐウェル１０５の深さとは、拡散層１０１の底面からＰウェル１０５の底面までの距離と定義し、Ｎウェルの深さとは、Ｐウェル１０５からＮウェル１０６の底面までの距離と定義する。かかる構成によれば、Ｐ＋拡散層１０５とＮウェル１０６との間に接続されたＰウェルの寄生抵抗２００の抵抗値が高くなりブレイクダウン電流が低減されるとともに、Ｎウェル１０６中の水平方向の電界が緩和されるためより保護抵抗のノイズへの耐性が向上し、より信頼性の高い半導体チップを提供できる。   FIG. 4 shows a modification of the protective resistance of the semiconductor chip according to the first embodiment. In the vicinity of the first terminal portion 107, the protrusion amount 401 of the P well 105 is set to a depth 402 or more of the P well 105, and the protrusion amount 400 of the N well is set to a depth 403 or more of the N well. Here, the protruding amount 401 of the P well 105 is a horizontal protruding distance of the edge 405 of the P well with respect to the edge 404 of the diffusion layer. Similarly, the protruding amount 400 of the N well 106 is the edge 405 of the P well. Is the horizontal protrusion distance of the edge 406 of the N well 106. The depth of the P well 105 is defined as the distance from the bottom surface of the diffusion layer 101 to the bottom surface of the P well 105, and the depth of the N well is defined as the distance from the P well 105 to the bottom surface of the N well 106. . According to such a configuration, the resistance value of the parasitic resistance 200 of the P well connected between the P + diffusion layer 105 and the N well 106 is increased, the breakdown current is reduced, and the horizontal direction in the N well 106 is reduced. Since the electric field is alleviated, the resistance of the protective resistor to noise is improved, and a more reliable semiconductor chip can be provided.

実施例１において、拡散層１０１、Ｐウェル１０５、Ｎウェル１０６のコーナー部の角を取るとなおよい。より具体的には、図５の変形例に示すとおり、拡散層１０１、Ｐウェル１０５、Ｎウェル１０６の角を曲線で構成する。または、２つ以上の頂点をもつ多角形状とするとよい。かかる構成によれば、ノイズ印加時にコーナー部に電界が集中することによる接合破壊を抑制することができ、より信頼性の高い半導体チップを実現できる。   In the first embodiment, the corners of the diffusion layer 101, the P well 105, and the N well 106 may be cornered. More specifically, as shown in the modification of FIG. 5, the corners of the diffusion layer 101, the P well 105, and the N well 106 are configured by curves. Alternatively, it may be a polygonal shape having two or more vertices. According to such a configuration, it is possible to suppress the junction breakdown due to the concentration of the electric field at the corner portion when noise is applied, and a more reliable semiconductor chip can be realized.

図６は第１実施例をなす半導体チップの保護抵抗の変形例である。第１端子部１０７を構成するシリサイド領域６００の周辺に、シリサイド化しない分離領域６０２を加えたことを特徴とする。シリサイド領域は拡散層の表面に形成されるシリコンと金属の化合物層であり、拡散層と比較すると厚みが薄く、抵抗が低い。パッドに拡散抵抗の耐圧以上のノイズの高電圧が印加されると、シリサイド６００から拡散層１０１、Ｐウェル１０５、Ｎウェル１０６、Ｐ基板１０４、基板コンタクト６０３を経由してブレイクダウン電流が流れる。このとき、電流は、最も抵抗が低くなるように、最短経路６０４に多く流れる。その結果、特にフィールド酸化膜１０２と半導体との界面や、フィールド酸化膜１０２のコーナー部分６０６に特に電流が集中し、接合が破壊される恐れがある。一方、本実施例においては、シリサイドの周辺に分離領域６０２を設けることでブレイクダウン電流の経路が６０５となり、電流集中が緩和されるため、保護抵抗のノイズへの耐性が向上し、より信頼性の高い半導体チップを提供できる。   FIG. 6 shows a modification of the protective resistance of the semiconductor chip according to the first embodiment. An isolation region 602 that is not silicided is added around the silicide region 600 constituting the first terminal portion 107. The silicide region is a compound layer of silicon and metal formed on the surface of the diffusion layer, and has a smaller thickness and lower resistance than the diffusion layer. When a high voltage of noise exceeding the withstand voltage of the diffusion resistance is applied to the pad, a breakdown current flows from the silicide 600 through the diffusion layer 101, the P well 105, the N well 106, the P substrate 104, and the substrate contact 603. At this time, a large amount of current flows through the shortest path 604 so that the resistance becomes the lowest. As a result, current is particularly concentrated on the interface between the field oxide film 102 and the semiconductor and the corner portion 606 of the field oxide film 102, and the junction may be broken. On the other hand, in this embodiment, by providing the isolation region 602 around the silicide, the breakdown current path becomes 605 and the current concentration is reduced, so that the resistance of the protective resistance to noise is improved and the reliability is improved. A high-quality semiconductor chip can be provided.

本発明の第２実施例をなす半導体チップの保護回路を図３により説明する。図３は、第２実施例をなす半導体チップの保護抵抗の断面図である。本実施例における保護抵抗は、第１実施例をなす半導体チップの保護抵抗１０１において、Ｐウェル１０５の範囲を第１端子部１０７周辺に限定したことを特徴とする。すなわち、第１端子部１０７の周辺の縦構造を上層から順にＰ＋拡散層１０１、Ｐウェル１０５、Ｎウェル１０６、Ｐ基板１０４とした一方、第２端子部１０８の周辺の縦構造は上層から順にＰ＋拡散層１０１、Ｎウェル１０６、Ｐ基板１０４とした。ノイズ印加時にかかる電圧は第１端子部１０７が最も高く（負電圧ノイズの場合は最も低く）、従って高い耐圧が必要なのは第１端子部側であるため、かかる構成によっても実施例１と同等の効果が得られる。さらに、拡散層１０１とＰウェル１０５の並走距離が短くなることで、新たに次に示す効果が得られる。一般にＰウェルはＰ＋拡散層抵抗に比べて抵抗値の温度依存性が高い。すなわち、Ｐ＋拡散層とＰウェルの並走距離が長いと、その合成抵抗はＰウェル抵抗の温度依存性の影響を受けやすくなる。その結果、例えば広い温度範囲での動作が要求される車載用の半導体チップにおいて、出力保護抵抗として拡散抵抗を使う場合に、こうした温度依存性は出力信号の誤差を大きくする要因となりうる。実施例２によれば、Ｐウェル抵抗の並走距離が短くなることで相対的にＰウェル抵抗の温度依存性の影響が減少し、広い温度範囲において安定した抵抗値を実現することが可能である。   A semiconductor chip protection circuit according to a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a cross-sectional view of the protective resistance of the semiconductor chip according to the second embodiment. The protective resistor in this embodiment is characterized in that the range of the P well 105 is limited to the periphery of the first terminal portion 107 in the protective resistor 101 of the semiconductor chip in the first embodiment. That is, the vertical structure around the first terminal portion 107 is the P + diffusion layer 101, the P well 105, the N well 106, and the P substrate 104 in order from the upper layer, while the vertical structure around the second terminal portion 108 is in order from the upper layer. The P + diffusion layer 101, the N well 106, and the P substrate 104 were used. The voltage applied at the time of applying noise is highest in the first terminal portion 107 (lowest in the case of negative voltage noise). Therefore, it is the first terminal portion side that requires a high breakdown voltage. An effect is obtained. Furthermore, since the parallel running distance between the diffusion layer 101 and the P well 105 is shortened, the following effects can be newly obtained. In general, the P well has a temperature dependency of the resistance value higher than that of the P + diffusion layer resistance. That is, when the parallel running distance between the P + diffusion layer and the P well is long, the combined resistance is easily affected by the temperature dependence of the P well resistance. As a result, for example, in a vehicle-mounted semiconductor chip that is required to operate in a wide temperature range, such a temperature dependency can cause an error in an output signal when a diffusion resistor is used as an output protection resistor. According to the second embodiment, since the parallel running distance of the P well resistance is shortened, the influence of the temperature dependence of the P well resistance is relatively reduced, and a stable resistance value can be realized in a wide temperature range. is there.

本発明の第３実施例をなす半導体チップの保護回路を図７により説明する。図７は、第３実施例をなす半導体チップの保護抵抗の断面図である。本実施例における保護抵抗は、第１実施例をなす半導体チップの保護抵抗１０１において、パッド１００の直下に保護抵抗１０１の第１端子部１０７を配置したことを特徴とする。パッド１００と拡散層１０１はビア７０２、下位配線層７０１、コンタクト７００、シリサイド６００を介して接続される。かかる構成によれば、面積を要するコンタクト部分とパッドを共用化できるためチップ面積を小さくすることができる。また、パッドに過大な正負ノイズ電圧が印加された場合、パッドから基板に向かって直線的にブレイクダウン電流が流れることで、個々のコンタクト７００やビア７０２に流れる電流が平準化され、特定のコンタクトやビアへの電流集中を抑制できるため、コンタクトやビアのノイズへの耐性が向上する。別の作用として、拡散抵抗１０１とパッド１００が最短距離で接続されるため、ノイズ印加時に拡散抵抗で発生する熱を、コンタクト７００、配線７０１、ビア７０２、パッド１００といった、熱抵抗の低い金属経路を通ってボンディングワイヤへと逃がすことができる。以上により、より信頼性の高い半導体チップを提供できる。   A semiconductor chip protection circuit according to a third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a sectional view of the protective resistance of the semiconductor chip according to the third embodiment. The protective resistor in the present embodiment is characterized in that the first terminal portion 107 of the protective resistor 101 is arranged immediately below the pad 100 in the protective resistor 101 of the semiconductor chip according to the first embodiment. The pad 100 and the diffusion layer 101 are connected via a via 702, a lower wiring layer 701, a contact 700, and a silicide 600. According to such a configuration, the contact area and the pad that require an area can be shared, so that the chip area can be reduced. In addition, when an excessive positive / negative noise voltage is applied to the pad, a breakdown current flows linearly from the pad toward the substrate, so that the current flowing through each contact 700 or via 702 is leveled and a specific contact is obtained. Since current concentration on the vias and vias can be suppressed, the resistance to contact and via noise is improved. As another effect, since the diffused resistor 101 and the pad 100 are connected at the shortest distance, the heat generated by the diffused resistor when noise is applied is transferred to a metal path having a low thermal resistance, such as the contact 700, the wiring 701, the via 702, and the pad 100. Can pass through to the bonding wire. As described above, a more reliable semiconductor chip can be provided.

図８ならびに図９は第３実施例をなす半導体チップの保護抵抗の変形例である。図８は第３実施例をなす保護抵抗の断面図であり、図９はその上面図を示す。本変形例において、第１端子部１０７は拡散層１０１の中心に配置され、第２端子部１０８は第１端子部の周囲を囲むように拡散層１０１の外周辺に沿って配置されることを特徴とする。かかる構成によれば、抵抗面積の増加を抑制しつつ、ノイズ印加時に高い電圧（負ノイズの場合は低い電圧）が印加される第１端子部１０７とグラウンド電位の基板コンタクト８０１までの距離をとることができ、電界が緩和される。また、ジュール発熱時に最も温度が上がりやすい抵抗の中心部とパッド１００とが最短距離で接続されるため、第３実施例と同様にボンディングワイヤ８０２への放熱によって拡散抵抗の最高到達温度を下げることが可能になる。以上により、より信頼性の高い半導体チップを提供できる。   8 and 9 show modifications of the protective resistance of the semiconductor chip according to the third embodiment. FIG. 8 is a cross-sectional view of a protective resistor according to the third embodiment, and FIG. 9 is a top view thereof. In this modification, the first terminal portion 107 is disposed at the center of the diffusion layer 101, and the second terminal portion 108 is disposed along the outer periphery of the diffusion layer 101 so as to surround the first terminal portion. Features. According to such a configuration, the distance between the first terminal portion 107 to which a high voltage (low voltage in the case of negative noise) is applied and the ground potential substrate contact 801 is increased while suppressing an increase in the resistance area. And the electric field is relaxed. In addition, since the central portion of the resistor whose temperature is most likely to rise during Joule heat generation and the pad 100 are connected at the shortest distance, the maximum temperature of the diffusion resistance is lowered by heat radiation to the bonding wire 802 as in the third embodiment. Is possible. As described above, a more reliable semiconductor chip can be provided.

本発明の第４実施例をなす半導体チップの保護抵抗を図１０から図１２により説明する。図１０は第４実施例をなす半導体チップの保護抵抗の断面図である。本実施例における保護抵抗は、第１実施例をなす半導体チップにおける保護抵抗１０１とパッド１００との間にさらにポリシリコン抵抗１０００を直列に接続したことを特徴とする。図１１は図１０のパッド１００から内部回路１０３までの等価回路図である。本実施例においては、拡散抵抗より耐圧の高いポリシリコン抵抗により、拡散抵抗自体を保護する。具体的には、ノイズ印加時の電圧をポリシリコン抵抗でドロップさせ、第１端子部１０７の電圧を拡散抵抗１０１の耐圧以下に抑制することで、拡散抵抗から基板に向かって大きなブレイクダウン電流が流れて第１端子部周辺が破壊されることを防ぐ。ここで、ポリシリコン抵抗の抵抗値ＲＰが高いほどポリシリコン抵抗での電圧ドロップ幅が増える。一方、吸収エネルギーの観点でいえば拡散抵抗の抵抗値ＲＤが可能な限り高いことが望ましい。なぜなら、ポリシリコン抵抗と拡散層抵抗の吸収エネルギーはそれぞれの抵抗値に比例するからである。拡散抵抗の比率を増やすことでエネルギーの多くを熱逃げのよい拡散抵抗で吸収させることができ、結果として保護抵抗全体の面積を最小化できる。図１２は、ポリシリコン抵抗の抵抗値ＲＰと拡散抵抗の抵抗値ＲＤの比率を変えたときの第１端子部の電圧と、保護抵抗の全体面積とのトレードオフ関係の例を示した図である。ポリシリコン抵抗の抵抗値Ｒ-Ｐの値は、想定される最大ノイズ電圧に対して端子部１０７の値を拡散抵抗の耐圧以下に抑制できる最小限の抵抗値とし、なるべく拡散抵抗の比率を大きくすることが望ましい。このようにすることで、ノイズのエネルギーの大部分は放熱性の高い拡散抵抗で吸収させつつ、拡散抵抗の破壊も防ぐことができる。言い換えれば、高いノイズ耐性を実現しつつ、保護抵抗全体としての面積を最小化することができる。 The protection resistance of the semiconductor chip according to the fourth embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a sectional view of the protective resistance of the semiconductor chip according to the fourth embodiment. The protective resistor in this embodiment is characterized in that a polysilicon resistor 1000 is further connected in series between the protective resistor 101 and the pad 100 in the semiconductor chip of the first embodiment. FIG. 11 is an equivalent circuit diagram from the pad 100 to the internal circuit 103 in FIG. In this embodiment, the diffused resistor itself is protected by a polysilicon resistor having a higher breakdown voltage than the diffused resistor. Specifically, the voltage at the time of applying noise is dropped by a polysilicon resistor, and the voltage of the first terminal portion 107 is suppressed to the breakdown voltage of the diffusion resistor 101 or less, so that a large breakdown current from the diffusion resistor to the substrate is generated. This prevents the surrounding area of the first terminal portion from being broken. Here, as the resistance value R P of the polysilicon resistor is high voltage drop width at polysilicon resistor increases. On the other hand, from the viewpoint of absorbed energy, it is desirable that the resistance value RD of the diffusion resistance is as high as possible. This is because the absorbed energy of the polysilicon resistor and the diffusion layer resistor is proportional to the respective resistance values. By increasing the ratio of the diffusion resistance, most of the energy can be absorbed by the diffusion resistance with good heat escape, and as a result, the area of the entire protection resistance can be minimized. Figure 12 shows an example of a trade-off relationship between the voltage and the overall area of the protection resistance of the first terminal portion when changing the ratio of the resistance value R D of the diffusion resistance and the resistance value R P of the polysilicon resistor FIG. The value of resistance R- P polysilicon resistor, a minimum resistance value which can suppress the value of the terminal part 107 below the breakdown voltage of the diffusion resistance to the maximum noise voltage is assumed, increasing the proportion of possible diffusion resistance It is desirable to do. By doing so, most of the energy of the noise can be absorbed by the diffusion resistor having high heat dissipation, and the destruction of the diffusion resistor can be prevented. In other words, the area of the entire protective resistor can be minimized while realizing high noise resistance.

本発明の第５実施例をなす半導体チップの保護回路を図１３ならびに図１４により説明する。図１３は、第５実施例をなす半導体チップの保護回路である。本実施例における保護回路は、第１実施例をなす半導体チップにおける保護抵抗１０１とパッド１００との間にさらにポリシリコン抵抗１００３とキャパシタ１３０１から構成されるローパスフィルタ１３０２を直列に接続したことを特徴とする。本実施例における保護回路の動作について図１４を用いて説明する。ここでは内部回路１０３から出力された信号が保護抵抗１０１を介してパッドに出力される例を考える。パッド１００から出力される信号をワイヤーハーネスなどの配線で外部の受信機器に伝達する装置の場合、電波環境下に置かれるとワイヤーハーネスを介して出力信号にノイズが重畳される。図１４は、半導体チップの内部回路１０３の出力信号１４００に対して、電波照射によって正弦波が重畳された出力波形１４０２を示している。一般的に電波照射環境下で使うことを想定した装置、例えば、車載用のセンサ装置では、センサの信号を処理して出力する半導体チップとエンジン制御装置（ＥＣＵ）との間がワイヤーハーネスにより接続されており、電波照射によってワイヤーハーネス上の信号にノイズが重畳されても正しくＥＣＵで信号が受信できるよう、ＥＣＵ側にローパスフィルタが搭載されている。このローパスフィルタにより重畳ノイズを除去するため、１４０２のように上下対称の波形が重畳される限りは、ＥＣＵは正しい信号値１４００を受信することができる。しかし、仮にノイズが重畳された出力波形１４０２のピーク電圧が、半導体チップの内部回路１０３の出力端子部とパッド１００に接続された拡散抵抗のブレイクダウン電圧を超えた場合、パッドから出力される信号は１４０３のようにピークがクランプされる。その結果、波形１４０３の平均値は１４０１のように本来の信号値１４００からΔＶだけずれ、ＥＣＵが受け取る信号に誤差が生じる。実施例５をなす半導体チップに含まれるローパスフィルタ１３０２はかかる課題を解決するものである。具体的には、ローパスフィルタ１３０２により重畳波形１４０２の波形のピークを拡散抵抗のブレイクダウン電圧以下に抑制することで、先に述べた平均値ずれを防ぎ、信号をより高精度に送受信できるようになる。ローパスフィルタ１３０２のカットオフ周波数は、内部回路が出力する信号の周波数よりは高く、また、想定される電波の周波数より低く設定することが望ましい。   A semiconductor chip protection circuit according to a fifth embodiment of the present invention will be described with reference to FIGS. FIG. 13 shows a semiconductor chip protection circuit according to the fifth embodiment. The protection circuit in this embodiment is characterized in that a low-pass filter 1302 including a polysilicon resistor 1003 and a capacitor 1301 is further connected in series between the protection resistor 101 and the pad 100 in the semiconductor chip of the first embodiment. And The operation of the protection circuit in this embodiment will be described with reference to FIG. Here, consider an example in which the signal output from the internal circuit 103 is output to the pad via the protective resistor 101. In the case of a device that transmits a signal output from the pad 100 to an external receiving device through wiring such as a wire harness, noise is superimposed on the output signal via the wire harness when placed in a radio wave environment. FIG. 14 shows an output waveform 1402 in which a sine wave is superimposed on the output signal 1400 of the internal circuit 103 of the semiconductor chip by radio wave irradiation. In a device that is generally assumed to be used in a radio wave irradiation environment, for example, an in-vehicle sensor device, a semiconductor chip that processes and outputs a sensor signal and an engine control device (ECU) are connected by a wire harness. A low-pass filter is mounted on the ECU side so that the signal can be correctly received by the ECU even if noise is superimposed on the signal on the wire harness due to radio wave irradiation. Since the superposition noise is removed by this low-pass filter, the ECU can receive a correct signal value 1400 as long as a vertically symmetrical waveform is superimposed as in 1402. However, if the peak voltage of the output waveform 1402 on which noise is superimposed exceeds the breakdown voltage of the diffused resistor connected to the output terminal portion of the internal circuit 103 of the semiconductor chip and the pad 100, a signal output from the pad The peak is clamped like 1403. As a result, the average value of the waveform 1403 is shifted from the original signal value 1400 by ΔV as indicated by 1401, and an error occurs in the signal received by the ECU. The low-pass filter 1302 included in the semiconductor chip according to the fifth embodiment solves this problem. Specifically, by suppressing the peak of the superimposed waveform 1402 below the breakdown voltage of the diffusion resistor by the low-pass filter 1302, the above-described average value deviation can be prevented and signals can be transmitted and received with higher accuracy. Become. The cut-off frequency of the low-pass filter 1302 is preferably set higher than the frequency of the signal output from the internal circuit and lower than the assumed radio wave frequency.

本発明の第６実施例をなす半導体チップの保護回路を図１５により説明する。図１５は、第１実施例をなす半導体チップの保護回路の回路である。本実施例における保護回路は、第１実施例をなす半導体チップにおける保護抵抗１０１から内部回路に至る経路上にクランプ素子としてダイオード１５００を加えたことを特徴とする。かかる構成によれば、ダイオード１５００によりノイズ印加時に内部回路に印加される電圧がクランプされるため、内部回路の保護性能が向上し、より信頼性の高い半導体チップを提供することができる。より好ましくは、ダイオード１５００のブレイクダウン電圧は、拡散抵抗１０１のブレイクダウン電圧より低く設定する。かかる構成によれば、拡散抵抗１０１のブレイクダウンを抑制できる。クランプ素子の種類はダイオードに限定されない。例えば図１６に示すように、ゲートとソースを共通にして高電位側に接続したＰＭＯＳや、ゲートとソースを共通にしてＧＮＤに接続したＧａｔｅ Ｇｒｏｕｎｄｅｄ ＮＭＯＳ (ｇｇＮＭＯＳ)でもよい。また、図１７のようにベースとエミッタを共通にして高電位側につないだＰＮＰバイポーラトランジスタや、ベースとエミッタを共通にしてＧＮＤにつないだＮＰＮバイポーラトランジスタや、バリスタ素子でもよい。クランプ素子の拡散層は、拡散抵抗１０１と共通の拡散層を用いて構成することで保護回路の面積を節約できる。例えば図１８に示すように、拡散層抵抗１０１の拡散層をＮウェル１０６上にまで延長し、クランプトランジスタ１６００のソース端子部として使うことができる。かかる構成によれば、クランプトランジスタ１６００のソース端子部へのコンタクトが不要となり、より省面積な保護回路を実現できる。   A semiconductor chip protection circuit according to a sixth embodiment of the present invention will be described with reference to FIG. FIG. 15 is a circuit diagram of a semiconductor chip protection circuit according to the first embodiment. The protection circuit in this embodiment is characterized in that a diode 1500 is added as a clamp element on the path from the protection resistor 101 to the internal circuit in the semiconductor chip of the first embodiment. According to this configuration, the voltage applied to the internal circuit when noise is applied is clamped by the diode 1500, so that the protection performance of the internal circuit is improved and a more reliable semiconductor chip can be provided. More preferably, the breakdown voltage of the diode 1500 is set lower than the breakdown voltage of the diffusion resistor 101. According to such a configuration, breakdown of the diffused resistor 101 can be suppressed. The type of clamp element is not limited to a diode. For example, as shown in FIG. 16, a PMOS having a common gate and source connected to the high potential side or a gate grounded NMOS (ggNMOS) having a common gate and source connected to GND may be used. Further, as shown in FIG. 17, a PNP bipolar transistor having a base and an emitter connected to the high potential side, an NPN bipolar transistor having a base and an emitter connected to GND, or a varistor element may be used. The area of the protection circuit can be saved by configuring the diffusion layer of the clamp element using the diffusion layer common to the diffusion resistor 101. For example, as shown in FIG. 18, the diffusion layer of the diffusion layer resistor 101 can be extended to the N well 106 and used as the source terminal portion of the clamp transistor 1600. According to such a configuration, a contact to the source terminal portion of the clamp transistor 1600 becomes unnecessary, and a protection circuit with a smaller area can be realized.

本発明の第７実施例をなす半導体チップ１９０３を含むセンサ装置を図１９により説明する。本実施例におけるセンサ装置は、センサエレメント１９０７、半導体チップ１９０３を含む。センサエレメント１９０７は物理量に応じて電気的特性の変化する素子である。図１９ではディスクリートの部品として示したが、半導体チップ１９０３に形成されていてもよい。半導体チップは電源パッド１９００、出力パッド１９０１、グランドパッド１９０２、保護抵抗１９０４および１９０５、内部回路１９０６からなる。半導体チップ１９０３はセンサエレメント１９０７を制御し、センサエレメント１９０７の出力信号を処理して出力パッド１９０１に出力する。保護抵抗１９０４および１９０５はこれまでの実施例に示したものである。電源端子部は保護抵抗１９０４によって、出力端子部は保護抵抗１９０５によって、センサ装置１４００の外部から端子部１９００、１９０１，１９０２に印加される静電気やサージなどのノイズから保護される。かかる構成によれば、ノイズへの耐性を半導体チップ１９０３に持たせることで、半導体チップ１９０３の外付けの保護素子を削減し、センサ装置に含まれるディスクリート部品を削減し、コストを抑えつつセンサ装置の信頼性を高めることができる。   A sensor device including a semiconductor chip 1903 according to a seventh embodiment of the present invention will be described with reference to FIG. The sensor device in this embodiment includes a sensor element 1907 and a semiconductor chip 1903. The sensor element 1907 is an element whose electrical characteristics change according to a physical quantity. Although shown as discrete components in FIG. 19, they may be formed on the semiconductor chip 1903. The semiconductor chip includes a power supply pad 1900, an output pad 1901, a ground pad 1902, protective resistors 1904 and 1905, and an internal circuit 1906. The semiconductor chip 1903 controls the sensor element 1907, processes the output signal of the sensor element 1907, and outputs it to the output pad 1901. The protective resistors 1904 and 1905 are shown in the previous examples. The power supply terminal portion is protected by a protective resistor 1904, and the output terminal portion is protected by a protective resistor 1905 from noise such as static electricity and surge applied to the terminal portions 1900, 1901, and 1902 from the outside of the sensor device 1400. According to this configuration, by providing the semiconductor chip 1903 with noise resistance, the number of external protection elements of the semiconductor chip 1903 can be reduced, the number of discrete components included in the sensor device can be reduced, and the cost of the sensor device can be reduced. Can improve the reliability.

第１実施例から第７実施例に記載した半導体チップの発展形状について図２０で説明する。本発展形状では、内部回路１９０６の他に、吸気管を流れる流体の物理量を検出する物理量検出部２００１がさらに半導体チップ２０００に形成されている。係る構成によれば、物理量を検出する物理量検出部２００１を内部回路１９０６と同一の半導体チップに形成しているので、内部回路１９０６と物理量検出部２００１とを導通するワイヤボンディングが省略可能である。そのため、第１実施例から第７実施例で述べた効果に加えて、小型化および電気的接続部の信頼性が向上することが可能となる。物理量検出部２００１の例としては、詳細な形状は省略するが、静電容量式の湿度検出部、熱式の湿度検出部、歪ゲージを利用した圧力検出部、ダイアフラムに形成される発熱抵抗体を有する熱式の流量検出部が挙げられる。   The developed shape of the semiconductor chip described in the first to seventh embodiments will be described with reference to FIG. In this developed shape, in addition to the internal circuit 1906, a physical quantity detection unit 2001 that detects the physical quantity of the fluid flowing through the intake pipe is further formed in the semiconductor chip 2000. According to such a configuration, since the physical quantity detection unit 2001 that detects the physical quantity is formed on the same semiconductor chip as the internal circuit 1906, wire bonding for connecting the internal circuit 1906 and the physical quantity detection unit 2001 can be omitted. Therefore, in addition to the effects described in the first to seventh embodiments, it is possible to reduce the size and improve the reliability of the electrical connection portion. Although the detailed shape is omitted as an example of the physical quantity detection unit 2001, a capacitive humidity detection unit, a thermal humidity detection unit, a pressure detection unit using a strain gauge, and a heating resistor formed on a diaphragm There is a thermal flow rate detector having

以上これまでに述べた実施例では、Ｐ型のシリコン基板をベースとし、Ｐ型の拡散層抵抗をＰウェル上に形成し、さらにＰウェルをフローティングのＮウェル上に形成する場合を説明したが、各半導体層の極性の組み合わせはこれに限られない。もちろん、Ｎ型のシリコン基板をベースとし、Ｎ型の拡散層抵抗をＮウェル上に形成し、さらにＮウェルをフローティングのＰウェル上に形成しても同様の効果が得られる。   In the above-described embodiments, the case where the P-type silicon substrate is used as a base, the P-type diffusion layer resistance is formed on the P-well, and the P-well is formed on the floating N-well has been described. The combination of polarities of the semiconductor layers is not limited to this. Of course, the same effect can be obtained by using an N-type silicon substrate as a base, forming an N-type diffusion layer resistor on the N-well, and further forming an N-well on the floating P-well.

すなわち、シリコン基板の極性を第一導電型と定義した場合、拡散層抵抗の極性は第一導電型、拡散層抵抗が形成されるウェルの極性は第一導電型、フローティングのウェルの極性は第二導電型と定義可能である。   That is, when the polarity of the silicon substrate is defined as the first conductivity type, the polarity of the diffusion layer resistance is the first conductivity type, the polarity of the well in which the diffusion layer resistance is formed is the first conductivity type, and the polarity of the floating well is the first conductivity type. It can be defined as a two conductivity type.

１００：パッド、１０１：Ｐ＋拡散層、１０２：酸化膜、１０３内部回路、１０４：Ｐ型シリコン基板、１０５：Ｐ型ウェル、１０６：Ｎ型ウェル、１０７：第１端子部、１０８：第２端子部、１０９：ＧＮＤ、２００：ウェル寄生抵抗、２０１、２０２：寄生ダイオード、４００：Ｐウェル突き出し幅、４０１：Ｎウェル突き出し幅、４０２：Ｐウェル深さ、４０３：Ｎウェル深さ、４０４：拡散層のエッジ、４０５Ｐウェルのエッジ、４０６Ｎウェルのエッジ、６００、６０１：シリサイド、６０２：非シリサイド領域、６０３：基板コンタクト、６０４、６０５：ブレイクダウン電流の経路、６０６：フィールド酸化膜のコーナー、７００：コンタクト、７０１：配線、７０２：ビア、８００：配線、８０１：基板コンタクト、８０２：ボンディングワイヤ、１０００、１１００、１３００：ポリシリコン抵抗、１３０１：キャパシタ、１３０２：フィルタ、１４００、１４０１：平均値、１４０２、１４０３：電波ノイズが重畳された出力信号、１５００、１６００、１７００：クランプ素子、１８００：ゲート、１９００：電源パッド、１９０１：入出力パッド、１９０２：ＧＮＤパッド、１９０３、２０００：半導体チップ、１９０４、１９０５：拡散抵抗、１９０６：内部回路、１９０７：センサエレメント、２００１：物理量検出部、ＢＶ：ブレイクダウン電圧、ＧＮＤ：グラウンド、ＶＭＡＸ、ＶＭＡＸ１、ＶＭＡＸ２：耐圧、ＶＳＵＧ：ノイズ電圧、ΔＶ：誤差、ＶＴＲＭ：端子部電圧、ＶＩＮＴ：内部回路のクランプ電圧、ＰＰ、ＰＤ：エネルギー、ＲＰ：ポリシリコン抵抗の抵抗値、ＲＤ：拡散抵抗の抵抗値 100: pad, 101: P + diffusion layer, 102: oxide film, 103 internal circuit, 104: P-type silicon substrate, 105: P-type well, 106: N-type well, 107: first terminal portion, 108: second terminal 109: GND, 200: well parasitic resistance, 201, 202: parasitic diode, 400: P well protruding width, 401: N well protruding width, 402: P well depth, 403: N well depth, 404: diffusion Layer edge, 405P well edge, 406N well edge, 600, 601: silicide, 602: non-silicide region, 603: substrate contact, 604, 605: breakdown current path, 606: field oxide corner, 700 : Contact, 701: wiring, 702: via, 800: wiring, 801: substrate contact, 802 Bonding wire, 1000, 1100, 1300: polysilicon resistance, 1301: capacitor, 1302: filter, 1400, 1401: average value, 1402, 1403: output signal on which radio noise is superimposed, 1500, 1600, 1700: clamp element, 1800: Gate, 1900: Power supply pad, 1901: I / O pad, 1902: GND pad, 1903, 2000: Semiconductor chip, 1904, 1905: Diffusion resistor, 1906: Internal circuit, 1907: Sensor element, 2001: Physical quantity detection unit, BV: breakdown voltage, GND: ground, VMAX, VMAX1, VMAX2: breakdown voltage, VSUG: noise voltage, ΔV: error, VTRM: terminal voltage, VINT: clamp voltage of internal circuit, PP, PD: energy, RP: port Resistance value of silicon resistance, RD: Resistance value of diffusion resistance

Claims (18)

第１導電型の半導体基板と、パッドと、内部回路と、第１導電型の第１のウェルと、第２導電型で、かつ、フローティングの第２のウェルと、第１導電型の拡散抵抗と、を有し、
前記拡散抵抗は、前記パッドおよび前記内部回路と電気的に接続され、
前記第１のウェルは、前記第２のウェルと前記拡散抵抗の間に形成される車載用の半導体チップ First conductivity type semiconductor substrate, pad, internal circuit, first conductivity type first well, second conductivity type and floating second well, first conductivity type diffused resistor And having
The diffused resistor is electrically connected to the pad and the internal circuit,
The first well is an in-vehicle semiconductor chip formed between the second well and the diffused resistor. 前記拡散抵抗は、前記パッド側に接続される第１の端子部と、前記内部回路側に接続される第２の端子部と、を有し、前記第２の端子部は前記第２ウェルに接している請求項１に記載の半導体チップ   The diffused resistor has a first terminal portion connected to the pad side and a second terminal portion connected to the internal circuit side, and the second terminal portion is connected to the second well. The semiconductor chip according to claim 1, which is in contact with the semiconductor chip. 前記拡散抵抗は、前記パッド側に接続される第１の端子部と、前記内部回路側に接続される第２の端子部と、を有し、
前記第１の端子部と前記第２のウェルの間に前記第１のウェルが形成されており、
前記第１のウェルは、前記拡散抵抗よりも短い請求項１に記載の半導体チップ The diffusion resistor has a first terminal portion connected to the pad side and a second terminal portion connected to the internal circuit side,
The first well is formed between the first terminal portion and the second well;
The semiconductor chip according to claim 1, wherein the first well is shorter than the diffusion resistance. 前記第１端子部の外周部から前記第１ウェルの外周部までの水平距離が前記拡散抵抗の底部から前記第１ウェルの底部までの距離以上である請求項２または３に記載の半導体チップ。   4. The semiconductor chip according to claim 2, wherein a horizontal distance from an outer peripheral portion of the first terminal portion to an outer peripheral portion of the first well is equal to or greater than a distance from a bottom portion of the diffusion resistor to a bottom portion of the first well. 前記第１ウェルの外周部から前記第２ウェルの外周部までの水平距離が前記第１ウェルの底部から前記第２ウェルの底部までの距離以上であることを特徴とする請求項１乃至４の何れかに記載の半導体チップ The horizontal distance from the outer periphery of the first well to the outer periphery of the second well is equal to or greater than the distance from the bottom of the first well to the bottom of the second well. Semiconductor chip according to any 前記拡散層と前記第１ウェルと前記第２ウェルのうち少なくともどちらかのコーナーが多角形状か曲線形状であることを特徴とする請求項１乃至５の何れかに記載の半導体チップ   6. The semiconductor chip according to claim 1, wherein at least one of the corners of the diffusion layer, the first well, and the second well has a polygonal shape or a curved shape. 前記第１の端子部は第１のシリサイド領域を有し、前記第２の端子部は第２のシリサイド領域を有し、前記第１のシリサイド領域と前記第２のシリサイド領域の少なくとも一方の周囲がシリサイド化されていない拡散層により囲まれている請求項２または３に記載の半導体チップ   The first terminal portion has a first silicide region, the second terminal portion has a second silicide region, and surrounds at least one of the first silicide region and the second silicide region. 4. The semiconductor chip according to claim 2, wherein the semiconductor chip is surrounded by a non-silicided diffusion layer. 前記第１の端子部は前記パッドの下部に配置されている請求項２または３に記載の車載用の半導体チップ   The in-vehicle semiconductor chip according to claim 2 or 3, wherein the first terminal portion is disposed below the pad. 前記第２の端子部は前記第１の端子部の周囲を囲むように配置される請求項８に記載の半導体チップ   The semiconductor chip according to claim 8, wherein the second terminal portion is disposed so as to surround a periphery of the first terminal portion. 前記パッドと前記拡散抵抗との電気的経路の間に、ポリシリコンおよび/または高抵抗金属を有する請求項乃至３の何れかに記載の半導体チップ   4. The semiconductor chip according to claim 3, comprising polysilicon and / or a high-resistance metal between electrical paths between the pad and the diffused resistor. 前記パッドと前記拡散抵抗との間に減衰フィルタが接続される請求項１乃至３の何れかに記載の半導体チップ   4. The semiconductor chip according to claim 1, wherein an attenuation filter is connected between the pad and the diffused resistor. 前記減衰フィルタのカットオフ周波数は、前記内部回路から前記パッドに出力される信号の周波数よりも高い請求項１１に記載の半導体チップ   The semiconductor chip according to claim 11, wherein a cutoff frequency of the attenuation filter is higher than a frequency of a signal output from the internal circuit to the pad. 前記拡散抵抗と前記内部回路とを接続する配線にクランプ素子が接続される請求項１乃至３の何れかに記載の半導体チップ   4. The semiconductor chip according to claim 1, wherein a clamp element is connected to a wiring that connects the diffused resistor and the internal circuit. 前記クランプ素子はＰ型のＭＯＳトランジスタであり、
前記Ｐ型のＭＯＳトランジスタのゲート端子部とソース端子部が前記第１の配線に接続され、ドレイン端子部がグラウンドに接続され、
前記ソース端子部は、前記第１導電型の拡散層と共通の拡散層で構成される請求項１３に記載の半導体チップ The clamp element is a P-type MOS transistor,
The gate terminal portion and the source terminal portion of the P-type MOS transistor are connected to the first wiring, the drain terminal portion is connected to the ground,
The semiconductor chip according to claim 13, wherein the source terminal portion includes a diffusion layer shared with the diffusion layer of the first conductivity type. 前記クランプ素子はＮ型のＭＯＳトランジスタであり、
前記Ｎ型のＭＯＳトランジスタのドレイン端子部が前記第１の配線に接続され、ゲート端子部とドレイン端子部がグラウンドに接続され、
前記ドレイン端子部は、前記第１導電型の拡散層と共通の拡散層で構成される請求項１３に記載の半導体チップ The clamp element is an N-type MOS transistor,
The drain terminal portion of the N-type MOS transistor is connected to the first wiring, the gate terminal portion and the drain terminal portion are connected to the ground,
The semiconductor chip according to claim 13, wherein the drain terminal portion is formed of a diffusion layer common to the diffusion layer of the first conductivity type. 物理量に応じて電気的特性の変化するセンサエレメントと、請求項１乃至１５の何れかに記載の半導体チップと、を有する車載用センサ装置。   An in-vehicle sensor device comprising: a sensor element whose electrical characteristics change according to a physical quantity; and the semiconductor chip according to claim 1. 請求項１乃至１５の何れかに記載の半導体チップを備え、
前記半導体チップは、物理量に応じて電気的特性の変化する検出部がさらに形成されている
車載用センサ装置。 A semiconductor chip according to any one of claims 1 to 15,
The semiconductor chip is an in-vehicle sensor device in which a detection unit whose electrical characteristics change according to a physical quantity is further formed. 請求項１乃至１５の何れかに記載の半導体チップを有する車載用電子装置。   An in-vehicle electronic device comprising the semiconductor chip according to claim 1.
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