JP2020085500A - Humidity detector and method for determining failures - Google Patents

Abstract

To increase the flatness of a parallel flat-type electrode formed above a heating unit.SOLUTION: The humidity detector includes: a semiconductor substrate; a heating unit formed by an impurity diffusion layer in the semiconductor substrate; a lower electrode located above the heating unit with an insulating film in between; a humidity sensing film covering the lower electrode; and an upper electrode formed on the humidity sensing film.SELECTED DRAWING: Figure 9

Description

The present invention relates to a humidity detection device and a failure determination method.

As the humidity detecting device, there is an electrostatic capacitance type device using a moisture sensitive film formed of a polymer material whose dielectric constant changes according to the amount of absorbed water, as a dielectric. In this capacitance type humidity detecting device, a humidity sensitive film is arranged between the electrodes, and the humidity (relative humidity) is obtained by measuring the capacitance between the electrodes.

A comb-teeth type or a parallel plate type is known as an electrode structure of a capacitance type humidity detecting device. The comb-teeth type is a structure in which a pair of opposing comb-teeth electrodes are provided on the same plane, and a moisture sensitive film is provided on the pair of comb-teeth electrodes. The parallel plate type is a structure in which a moisture sensitive film is provided between a lower electrode formed on a substrate and an upper electrode provided so as to face the lower electrode.

Further, it is known that a capacitance type humidity detecting device is provided with a heating unit for adjusting the amount of water in a moisture sensitive film by heating (see, for example, Patent Document 1). Patent Document 1 proposes that a wiring layer formed of polysilicon or the like is used as a heating resistor to form a heating portion on a substrate.

JP, 2006-234576, A

However, in the case where the electrode structure is a parallel plate type, when the heating part is formed on the substrate as described in Patent Document 1, the electrode formed by stacking the insulating film above the heating part is the heating part. Shape affects the flatness. For example, when the heating portion is formed in a bellows shape as described in Patent Document 1, it is conceivable that the electrode has an uneven shape.

As described above, when the flatness of the electrodes is reduced, the distance between the electrodes becomes uneven, which not only increases manufacturing variations in capacitance, but also decreases the humidity detection accuracy.

An object of the present invention is to improve the flatness of a parallel plate type electrode formed above a heating part.

The disclosed technology includes a semiconductor substrate, a heating portion formed of an impurity diffusion layer in the semiconductor substrate, a lower electrode formed above the heating portion via an insulating film, and a moisture-sensitive material covering the lower electrode. A humidity detecting device having a film and an upper electrode formed on the moisture sensitive film.

According to the present invention, it is possible to improve the flatness of the parallel plate type electrode formed above the heating portion.

It is a figure which illustrates the schematic structure of the humidity detection apparatus which concerns on one Embodiment of this invention. It is sectional drawing which shows roughly the cross section along the AA line in FIG. It is a top view of the humidity detecting device in a state where the mold resin is removed. It is a schematic plan view which shows the structure of a sensor chip. It is a circuit diagram which illustrates the structure of an ESD protection circuit. It is a figure which illustrates the layer structure of the NMOS transistor which comprises an ESD protection circuit. It is a circuit diagram which illustrates the composition of a humidity primary detecting element. It is a circuit diagram which illustrates the structure of a temperature detection part. It is a schematic sectional drawing for demonstrating the element structure of a sensor chip. It is a top view which illustrates the shape of a lower electrode and an upper electrode. It is a top view which illustrates the shape of the n-type diffusion layer which comprises a heating part. It is a block diagram which illustrates the functional composition of an ASIC chip. It is a flowchart explaining a failure determination process. It is a figure which shows the example which used the resistance type temperature sensor for the temperature detection part.

Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In each drawing, the same components may be denoted by the same reference numerals, and duplicate description may be omitted. In the present disclosure, the humidity in the case where it is simply described as humidity means relative humidity.

[Schematic configuration]
A configuration of the humidity detecting device 10 according to the embodiment of the present invention will be described.

FIG. 1 is a diagram illustrating a schematic configuration of a humidity detection device 10 according to an embodiment of the present invention. FIG. 1A is a plan view of the humidity detecting device 10 as viewed from above. FIG. 1B is a bottom view of the humidity detecting device 10 as viewed from below. FIG. 1C is a side view of the humidity detecting device 10 as viewed from the lateral direction. Further, FIG. 2 is a sectional view schematically showing a section taken along the line AA in FIG.

The humidity detecting device 10 has a substantially rectangular planar shape, and one of two opposing two sides is parallel to the X direction and the other is parallel to the Y direction. The X direction and the Y direction are orthogonal to each other. Further, the humidity detecting device 10 has a thickness in the Z direction orthogonal to the X direction and the Y direction. The planar shape of the humidity detecting device 10 is not limited to the rectangular shape, and may be a circle, an ellipse, a polygon, or the like.

The humidity detection device 10 includes a sensor chip 20 as a first semiconductor chip, an ASIC (Application Specific Integrated Circuit) chip 30 as a second semiconductor chip, a mold resin 40, and a plurality of lead terminals 41.

The sensor chip 20 is stacked on the ASIC chip 30 via a first DAF (Die Attach Film) 42. That is, the sensor chip 20 and the ASIC chip 30 have a stack structure.

The sensor chip 20 and the ASIC chip 30 are electrically connected by a plurality of first bonding wires 43. The ASIC chip 30 and the lead terminals 41 are electrically connected by the second bonding wires 44.

The thus laminated sensor chip 20 and ASIC chip 30, the plurality of first bonding wires 43, the plurality of second bonding wires 44, and the plurality of lead terminals 41 are sealed by the mold resin 40 and packaged. ing. This package method is called a PLP (Plating Lead Package) method.

As will be described later in detail, the second DAF 45 used for packaging by the PLP method remains on the lower surface of the ASIC chip 30. The second DAF 45 has a role of insulating the lower surface of the ASIC chip 30. The second DAF 45 and a plurality of lead terminals 41 are exposed on the lower surface of the humidity detecting device 10.

Each lead terminal 41 is made of nickel or copper. The first DAF 42 and the second DAF 45 are each made of an insulating material made of a mixture of resin and silica. The mold resin 40 is a light-shielding black resin such as an epoxy resin containing a mixture of carbon black and silica.

An opening 50 for exposing a part of the sensor chip 20 from the molding resin 40 is formed on the upper surface side of the humidity detecting device 10. The opening 50 has, for example, a tapered wall portion, and the opening area becomes smaller as it goes downward. Of the openings 50, the lowermost portion where the sensor chip 20 is actually exposed is called an effective opening 51.

When forming the opening 50, the mold is pressed against the sensor chip 20 and sealed with the mold resin 40. At this time, the pressing force applied to the sensor chip 20 and the ASIC chip 30 by the mold may cause damage such as chip cracking. In order to prevent this damage, the thickness T1 of the sensor chip 20 and the thickness T2 of the ASIC chip 30 are preferably 200 μm or more, respectively.

FIG. 3 is a plan view of the humidity detecting device 10 with the mold resin 40 removed. As shown in FIG. 3, each of the sensor chip 20 and the ASIC chip 30 has a substantially rectangular planar shape, and has two sides parallel to the X direction and two sides parallel to the Y direction. The sensor chip 20 is smaller than the ASIC chip 30 and is stacked on the surface of the ASIC chip 30 via the first DAF 42.

The sensor chip 20 is provided with a humidity detecting section 21, a temperature detecting section 22, and a heating section 23 in a region exposed by the effective opening 51. The heating unit 23 is formed on the lower surface side of the humidity detecting unit 21 so as to cover the formation region of the humidity detecting unit 21. That is, the area of the heating unit 23 is larger than that of the humidity detecting unit 21. As described above, the mold resin 40 as the sealing member seals the sensor chip 20 and the like with the humidity detecting unit 21 and the temperature detecting unit 22 exposed.

In addition, a plurality of bonding pads (hereinafter, simply referred to as pads) 24 are formed at the ends of the sensor chip 20. In this embodiment, six pads 24 are formed. The pad 24 is formed of, for example, aluminum or aluminum silicon alloy (AlSi).

The ASIC chip 30 is a semiconductor chip for signal processing and control, and has a humidity measurement processing unit 31, a temperature measurement processing unit 32, a heating control unit 33, and a failure determination unit 34 (all of which are shown in FIG. 12) described later. Has been done.

Further, a plurality of first pads 35 and a plurality of second pads 36 are provided in a region of the surface of the ASIC chip 30 which is not covered with the sensor chip 20. The first pad 35 and the second pad 36 are made of, for example, aluminum or aluminum silicon alloy (AlSi).

The first pad 35 is connected to the corresponding pad 24 of the sensor chip 20 via the first bonding wire 43. The second pad 36 is connected to the corresponding lead terminal 41 via the second bonding wire 44. The lead terminal 41 is arranged around the ASIC chip 30.

At the time of manufacturing, the mounting position of the ASIC chip 30 is determined with the lead terminal 41 as a reference. The mounting position of the sensor chip 20 on the ASIC chip 30 is determined based on either the position of the ASIC chip 30 or the lead terminal 41. The opening 50 is formed by a transfer molding method or the like using a mold, and the position of this mold is determined with the lead terminal 41 as a reference.

Reference numeral 25 shown in FIG. 3 represents a formation permissible region of the humidity detecting portion 21 and the temperature detecting portion 22 on the sensor chip 20. The formation allowance region 25 is formed so as to be surely exposed from the opening 50 even when the largest displacement occurs between the ASIC chip 30, the sensor chip 20, and the mold during mounting. It is set within 50 forming regions. If the humidity detecting portion 21 and the temperature detecting portion 22 are formed in the formation permitting region 25, the humidity detecting portion 21 and the temperature detecting portion 22 are surely exposed from the opening 50 regardless of the positional deviation.

[Configuration of sensor chip]
Next, the configuration of the sensor chip 20 will be described.

FIG. 4 is a schematic plan view showing the configuration of the sensor chip 20. The pad 24 described above is a terminal used for voltage application from the outside and potential detection. In FIG. 4, the plurality of pads 24 shown in FIG. 3 are shown separately from the pads 24a to 24f. When it is not necessary to distinguish the pads 24a to 24f, they are simply referred to as the pads 24.

The pad 24a functions as a ground electrode terminal (GND) that is grounded to the ground potential. The pad 24a is electrically connected to each part such as the temperature detecting part 22 and the heating part 23 via a wiring or a substrate.

The pad 24b is a lower electrode terminal (BOT) electrically connected to the lower electrode 83 of the humidity detector 21. The pad 24b is used to supply a drive voltage to the lower electrode 83. The pad 24c is a humidity detection terminal (HMD) electrically connected to the upper electrode 84 of the humidity detection unit 21. The pad 24c is used to obtain a relative humidity detection signal from the upper electrode 84. The pad 24d is a reference electrode terminal (REF) electrically connected to the reference electrode 82 of the humidity detector 21. The pad 24d is used to acquire a reference signal for humidity detection from the reference electrode 82.

The pad 24e is a temperature detection terminal (TMP) electrically connected to the temperature detection unit 22. The pad 24e is used to acquire a temperature detection signal. The pad 24f is a heating terminal (HT) electrically connected to the heating unit 23. The pad 24f is used to supply a drive voltage for driving the heating unit 23.

An electrostatic discharge (ESD) protection circuit 60 is connected to each of the pads 24b to 24f other than the pad 24a. Each ESD protection circuit 60 is connected between each of the pads 24b to 24f as input terminals or output terminals and the pad 24a as a ground electrode terminal. In the present embodiment, the ESD protection circuit 60 is composed of one diode 61. The diode 61 has an anode side connected to the pad 24a and a cathode side connected to any of the pads 24b to 24f.

The ESD protection circuit 60 is preferably arranged near the pads 24b to 24f so as to be separated from the effective opening 51 as much as possible. Since the ESD protection circuit 60 is covered with the mold resin 40, unnecessary charge generation due to the photoelectric effect does not occur.

[Configuration of ESD protection circuit]
Next, the configuration of the ESD protection circuit 60 will be described.

FIG. 5 is a circuit diagram illustrating the configuration of the ESD protection circuit 60. As shown in FIG. 5, the diode 61 forming the ESD protection circuit 60 is formed of, for example, an N-channel MOS (Metal-Oxide-Semiconductor) transistor (hereinafter referred to as an NMOS transistor). Specifically, the diode 61 is a NMOS transistor whose source, gate, and back gate are short-circuited (so-called diode connection). This short circuit portion functions as an anode. The drain of this NMOS transistor functions as a cathode.

FIG. 6 is a diagram illustrating a layered structure of an NMOS transistor included in the ESD protection circuit 60. This NMOS transistor has two n-type diffusion layers 71 and 72 formed on the surface layer of a p-type semiconductor substrate 70 for forming the sensor chip 20, a contact layer 73, and a gate electrode 74. The gate electrode 74 is formed on the surface of the p-type semiconductor substrate 70 via a gate insulating film 75. The gate electrode 74 is arranged between the two n-type diffusion layers 71 and 72.

For example, the n-type diffusion layer 71 functions as a source and the n-type diffusion layer 72 functions as a drain. The contact layer 73 is a low resistance layer (p-type diffusion layer) for electrical connection with the p-type semiconductor substrate 70 as a back gate. The n-type diffusion layer 71, the gate electrode 74, and the contact layer 73 are commonly connected and short-circuited. This short circuit portion functions as an anode, and the n-type diffusion layer 72 functions as a cathode.

The p-type semiconductor substrate 70 is, for example, a p-type silicon substrate. The gate electrode 74 is formed of metal or polycrystalline silicon (polysilicon). The gate insulating film 75 is formed of, for example, an oxide film such as silicon dioxide.

[Configuration of humidity detector]
Next, the configuration of the humidity detector 21 will be described.

FIG. 7 is a circuit diagram illustrating the configuration of the humidity detector 21. As shown in FIG. 7, the humidity detecting section 21 has a humidity detecting capacitor 80 and a reference capacitor 81.

One electrode (lower electrode 83) of the humidity detecting section 21 is connected to the pad 24b as a lower electrode terminal. The other electrode (upper electrode 84) of the humidity detecting portion 21 is connected to the pad 24c as a humidity detecting terminal. One electrode of the reference capacitor 81 is common with one electrode (lower electrode 83) of the humidity detecting section 21. The other electrode (reference electrode 82) of the reference capacitor 81 is connected to the pad 24d as a reference electrode terminal.

The humidity detecting capacitor 80 is provided with a moisture sensitive film 86 described below between the electrodes. The moisture sensitive film 86 is formed of a polymer material such as polyimide that absorbs moisture in the air and has a dielectric constant that changes according to the amount of absorbed moisture. Therefore, the capacitance of the humidity detecting capacitor 80 changes according to the amount of water absorbed by the moisture sensitive film 86.

The reference capacitor 81 is provided with a second insulating film 111 (see FIG. 9) described later between the electrodes. The second insulating film 111 is formed of an insulating material such as silicon dioxide (SiO ₂ ) that does not absorb moisture. Therefore, the capacitance of the reference capacitor 81 does not change, or even if it changes, it is very small.

The amount of water contained in the moisture sensitive film 86 corresponds to the humidity around the humidity detecting device 10. Therefore, by detecting the difference between the capacitance of the humidity detecting capacitor 80 and the capacitance of the reference capacitor 81. , Relative humidity can be measured. The measurement of the relative humidity is performed by the humidity measurement processing unit 31 (see FIG. 12) in the ASIC chip 30 based on the potential of the pad 24c as the humidity detecting terminal and the potential of the pad 24d as the reference electrode terminal. ..

[Configuration of temperature detector]
Next, the configuration of the temperature detection unit 22 will be described.

FIG. 8 is a circuit diagram illustrating the configuration of the temperature detection unit 22. The temperature detection unit 22 is a bandgap type temperature sensor that detects a temperature by utilizing a characteristic in which the electrical characteristics of the semiconductor bandgap change proportionally with a temperature change. For example, the temperature detection unit 22 includes one or a plurality of bipolar transistors having two terminals by connecting any two of a base, an emitter, and a collector. The temperature can be measured by detecting the resistance value between the two terminals.

As shown in FIG. 8, in the present embodiment, the temperature detection unit 22 is configured by connecting a plurality of (e.g., 8) npn-type bipolar transistors 90 whose base and collector are connected in parallel. By connecting the plurality of bipolar transistors 90 in parallel in this manner, the junction area of the pn junction is increased and the ESD resistance is improved.

The emitter of the bipolar transistor 90 is connected to the pad 24a as the ground electrode terminal. The base and collector of the bipolar transistor 90 are connected to the pad 24e as a temperature detecting terminal.

The temperature measurement is performed by the temperature measurement processing unit 32 (see FIG. 12) in the ASIC chip 30 based on the potential of the pad 24e.

[Element structure of sensor chip]
Next, the element structure of the sensor chip 20 will be described.

FIG. 9 is a schematic cross-sectional view for explaining the element structure of the sensor chip 20. In FIG. 9, the pads 24a, 24b, 24c, 24e are shown in the same cross section as the humidity detecting section 21, the temperature detecting section 22, and the heating section 23, but this facilitates understanding of the structure. However, it does not mean that they actually exist in the same cross section. The cross sections of the humidity detecting unit 21, the temperature detecting unit 22, and the heating unit 23 are also simplified for easy understanding of the structure, and the positional relationship of each unit is different from the actual one.

As shown in FIG. 9, the sensor chip 20 is formed using the p-type semiconductor substrate 70 described above. A first deep n-well 100a and a second deep n-well 100b are formed on the p-type semiconductor substrate 70. The temperature detector 22 is formed in the first deep n-well 100a. The heating unit 23 is formed in the second deep n-well 100b.

P wells 103a and 103b are formed in the surface layer of the p-type semiconductor substrate 70 in which neither the first deep n well 100a nor the second deep n well 100b is formed. Contact layers 104a and 104b made of p-type diffusion regions are formed on the surface layers of the p wells 103a and 103b, respectively. The contact layers 104a and 104b are low resistance layers (p-type diffusion layers) for electrically connecting a predetermined wiring layer formed on the p-type semiconductor substrate 70 and the p-type semiconductor substrate 70.

A p well 101 and an n well 102 are formed in the surface layer of the first deep n well 100a. An n-type diffusion layer 91 and a p-type diffusion layer 92 are formed on the surface layer of the p-well 101. An n-type diffusion layer 93 is formed on the surface layer of the n-well 102. The n-type diffusion layer 91, the p-type diffusion layer 92, and the n-type diffusion layer 93 configure the npn-type bipolar transistor 90 described above, and function as an emitter, a base, and a collector, respectively.

A p-well 105 is formed on the surface of the second deep n-well 100b. One or more n-type diffusion layers 106 are formed on the surface layer of the p-well 105. In this embodiment, a plurality of n-type diffusion layers 106 are formed. For example, each n-type diffusion layer 106 extends in a direction orthogonal to the paper surface and has a one-dimensional lattice shape as a whole (see FIG. 11). The n-type diffusion layer 106 has a predetermined resistance value (for example, a sheet resistance value of about 3Ω), and functions as a resistor that generates heat when a current flows. That is, the n-type diffusion layer 106 constitutes the heating unit 23 described above.

Each layer in the p-type semiconductor substrate 70 is formed using a normal semiconductor manufacturing process (CMOS process). Therefore, the n-type diffusion layer 106 as a resistor is formed in the same manufacturing process as the n-type diffusion layers 91 and 93 included in a part of the temperature detection unit 22. The n-type diffusion layers 106, 91 and 93 are simultaneously formed by an ion implantation step of implanting impurities into the substrate by ion-implanting n-type impurities (for example, phosphorus). That is, the n-type diffusion layer 106 as a resistor has the same depth from the surface of the p-type semiconductor substrate 70 as the n-type diffusion layers 91 and 93 included in a part of the temperature detection unit 22. The n-type diffusion layer 106 may have the same depth from the surface of the p-type semiconductor substrate 70 as the p-type diffusion layer 92 included in a part of the temperature detection unit 22.

Note that the n-type diffusion layers 106, 91, 93 can be formed by a thermal diffusion process in which impurities are added by heat treatment instead of the ion implantation process.

The n-type diffusion layers 71, 72 of the ESD protection circuit 60 described above are also formed by the same manufacturing process (ion implantation process or thermal diffusion process) as the n-type diffusion layers 106, 91, 93. The contact layer 73 is formed in the same manufacturing process (ion implantation process or thermal diffusion process) as the p-type diffusion layer 92 and the contact layers 104a and 104b.

Since the other layers in the p-type semiconductor substrate 70 mainly function as contact layers, the description thereof will be omitted.

A first insulating film 110, a second insulating film 111, and a third insulating film 112 are sequentially stacked on the surface of the p-type semiconductor substrate 70. These are formed of an insulating material such as silicon dioxide (SiO ₂ ) or silicon nitride (SiN).

A first wiring layer 120 is formed on the first insulating film 110. A second wiring layer 121 is formed on the second insulating film 111. The second insulating film 111 covers the first wiring layer 120. The third insulating film 112 covers the second wiring layer 121. The first wiring layer 120 and the second wiring layer 121 are made of a conductive material such as aluminum.

A first plug layer 122 having a plurality of first plugs for connecting the first wiring layer 120 to the p-type semiconductor substrate 70 is formed in the first insulating film 110. A second plug layer 123 having a plurality of second plugs for connecting the first wiring layer 120 and the second wiring layer 121 is formed in the second insulating film 111. The first plug layer 122 and the second plug layer 123 are formed of a conductive material such as tungsten.

For example, the wiring 94 for connecting the base and collector of the bipolar transistor 90 described above is formed by the first wiring layer 120, and is formed in the p-type diffusion layer 92 and the n-type diffusion layer 93 via the first plug layer 122. Connected. Further, the wiring 94 is connected to the pad 24e as the temperature detecting terminal via the second plug layer 123 and the second wiring layer 121. The n-type diffusion layer 91 as the emitter of the bipolar transistor 90 is connected to the pad 24a as the ground electrode terminal via the first plug layer 122, the first wiring layer 120, and the second wiring layer 121.

The wiring 107 for grounding one end of the heating unit 23 to the ground potential is formed by the first wiring layer 120 and is connected to the n-type diffusion layer 106 and the contact layer 104b via the first plug layer 122. The wiring 108 for connecting the other end of the heating unit 23 to the pad 24f as a heating terminal is connected to the n-type diffusion layer 106 via the first plug layer 122, and the second plug layer 123 and It is connected to the pad 24f via the second wiring layer 121.

The reference electrode 82 of the reference capacitor 81 is formed by the first wiring layer 120, and is connected to the pad 24d (not shown in FIG. 9) as a reference electrode terminal via the second plug layer 123 and the second wiring layer 121. Connected.

The lower electrode 83 of the humidity detecting capacitor 80 is formed by the second wiring layer 121 and is connected to the pad 24b as the lower electrode terminal. Further, the wiring 85 for connecting the upper electrode 84 of the humidity detecting capacitor 80 to the pad 24c as the humidity detecting terminal is formed by the second wiring layer 121. The lower electrode 83 is arranged at a position facing the reference electrode 82 via the second insulating film 111.

The pads 24a to 24f are formed of a conductive material such as aluminum on the third insulating film 112, penetrate the third insulating film 112, and are connected to the second wiring layer 121.

A moisture sensitive film 86 is formed on the third insulating film 112. The moisture sensitive film 86 has a thickness of 0.5 μm to 1.5 μm and is made of a polymer material that easily adsorbs and desorbs water molecules depending on humidity. The moisture sensitive film 86 is, for example, a polyimide film having a thickness of 1 μm. The polymer material forming the moisture sensitive film 86 is not limited to polyimide, and may be cellulose, polymethylmethacrylate (PMMA), polyvinyl alcohol (PVA), or the like.

The upper surface of the moisture sensitive film 86 is flat, and the flat upper electrode 84 is formed on this upper surface. The upper electrode 84 is formed at a position facing the lower electrode 83 via the moisture sensitive film 86. Part of the upper electrode 84 is connected to the wiring 85. The upper electrode 84 is a conductive film made of, for example, aluminum having a thickness of 200 nm. Further, in the upper electrode 84, a plurality of openings 84a are formed in order to efficiently take in water molecules in the air into the moisture sensitive film 86.

An overcoat film 87 is provided on the moisture sensitive film 86 so as to cover the upper electrode 84. The overcoat film 87 is formed of a polymer material, for example, the same material as the moisture sensitive film 86. The overcoat film 87 has a thickness of, for example, 0.5 μm to 10 μm.

The moisture sensitive film 86 and the overcoat film 87 have openings for exposing the pads 24a to 24f.

Thus, the lower electrode 83 and the upper electrode 84 form a parallel plate humidity detecting capacitor 80. The lower electrode 83 and the reference electrode 82 form a parallel plate reference capacitor 81. The humidity detecting capacitor 80 and the reference capacitor 81 are arranged above the heating unit 23.

Therefore, when the heating unit 23 generates heat, the moisture sensitive film 86 between the lower electrode 83 and the upper electrode 84 is heated. As a result, the moisture-sensitive film 86 adsorbs water molecules in an amount corresponding to humidity as the temperature rises due to heating, so that the dielectric constant changes and the capacitance of the humidity detecting capacitor 80 decreases. Further, the temperature detection unit 22 detects a temperature rise caused by the heating unit 23.

FIG. 10 is a plan view illustrating the shapes of the lower electrode 83 and the upper electrode 84. As shown in FIG. 10, both the lower electrode 83 and the upper electrode 84 have a rectangular shape. The upper electrode 84 is formed so as to cover the lower electrode 83.

The opening 84a is preferably as small as possible, and the smaller the size, the more the leakage of the electric field into the air is prevented. In reality, many openings 84a are formed. The opening 84a is not limited to a square shape, and may be an elongated strip shape or a circular shape. The openings 84a may be arranged in a staggered pattern. The openings 84a are preferably circular and staggered.

Although not shown in FIG. 10, a rectangular reference electrode 82 is formed below the lower electrode 83.

FIG. 11 is a plan view illustrating the shape of the n-type diffusion layer 106 that constitutes the heating unit 23. As shown in FIG. 11, the n-type diffusion layer 106 has a one-dimensional lattice shape in which a plurality of elongated strip-shaped regions are arranged in parallel. One end of the one-dimensional lattice-shaped n-type diffusion layer 106 is connected to the wiring 107 described above, and the other end is connected to the wiring 108 described above. The heating unit 23 is located below the temperature detection unit 22 so as to cover the entire temperature detection unit 22.

[Functional configuration of ASIC chip]
Next, the functional units included in the ASIC chip 30 will be described.

FIG. 12 is a block diagram illustrating the functional configuration of the ASIC chip 30. As shown in FIG. 12, the ASIC chip 30 includes a humidity measurement processing unit 31, a temperature measurement processing unit 32, a heating control unit 33, and a failure determination unit 34.

The humidity measurement processing unit 31 applies a predetermined drive voltage to the pad 24b serving as the lower electrode terminal, and detects the potential of the pad 24c serving as the humidity detecting terminal and the potential of the pad 24d serving as the reference electrode terminal. Then, the humidity measurement processing unit 31 calculates the relative humidity (%RH) based on the potential difference between the two.

The temperature measurement processing unit 32 detects the potential of the pad 24e as the temperature detecting terminal and calculates the temperature corresponding to the detected potential.

The heating control unit 33 applies a predetermined driving voltage to the pad 24f serving as a heating terminal to cause a current (for example, about 10 mA) to flow through the heating unit 23 to generate heat. The heating control unit 33 controls the amount of heat generated by controlling the voltage applied to the pad 24f.

The failure determination unit 34 makes a failure determination based on the relative humidity measured by the humidity measurement processing unit 31 and the temperature measured by the temperature measurement processing unit 32. The failure determination unit 34 gives instructions to the heating control unit 33 regarding the start and end of heating of the heating unit 23 at the time of failure determination.

[Fault determination processing]
Next, the failure determination process performed by the failure determination unit 34 will be described.

FIG. 13 is a flowchart illustrating the failure determination process. The failure determination process starts, for example, in response to a start signal input to the ASIC chip 30 from outside the humidity detection device 10.

As illustrated in FIG. 13, when the failure determination process starts, the failure determination unit 34 acquires the relative humidity measurement value H1 (hereinafter, referred to as humidity H1) from the humidity measurement processing unit 31, and from the temperature measurement processing unit 32. A measured value T1 of temperature (hereinafter referred to as temperature T1) is acquired (step S1). The humidity H1 and the temperature T1 are measured values in the initial state when the heating unit 23 does not generate heat.

Next, the failure determination unit 34 gives a heating start instruction to the heating control unit 33 to start heating by the heating unit 23 (step S2). Then, the failure determination unit 34 acquires the measured value H2 of relative humidity (hereinafter, referred to as humidity H2) from the humidity measurement processing unit 31 again after the elapse of a certain time, and the measured value of temperature from the temperature measurement processing unit 32. T2 (hereinafter referred to as temperature T2) is acquired (step S3). After that, the failure determination unit 34 gives a heating end instruction to the heating control unit 33 to end the heating by the heating unit 23 (step S4).

Next, the failure determination unit 34 compares the temperature T1 with the temperature T2 (step S5). If T2>T1, that is, if the temperature rises due to heating (YES determination), the process proceeds to step S6. Proceed. In step S6, the failure determination unit 34 compares the humidity H1 with the humidity H2, and when H2<H1, that is, when the humidity is decreased by heating (YES determination), each unit of the humidity detection device 10 is normal. Is determined (step S7).

On the other hand, when the failure determination unit 34 does not satisfy T2>T1 in step S5, that is, when the temperature does not rise due to heating (NO determination), the heating unit 23 or the temperature detection unit 22 has a failure. (Step S8). This is because it is considered that there is an abnormality in the heating operation by the heating unit 23 or an abnormality in the temperature detection operation by the temperature detection unit 22. The cause of the failure includes disconnection of the first bonding wire 43 and the like.

Further, when the H2<H1 is not satisfied in step S6, that is, when the humidity does not decrease due to heating (NO determination), the failure determination unit 34 determines that the humidity detection unit 21 has failed (NO). Step S9). This is because the humidity detecting operation by the humidity detecting unit 21 is not functioning even though the heating operation by the heating unit 23 is normal. The cause of the failure includes disconnection of the first bonding wire 43 and the like.

With the above, the failure determination processing ends. The failure determination unit 34 appropriately outputs the determination results in steps S7 to S9 to the outside via the lead terminal 41.

For example, when T1=23.0° C. and H1=50% RH in the initial state, the dew point is 12.03° C. DP. When the temperature is raised by 2.0° C. by the heating by the heating unit 23, T2=25.0° C. in a normal state. At this time, assuming that the atmosphere does not change and the dew point is constant at 12.03° C. DP, H2=44.3% RH in a normal state.

As described above, in the failure determination process, when the temperature does not increase, and when the temperature increases but the humidity does not decrease, it is determined as a failure. By this failure determination, the failure of the humidity detecting device 10 can be easily detected.

[effect]
In the above-described embodiment, the heating portion 23 is formed by the n-type diffusion layer 106, and the surface layer of the p-type semiconductor substrate 70 on which the n-type diffusion layer 106 is formed is flat. Therefore, it is formed on the p-type semiconductor substrate 70. The flatness of the first to third insulating films 110 to 112 and the moisture sensitive film 86 is high. Therefore, the reference electrode 82, the lower electrode 83, and the upper electrode 84 formed above the heating unit 23 are not affected by the shape of the heating unit 23, and the flatness is improved. Therefore, the unevenness is suppressed in the inter-electrode distance (the inter-electrode distance between the lower electrode 83 and the upper electrode 84 and the inter-electrode distance between the lower electrode 83 and the reference electrode 82) of the parallel plate formed above the heating unit 23. As a result, the humidity becomes substantially constant, and a decrease in humidity detection accuracy is suppressed.

In the above embodiment, the first DAF 42, which is a resin film, is arranged on the lower surface of the sensor chip 20. Since this resin film has a low thermal conductivity and has an effect of suppressing heat radiation from the sensor chip 20 to the ASIC chip 30, the heat conduction efficiency from the heating unit 23 to the moisture sensitive film 86 is improved.

Further, in the above-described embodiment, the n-type diffusion layer 106 forming the heating unit 23 has a one-dimensional lattice shape, so that the uniformity of heat generation is improved. This is because, if the n-type diffusion layer 106 were formed as one region, it is considered that current is concentrated in a portion having high conductivity due to unevenness of impurity addition or the like, and heat generation becomes non-uniform. .

[Modification]
Various modifications will be described below.

In the above embodiment, the reference electrode 82 is arranged above the heating section 23, but the reference electrode 82 does not necessarily have to be above the heating section 23.

Further, in the above embodiment, the p-type semiconductor substrate 70 is used as the semiconductor substrate for forming the sensor chip 20, but it is also possible to use the n-type semiconductor substrate. In this case, the heating unit 23 may be formed by the p-type diffusion layer. That is, the heating unit may be formed of an impurity diffusion layer formed by adding impurities to the surface layer of the semiconductor substrate.

Further, in the above-described embodiment, the temperature detection unit 22 is configured by the npn-type bipolar transistor 90, but it may be configured by the pnp-type bipolar transistor. Further, the temperature detection unit 22 may be configured by one or a plurality of pn junction diodes instead of the bipolar transistor.

Further, the temperature detection unit 22 may be a temperature sensor other than a band gap type sensor having a pn junction. For example, the temperature detection unit 22 may be a resistance-type temperature sensor that uses an impurity diffusion layer (n-type diffusion layer or p-type diffusion layer) as a resistor and detects the temperature based on the temperature dependence of the resistance value. ..

FIG. 14 is a diagram showing an example in which the temperature detecting unit is a resistance type temperature sensor. The temperature detection unit 22a illustrated in FIG. 14 includes a bridge circuit 200 in which a first resistor 201, a second resistor 202, a third resistor 203, and a fourth resistor 204 are connected to each other.

The first resistor 201 and the second resistor 202 are connected in series between the power supply potential (VDD) and the ground potential. Similarly, the third resistor 203 and the fourth resistor 204 are connected in series between the power supply potential and the ground potential.

The first to fourth resistors 201 to 204 are n-type diffusion layers or p-type diffusion layers formed on the surface layer of the semiconductor substrate. The first resistor 201 and the fourth resistor 204 have substantially the same impurity concentration and substantially the same temperature coefficient. The second resistor 202 and the third resistor 203 have almost the same impurity concentration and substantially the same temperature coefficient.

The potential V1 at the connection between the first resistor 201 and the second resistor 202 is input to the differential amplifier 210 via the external terminal OUT1. The potential V2 at the connection between the third resistor 203 and the fourth resistor 204 is input to the differential amplifier 210 via the external terminal OUT2. The external terminals OUT1 and OUT2 are formed by two pads 24 instead of the above-mentioned temperature detecting terminals.

The differential amplifier 210 is provided, for example, in the ASIC chip 30, and amplifies the difference between the potential V1 and the potential V2 and outputs a differential output Vout. When the resistance value of the first resistor 201 and the fourth resistor 204 is R1 and the resistance value of the second resistor 202 and the third resistor 203 is R2, the differential output value Vout is expressed by the following equation (1). expressed.

Vout=[(R1−R2)/(R1+R2)]×VDD (1)
Since the changes of the resistance values R1 and R2 with respect to the temperature are different, the temperature can be obtained based on the differential output Vout. Since the differential output Vout depends on the power supply potential VDD according to the equation (1), it is preferable to obtain the temperature based on the value Vout/VDD obtained by dividing the differential output Vout by the power supply potential VDD.

Further, in the above embodiment, the ESD protection circuit 60 is composed of the NMOS transistor, but it may be composed of the PMOS transistor. Further, the manufacturing process of the sensor chip 20 is simplified by making the step of forming the gate electrode of the MOS transistor configuring the ESD protection circuit 60 common with the step of forming the wiring layers of the humidity detecting unit 21 and the temperature detecting unit 22. To be done. Furthermore, the ESD protection circuit 60 can be configured by a pn junction in the semiconductor substrate. In this case, since the gate electrode is unnecessary, the manufacturing process of the sensor chip 20 is simplified.

In the above embodiment, the failure determination unit 34 is provided in the ASIC chip 30, but the failure determination unit 34 is provided outside the ASIC chip 30, that is, in an external device (for example, a microcomputer) outside the humidity detection device 10. May be.

Further, in the present disclosure, the positional relationship between the two elements represented by the words “cover” and “upper” means that the first element is indirectly provided on the surface of the second element via the other element. Both when provided and when provided directly.

Although the preferred embodiments of the present invention have been described above in detail, the present invention is not limited to the above-described embodiments, and various modifications are made to the above-described embodiments without departing from the scope of the present invention. And substitutions can be added.

10 Humidity detection device, 20 Sensor chip, 21 Humidity detection part, 22 Temperature detection part, 23 Heating part, 24, 24a-24f Bonding pad, 30 ASIC chip, 31 Humidity measurement processing part, 32 Temperature measurement processing part, 33 Heating control Section, 34 failure determination section, 40 mold resin, 41 lead terminal, 42 first DAF, 45 second DAF, 50 opening, 51 effective opening, 60 ESD protection circuit, 61 diode, 70 p-type semiconductor substrate, 80 for humidity detection Capacitor, 81 Reference capacitor, 82 Reference electrode, 83 Lower electrode, 84 Upper electrode, 84a Opening, 86 Moisture sensitive film, 87 Overcoat film, 90 Bipolar transistor, 91 n-type diffusion layer, 92 p-type diffusion layer, 93 n Type diffusion layer, 106 n-type diffusion layer, 110 first insulating film, 111 second insulating film, 112 third insulating film, 120 first wiring layer, 121 second wiring layer, 122 first plug layer, 123 second plug layer

Claims (14)

A semiconductor substrate,
A heating portion formed by the impurity diffusion layer in the semiconductor substrate,
A lower electrode formed above the heating portion via an insulating film,
A moisture-sensitive film covering the lower electrode,
An upper electrode formed on the moisture-sensitive film,
Humidity detection device having. The humidity detection device according to claim 1, wherein the impurity diffusion layer has a one-dimensional lattice shape. The humidity detecting device according to claim 1, further comprising a temperature detecting unit formed on the semiconductor substrate. The humidity detecting device according to claim 3, wherein the temperature detecting unit is a bandgap type and includes one or a plurality of bipolar transistors having a base and a collector connected to each other. The humidity detecting device according to claim 3, wherein the temperature detecting unit is a band gap type and includes one or a plurality of pn junction diodes. The temperature detection unit is a resistance-type temperature sensor that uses an n-type diffusion layer or a p-type diffusion layer formed in the semiconductor substrate as a resistor and detects temperature based on the temperature dependence of the resistor. Item 3. The humidity detection device according to item 3. The humidity detecting device according to claim 6, wherein the temperature detecting unit includes a bridge circuit in which a plurality of resistors having different impurity concentrations are connected to each other. 8. The depth of the impurity diffusion layer from the surface of the semiconductor substrate is the same as the depth of the n-type diffusion layer or the p-type diffusion layer included in a part of the temperature detection unit. Humidity detector. 9. The humidity detecting device according to claim 1, wherein the semiconductor substrate is a p-type semiconductor substrate, and the impurity diffusion layer is an n-type diffusion layer. The humidity detecting device according to claim 1, wherein the moisture sensitive film is made of polyimide. 4. A failure determination unit that performs a failure determination based on the humidity detected based on the capacitance between the lower electrode and the upper electrode and the temperature detected by the temperature detection unit. 8. The humidity detecting device according to any one of 8 above. The humidity detection device according to claim 11, wherein the failure determination unit determines a failure when the heating unit generates heat and the temperature does not increase, and when the temperature increases but the humidity does not decrease. A semiconductor substrate,
A heating portion formed by the impurity diffusion layer in the semiconductor substrate,
A lower electrode formed above the heating portion via an insulating film,
A moisture-sensitive film covering the lower electrode,
An upper electrode formed on the moisture-sensitive film,
A temperature detector formed on the semiconductor substrate;
A failure determination method for a humidity detector having:
A failure determination method for performing a failure determination based on the humidity detected based on the capacitance between the lower electrode and the upper electrode and the temperature detected by the temperature detection unit. The failure determination method according to claim 13, wherein the failure is determined when the heating unit is caused to generate heat and the temperature does not increase, and when the temperature increases but the humidity does not decrease.

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